One small change I forgot to make in
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Mon Sep 8 14:25:41 2014 +0100
drm/i915: Evict CS TLBs between batches
was to update the copy width for the compact BLT copy instruction.
Reported-by:
On Thu, 11 Sep 2014, Gustavo Padovan gust...@padovan.org wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
7e4bf45dbd99a965c7b5d5944c6dc4246f171eb5 introduced the regression.
We fix it by doing the right assignment of crtc_y
Bugzilla:
Am 12.09.2014 08:37, schrieb Chris Wilson:
One small change I forgot to make in
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Mon Sep 8 14:25:41 2014 +0100
drm/i915: Evict CS TLBs between batches
was to update the copy width for the
On Thu, 11 Sep 2014, Jesse Barnes jbar...@virtuousgeek.org wrote:
Then I'd say let's go for it. We can always whitelist systems where we
can use fewer lanes (e.g. some Chromebooks).
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
You're late to the party! ;)
commit
On Fri, 12 Sep 2014, Chris Wilson ch...@chris-wilson.co.uk wrote:
One small change I forgot to make in
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Mon Sep 8 14:25:41 2014 +0100
drm/i915: Evict CS TLBs between batches
was to
Hi Dave,
So updated vblank-rework pull request, now with the polish that Mario
requested applied (and reviewed by him). Also with backmerge like you've
requested for easier merging.
The neat thing this finally allows is to immediately disable the vblank
interrupt on the last drm_vblank_put if
On Fri, Sep 12, 2014 at 10:12:37AM +0300, Jani Nikula wrote:
On Thu, 11 Sep 2014, Gustavo Padovan gust...@padovan.org wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
7e4bf45dbd99a965c7b5d5944c6dc4246f171eb5 introduced the regression.
We fix it by doing the right assignment of
On Thu, Sep 11, 2014 at 11:20:13AM -0700, Jesse Barnes wrote:
Tried to find a JIRA for this but only came up with VIZ-1789. Looks
like it might be close enough for Wayland?
Different thing - this only avoids reprobing within a single detect cycle
when we grab the edid multiple times. Edid
On Fri, Sep 12, 2014 at 10:34:23AM +0200, Daniel Vetter wrote:
On Thu, Sep 11, 2014 at 11:20:13AM -0700, Jesse Barnes wrote:
Tried to find a JIRA for this but only came up with VIZ-1789. Looks
like it might be close enough for Wayland?
Different thing - this only avoids reprobing within a
Hi,
Firstly, please cc me on any reply because I'm not subscribed to LKML.
I've just built and installed the current development kernel
(v3.17-rc4-222-gc73f6fd)on a desktop machine and I'm
getting a warning that I haven't seen before. A full dmesg is attached, but the
warning is:
[
Why doesn't mesa allocate buffers in the same way for those chips, then?
Do you have any documentation about this?
On Thu, Sep 11, 2014 at 12:37 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Sep 10, 2014 at 02:09:07PM -0700, Keith Packard wrote:
[PATCH 2/2] Correct BO allocation
On Fri, Sep 12, 2014 at 08:49:48AM +0100, Chris Clayton wrote:
Hi,
Firstly, please cc me on any reply because I'm not subscribed to LKML.
I've just built and installed the current development kernel
(v3.17-rc4-222-gc73f6fd)on a desktop machine and I'm
getting a warning that I haven't
On Thu, Sep 11, 2014 at 01:28:29PM +0200, Daniel Vetter wrote:
Based upon a patch from Deepak, but reworked to only apply on gen7+
and with the logic a bit clarified.
Cc: Deepak S deepa...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
On 09/12/14 09:51, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 08:49:48AM +0100, Chris Clayton wrote:
Hi,
Firstly, please cc me on any reply because I'm not subscribed to LKML.
I've just built and installed the current development kernel
(v3.17-rc4-222-gc73f6fd)on a desktop machine and
On Fri, Sep 12, 2014 at 12:23:14PM +0300, Ville Syrjälä wrote:
On Thu, Sep 11, 2014 at 01:28:29PM +0200, Daniel Vetter wrote:
Based upon a patch from Deepak, but reworked to only apply on gen7+
and with the logic a bit clarified.
Cc: Deepak S deepa...@intel.com
Signed-off-by: Daniel
From: Ville Syrjälä ville.syrj...@linux.intel.com
The limited color range knob is in the port registers on
g4x and vlv/chv for HDMI, and on g4x for DP. Add the relevant code
to read out the hardware state into pipe config. On vlv/chv the
DP port limited color range knob is in PIPECONF for which
While discussing/reviewing __GFP_MOVEABLE behaviour and interactions
with our various page allocations on irc Chris brought up that the
scratch page isn't allocated as moveable, but we still grab/put a
reference to lock it in place. Which is unecessary.
So drop that.
Acked-by: Chris Wilson
If a page isn't allocated as __GFP_MOVEABLE it won't move around, so
no need to grab a reference to lock it into place.
Discovered while reviewing page allocation handling in i915 gem.
Acked-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
IVB introduced the CUR_FBC_CTL register which allows reducing the cursor
height down to 8 lines from the otherwise square cursor dimensions.
Implement support for it.
Commandeer the otherwise unused intel_crtc-cursor_size to track the
current
From: Ville Syrjälä ville.syrj...@linux.intel.com
IVB introduced the CUR_FBC_CTL register which allows reducing the cursor
height down to 8 lines from the otherwise square cursor dimensions.
Implement support for it.
Commandeer the otherwise unused intel_crtc-cursor_size to track the
current
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no similar restriction listed for HSW, so leave that one alone
for now.
v2: Add
From: Ville Syrjälä ville.syrj...@linux.intel.com
Unlike the kernel IS_VALLEYVIEW() doesn't cover chv in igt. Add the
appropriate IS_CHERRYVIEW() checks to the various sideband poking tools.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
tools/intel_dpio_read.c | 2 +-
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add a bunc of symbolic sideband unit names so that you don't have to go
trawling through the sideband HAS every time you want to poke at
something with the tool. You can still specify the port manually though
if you know them by heart already.
From: Ville Syrjälä ville.syrj...@linux.intel.com
intel_iosf_sb_{read,write} provide the same functionality.
intel_dpio_{read,write} are still left in place since they use a
different opcode to do the register access. Need to verify if
both opcodes work.
Signed-off-by: Ville Syrjälä
On Fri, 12 Sep 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
intel_iosf_sb_{read,write} provide the same functionality.
intel_dpio_{read,write} are still left in place since they use a
different opcode to do the register access. Need to verify
On Fri, Sep 12, 2014 at 05:55:40PM +0300, Jani Nikula wrote:
On Fri, 12 Sep 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
intel_iosf_sb_{read,write} provide the same functionality.
intel_dpio_{read,write} are still left in place since they
On Fri, 12 Sep 2014, Jani Nikula jani.nik...@intel.com wrote:
On Fri, 12 Sep 2014, Chris Wilson ch...@chris-wilson.co.uk wrote:
One small change I forgot to make in
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Mon Sep 8 14:25:41 2014
Bunch of things amiss:
- Updating crtc-cursor_x/y was done without any locking. Spotted by
David Herrmann.
- Dereferencing crtc-cursor-fb was using the wrong lock, should take
the crtc lock.
- Grabbing _all_ modeset locks torpedoes the reason why we added
fine-grained locks originally:
The comment says that the caller must hold the dev-event_lock
spinlock, so let's enforce this.
A quick audit over all driver shows that except for the one place in
i915 which motivated this all callers fullfill this requirement
already.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc:
On 09/12/14 13:46, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The limited color range knob is in the port registers on
g4x and vlv/chv for HDMI, and on g4x for DP. Add the relevant code
to read out the hardware state into pipe config. On vlv/chv
From: Ben Widawsky benjamin.widaw...@intel.com
The simple explanation is, the docs say to do this for GEN8. Perhaps we
want to do this for GEN7 too, I am not certain.
PDPs are saved and restored with context. Contexts (without execlists)
only exist on the render ring. The docs say that PDPs are
On Fri, Sep 12, 2014 at 03:40:56PM +0200, Daniel Vetter wrote:
The comment says that the caller must hold the dev-event_lock
spinlock, so let's enforce this.
A quick audit over all driver shows that except for the one place in
i915 which motivated this all callers fullfill this requirement
On Fri, Sep 12, 2014 at 04:23:29PM +0100, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 03:40:56PM +0200, Daniel Vetter wrote:
The comment says that the caller must hold the dev-event_lock
spinlock, so let's enforce this.
A quick audit over all driver shows that except for the one place in
On Fri, Sep 12, 2014 at 04:10:01PM +0100, Michel Thierry wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The simple explanation is, the docs say to do this for GEN8. Perhaps we
want to do this for GEN7 too, I am not certain.
PDPs are saved and restored with context. Contexts (without
Hi Dave,
So here's the header cleanup, rebased on top of drm-next. Two new header
files are created here:
- drivers/gpu/drm/drm_internal.h for non-legacy drm.ko private
declarations.
- include/drm/drm_legacy.h for legacy interfaces used by non-kms drivers.
And of course lots fo stuff gets
On Fri, Sep 12, 2014 at 06:35:10PM +0300, Ville Syrjälä wrote:
On Fri, Sep 12, 2014 at 04:10:01PM +0100, Michel Thierry wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The simple explanation is, the docs say to do this for GEN8. Perhaps we
want to do this for GEN7 too, I am not
On Fri, Sep 12, 2014 at 05:01:57PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no
On Fri, Sep 12, 2014 at 04:42:33PM +0100, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 05:01:57PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core
On Fri, Sep 12, 2014 at 05:34:56PM +0200, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 04:23:29PM +0100, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 03:40:56PM +0200, Daniel Vetter wrote:
The comment says that the caller must hold the dev-event_lock
spinlock, so let's enforce this.
On 9/12/2014 4:40 PM, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 06:35:10PM +0300, Ville Syrjälä wrote:
On Fri, Sep 12, 2014 at 04:10:01PM +0100, Michel Thierry wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The simple explanation is, the docs say to do this for GEN8. Perhaps we
want
On Fri, Sep 12, 2014 at 05:56:30PM +0100, Michel Thierry wrote:
On 9/12/2014 4:40 PM, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 06:35:10PM +0300, Ville Syrjälä wrote:
On Fri, Sep 12, 2014 at 04:10:01PM +0100, Michel Thierry wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
The
On Fri, Sep 12, 2014 at 01:03:51PM -0400, Peter Hurley wrote:
On 09/12/2014 12:04 PM, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 05:34:56PM +0200, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 04:23:29PM +0100, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 03:40:56PM +0200, Daniel Vetter
Adding code to enable DRRS during ddi enable and disable DRRS during ddi disable
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 48
drivers/gpu/drm/i915/intel_drv.h |
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next
Calls to switch between high and low refresh rates based on calls made to
fb_invalidate and fb_flush.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5
drivers/gpu/drm/i915/intel_dp.c | 51
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files changed, 9
As part of implementing DRRS based on frontbuffer tracking, this patch series
includes some modifications related to the data for DRRS, code to enable/
disable DRRS during init or uninit, calls to switch between high and low
refresh rates based on calls to mark_fb_busy.
Instead of having a module
Initializing DRRS work to program lower refresh rate.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 36
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
Moving around and changing some data related to DRRS to support
DRRS based on frontbuffer tracking in the following patches
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 32 ++---
drivers/gpu/drm/i915/intel_dp.c | 51
Hi Dave,
Usual pile of random drm patches all over. One i915 one in here for the
hdmi doubleclock stuff since I've put both of Clint's patches into this
branch.
Rebased just now only to check what you've merged already, otherwise this
has been hanging out in -nightly for quite a while.
Cheers,
On 09/12/2014 01:25 PM, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 01:03:51PM -0400, Peter Hurley wrote:
On 09/12/2014 12:04 PM, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 05:34:56PM +0200, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 04:23:29PM +0100, Chris Wilson wrote:
On Fri, Sep 12,
From: Ville Syrjälä ville.syrj...@linux.intel.com
To make the code a bit more undestandable move the
intel_crtc-cursor_base assignment into the low level update cursor
routines. That's were we compare the current value with the new one
so immediately seeing that it gets assigned only afterwards
On Fri, Sep 12, 2014 at 05:07:32PM +0200, Daniel Vetter wrote:
Bunch of things amiss:
- Updating crtc-cursor_x/y was done without any locking. Spotted by
David Herrmann.
- Dereferencing crtc-cursor-fb was using the wrong lock, should take
the crtc lock.
- Grabbing _all_ modeset locks
From: Ville Syrjälä ville.syrj...@linux.intel.com
Only write CURBASE when something about the cursor changed. Also
eliminate the unnecessary posting read after writing CURCNTR.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1
From: Ville Syrjälä ville.syrj...@linux.intel.com
It seems cleaner if we keep CURCNTR at 0 when the cursor is disabled,
so don't set the CURSOR_PIPE_CSC_ENABLE bit unless the cursor is
enabled.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c |
From: Ville Syrjälä ville.syrj...@linux.intel.com
IVB introduced the CUR_FBC_CTL register which allows reducing the cursor
height down to 8 lines from the otherwise square cursor dimensions.
Implement support for it.
Commandeer the otherwise unused intel_crtc-cursor_size to track the
current
From: Armin Reese armin.c.re...@intel.com
This patch includes the Gen9 batch buffer to generate
a 'golden context' for that product family.
Also:
1) IS_GEN9 macro has been added to drivers/gpu/drm/i915/i915_drv.h
2) drivers/gpu/drm/i915/intel_renderstate_gen8.c has been updated
to the version
From: Armin Reese armin.c.re...@intel.com
The new 'i915_context_dump' file generates a hex dump of the
entire logical context DRM object. It is useful for
validating the contents of the default context set up by
the golden state batch buffer.
Signed-off-by: Armin Reese armin.c.re...@intel.com
From: Armin Reese armin.c.re...@intel.com
Golden context batch buffers now can contain a set of offsets in
which to optionally place MI_BATCH_BUFFER_END commands. This
allows the driver to customize the GC batch for various chipsets
in a family by requesting that the GC BB exit early for one
From: Ville Syrjälä ville.syrj...@linux.intel.com
To minimally verify that non-square cursors work on the platforms where
they're supported perform the tests first with WxH cursor and then
repeat with WxH/3 cursor.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow tests to specify the plane size instead of assuming that the
entire FB will be scanned out.
To keep the current tests working without having to sprinkle
igt_plane_set_size() calls all over the place, make
igt_plane_set_fb() reset the plane
On 09/12/2014 12:04 PM, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 05:34:56PM +0200, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 04:23:29PM +0100, Chris Wilson wrote:
On Fri, Sep 12, 2014 at 03:40:56PM +0200, Daniel Vetter wrote:
The comment says that the caller must hold the dev-event_lock
On Wednesday, September 10, 2014 02:09:07 PM Keith Packard wrote:
Here are a couple of small bug fixes which make DRI3/Present work
better with UXA.
[PATCH 1/2] Do not clear pending kernel events on mode switch
This patch prevents GL-based compositing managers from wedging when
Usual pile of random drm patches all over. One i915 one in here for the
hdmi doubleclock stuff since I've put both of Clint's patches into this
branch.
Rebased just now only to check what you've merged already, otherwise this
has been hanging out in -nightly for quite a while.
I already
In some cases like when PSR just got enabled the panel need more vblank
times to calculate CRC. I figured that out with the new PSR test cases
facing some cases that I had a green screen but a blank CRC. Even with
2 vblank waits on kernel + 2 vblank waits on test case.
So let's give up to 6
On Fri, Sep 12, 2014 at 11:25:14AM -0700, armin.c.re...@intel.com wrote:
From: Armin Reese armin.c.re...@intel.com
This patch includes the Gen9 batch buffer to generate
a 'golden context' for that product family.
Also:
1) IS_GEN9 macro has been added to drivers/gpu/drm/i915/i915_drv.h
2)
Please ignore this full series here.
I have a better one that let PSR on HSW in a better stage with only 1 idle
frame and without changing the 100ms. Actually if we are brave we can
reduce this to 24 or less. The new work is currently under
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