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Task id: 6385
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Platform Delta drm-intel-nightly Series Applied
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On Thu, May 14, 2015 at 03:41:54PM +0100, Damien Lespiau wrote:
gem_bad_blit.c: In function ‘bad_blit’:
gem_bad_blit.c:89:3: warning: right shift count = width of type [enabled by
default]
OUT_BATCH(BAD_GTT_DEST 32); /* Upper 16 bits */
Signed-off-by: Damien Lespiau
On Thu, 14 May 2015, Damien Lespiau damien.lesp...@intel.com wrote:
gem_bad_blit.c: In function ‘bad_blit’:
gem_bad_blit.c:89:3: warning: right shift count = width of type [enabled by
default]
OUT_BATCH(BAD_GTT_DEST 32); /* Upper 16 bits */
Signed-off-by: Damien Lespiau
Hi,
On 05/13/2015 01:22 PM, Chris Wilson wrote:
On Wed, May 13, 2015 at 11:13:24AM +0300, Abdiel Janulgue wrote:
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai minu.mat...@intel.com)
Signed-off-by: Abdiel Janulgue
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6384
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Platform Delta drm-intel-nightly Series Applied
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On Wed, 2015-05-13 at 18:25 +0100, Damien Lespiau wrote:
On Wed, May 13, 2015 at 05:56:17PM +0100, Damien Lespiau wrote:
On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Since commit 4978cc93d9ac240b435ce60431aef24239b4c270
On Fri, 15 May 2015, Mario Kleiner mario.kleiner...@gmail.com wrote:
Hi all,
since Linux 4.0 i experience some massive display flicker problem on my
Intel HD Ironlake mobile (2010 MacBookPro6,2) under Waylands reference
compositor Weston.
- Only happens on Linux = 4.0 on intel-kms with
On Tue, Feb 24, 2015 at 09:52:16PM +0100, Daniel Vetter wrote:
On Tue, Feb 24, 2015 at 10:37:10AM -0800, Bob Paauwe wrote:
On Tue, 24 Feb 2015 14:57:48 +0100
Daniel Vetter dan...@ffwll.ch wrote:
As Jani points out we already have vbt headaches, it would be good if we
only have those
When the modeset code is reached with a CRTC that only needs a flip, the
code that assigns PLLs is skipped. But since there is still a state swap
for that CRTC, the current PLL assignment needs to be preserved. I
missed the ddi_pll_sel field in the following commit, which causes
warnings in DDI
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6386
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Platform Delta drm-intel-nightly Series Applied
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On Wed, 2015-05-13 at 22:23 +0200, Maarten Lankhorst wrote:
From: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
The last remaining portion that required the modeset_crtc argument is
converted to deal with all crtcs in the state that need_modeset(). By
doing that,
If ANDROID_HAS_CAIRO is not set, automatically add all
kms tests to the skip_tests_list.
Building for android currently fails due to the addition of
new kms tests. Rather than just adding the new tests to the
exclusion list, autogenerating a list of all kms tests and
excluding them will reduce
Hi,
On 05/15/2015 11:34 AM, Ander Conselvan de Oliveira wrote:
In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens just
before the call the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6387
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Platform Delta drm-intel-nightly Series Applied
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On Fri, May 15, 2015 at 04:05:01PM +0600, Pavel Popov wrote:
The gem_bad_address test started to fail on Gen7 with enabled command parser.
Error message is printed because MI_GLOBAL_GTT equals to MI_MEM_VIRTUAL:
CMD: Rejected command 0x1062 for bitmask 0x0040
MI_MEM_VIRTUAL
The gem_bad_address test started to fail on Gen7 with enabled command parser.
Error message is printed because MI_GLOBAL_GTT equals to MI_MEM_VIRTUAL:
CMD: Rejected command 0x1062 for bitmask 0x0040
MI_MEM_VIRTUAL means global gtt. This bit shouldn't be set for ppgtt.
Changed test
In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens just
before the call the .crtc_compute_clock() hook. The DP code for SKL,
however, sets up the
On Fri, 2015-05-15 at 13:56 +0300, Jani Nikula wrote:
On Fri, 15 May 2015, Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com wrote:
In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
On Fri, May 15, 2015 at 12:16:06PM +0300, Abdiel Janulgue wrote:
Hi,
On 05/13/2015 01:22 PM, Chris Wilson wrote:
On Wed, May 13, 2015 at 11:13:24AM +0300, Abdiel Janulgue wrote:
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6395
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Platform Delta drm-intel-nightly Series Applied
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From: Mika Kuoppala mika.kuopp...@linux.intel.com
Reading from disconnected ports will spit out timeout error
on the dmesg. Skip the attempted read if the port is not
connected and avoid confusing users/testcases about
expected timeouts.
This new dpcd debugfs entry was introduced by commit
On 14 May 2015 at 09:59, Derek Morton derek.j.mor...@intel.com wrote:
On android with small memory footprints gem_cpu_reloc can fail
due to OOM.
Refactor gem_cpu_reloc into 2 tests, a basic test which performs
10 relocations and a full test which skips if there is insufficient
memory.
Mika encountered one pathological scenario under X where acquiring all
the mm locks (required to insert a mmu notifier) was very slow, so slow
that by the time we tried to lock the struct_mutex with the usual call
to i915_mutex_lock_interruptible(), X's signal timer had fired causing
us to restart
Hi,
On 05/15/2015 11:42 AM, Chris Wilson wrote:
Mika encountered one pathological scenario under X where acquiring all
the mm locks (required to insert a mmu notifier) was very slow, so slow
that by the time we tried to lock the struct_mutex with the usual call
to
On Wed, 2015-05-13 at 17:56 +0100, Damien Lespiau wrote:
On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
dpll state and recomputing it via
On Fri, 15 May 2015, Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com wrote:
In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens
On Fri, May 15, 2015 at 01:34:29PM +0300, Ander Conselvan de Oliveira wrote:
In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens just
before the
On Fri, May 15, 2015 at 02:08:22AM +0530, Ramalingam C wrote:
After scheduling a flip for obj, we are supposed to invalidate the
drrs.
Action:
Adding a call to intel_edp_drrs_invalidate at
intel_frontbuffer_flip_prepare.
Signed-off-by: Ramalingam C ramalinga...@intel.com
On Fri, May 15, 2015 at 11:24:55AM +0100, Derek Morton wrote:
If ANDROID_HAS_CAIRO is not set, automatically add all
kms tests to the skip_tests_list.
Building for android currently fails due to the addition of
new kms tests. Rather than just adding the new tests to the
exclusion list,
On Fri, May 15, 2015 at 11:24:55AM +0100, Derek Morton wrote:
If ANDROID_HAS_CAIRO is not set, automatically add all kms tests to
the skip_tests_list.
Building for android currently fails due to the addition of new kms
tests. Rather than just adding the new tests to the exclusion list,
Summary
We covered the platforms: Skylake, Braswell, Broadwell, Haswell, Baytrail and
IvyBridge. In this circle, 7 new bugs have been found in manual testing and 7
new bugs have been found in nightly testing.
90431https://bugs.freedesktop.org/show_bug.cgi?id=90431 - [SKL] Call Trace
appears
On Fri, May 15, 2015 at 11:51:50AM +0300, Ander Conselvan de Oliveira wrote:
When the modeset code is reached with a CRTC that only needs a flip, the
code that assigns PLLs is skipped. But since there is still a state swap
for that CRTC, the current PLL assignment needs to be preserved. I
Ville noticed in another patch we we didn't need them at all, so remove
them. It's worth saying that it makes no difference to code generated as
gcc is clever enough to optimize it out.
v2: Remove 'break' after 'return' in switches (Ville)
Suggested-by: Ville Syrjälä
On Fri, May 15, 2015 at 12:15:36PM +0100, Morton, Derek J wrote:
On Fri, May 15, 2015 at 11:24:55AM +0100, Derek Morton wrote:
If ANDROID_HAS_CAIRO is not set, automatically add all kms tests to
the skip_tests_list.
Building for android currently fails due to the addition of new kms
On Fri, May 15, 2015 at 06:54:54PM +0530, Ramalingam C wrote:
On Friday 15 May 2015 05:28 PM, Chris Wilson wrote:
On Fri, May 15, 2015 at 02:08:22AM +0530, Ramalingam C wrote:
After scheduling a flip for obj, we are supposed to invalidate the
drrs.
Action:
Adding a call to
I'm still experiencing video lockups even though I'm currently running
the kernel shown in my sig along with Module intel: vendor=X.Org
Foundation compiled for 1.15.1, module version = 2.99.917. I thought I'd
narrowed the problem down to X-Screensaver as each time I start it
running I'd get the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6407
-Summary-
Platform Delta drm-intel-nightly Series Applied
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Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6409
-Summary-
Platform Delta drm-intel-nightly Series Applied
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On Tue, May 12, 2015 at 09:50:16PM +0200, Andreas Reis wrote:
Hi,
drm-intel-nightly @ 2015y-05m-12d-17h-21m-03s.
Warnings (27 each boot, here's three different ones) have been there for
a few days already. No noticeable effect.
Haswell 4770, two HDMI monitors to its IGP.
This should
On Friday 15 May 2015 05:28 PM, Chris Wilson wrote:
On Fri, May 15, 2015 at 02:08:22AM +0530, Ramalingam C wrote:
After scheduling a flip for obj, we are supposed to invalidate the
drrs.
Action:
Adding a call to intel_edp_drrs_invalidate at
intel_frontbuffer_flip_prepare.
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6411
-Summary-
Platform Delta drm-intel-nightly Series Applied
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Hi,
I have been seeing below warning on skylake system on which dmc fw isn't placed.
Is below warning expected? If so what is it conveying?
-Chandra
May 15 15:53:53 cmkondur-skl kernel: [19587.475013] WARNING: CPU: 0 PID: 1453
at
From: Runyan, Arthur J
I'll take a look.
Art, Any update to close on this?
[snip]
@@ -13144,6 +13149,10 @@ intel_check_primary_plane(struct
drm_plane
*plane,
if (fb format_is_yuv(fb-pixel_format)) {
src-x1 = ~0x1;
src-x2 =
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
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Task id: 6410
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We can only do something with ARGB buffers on VLV/CHV and gen9+. Let's not
expose those format before then.
Technically this is an ABI break but we did check the DDX wasn't using those,
so give it a shot.
--
Damien
Damien Lespiau (4):
drm/i915: Remove the COMMON_PRIMARY_FORMATS defines
That define makes it hard to figure out what is the actual list of
formats at a glance. Expand it then.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17 -
1 file
We don't actually do anything different for the A version of the
RGB formats before SKL. Don't let user space think we can support alpha
blending.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 35 ---
1 file
On Fri, May 15, 2015 at 07:57:13PM +0100, Damien Lespiau wrote:
We decided that liked the explicit list of IDs better than the encoded
one. The DDX may like this as well, if just to keep the files identical.
The point is that it is an exact copy. I have been referencing the
kernel commit that
On Fri, May 15, 2015 at 07:06:00PM +0100, Damien Lespiau wrote:
That define makes it hard to figure out what is the actual list of
formats at a glance. Expand it then.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
On Fri, May 15, 2015 at 07:06:01PM +0100, Damien Lespiau wrote:
We just have have VLV and CHV sprites programming the hardware
differently for the ABGR2101010 so keep them working.
Right. We'd need to update the primary plane programming for VLV/CHV
(and potentially gen4 sprite C) to support it
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
include/drm/i915_pciids.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index bd0d644..17c4456 100644
---
On Fri, May 15, 2015 at 07:06:03PM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Based on the docs these probably only support alpha with the
format.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c
We don't actually do anything different for the A version of the
RGB formats before SKL. Don't let user space think we can support alpha
blending.
v2: Fix the logic to forbid the creation ABGR2101010 fbs (Ville)
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/intel_chipset.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 37554e6..7f611ed 100644
--- a/lib/intel_chipset.h
+++
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_chipset.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e22a867..253ea71 100644
---
On Fri, May 15, 2015 at 07:06:02PM +0100, Damien Lespiau wrote:
We don't actually do anything different for the A version of the
RGB formats before SKL. Don't let user space think we can support alpha
blending.
gen2/3 planes B/C, gen4 plane C, and all VLV/CHV primary planes might
support
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
src/i915_pciids.h | 4
src/intel_module.c | 5 +
2 files changed, 9 insertions(+)
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index 6133723..17c4456 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -286,5 +286,9
We decided that liked the explicit list of IDs better than the encoded
one. The DDX may like this as well, if just to keep the files identical.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
src/i915_pciids.h | 49 +
1 file changed, 25
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c784f9a..c957a45 100644
---
We just have have VLV and CHV sprites programming the hardware
differently for the ABGR2101010 so keep them working.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff
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