On Tuesday 21 July 2015 07:35 PM, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 07:22:37PM +0800, kbuild test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel topic/crc-pmic
head: b029e66fa8e39ba10dcc47b114be8da8b082493b
commit: 61dd2ca2d44e493b050adbbb75bc50db11c367dd [2/7] mfd:
This patch series introduces the following features:
* Feature 1: TDR (Timeout Detection and Recovery) for gen8 execlist mode.
TDR is an umbrella term for anything that goes into detecting and recovering
from GPU hangs and is a term more widely used outside of the upstream driver.
This feature
On Tue, Jul 21, 2015 at 04:32:26PM +0200, Maarten Lankhorst wrote:
Op 21-07-15 om 16:14 schreef Daniel Vetter:
On Tue, Jul 21, 2015 at 01:29:01PM +0200, Maarten Lankhorst wrote:
Instead of doing a hack during primary plane commit the state
is updated during atomic evasion. It handles
On Tue, 2015-07-21 at 11:40 +0530, Jindal, Sonika wrote:
For the patch 3, the commit message can be changed to only long pulse
detection instead of long/short because you are not adding support
for short pulse detection.
Well it is support for differentiating between long and short pulses.
[1.] One line summary of the problem:
8086:1616 [Lenovo ThinkPad T450s] External monitor is disabled after
resume
[2.] Full description of the problem/report:
I have an external screen connected to my machine (T450s, via docking
station) and after resuming from suspend, my external monitor is
On Tue, Jul 21, 2015 at 02:08:23PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
A helpful function for when you want to read a whole debugfs file to a
string and don't want to worry about opening and closing file
descriptors and asserting buffer sizes.
We've been
On Tuesday 21 July 2015 11:10 PM, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 09:17:21PM +0530, Kumar, Shobhit wrote:
On Tuesday 21 July 2015 07:35 PM, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 07:22:37PM +0800, kbuild test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel
On Tue, Jul 21, 2015 at 09:17:21PM +0530, Kumar, Shobhit wrote:
On Tuesday 21 July 2015 07:35 PM, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 07:22:37PM +0800, kbuild test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel topic/crc-pmic
head:
From: Paulo Zanoni paulo.r.zan...@intel.com
A helpful function for when you want to read a whole debugfs file to a
string and don't want to worry about opening and closing file
descriptors and asserting buffer sizes.
We've been using this already for kms_frontbuffer_tracking and
kms_fbcon_fbt,
Hi David,
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
David Henningsson
Sent: Tuesday, July 21, 2015 1:27 PM
To: alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org;
ti...@suse.de; Vetter, Daniel;
jani.nik...@linux.intel.com
Clearing the watermarks for all pipes/planes when updating the
watermarks for a single CRTC change seems like the wrong thing to
do here. As is, this code will ony update any pipe/plane watermarks
that need updating and leave the remaining set to zero. Later, the
watermark checks in
On Tue, 2015-07-21 at 13:51 +0530, Sivakumar Thulasimani wrote:
On 7/21/2015 3:13 AM, Imre Deak wrote:
Currently HPD_PORT_A is used as an alias for HPD_NONE to mean that the
given port doesn't support long/short HPD pulse detection. SDVO and CRT
ports are like this and for these ports
On 21.07.2015 16:03, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 02:48:21PM +0200, Krzysztof Kolasa wrote:
On 21.07.2015 11:43, Chris Wilson wrote:
On Tue, Jul 21, 2015 at 11:07:20AM +0200, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 10:58:50AM +0200, Krzysztof Kolasa wrote:
On 21.07.2015
On Tue, 2015-07-21 at 13:50 +0530, Sivakumar Thulasimani wrote:
On 7/21/2015 3:13 AM, Imre Deak wrote:
These functions are quite similar, so combine them with the use of a new
argument for a function that detects long pulses. This will be also
needed by an upcoming patch adding support
2015-07-21 14:43 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Tue, Jul 21, 2015 at 02:08:23PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
A helpful function for when you want to read a whole debugfs file to a
string and don't want to worry about opening and closing
Hi Nabendu,
PFA. I came across this patch from Damien Lespiau which prevents the topmost
plane from being exposed to user space.
Once this patch is merged, the following correction in i-g-t won't be required
as it takes care of exposing only four planes when drmModeGetPlaneResources is
Currently HPD_PORT_A is used as an alias for HPD_NONE to mean that the
given port doesn't support long/short HPD pulse detection. SDVO and CRT
ports are like this and for these ports we only want to know whether an
hot plug event was detected on the corresponding pin. Since at least on
BXT we need
These functions are quite similar, so combine them with the use of a new
argument for a function that detects long pulses. This will be also
needed by an upcoming patch adding support for BXT long pulse detection.
No functional change.
v2:
- rebase on top -nightly (Daniel)
Signed-off-by: Imre
On Tue, Jul 21, 2015 at 04:40:08PM +0530, Malladi, Kausal wrote:
On Tuesday 21 July 2015 05:33 AM, Matt Roper wrote:
On Wed, Jul 15, 2015 at 06:39:35PM +0530, Kausal Malladi wrote:
...
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
On Fri, Jul 17, 2015 at 03:31:17PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
There is a construct in the linux kernel called 'struct fence' that is
intended
to keep track of work that is executed on hardware. I.e. it solves the basic
problem that
On Tue, Jul 21, 2015 at 12:43:48PM +0530, Shobhit Kumar wrote:
On Fri, Jul 10, 2015 at 6:36 PM, Shobhit Kumar ku...@shobhit.info wrote:
On Mon, Jun 29, 2015 at 3:48 AM, Paul Gortmaker
paul.gortma...@windriver.com wrote:
[Re: [Intel-gfx] [v3 0/7] Crystalcove (CRC) PMIC based panel and pwm
On Tue, Jul 21, 2015 at 12:11:18PM +0530, Sudip Mukherjee wrote:
On Mon, Jul 20, 2015 at 05:33:50PM +0200, Daniel Vetter wrote:
On Mon, Jul 20, 2015 at 08:36:01PM +0530, Sudip Mukherjee wrote:
While creating the debugfs file we are setting the inode-i_private to
dev. That same dev is
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp_mst.c | 44 -
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index
On Fri, Jul 17, 2015 at 05:38:05PM -0700, O'Rourke, Tom wrote:
On Thu, Jul 09, 2015 at 07:29:04PM +0100, Dave Gordon wrote:
intel_guc_fwif.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC. These MUST
be kept in sync with the definitions
On Fri, Jul 17, 2015 at 03:31:21PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should
be
set on demand rather than polled. That is, there should not be a need for a
'signaled'
On Mon, Jul 20, 2015 at 10:46:11AM +0100, Arun Siluvery wrote:
This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context
initialization.
The pooled mode is global, once enabled it has to stay the same
Op 21-07-15 om 08:51 schreef Daniel Vetter:
On Mon, Jul 20, 2015 at 04:52:11PM +0200, Maarten Lankhorst wrote:
Op 16-07-15 om 14:57 schreef Maarten Lankhorst:
Move it from intel_crtc_atomic_commit to prepare_plane_fb.
Waiting is done before committing, otherwise it's too late
to undo the
On 7/21/2015 3:13 AM, Imre Deak wrote:
Currently HPD_PORT_A is used as an alias for HPD_NONE to mean that the
given port doesn't support long/short HPD pulse detection. SDVO and CRT
ports are like this and for these ports we only want to know whether an
hot plug event was detected on the
On Mon, Jul 20, 2015 at 05:33:50PM +0200, Daniel Vetter wrote:
On Mon, Jul 20, 2015 at 08:36:01PM +0530, Sudip Mukherjee wrote:
While creating the debugfs file we are setting the inode-i_private to
dev. That same dev is passed to these functions as private of struct
seq_file via
On Mon, Jul 20, 2015 at 04:52:11PM +0200, Maarten Lankhorst wrote:
Op 16-07-15 om 14:57 schreef Maarten Lankhorst:
Move it from intel_crtc_atomic_commit to prepare_plane_fb.
Waiting is done before committing, otherwise it's too late
to undo the changes.
Signed-off-by: Maarten Lankhorst
On Tue, Jul 21, 2015 at 08:48:05AM +0200, Daniel Vetter wrote:
On Thu, Jul 16, 2015 at 2:04 PM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Thu, Jul 16, 2015 at 12:24:19PM +0100, Chris Wilson wrote:
On Thu, Jul 16, 2015 at 01:19:09PM +0200, Michał Winiarski wrote:
When reading the
On Fri, Jul 17, 2015 at 05:08:51PM +0100, Arun Siluvery wrote:
From: Mika Kuoppala mika.kuopp...@linux.intel.com
Kunmap the renderstate page on error path.
Reviewed-by: Arun Siluvery arun.siluv...@linux.intel.com
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Queued for -next,
On Fri, Jul 17, 2015 at 03:42:34PM +, Morton, Derek J wrote:
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Friday, July 17, 2015 3:18 PM
To: Morton, Derek J
Cc: Intel Graphics Development
Subject: Re: [PATCH i-g-t v3] Android.mk: Disable tools
On Fri, Jul 10, 2015 at 6:36 PM, Shobhit Kumar ku...@shobhit.info wrote:
On Mon, Jun 29, 2015 at 3:48 AM, Paul Gortmaker
paul.gortma...@windriver.com wrote:
[Re: [Intel-gfx] [v3 0/7] Crystalcove (CRC) PMIC based panel and pwm
control] On 26/06/2015 (Fri 20:47) Ville Syrjälä wrote:
On Fri,
On Fri, Jul 17, 2015 at 03:33:12PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
A later patch in this series re-organises the batch buffer submission
code. Part of that is to reduce the scope of a pm_get/put pair.
Specifically, they previously wrapped
tree: git://anongit.freedesktop.org/drm-intel topic/drm-misc
head: 1d7828f8505146eff1af8f2f973310e9df1f3b53
commit: 1d7828f8505146eff1af8f2f973310e9df1f3b53 [18/18] drm: Make the
connector dpms callback return a value, v2.
config: x86_64-rhel (attached as .config)
reproduce:
git checkout
On Fri, Jul 17, 2015 at 03:33:36PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
There is a sync framework to allow work for multiple independent
systems to be synchronised with each other but without stalling
the CPU whether in the application or the
For the patch 3, the commit message can be changed to only long pulse
detection instead of long/short because you are not adding support
for short pulse detection.
Otherwise, this series looks good to me.
Reviewed-by: Sonika Jindal sonika.jin...@intel.com
On 7/21/2015 3:13 AM, Imre Deak
On Thu, Jul 16, 2015 at 2:04 PM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Thu, Jul 16, 2015 at 12:24:19PM +0100, Chris Wilson wrote:
On Thu, Jul 16, 2015 at 01:19:09PM +0200, Michał Winiarski wrote:
When reading the timestamp register with single 64b read, we are observing
invalid
On Sun, Jul 19, 2015 at 08:07:19PM +0200, Krzysztof Kolasa wrote:
Photo laptop screen:
https://drive.google.com/open?id=0B1LAMAFWTdeweTJycjFoZkNSVmM
bisected first bad commit: [0875546c5318c85c13d07014af5350e9000bc9e9]
drm/i915: Fix up the vma aliasing ppgtt binding
Are you sure about
On Fri, Jul 17, 2015 at 03:33:13PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler decouples the submission of batch buffers to the driver with
their
submission to the hardware. This basically means splitting the execbuffer()
function in
On 7/21/2015 3:13 AM, Imre Deak wrote:
These functions are quite similar, so combine them with the use of a new
argument for a function that detects long pulses. This will be also
needed by an upcoming patch adding support for BXT long pulse detection.
No functional change.
Signed-off-by:
On Thu, Jul 16, 2015 at 02:57:47PM +0200, Maarten Lankhorst wrote:
-EDEADLK has special meaning in atomic, but get_fence may call
i915_find_fence_reg which can return -EDEADLK.
This has special meaning in the atomic world, so convert the error
to -EBUSY for this case.
Signed-off-by:
The extra check for connector_type is not required as we are already
checking for connector_type != DRM_MODE_CONNECTOR_DisplayPort.
The check was added by commit eb3394faeb97 (drm/i915: Add debugfs test
control files for Displayport compliance testing)
Signed-off-by: Sudip Mukherjee
While creating the debugfs file we are setting the inode-i_private to
dev. That same dev is passed to these functions as private of struct
seq_file via single_open(). Moreover single_open is setting
file-private_data-private to dev.
So at this point it can never be NULL.
This check was added by
This is probably slightly wrong, but better than not sending events.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 82da2c54bd2e..10bb66ec493a 100644
---
On Tuesday 21 July 2015 05:33 AM, Matt Roper wrote:
On Wed, Jul 15, 2015 at 06:39:34PM +0530, Kausal Malladi wrote:
This patch adds set_property handler for Gamma color correction and
enhancement capability at Pipe level on CHV/BSW platform. The set
function just attaches the Gamma blob to CRTC
On Tuesday 21 July 2015 05:33 AM, Matt Roper wrote:
On Wed, Jul 15, 2015 at 06:39:35PM +0530, Kausal Malladi wrote:
CHV/BSW platform supports various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Adds the core
On Thu, Jul 16, 2015 at 02:57:51PM +0200, Maarten Lankhorst wrote:
Move it from intel_crtc_atomic_commit to prepare_plane_fb.
Waiting is done before committing, otherwise it's too late
to undo the changes.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
In intel it's useful to keep track of some state changes with old
crtc state vs new state, for example to disable initial planes or
when a modeset's prevented during fastboot.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
This continues the previous work to make fastboot more atomic.
Looking at the changes in pipe_config_compare I guess it was broken for
everyone, but with some splitting it was easy to revive it and make
it less scary.
Maarten Lankhorst (6):
drm/atomic: add connectors_changed to separate it from
This might not have been set during boot, and when we preserve
the initial mode this can result in a black screen.
Cc: Daniel Stone dani...@collabora.com
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3
The initial state is read out correctly and the state is atomic,
so it's safe to preserve the fb without any hacks if it's suitable.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
This is done as a separate commit, to make it easier to revert
when things break.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_params.c | 5 -
drivers/gpu/drm/i915/intel_display.c | 3 +--
3
This can be a separate case from mode_changed, when connectors stay the
same but only the mode is different. Drivers may choose to implement specific
optimizations to prevent a full modeset for this case.
Changes since v1:
- Update kerneldocs slightly.
Cc: dri-de...@lists.freedesktop.org
Instead of doing a hack during primary plane commit the state
is updated during atomic evasion. It handles differences in
pipe size and the panel fitter.
This is continuing on top of Daniel's work to make faster
modesets atomic, and not yet enabled by default.
Signed-off-by: Maarten Lankhorst
On Thu, Jul 16, 2015 at 02:57:50PM +0200, Maarten Lankhorst wrote:
Now that intel_display_suspend is atomic it's safe to remove
wait_for_pending_flips from intel_crtc_disable_noatomic. It
will only be used during hw load or resume, in which case there
will be no pending flips anyway.
A
userptr requires mmu-notifier for full unprivileged support. Most
systems have mmu-notifier support already enabled as a requirement for
virtualisation support, but we should make the option for i915 to take
advantage of mmu-notifiers explicit (and enable by default so that
regular userspace can
tree: git://anongit.freedesktop.org/drm-intel topic/crc-pmic
head: b029e66fa8e39ba10dcc47b114be8da8b082493b
commit: 61dd2ca2d44e493b050adbbb75bc50db11c367dd [2/7] mfd:
intel_soc_pmic_core: Add lookup table for Panel Control as GPIO signal
config: x86_64-randconfig-i0-201529 (attached as
Op 21-07-15 om 14:05 schreef Maarten Lankhorst:
This is probably slightly wrong, but better than not sending events.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
On Tue, Jul 21, 2015 at 02:48:31PM +0530, Sonika Jindal wrote:
This is to get PSR support for bxt.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Maybe with a drm/i915/bxt prefix:
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
--
Damien
---
drivers/gpu/drm/i915/i915_drv.h |
On Tue, Jul 21, 2015 at 10:31:19AM +0100, Damien Lespiau wrote:
On Tue, Jul 21, 2015 at 02:48:31PM +0530, Sonika Jindal wrote:
This is to get PSR support for bxt.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Maybe with a drm/i915/bxt prefix:
Reviewed-by: Damien Lespiau
On Tue, Jul 21, 2015 at 10:58:50AM +0200, Krzysztof Kolasa wrote:
On 21.07.2015 10:41, Daniel Vetter wrote:
I meant whether you can reset the bad commit and it's immediate parent
extensively to make sure the bisect is really correct. gpu's occasionally
take a while to hang themselves, so
On Fri, Jul 17, 2015 at 03:33:28PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler can cause batch buffers, and hence requests, to be submitted to
the ring out of order and asynchronously to their submission to the driver.
Thus
at the
On Fri, Jul 17, 2015 at 03:33:16PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Initial creation of scheduler source files. Note that this patch implements
most
of the scheduler functionality but does not hook it in to the driver yet. It
also leaves
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Tuesday, July 21, 2015 7:54 AM
To: Morton, Derek J
Cc: Intel Graphics
On Tue, Jul 21, 2015 at 11:07:20AM +0200, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 10:58:50AM +0200, Krzysztof Kolasa wrote:
On 21.07.2015 10:41, Daniel Vetter wrote:
I meant whether you can reset the bad commit and it's immediate parent
extensively to make sure the bisect is really
On Fri, Jul 17, 2015 at 03:33:33PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
When the seqno wraps around zero, the entire GPU is forced to be idle
for some reason (possibly only to work around issues with hardware
semaphores but no-one seems too
On 21.07.2015 10:41, Daniel Vetter wrote:
I meant whether you can reset the bad commit and it's immediate parent
extensively to make sure the bisect is really correct. gpu's occasionally
take a while to hang themselves, so could be that the bisect was
mislead somewhere.
Again I will bisect,
On Tue, Jul 21, 2015 at 09:56:15AM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp_mst.c | 44
-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git
On Tue, Jul 21, 2015 at 09:57:25AM +0200, David Henningsson wrote:
On HDMI hotplug events, notify the audio driver. This will enable
the audio driver to get the information at all times (even when
audio is in different powersave states), and also without reading
it from the hardware.
Op 21-07-15 om 11:09 schreef Daniel Vetter:
On Tue, Jul 21, 2015 at 09:56:15AM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp_mst.c | 44
-
1 file changed, 43
This is to get PSR support for bxt.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 718170c..54d2729 100644
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, July 21, 2015 7:54 AM
To: Morton, Derek J
Cc: Wood, Thomas; Intel Graphics Development
Subject: Re: [Intel-gfx] [PATCH i-g-t v3] Android.mk: Disable tools that do
not build
On Tue, Jul 21, 2015 at 10:45:45AM +0100, Chris Wilson wrote:
On Tue, Jul 21, 2015 at 08:49:31AM +0200, Daniel Vetter wrote:
On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
Since the hardware sometimes
On Tue, Jul 21, 2015 at 08:49:31AM +0200, Daniel Vetter wrote:
On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register
On Tue, Jul 21, 2015 at 05:36:45PM +0530, Sudip Mukherjee wrote:
While creating the debugfs file we are setting the inode-i_private to
dev. That same dev is passed to these functions as private of struct
seq_file via single_open(). Moreover single_open is setting
file-private_data-private to
On Tue, Jul 21, 2015 at 03:51:40PM +0200, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 05:36:45PM +0530, Sudip Mukherjee wrote:
While creating the debugfs file we are setting the inode-i_private to
dev. That same dev is passed to these functions as private of struct
seq_file via
When submitting semaphores in execlist mode the hang checker crashes in this
function because it is only runnable in ring submission mode. The reason this
is of particular interest to the TDR patch series is because we use semaphores
as a mean to induce hangs during testing (which is the
Makes i915_gem_reset_ring_status() public for use from engine reset path in
order to replicate the same behavior as in full GPU reset but for a single
engine.
Signed-off-by: Tomas Elf tomas@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
---
Op 21-07-15 om 15:31 schreef Chris Wilson:
On Tue, Jul 21, 2015 at 02:33:33PM +0200, Maarten Lankhorst wrote:
+ if (plane-type == DRM_PLANE_TYPE_PRIMARY old_obj) {
Would feel safer is we just asked if the CRTC had pending flips
irrespective of old_obj. Do you plan on moving the pending flips
This change introduces support for TDR-style per-engine reset as a initial,
less intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. Initially we're only
supporting gen8 but adding support for gen7 is straight-forward since
This patch series introduces the following features:
* Feature 1: TDR (Timeout Detection and Recovery) for gen8 execlist mode.
TDR is an umbrella term for anything that goes into detecting and recovering
from GPU hangs and is a term more widely used outside of the upstream driver.
This feature
i915_gem_wedge now returns a positive result in three different cases:
1. Legacy: A hang has been detected and full GPU reset has been promoted.
2. Per-engine recovery:
a. A single engine reference can be passed to the function, in which
case only that engine will be checked. If
There used to be a work queue separating the error handler from the hang
recovery path, which was removed a while back in this commit:
commit b8d24a06568368076ebd5a858a011699a97bfa42
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Wed Jan 28 17:03:14 2015 +0200
Watchdog timeout (or media engine reset as it is sometimes called, even
though the render engine is also supported) is a feature that allows userland
applications to enable hang detection on individual batch buffers. The
detection mechanism itself is mostly bound to the hardware and the only thing
This is a partial port of the following patch from John Harrison's GPU
scheduler patch series: (patch sent to Intel-GFX with the subject line
[Intel-gfx] [RFC 19/39] drm/i915: Added scheduler support to __wait_request()
calls on Fri 17 July 2015)
Author: John Harrison
1. The i915_wedged_set() function allows us to schedule three forms of hang
recovery:
a) Legacy hang recovery: By passing e.g. -1 we trigger the legacy full
GPU reset recovery path.
b) Single engine hang recovery: By passing an engine ID in the interval
of [0,
On Tue, Jul 21, 2015 at 02:48:21PM +0200, Krzysztof Kolasa wrote:
On 21.07.2015 11:43, Chris Wilson wrote:
On Tue, Jul 21, 2015 at 11:07:20AM +0200, Daniel Vetter wrote:
On Tue, Jul 21, 2015 at 10:58:50AM +0200, Krzysztof Kolasa wrote:
On 21.07.2015 10:41, Daniel Vetter wrote:
I meant
A recurring issue during long-duration operations testing of concurrent
rendering tasks with intermittent hangs is that context completion interrupts
following engine resets are sometimes lost. This becomes a real problem since
the hardware might have completed a previously hung context following
Use is_locked parameter in __i915_wait_request() to determine if a thread
should be forced to back off and retry or if it can continue sleeping. Don't
return -EIO from __i915_wait_request since that is bad for the upper layers,
only -EAGAIN to signify reset in progress.
Also, use is_locked in
Defined trace points and sprinkled the usage of these throughout the
TDR/watchdog implementation.
The following trace points are supported:
1. trace_i915_tdr_gpu_recovery:
Called at the onset of the full GPU reset recovery path.
2. trace_i915_tdr_engine_recovery:
These new TDR-specific metrics have previously been added to
i915_hangcheck_info() in debugfs. During design review Chris Wilson asked for
these metrics to be added to the error state as well.
Signed-off-by: Tomas Elf tomas@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mika Kuoppala
On Tue, Jul 21, 2015 at 07:22:37PM +0800, kbuild test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel topic/crc-pmic
head: b029e66fa8e39ba10dcc47b114be8da8b082493b
commit: 61dd2ca2d44e493b050adbbb75bc50db11c367dd [2/7] mfd:
intel_soc_pmic_core: Add lookup table for Panel
-EDEADLK has special meaning in atomic, but get_fence may call
i915_find_fence_reg which can return -EDEADLK.
This has special meaning in the atomic world, so convert the error
to -EBUSY for this case.
Changes since v1:
- Add comment in the code.
Signed-off-by: Maarten Lankhorst
On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two
This lets interested codec(s) be notified of HDMI hotplug
events sent from the i915 driver.
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
include/sound/hdaudio.h |4
sound/hda/hdac_i915.c | 24
2 files changed, 28 insertions(+)
diff
This patch set aims to resolve three problems:
* The first - and most serious one - is that the audio driver is not woken up
properly when in power save modes, especially not when the HDA controller is
in D3. By having the i915 driver call directly into the hda driver, the HDA
driver is
On HDMI hotplug events, notify the audio driver. This will enable
the audio driver to get the information at all times (even when
audio is in different powersave states), and also without reading
it from the hardware.
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
As a first cautious step, we're not going to trust the information
coming directly from the i915 driver, we're just going to use
the fact that there was an event to wakeup the codec and ask for
its status.
This fixes the issue with lost unsol events in power save mode,
the codec and controller
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