On Thu, Nov 17, 2016 at 02:51:28PM +0800, Zhenyu Wang wrote:
>
> On 2016.11.16 15:50:27 +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Please pull current GVT-g device model fixes.
> >
>
> Sorry, pls hold on this as found a possible conflict, as this is
> supposed to be last pull before 4.10 mer
On Thu, Nov 17, 2016 at 01:53:31AM +, Pandiyan, Dhinakaran wrote:
> On Sun, 2016-11-13 at 11:39 +0100, Daniel Vetter wrote:
> > On Fri, Nov 11, 2016 at 10:21:39PM +0100, Daniel Vetter wrote:
> > > On Mon, Nov 07, 2016 at 04:27:30PM -0800, Dhinakaran Pandiyan wrote:
> > > > Hotplugging a monitor
Since the submit/execute split in commit d55ac5bf97c6 ("drm/i915: Defer
transfer onto execution timeline to actual hw submission") the
global seqno advance was deferred until the submit_request callback.
After wedging the GPU, we were installing a nop_submit_request handler
(to avoid waking up the
On Fri, Oct 28, 2016 at 10:10:50AM +0200, Daniel Vetter wrote:
> Looking at the ioctl permission checks I noticed that it's impossible
> to import gem buffers into a control nodes, and fd2handle/handle2fd
> also don't work, so no joy with dma-bufs.
>
> The only way to do anything with a control no
On 2016.11.16 15:50:27 +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Please pull current GVT-g device model fixes.
>
Sorry, pls hold on this as found a possible conflict, as this is
supposed to be last pull before 4.10 merge window, like to include
the fix for that, will send update later.
> Thanks.
>
On 2016.11.16 22:05:04 +0800, Min He wrote:
> For a singl_port_submission context, it can only be submitted to port 0,
> and there shouldn't be any other context in port 1 at the same time. This
> is required by GVT-g context to have an opportunity to save/restore some
> non-hw context render regis
Hi all,
Could anyone help review the patches? Thanks.
Regards,
Libin
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Yang, Libin
> Sent: Monday, November 14, 2016 1:41 PM
> To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.inte
On Sun, 2016-11-13 at 11:39 +0100, Daniel Vetter wrote:
> On Fri, Nov 11, 2016 at 10:21:39PM +0100, Daniel Vetter wrote:
> > On Mon, Nov 07, 2016 at 04:27:30PM -0800, Dhinakaran Pandiyan wrote:
> > > Hotplugging a monitor in DP MST configuration triggers short pulses.
> > > Although the short pulse
On Fri, 2016-11-11 at 23:05 +0200, Ville Syrjälä wrote:
> On Fri, Nov 11, 2016 at 08:43:53PM +, Pandiyan, Dhinakaran wrote:
> > On Tue, 2016-11-08 at 13:04 +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 07, 2016 at 04:27:30PM -0800, Dhinakaran Pandiyan wrote:
> > > > Hotplugging a monitor in DP
Hi,
On Wed, Nov 16, 2016 at 09:14:28PM +0100, Paolo Stivanin wrote:
> Hello all,
> @Jani Nikula: I just tried the patches you linked and they work
> *perfectly* on my notebook (Clevo P640RE). I also tried to suspend and
> resume the laptop and it works like a charm!
> I applied the patches against
On 2016.11.16 12:13:59 +0200, Jani Nikula wrote:
> We no longer cater for pre-production revisions of Skylake.
>
> Fixes: d4362225e8cb ("drm/i915/gvt: update misc ctl regs base on stepping
> info")
> Cc: Ping Gao
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc:
> Signed-off-by: Jani Nikula
> ---
appl
>-Original Message-
>From: Mcgee, Jeff
>Sent: Tuesday, November 15, 2016 2:46 PM
>To: Srivatsa, Anusha
>Cc: Tvrtko Ursulin ; Ursulin, Tvrtko
>; intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/GuC: Combine the two kernel
>parameter into one
>
>O
On Wed, Nov 16, 2016 at 05:52:43PM -0200, Paulo Zanoni wrote:
> Em Qua, 2016-11-16 às 19:07 +, Chris Wilson escreveu:
> > I tried to avoid having to track the write for every VMA by only
> > tracking writes to the ggtt. However, for the purposes of frontbuffer
> > tracking this is insufficient
On Wed, Nov 16, 2016 at 07:25:17PM +, Matthew Auld wrote:
> We already have an i915_address_space_init, so for symmetry we should
> also have a _fini, plus we already open code it twice. This then also
> fixes a bug where we leak the timeline for the ggtt vm.
>
> Cc: Chris Wilson
> Signed-off
On Wed, Nov 16, 2016 at 07:32:49PM +, Matthew Auld wrote:
> We need to clean up the global_timeline in i915_gem_load_cleanup.
>
> Cc: Chris Wilson
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/dr
== Series Details ==
Series: drm/i915: don't leak global_timeline
URL : https://patchwork.freedesktop.org/series/15439/
State : warning
== Summary ==
Series 15439v1 drm/i915: don't leak global_timeline
https://patchwork.freedesktop.org/api/1.0/series/15439/revisions/1/mbox/
Test drv_module_re
== Series Details ==
Series: drm/i915: add i915_address_space_fini
URL : https://patchwork.freedesktop.org/series/15437/
State : warning
== Summary ==
Series 15437v1 drm/i915: add i915_address_space_fini
https://patchwork.freedesktop.org/api/1.0/series/15437/revisions/1/mbox/
Test drv_module_
Hello all,
@Jani Nikula: I just tried the patches you linked and they work
*perfectly* on my notebook (Clevo P640RE). I also tried to suspend and
resume the laptop and it works like a charm!
I applied the patches against the Linux kernel v4.8.8 taken from
upstream.
Thanks again :)
Cheers,
Paolo
Em Qua, 2016-11-16 às 19:07 +, Chris Wilson escreveu:
> I tried to avoid having to track the write for every VMA by only
> tracking writes to the ggtt. However, for the purposes of frontbuffer
> tracking this is insufficient as we need to invalidate around writes
> not
> just to the the ggtt bu
== Series Details ==
Series: drm/i915: Move frontbuffer CS write tracking from ggtt vma to object
URL : https://patchwork.freedesktop.org/series/15435/
State : success
== Summary ==
Series 15435v1 drm/i915: Move frontbuffer CS write tracking from ggtt vma to
object
https://patchwork.freedeskt
We need to clean up the global_timeline in i915_gem_load_cleanup.
Cc: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3fb5e66..c440e72 10064
We already have an i915_address_space_init, so for symmetry we should
also have a _fini, plus we already open code it twice. This then also
fixes a bug where we leak the timeline for the ggtt vm.
Cc: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +
I tried to avoid having to track the write for every VMA by only
tracking writes to the ggtt. However, for the purposes of frontbuffer
tracking this is insufficient as we need to invalidate around writes not
just to the the ggtt but all aliased ppgtt views of the framebuffer. By
moving the critical
Jani/Ville could you please review this patch?
This has been ACKed by DRM and is good from DRM point fo view.
But I need r-b from either of you for this to get merged.
Regards
Manasi
On Mon, Nov 14, 2016 at 07:13:23PM -0800, Manasi Navare wrote:
> If link training at a link rate optimal for a par
Jani/Ville , could you please review this patch?
Jani, you had mentioned it looks good and we were only waiting for
ACKs from DRM, so now from the DRM point of view all these patches
are ACKed and it looks good.
But I need r-b for these two i915 specific patches to get them merged.
Regards
Manasi
On Wed, Nov 16, 2016 at 05:20:34PM +0200, Mika Kuoppala wrote:
> Bannable property, banned status, guilty and active counts are
> properties of i915_gem_context. Make them so.
>
> v2: rebase
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
Been hesistating since the substruct might have hel
On Wed, Nov 16, 2016 at 05:20:33PM +0200, Mika Kuoppala wrote:
> If we have a bad client submitting unfavourably across different
> contexts, creating new ones, the per context scoring of badness
> doesn't remove the root cause, the offending client.
> To counter, keep track of per client context b
Hi Dave,
Another pile of misc:
- Explicit fencing for atomic! Big thanks to Gustavo, Sean, Rob 3x, Brian
and anyone else I've forgotten to make this happen.
- roll out fbdev helper ops to drivers (Stefan Christ)
- last bits of drm_crtc split-up&kerneldoc
- some drm_irq.c crtc functions cleanup
-
On Wed, Nov 16, 2016 at 05:20:31PM +0200, Mika Kuoppala wrote:
> As hangcheck score was removed, the active decay of score
> was removed also. This removed feature for hangcheck to detect
> if the gpu client was accidentally or maliciously causing intermittent
> hangs. Reinstate the scoring as a pe
On Wed, Nov 16, 2016 at 05:20:30PM +0200, Mika Kuoppala wrote:
> - ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
> - if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
> + ring_hung = engine->hangcheck.stall;
> + if (engine->hangcheck.seqno != intel_e
== Series Details ==
Series: drm/i915/execlists: Use a local lock for dfs_link access
URL : https://patchwork.freedesktop.org/series/15425/
State : warning
== Summary ==
Series 15425v1 drm/i915/execlists: Use a local lock for dfs_link access
https://patchwork.freedesktop.org/api/1.0/series/154
== Series Details ==
Series: series starting with [1/6] drm/i915: Split up hangcheck phases
URL : https://patchwork.freedesktop.org/series/15423/
State : warning
== Summary ==
Series 15423v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/15423/revisions/1/mbox/
T
On Wed, Nov 16, 2016 at 03:54:23PM +, Tvrtko Ursulin wrote:
>
> On 16/11/2016 15:27, Chris Wilson wrote:
> >Avoid requiring struct_mutex for exclusive access to the temporary
> >dfs_link inside the i915_dependency as not all callers may want to touch
> >struct_mutex. So rather than force them
== Series Details ==
Series: series starting with [1/2] HAX drm/i915: Enable guc submission (rev3)
URL : https://patchwork.freedesktop.org/series/15407/
State : failure
== Summary ==
Series 15407v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/15407/revisions/3/m
On 16/11/2016 15:27, Chris Wilson wrote:
Avoid requiring struct_mutex for exclusive access to the temporary
dfs_link inside the i915_dependency as not all callers may want to touch
struct_mutex. So rather than force them to take a highly contended
lock, introduce a local lock for the execlists s
Bannable property, banned status, guilty and active counts are
properties of i915_gem_context. Make them so.
v2: rebase
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h| 31 ++
drivers/gpu/drm/i915/i915_gem.c|
If we have a bad client submitting unfavourably across different
contexts, creating new ones, the per context scoring of badness
doesn't remove the root cause, the offending client.
To counter, keep track of per client context bans. Deny access if
client is responsible for more than 3 context bans
Hangcheck state accumulation has gained more steps
along the years, like head movement and more recently the
subunit inactivity check. As the subunit sampling is only
done if the previous state check showed inactivity, we
have added more stages (and time) to reach a hang verdict.
Asymmetric engine
Now when driver has per context scoring of 'hanging badness'
and also subsequent hangs during short windows are allowed,
if there is progress made in between, it does not make sense
to expose a ban timing window as a context parameter anymore.
Let the scoring be the sole indicator for ban policy a
Avoid requiring struct_mutex for exclusive access to the temporary
dfs_link inside the i915_dependency as not all callers may want to touch
struct_mutex. So rather than force them to take a highly contended
lock, introduce a local lock for the execlists schedule operation.
Reported-by: David Weine
As hangcheck score was removed, the active decay of score
was removed also. This removed feature for hangcheck to detect
if the gpu client was accidentally or maliciously causing intermittent
hangs. Reinstate the scoring as a per context property, so that if
one context starts to act unfavourably,
In order to simplify hangcheck state keeping, split hangcheck
per engine loop in three phases: state load, action, state save.
Add few more hangcheck actions to separate between seqno, head
and subunit movements. This helps to gather all the hangcheck
actions under a single switch umbrella.
Cc: C
== Series Details ==
Series: drm/i915: fix the dequeue logic for single_port_submission context
(rev3)
URL : https://patchwork.freedesktop.org/series/15391/
State : success
== Summary ==
Series 15391v3 drm/i915: fix the dequeue logic for single_port_submission
context
https://patchwork.freed
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However
On Wed, Nov 16, 2016 at 03:41:53PM +0100, Daniel Vetter wrote:
> On Wed, Nov 16, 2016 at 08:58:30AM +, Chris Wilson wrote:
> > Soft-pinning depends upon being able to check for availabilty of an
> > interval and evict overlapping object from a drm_mm range manager very
> > quickly. Currently it
== Series Details ==
Series: series starting with [1/2] HAX drm/i915: Enable guc submission (rev2)
URL : https://patchwork.freedesktop.org/series/15407/
State : failure
== Summary ==
Series 15407v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/15407/revisions/2/m
On Wed, Nov 16, 2016 at 01:54:45PM +, He, Min wrote:
>
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > Sent: Wednesday, November 16, 2016 9:48 PM
> > To: He, Min
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH v2] drm/i91
On Wed, Nov 16, 2016 at 08:58:30AM +, Chris Wilson wrote:
> Soft-pinning depends upon being able to check for availabilty of an
> interval and evict overlapping object from a drm_mm range manager very
> quickly. Currently it uses a linear list, and so performance is dire and
> not suitable as a
On Mon, 07 Nov 2016, Rainer Koenig wrote:
> this is sad and also bad news. Means that actually we don't have any
> driver which makes the brightness keys on the Fujitsu LIFEBOOK E7x6
> series work.
I hope we can make this work [1].
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/15403/
For a singl_port_submission context, it can only be submitted to port 0,
and there shouldn't be any other context in port 1 at the same time. This
is required by GVT-g context to have an opportunity to save/restore some
non-hw context render registers.
This patch is to implement the correct logic i
On Wed, Nov 16, 2016 at 04:07:33PM +0200, Abdiel Janulgue wrote:
>
>
> On 16.11.2016 15:56, Chris Wilson wrote:
> > On Wed, Nov 16, 2016 at 11:18:01PM +0200, Abdiel Janulgue wrote:
> >> A lot of igt testcases need some GPU workload to make sure a race
> >> window is big enough. Unfortunately havi
== Series Details ==
Series: Remove __I915__ magic macro (rev2)
URL : https://patchwork.freedesktop.org/series/15393/
State : warning
== Summary ==
Series 15393v2 Remove __I915__ magic macro
https://patchwork.freedesktop.org/api/1.0/series/15393/revisions/2/mbox/
Test kms_force_connector_basi
On Wed, Nov 16, 2016 at 04:08:30PM +0200, Jani Nikula wrote:
> On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
> > On 16 November 2016 at 13:58, Jani Nikula
> > wrote:
> >> On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
> >>> On 15 November 2016 at 09:27, Jani Nikula
> >>> wrote:
> On Tue, 15 Nov 201
On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
> On 16 November 2016 at 13:58, Jani Nikula wrote:
>> On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
>>> On 15 November 2016 at 09:27, Jani Nikula
>>> wrote:
On Tue, 15 Nov 2016, David Weinehall wrote:
> On Mon, Nov 14, 2016 at 12:44:25PM +0200, Jan
On 16.11.2016 15:56, Chris Wilson wrote:
> On Wed, Nov 16, 2016 at 11:18:01PM +0200, Abdiel Janulgue wrote:
>> A lot of igt testcases need some GPU workload to make sure a race
>> window is big enough. Unfortunately having a fixed amount of
>> workload leads to spurious test failures or overtly l
On 16 November 2016 at 13:58, Jani Nikula wrote:
> On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
>> On 15 November 2016 at 09:27, Jani Nikula
>> wrote:
>>> On Tue, 15 Nov 2016, David Weinehall wrote:
On Mon, Nov 14, 2016 at 12:44:25PM +0200, Jani Nikula wrote:
> On Thu, 06 Oct 2016, Tomeu
On Wed, Nov 16, 2016 at 11:18:01PM +0200, Abdiel Janulgue wrote:
> A lot of igt testcases need some GPU workload to make sure a race
> window is big enough. Unfortunately having a fixed amount of
> workload leads to spurious test failures or overtly long runtimes
> on some fast/slow platforms. This
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Wednesday, November 16, 2016 9:48 PM
> To: He, Min
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: fix the dequeue logic for
> single_port_submission context
>
> On W
On Wed, Nov 16, 2016 at 09:32:56PM +0800, Min He wrote:
> For a singl_port_submission context, it can only be submitted to port 0,
> and there shouldn't be any other context in port 1 at the same time. This
> is required by GVT-g context to have an opportunity to save/restore some
> non-hw context
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However
On Wed, Nov 16, 2016 at 01:24:26PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] HAX drm/i915: Enable guc submission
> URL : https://patchwork.freedesktop.org/series/15407/
> State : failure
>
> == Summary ==
>
> Series 15407v1 Series without cover lette
For a singl_port_submission context, it can only be submitted to port 0,
and there shouldn't be any other context in port 1 at the same time. This
is required by GVT-g context to have an opportunity to save/restore some
non-hw context render registers.
This patch is to implement the correct logic i
== Series Details ==
Series: series starting with [1/2] HAX drm/i915: Enable guc submission
URL : https://patchwork.freedesktop.org/series/15407/
State : failure
== Summary ==
Series 15407v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/15407/revisions/1/mbox/
T
v7: Adapt to api rename
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/kms_busy.c | 75 +++-
1 file changed, 4 insertions(+), 71 deletions(-)
diff --git a/tests/kms_busy.c b/tests/kms_busy.c
index b555f99..680aeb
v7: Reuse NSEC_PER_SEC defines
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/kms_flip.c | 188 ++-
1 file changed, 4 insertions(+), 184 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 2a9fe2e
v7: Adapt to api rename
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Abdiel Janulgue
---
tests/gem_wait.c | 129 +++
1 file changed, 7 insertions(+), 122 deletions(-)
diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index b4127de..d2920
A lot of igt testcases need some GPU workload to make sure a race
window is big enough. Unfortunately having a fixed amount of
workload leads to spurious test failures or overtly long runtimes
on some fast/slow platforms. This library contains functionality
to submit GPU workloads that should consu
More and more test-cases are using this.
Signed-off-by: Abdiel Janulgue
---
lib/igt_aux.c | 11 ---
lib/igt_aux.h | 10 ++
lib/igt_core.c | 3 ---
tests/drv_hangman.c | 1 -
4 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/lib/igt_aux.c b/lib/ig
* Fix for Haswell in generating a dummy reloc
* code cleanups / api name clarifications
- Abdiel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Nov 16, 2016 at 12:53:07PM +, Tvrtko Ursulin wrote:
> On 16/11/2016 12:20, Chris Wilson wrote:
> >@@ -1538,8 +1541,7 @@ int i915_guc_submission_enable(struct drm_i915_private
> >*dev_priv)
> > list_for_each_entry(request,
> > &engine->timelin
On Wed, 16 Nov 2016, Tomeu Vizoso wrote:
> On 15 November 2016 at 09:27, Jani Nikula wrote:
>> On Tue, 15 Nov 2016, David Weinehall wrote:
>>> On Mon, Nov 14, 2016 at 12:44:25PM +0200, Jani Nikula wrote:
On Thu, 06 Oct 2016, Tomeu Vizoso wrote:
> diff --git a/drivers/gpu/drm/i915/inte
Op 03-11-16 om 16:11 schreef Ville Syrjälä:
> On Wed, Nov 02, 2016 at 09:28:46AM +0100, Maarten Lankhorst wrote:
>> Op 01-11-16 om 14:41 schreef Ville Syrjälä:
>>> On Tue, Nov 01, 2016 at 02:34:00PM +0100, Maarten Lankhorst wrote:
Op 01-11-16 om 14:09 schreef Ville Syrjälä:
> On Mon, Oct 1
On 16/11/2016 12:20, Chris Wilson wrote:
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which
== Series Details ==
Series: drm/i915/opregion: proper handling of DIDL, and some hacks on CADL
URL : https://patchwork.freedesktop.org/series/15403/
State : failure
== Summary ==
Series 15403v1 drm/i915/opregion: proper handling of DIDL, and some hacks on
CADL
https://patchwork.freedesktop.o
Em Qui, 2016-11-10 às 11:24 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
>
(removed a bunch of stuff here)
> >
> > >
> >
> >
> > >
> > > + bool y_tile_enabled = false;
> > > +
> > if (!platforms_that_require_the_wa) {
> > wa = WATERMARK_WA_NONE;
> > return;
> > }
> this function is not
On 16/11/2016 12:26, Chris Wilson wrote:
We don't spam the debug when we create a normal object, nor when we
allocate their pages. Yet we do for stolen objects, and since these are
quite frequently used (at least once per context), the resulting spam
floods the dmesg in CI.
Signed-off-by: Chris
From: Tvrtko Ursulin
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_display.c | 167 +++
3 files changed, 75 insertions(+), 97 deletions(-)
d
Em Qua, 2016-11-16 às 12:13 +0200, Jani Nikula escreveu:
> We no longer cater for pre-production revisions of Skylake.
Reviewed-by: Paulo Zanoni
>
> Fixes: d4362225e8cb ("drm/i915/gvt: update misc ctl regs base on
> stepping info")
> Cc: Ping Gao
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc:
> Sig
We don't spam the debug when we create a normal object, nor when we
allocate their pages. Yet we do for stolen objects, and since these are
quite frequently used (at least once per context), the resulting spam
floods the dmesg in CI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_
On 15 November 2016 at 09:27, Jani Nikula wrote:
> On Tue, 15 Nov 2016, David Weinehall wrote:
>> On Mon, Nov 14, 2016 at 12:44:25PM +0200, Jani Nikula wrote:
>>> On Thu, 06 Oct 2016, Tomeu Vizoso wrote:
>>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> > b/drivers/gpu/drm/i915/intel_
== Series Details ==
Series: HAX drm/i915: Enable guc submission
URL : https://patchwork.freedesktop.org/series/15402/
State : failure
== Summary ==
Series 15402v1 HAX drm/i915: Enable guc submission
https://patchwork.freedesktop.org/api/1.0/series/15402/revisions/1/mbox/
Test drv_module_relo
Something I missed before sending off the partial series was that the
non-scheduler guc reset path was broken (in the full series, this is
pushed to the execlists reset handler). The issue is that after a reset,
we have to refill the GuC workqueues, which we do by resubmitting the
requests. However
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d46ffe7086bc..599b913d8906 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_p
On 15 November 2016 at 22:44, Lyude Paul wrote:
> I'm fine with libsoup as well, I'll check it out and probably move all
> of the code over to using that instead.
Cool.
> On Tue, 2016-11-15 at 12:44 +0100, Tomeu Vizoso wrote:
>> On 11 November 2016 at 18:53, Lyude Paul wrote:
>> > > > - While
Hi,
On Friday 04 November 2016 12:36 AM, Paulo Zanoni wrote:
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
This patch adds support to decode system memory bandwidth
which will be used for arbitrated display memory percentage
calculation in GEN9 based system.
Changes from v1:
-
== Series Details ==
Series: drm/i915/gvt: drop checks for early Skylake revisions
URL : https://patchwork.freedesktop.org/series/15400/
State : success
== Summary ==
Series 15400v1 drm/i915/gvt: drop checks for early Skylake revisions
https://patchwork.freedesktop.org/api/1.0/series/15400/rev
Thanks for the review!
Cheers,
Mika
> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Wednesday, November 16, 2016 11:48 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Latvala, Petri ; dan...@ffwll.ch
> Subject: Re: [PATCH i-g
> -Original Message-
> From: Daniel Stone [mailto:dan...@fooishbar.org]
> Sent: Tuesday, November 15, 2016 3:20 PM
> To: Kahola, Mika
> Cc: intel-gfx
> Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_lowres: Plane
> visibility
> after atomic modesets
>
> Hi Mika,
>
> On 15 Nov
This is essentially the same thing as duplicating DIDL now that the
connector list has the ACPI device IDs.
Cc: Peter Wu
Cc: Rainer Koenig
Cc: Jan-Marek Glogowski
Cc: Maarten Lankhorst
Cc: Marcos Paulo de Souza
Cc: Paolo Stivanin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_op
The attempts to update CADL based on the actual active connectors have
not been successful. That is the right thing to do ultimately, but there
must be something we're still missing.
In the mean time, change the dumb CADL initialization we currently have
to put internal panels in front of the CADL
The graphics driver is supposed to define the DIDL, which are used for
_DOD, not the BIOS. Restore that behaviour.
This is basically a revert of
commit 3143751ff51a163b77f7efd389043e038f3e008e
Author: Zhang Rui
Date: Mon Mar 29 15:12:16 2010 +0800
drm/i915: set DIDL using the ACPI video o
Another spin of [1]. The pain point seems to be the CADL update based on
the list of active connectors. So I left it out for now, and instead
just hack it to ensure CADL contains the internal displays.
Let's see if this sticks. It shouldn't prevent us from fixing CADL
update properly down the line
This patch, or
commit 20311bd35060435badba8a0d46b06d5d184abaf7
Author: Chris Wilson
Date: Mon Nov 14 20:41:03 2016 +
drm/i915/scheduler: Execute requests in order of priorities
tricks sparse into warnings. It makes me unhappy to see the sparse
warnings accumulate because that will ev
== Series Details ==
Series: drm/i915: Add more keywords to firmware loading message
URL : https://patchwork.freedesktop.org/series/15397/
State : success
== Summary ==
Series 15397v1 drm/i915: Add more keywords to firmware loading message
https://patchwork.freedesktop.org/api/1.0/series/15397
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d46ffe7086bc..599b913d8906 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_p
On Wed, Nov 16, 2016 at 10:54:15AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: Invalidate the guc ggtt TLB
> upon insertion
> URL : https://patchwork.freedesktop.org/series/15396/
> State : failure
>
> == Summary ==
>
> Series 15396v1 Ser
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Invalidate the guc ggtt TLB
upon insertion
URL : https://patchwork.freedesktop.org/series/15396/
State : failure
== Summary ==
Series 15396v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/15396
On ke, 2016-11-16 at 11:33 +0200, Mika Kuoppala wrote:
> To find out what firmware we actually loaded (from dmesg) the explicit
> 'dmc' and 'firmware' are missing from the info printout. Add them.
>
> Cc: Imre Deak
> Signed-off-by: Mika Kuoppala
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm
On Thu, Nov 03, 2016 at 06:36:45PM +0200, Jani Nikula wrote:
> On Thu, 03 Nov 2016, Marius Vlad wrote:
> > v5:
> > - reworked gem_info to gem_sanitychecks (Chris Wilson)
> > - remove subgroups/subtests for gem_exec_store and gem_sanitycheck
> > (Chris Wilson)
> >
> > v4:
> > - adjust test to make
We no longer cater for pre-production revisions of Skylake.
Fixes: d4362225e8cb ("drm/i915/gvt: update misc ctl regs base on stepping info")
Cc: Ping Gao
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc:
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gvt/handlers.c | 6 ++
1 file changed, 2 insertio
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