Re: [Intel-gfx] [PATCH] drm/i915: Detect vma reserved for execbuf in evict-for-node

On Thu, Jan 12, 2017 at 09:34:13AM +0200, Joonas Lahtinen wrote: > On ke, 2017-01-11 at 18:21 +, Chris Wilson wrote: > > The vma->exec_list is still the only means we have for both reserving an > > object in execbuf, and for constructing the eviction list. So during the > > construction of the

Re: [Intel-gfx] [PATCH 02/37] drm/i915: Provide a hook for selftests

On Thu, Jan 12, 2017 at 07:29:59AM +, Tvrtko Ursulin wrote: > > On 11/01/2017 21:09, Chris Wilson wrote: > >diff --git a/tools/testing/selftests/drivers/gpu/i915.sh > >b/tools/testing/selftests/drivers/gpu/i915.sh > >index d407f0fa1e3a..c06d6e8a8dcc 100755 > >---

Re: [Intel-gfx] [PATCH v4] drm/i915/scheduler: emulate a scheduler for guc

On Thu, Jan 12, 2017 at 07:14:54AM +, Chris Wilson wrote: > On Thu, Jan 12, 2017 at 07:02:56AM +, Tvrtko Ursulin wrote: > > > > On 11/01/2017 21:24, Chris Wilson wrote: > > >This emulates execlists on top of the GuC in order to defer submission of > > >requests to the hardware. This

Re: [Intel-gfx] [PATCH] drm/i915: Detect vma reserved for execbuf in evict-for-node

On ke, 2017-01-11 at 18:21 +, Chris Wilson wrote: > The vma->exec_list is still the only means we have for both reserving an > object in execbuf, and for constructing the eviction list. So during the > construction of the eviction list, we must treat anything already on the > exec_list as

Re: [Intel-gfx] [PATCH 02/37] drm/i915: Provide a hook for selftests

On 11/01/2017 21:09, Chris Wilson wrote: Some pieces of code are independent of hardware but are very tricky to exercise through the normal userspace ABI or via debugfs hooks. Being able to create mock unit tests and execute them through CI is vital. Start by adding a central point where we can

Re: [Intel-gfx] [PATCH v4 00/10] Execlist based engine-reset (v4)

I'm sorry to do this, but there is a regression fix for gen3 required first that makes this more complicated. https://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=prescheduler=de399a0a6baae97910796d81d8b9324db3fdd77c

Re: [Intel-gfx] [PATCH 04/10] drm/i915/tdr: Modify error handler for per engine hang recovery

On Wed, Jan 11, 2017 at 08:18:11PM -0800, Michel Thierry wrote: > +/** > + * i915_reset - start either engine or full GPU reset to recover from a hang > + * @dev_priv: device private > + * > + * Wrapper function to initiate a GPU reset. If platform supports it, attempt > + * to reset the hung

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Pack the partial view size and offset into a single u64

On 11/01/2017 21:51, Chris Wilson wrote: Since the partial offset must be page aligned, we can use those low 12 bits to encode the size of the partial view (which then cannot be larger than 8MiB in pages). A requirement for avoiding unused bits inside the struct is imposed later by avoiding the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bxt: Add MST support when do DPLL calculation (rev2)

== Series Details == Series: drm/i915/bxt: Add MST support when do DPLL calculation (rev2) URL : https://patchwork.freedesktop.org/series/17815/ State : success == Summary == Series 17815v2 drm/i915/bxt: Add MST support when do DPLL calculation

Re: [Intel-gfx] [PATCH v4] drm/i915/scheduler: emulate a scheduler for guc

On Thu, Jan 12, 2017 at 07:02:56AM +, Tvrtko Ursulin wrote: > > On 11/01/2017 21:24, Chris Wilson wrote: > >This emulates execlists on top of the GuC in order to defer submission of > >requests to the hardware. This deferral allows time for high priority > >requests to gazump their way to the

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Compact memcmp in i915_vma_compare()

On 12/01/2017 07:08, Tvrtko Ursulin wrote: On 11/01/2017 21:51, Chris Wilson wrote: In preparation for the next patch to convert to using an anonymous union and leaving the excess bytes in the union uninitialised, we first need to make sure we do not compare using those uninitialised bytes.

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Compact memcmp in i915_vma_compare()

On 11/01/2017 21:51, Chris Wilson wrote: In preparation for the next patch to convert to using an anonymous union and leaving the excess bytes in the union uninitialised, we first need to make sure we do not compare using those uninitialised bytes. We also want to preserve the compactness of

Re: [Intel-gfx] [PATCH v4] drm/i915/scheduler: emulate a scheduler for guc

On 11/01/2017 21:24, Chris Wilson wrote: This emulates execlists on top of the GuC in order to defer submission of requests to the hardware. This deferral allows time for high priority requests to gazump their way to the head of the queue, however it nerfs the GuC by converting it back into a

[Intel-gfx] [PATCH v2] drm/i915/bxt: Add MST support when do DPLL calculation

From: "Lee, Shawn C" Kernel oops was trigger by DP MST monitor/hub connected. DP MST series patch already upstream and MST should be support also. MST monitor will display normally with this change on bxt platform. Fixes: a277ca7dc01d ("drm/i915: Split

Re: [Intel-gfx] GPU hang with kernel 4.10rc3

On 11/01/17 18:08, Chris Wilson wrote: > On Wed, Jan 11, 2017 at 05:33:34PM +0100, Juergen Gross wrote: >> With kernel 4.10rc3 running as Xen dm0 I get at each boot: >> >> [ 49.213697] [drm] GPU HANG: ecode 7:0:0x3d1d3d3d, in gnome-shell >> [1431], reason: Hang on render ring, action: reset >> [

[Intel-gfx] ✓ Fi.CI.BAT: success for Execlist based engine-reset (rev2)

== Series Details == Series: Execlist based engine-reset (rev2) URL : https://patchwork.freedesktop.org/series/16936/ State : success == Summary == Series 16936v2 Execlist based engine-reset https://patchwork.freedesktop.org/api/1.0/series/16936/revisions/2/mbox/ fi-bdw-5557u total:246

[Intel-gfx] [PATCH 04/10] drm/i915/tdr: Modify error handler for per engine hang recovery

From: Arun Siluvery This is a preparatory patch which modifies error handler to do per engine hang recovery. The actual patch which implements this sequence follows later in the series. The aim is to prepare existing recovery function to adapt to this new function

[Intel-gfx] [PATCH 01/10] drm/i915: Keep i915_handle_error kerneldoc parameters together

And before the function description. Tidy up from commit 14bb2c11796d70b ("drm/i915: Fix a buch of kerneldoc warnings"), all others kerneldoc blocks look ok. Cc: Tvrtko Ursulin Reviewed-by: Chris Wilson Reviewed-by: Tvrtko Ursulin

[Intel-gfx] [PATCH 03/10] drm/i915: Update i915.reset to handle engine resets

From: Arun Siluvery In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [PATCH 08/10] drm/i915/tdr: Export per-engine reset count info to debugfs

From: Arun Siluvery A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they are expected to trigger reset; these counts are checked before and after the test to ensure

[Intel-gfx] [PATCH 02/10] drm/i915: Update i915_reset parameter for kerneldoc

Since commit c033666a94b57 ("drm/i915: Store a i915 backpointer from engine, and use it") i915_reset receives dev_priv, but the kerneldoc was not updated. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH 10/10] drm/i915: Add engine reset count in get-reset-stats ioctl

Users/tests relying on the total reset count will start seeing a smaller number since most of the hangs can be handled by engine reset. Note that if reset engine x, context a running on engine y will be unaware and unaffected. To start the discussion, include just a total engine reset count. If

[Intel-gfx] [PATCH v4 00/10] Execlist based engine-reset (v4)

These patches are to add engine reset feature from Gen8. This is also referred to as Timeout detection and recovery (TDR). This complements to the full gpu reset feature available in i915 but it only allows to reset a particular engine instead of all engines thus providing a light weight engine

[Intel-gfx] [PATCH 07/10] drm/i915/tdr: Add engine reset count to error state

From: Arun Siluvery Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. A follow-up patch will provide

[Intel-gfx] [PATCH 09/10] drm/i915/tdr: Enable Engine reset and recovery support

From: Arun Siluvery This feature is made available only from Gen8, for previous gen devices driver uses legacy full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Tomas Elf

[Intel-gfx] [PATCH 05/10] drm/i915/tdr: Add support for per engine reset recovery

From: Arun Siluvery This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back to the legacy full GPU reset recovery mode if necessary. This is only supported from Gen8 onwards.

[Intel-gfx] [PATCH 06/10] drm/i915: Skip reset request if there is one already

From: Mika Kuoppala To perform engine reset we first disable engine to capture its state. This is done by issuing a reset request. Because we are reusing existing infrastructure, again when we actually reset an engine, reset function checks engine mask and issues

Re: [Intel-gfx] [igvt-g-dev] [PATCH v2 2/3] drm/i915: Extract reserving space in the GTT to a helper

On 2017.01.11 11:23:11 +, Chris Wilson wrote: > Extract drm_mm_reserve_node + calling i915_gem_evict_for_node into its > own routine so that it can be shared rather than duplicated. > > v2: Kerneldoc > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 1/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2

On Wed, Jan 11, 2017 at 7:51 PM, Ben Widawsky wrote: > > +struct drm_format_modifier { > + /* Bitmask of formats in get_plane format list this info > +* applies to. */ > + uint64_t formats; re: the uabi, I'd suggest to at least make this 'u32 offset; u32

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GET_PLANE2 w/ i915 implementation

This is expected because it's based on Ville's patch series to define the new modifiers. On 17-01-12 01:01:31, Patchwork wrote: == Series Details == Series: GET_PLANE2 w/ i915 implementation URL : https://patchwork.freedesktop.org/series/17873/ State : failure == Summary == LD [M]

[Intel-gfx] ✗ Fi.CI.BAT: failure for GET_PLANE2 w/ i915 implementation

== Series Details == Series: GET_PLANE2 w/ i915 implementation URL : https://patchwork.freedesktop.org/series/17873/ State : failure == Summary == LD [M] sound/pci/hda/snd-hda-codec-generic.o LD lib/built-in.o LD sound/pci/built-in.o LD drivers/acpi/built-in.o LD

[Intel-gfx] [PATCH 0/3] GET_PLANE2 w/ i915 implementation

This patch series implements GET_PLANE2 support for Intel platforms and defines the new kernel UAPI. The idea was originally introduced by Kristian. Ultimately, the purpose of the new API is to provide the ability to query per-plane modifiers in KMS. These modifiers, which are just fb modifiers,

[Intel-gfx] [PATCH 3/3] drm/i915: Add support for GET_PLANE2 CCS modifiers

Cc: Kristian Høgsberg Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_display.c | 10 -- drivers/gpu/drm/i915/intel_sprite.c | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 1/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2

Originally based off of a patch by Kristian. This new ioctl extends DRM_IOCTL_MODE_GETPLANE, by returning information about the modifiers that will work with each format. It's modified from Kristian's patch in that the modifiers and formats are setup by the driver, and then a callback is used to

[Intel-gfx] [PATCH 2/3] drm/i915: Add format modifiers for Intel

This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. Cc: Kristian H. Kristensen Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_display.c | 109

Re: [Intel-gfx] [PATCHv2] drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.

Daniel Vetter writes: > On Wed, Jan 11, 2017 at 12:24:59PM +, Chris Wilson wrote: >> On Wed, Jan 11, 2017 at 02:07:37PM +0200, Mika Kuoppala wrote: >> > Daniel Vetter writes: >> > >> > > On Mon, Jan 09, 2017 at 01:07:56PM -0800, Francisco Jerez wrote: >> >

Re: [Intel-gfx] [PATCHv2] drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.

Daniel Vetter writes: > On Mon, Jan 09, 2017 at 01:07:56PM -0800, Francisco Jerez wrote: >> The WaDisableLSQCROPERFforOCL workaround has the side effect of >> disabling an L3SQ optimization that has huge performance implications >> and is unlikely to be necessary for the correct

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view

== Series Details == Series: series starting with [1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view URL : https://patchwork.freedesktop.org/series/17858/ State : success == Summary == Series 17858v1 Series without cover letter

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev3)

== Series Details == Series: series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev3) URL : https://patchwork.freedesktop.org/series/17829/ State : failure == Summary == Series 17829v3 Series without cover letter

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Add render decompression support

On Wed, Jan 11, 2017 at 1:49 PM, Jason Ekstrand wrote: > On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä < > ville.syrj...@linux.intel.com> wrote: > >> On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote: >> > On Thu, Jan 5, 2017 at 7:14 AM,

[Intel-gfx] [PATCH 08/10] drm/i915/psr: enable psr2 for y cordinate panels

Psr2 is enabled only for y cordinate panels.Once GTC (global time code) is implemented,this restriction is removed so that psr2 can work on panels without y cordinate support. v2: (Rodrigo) - Move the check to intel_psr_match_conditions v3: (Rodrigo) - add return false v4: rebase Cc: Rodrigo

Re: [Intel-gfx] [PATCH] drm/i915/guc: Make sure vma containing firmware is GuC mappable

On 11/01/17 07:17, Michał Winiarski wrote: Since commit 4741da925fa3 ("drm/i915/guc: Assert that all GGTT offsets used by the GuC are mappable"), we're asserting that GuC firmware is in the GuC mappable range. Except we're not pinning the object with bias, which means it's possible to trigger

Re: [Intel-gfx] 4.10-rc2 oops in DRM connector code

On Wed, Jan 11, 2017 at 08:16:56AM -0800, Dave Hansen wrote: > On 01/11/2017 07:39 AM, Daniel Vetter wrote: > > Hm, just cherry-picked it on top of Linus' latest 4.10 git, applies > > cleanly there. The substituation was for 4.9. I can send you the patch > > here, but seems all fine from what I

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/37] drm: Provide a driver hook for drm_dev_release()

== Series Details == Series: series starting with [01/37] drm: Provide a driver hook for drm_dev_release() URL : https://patchwork.freedesktop.org/series/17852/ State : success == Summary == Series 17852v1 Series without cover letter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Detect vma reserved for execbuf in evict-for-node

== Series Details == Series: drm/i915: Detect vma reserved for execbuf in evict-for-node URL : https://patchwork.freedesktop.org/series/17846/ State : success == Summary == Series 17846v1 drm/i915: Detect vma reserved for execbuf in evict-for-node

[Intel-gfx] [PATCH 5/6] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

It is only being used to clear a struct and set the type, after which it is overwritten. Since we no longer check the unset bits of the union, skipping the clear is permissible. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen

[Intel-gfx] [PATCH 6/6] drm/i915: Eliminate superfluous i915_ggtt_view_normal

Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only one user of i915_ggtt_view_normal rodate. Just treat NULL as no special view in pin_to_display() like everywhere else. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen

[Intel-gfx] [PATCH 2/6] drm/i915: Pack the partial view size and offset into a single u64

Since the partial offset must be page aligned, we can use those low 12 bits to encode the size of the partial view (which then cannot be larger than 8MiB in pages). A requirement for avoiding unused bits inside the struct is imposed later by avoiding the clear of the struct (or of copying around

[Intel-gfx] [PATCH 1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view

Naming this pair will become useful shortly... Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git

[Intel-gfx] [PATCH 4/6] drm/i915: Convert i915_ggtt_view to use an anonymous union

Save a lot of characters by making the union anonymous, with the side-effect of ignoring unset bits when comparing views. v2: Roll up the memcmps back into one. v3: And split again as Ville points out we can't trust the compiler. Signed-off-by: Chris Wilson Cc: Daniel

[Intel-gfx] [PATCH 3/6] drm/i915: Compact memcmp in i915_vma_compare()

In preparation for the next patch to convert to using an anonymous union and leaving the excess bytes in the union uninitialised, we first need to make sure we do not compare using those uninitialised bytes. We also want to preserve the compactness of the code, avoiding a second call to memcmp or

[Intel-gfx] Anonymous ggtt_view params

It makes reading the vma->ggtt_view code more pleasant, but at an unfortunate cost in header complexity to ensure that no unwanted bits are in the struct and that gcc doesn't double the size of a few inlined functions. I like it, but I am biased. -Chris

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Add render decompression support

On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä < ville.syrj...@linux.intel.com> wrote: > On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote: > > On Thu, Jan 5, 2017 at 7:14 AM, wrote: > > > > > From: Ville Syrjälä > > > >

[Intel-gfx] [PATCH v4] drm/i915/scheduler: emulate a scheduler for guc

This emulates execlists on top of the GuC in order to defer submission of requests to the hardware. This deferral allows time for high priority requests to gazump their way to the head of the queue, however it nerfs the GuC by converting it back into a simple execlist (where the CPU has to wake up

[Intel-gfx] [PATCH 36/37] drm/i915: Initial selftests for exercising eviction

Very simple tests to just ask eviction to find some free space in a full GTT and one with some available space. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_evict.c | 4 +

[Intel-gfx] [PATCH 37/37] drm/i915: Add initial selftests for hang detection and resets

Check that we can reset the GPU and continue executing from the next request. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_hangcheck.c | 4 + .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +

[Intel-gfx] [PATCH 18/37] drm/i915: Test exhaustion of the mmap space

An unlikely error condition that we can simulate by stealing the most of the range before trying to insert new objects. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_object.c | 137 +++ 1 file changed, 137 insertions(+)

[Intel-gfx] [PATCH 29/37] drm/i915: Fill different pages of the GTT

Exercise filling different pages of the GTT Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 130 ++ 1 file changed, 130 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c

[Intel-gfx] [PATCH 28/37] drm/i915: Exercising filling the top/bottom portions of the global GTT

Same test as previously for the per-process GTT instead applied to the global GTT. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 118 +++--- 1 file changed, 88 insertions(+), 30 deletions(-) diff --git

[Intel-gfx] [PATCH 22/37] drm/i915: Sanity check all registers for matching fw domains

Add a late selftest that walks over all forcewake registers (those below 0x4) and uses the mmio debug register to check to see if any are unclaimed. This is possible if we fail to wake the appropriate powerwells for the register. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 19/37] drm/i915: Test coherency of and barriers between cache domains

Write into an object using WB, WC, GTT, and GPU paths and make sure that our internal API is sufficient to ensure coherent reads and writes. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c| 1 +

[Intel-gfx] [PATCH 21/37] drm/i915: Test all fw tables during mock selftests

In addition to just testing the fw table we load, during the initial mock testing we can test that all tables are valid (so the testing is not limited to just the platforms that load that particular table). Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 32/37] drm/i915: Exercise i915_vma_pin/i915_vma_insert

High-level testing of the struct drm_mm by verifying our handling of weird requests to i915_vma_pin. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_vma.c | 4 +- drivers/gpu/drm/i915/i915_vma.h | 4 +-

[Intel-gfx] [PATCH 34/37] drm/i915: Test creation of partial VMA

Mock testing to ensure we can create and lookup partial VMA. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_vma.c | 179 ++ 1 file changed, 179 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c

[Intel-gfx] [PATCH 31/37] drm/i915: Test creation of VMA

Simple test to exercise creation and lookup of VMA within an object. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_vma.c| 3 + .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_vma.c

[Intel-gfx] [PATCH 27/37] drm/i915: Exercising filling the top/bottom portions of the ppgtt

Allocate objects with varying number of pages (which should hopefully consist of a mixture of contiguous page chunks and so coalesced sg lists) and check that the sg walkers in insert_pages cope. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 30/37] drm/i915: Exercise filling and removing random ranges from the live GTT

Test the low-level i915_address_space interfaces to sanity check the live insertion/removal of address ranges. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 140 ++ 1 file changed, 140 insertions(+) diff --git

[Intel-gfx] [PATCH 23/37] drm/i915: Add some mock tests for dmabuf interop

Check that we can create both dmabuf and objects from dmabuf. v2: Cleanups, correct include, fix unpin on dead path and prevent explosion on dmabuf init failure Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ---

[Intel-gfx] [PATCH 35/37] drm/i915: Live testing for context execution

Check we can create and execution within a context. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c| 1 + drivers/gpu/drm/i915/selftests/i915_gem_context.c | 302 +

[Intel-gfx] [PATCH 33/37] drm/i915: Verify page layout for rotated VMA

Exercise creating rotated VMA and checking the page order within. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_vma.c | 130 ++ 1 file changed, 130 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c

[Intel-gfx] [PATCH 20/37] drm/i915: Move uncore selfchecks to live selftest infrastructure

Now that the kselftest infrastructure exists, put it to use and add to it the existing consistency checks on the fw register lookup tables. v2: s/tabke/table/ Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Matthew Auld

[Intel-gfx] [PATCH 26/37] drm/i915: Assert that we have allocated the drm_mm_node upon pinning

We currently check after the slow path that the vma is bound correctly, but we don't currently check after the fast path. This is important in case we accidentally take the fast path and leave the vma misplaced. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 24/37] drm/i915: Add initial selftests for i915_gem_gtt

Simple starting point for adding selftests for i915_gem_gtt, first try creating a ppGTT and filling it. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c| 1 +

[Intel-gfx] [PATCH 15/37] drm/i915: Add selftests for object allocation, phys

The phys object is a rarely used device (only very old machines require a chunk of physically contiguous pages for a few hardware interactions). As such, it is not exercised by CI and to combat that we want to add a test that exercises the phys object on all platforms. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 25/37] drm/i915: Move i915_ppgtt_close() into i915_gem_gtt.c

Move it alongside its ppgtt counterparts, in order to make it available for the ppgtt selftests. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 21 - drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +

[Intel-gfx] [PATCH 06/37] drm/i915: Add unit tests for the breadcrumb rbtree, wakeups

Third retroactive test, make sure that the seqno waiters are woken. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 171 + 1 file changed, 171 insertions(+) diff --git

[Intel-gfx] [PATCH 13/37] drm/i915: Add a simple fence selftest to i915_gem_request

Do a quick selftest on in the interoperability of dma_fence_wait on a i915_gem_request. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/selftests/i915_gem_request.c | 47 +++ 1 file

[Intel-gfx] [PATCH 08/37] drm/i915: Mock a GGTT for self-testing

A very simple mockery, just a random manager and timeline. Useful for inserting objects and ordering retirement; and not much else. v2: mock_fini_ggtt() to complement mock_init_ggtt(). Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ---

[Intel-gfx] [PATCH 12/37] drm/i915: Add a simple request selftest for waiting

A trivial kselftest to submit a request and wait upon it. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_request.c | 44 +++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c

[Intel-gfx] [PATCH 16/37] drm/i915: Add a live seftest for GEM objects

Starting with a placeholder test just to reassure that we can create a test object, Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_object.c | 47 ++ .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 + 2 files

[Intel-gfx] [PATCH 17/37] drm/i915: Test partial mappings

Create partial mappings to cover a large object, investigating tiling (fenced regions) and VMA reuse. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_object.c | 252 +++ 1 file changed, 252 insertions(+) diff --git

[Intel-gfx] [PATCH 14/37] drm/i915: Simple selftest to exercise live requests

Just create several batches of requests and expect it to not fall over! Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_request.c | 78 ++ .../gpu/drm/i915/selftests/i915_live_selftests.h | 1 + 2 files changed, 79

[Intel-gfx] [PATCH 11/37] drm/i915: Add selftests for i915_gem_request

Simple starting point for adding seltests for i915_gem_request, first mock a device (with engines and contexts) that allows us to construct and execute a request, along with waiting for the request to complete. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 10/37] drm/i915: Create a fake object for testing huge allocations

We would like to be able to exercise huge allocations even on memory constrained devices. To do this we create an object that allocates only a few pages and remaps them across its whole range - each page is reused multiple times. We can therefore pretend we are rendering into a much larger object.

[Intel-gfx] [PATCH 03/37] drm/i915: Add some selftests for sg_table manipulation

Start exercising the scattergather lists, especially looking at iteration after coalescing. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c| 11 +-

[Intel-gfx] [PATCH 07/37] drm/i915: Mock the GEM device for self-testing

A simulacrum of drm_i915_private to let us pretend interactions with the device. v2: Tidy init error paths Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.c | 4 +

[Intel-gfx] [PATCH 09/37] drm/i915: Mock infrastructure for request emission

Create a fake engine that runs requests using a timer to simulate hw. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c| 4 + drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 11 +- drivers/gpu/drm/i915/selftests/mock_context.c

[Intel-gfx] [PATCH 01/37] drm: Provide a driver hook for drm_dev_release()

Some state is coupled into the device lifetime outside of the load/unload timeframe and requires teardown during final unreference from drm_dev_release(). For example, dmabufs hold both a device and module reference and may live longer than expected (i.e. the current pattern of the driver tearing

[Intel-gfx] [PATCH 05/37] drm/i915: Add unit tests for the breadcrumb rbtree, completion

Second retroactive test, make sure that the waiters are removed from the global wait-tree when their seqno completes. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 107

[Intel-gfx] [PATCH 04/37] drm/i915: Add unit tests for the breadcrumb rbtree, insert/remove

First retroactive test, make sure that the waiters are in global seqno order after random inserts and removals. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/Makefile | 1 +

[Intel-gfx] [PATCH 02/37] drm/i915: Provide a hook for selftests

Some pieces of code are independent of hardware but are very tricky to exercise through the normal userspace ABI or via debugfs hooks. Being able to create mock unit tests and execute them through CI is vital. Start by adding a central point where we can execute unit tests and a parameter to

[Intel-gfx] Selftests

A small smattering of selftests. Coverage is getting better, but still a long way from providing coverage of every path I have planned. :| The tests we do have do nicely demonstrated the ease at which some in-depth testing can be done in the kernel, some that would be impossible from userspace.

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev2) URL : https://patchwork.freedesktop.org/series/17829/ State : failure == Summary == Series 17829v2 Series without cover letter

[Intel-gfx] [PATCH] dim: Update docs

- Remove branch overview, instead link to drm-intel and drm-misc pages. - Move quickstart to the top, to make it easier to find. - Make quickstart generic, we use dim for other stuff than drm-intel now. - s/drm-intel-rerere/drm-rerere/ - Remove the section about resolving conflicts, that's

[Intel-gfx] [PATCH i-g-t rfc 21/29] tests/kms_properties: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_properties.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/kms_properties.c b/tests/kms_properties.c index

[Intel-gfx] [PATCH i-g-t rfc 20/29] tests/kms_plane_scaling: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_plane_scaling.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/kms_plane_scaling.c

[Intel-gfx] [PATCH i-g-t rfc 27/29] tests/kms_universal_plane: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_universal_plane.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/kms_universal_plane.c

[Intel-gfx] [PATCH i-g-t rfc 24/29] tests/kms_rmfb: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_rmfb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_rmfb.c b/tests/kms_rmfb.c index 17a3065a..5753d74c 100644 ---

[Intel-gfx] [PATCH i-g-t rfc 26/29] tests/kms_sink_crc_basic: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_sink_crc_basic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_sink_crc_basic.c b/tests/kms_sink_crc_basic.c index

[Intel-gfx] [PATCH i-g-t rfc 28/29] tests/kms_vblank: Add support for dynamic number of planes

Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_vblank.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c index 9bc49296..73b3b2ad

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