Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.

On Mon, 23 Jan 2017, Rodrigo Vivi wrote: > Ander, can I carry your rv-b on this v2? > > Jani, with Ander confirmation can I merge these 2 patches? Acked-by: Jani Nikula > > > On Mon, Jan 23, 2017 at 11:24 AM, Patchwork >

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Add support for audio driver notifications

On Mon, 23 Jan 2017, Pierre-Louis Bossart wrote: >>> #include >>> @@ -630,6 +631,10 @@ void intel_audio_codec_enable(struct intel_encoder >>> *intel_encoder, >>> if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) >>>

[Intel-gfx] [PATCH] igt/gem_exec_schedule: Use igt_spin_batch

Signed-off-by: Abdiel Janulgue --- tests/gem_exec_schedule.c | 120 ++ 1 file changed, 15 insertions(+), 105 deletions(-) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index d8454d5..87d5a85 100644

[Intel-gfx] [PATCH i-g-t v4] tools: Add intel_dp_compliance for DisplayPort 1.2 compliance automation

From: "Navare, Manasi D" This is the userspace component of the Displayport Compliance testing software required for compliance testing of the I915 Display Port driver. This must be running in order to successfully complete Display Port compliance testing. This app and

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Improve handling of OA tail race

== Series Details == Series: drm/i915/perf: Improve handling of OA tail race URL : https://patchwork.freedesktop.org/series/18448/ State : success == Summary == Series 18448v1 drm/i915/perf: Improve handling of OA tail race

Re: [Intel-gfx] [Linux v4.10.0-rc1+] Still call-traces after suspend-resume (pm? i915? cpu/hotplug?)

On Fri, Dec 30, 2016 at 3:02 PM, Rafael J. Wysocki wrote: > On Fri, Dec 30, 2016 at 12:40 PM, Sedat Dilek wrote: >> Hi, >> >> I have already reported this issue in [1]. >> One of the issue was solved. >> Unfortunately, it looks like there is still a

[Intel-gfx] [PATCH 3/5] drm/i915/perf: avoid read back of head register

There's no need for the driver to keep reading back the head pointer from hardware since the hardware doesn't update it automatically. This way we can treat any invalid head pointer value as a software/driver bug instead of spurious hardware behaviour. This change is also a small stepping stone

[Intel-gfx] [PATCH 4/5] drm/i915/perf: no head/tail ref in gen7_oa_read

This avoids redundantly passing an (inout) head and tail pointer to gen7_append_oa_reports() from gen7_oa_read which doesn't need to reference either itself. Moving the head/tail reads and writes into gen7_append_oa_reports should have no functional effect except to avoid some redundant head

[Intel-gfx] [PATCH 2/5] drm/i915/perf: avoid poll, read, EAGAIN busy loops

If the function for checking whether there is OA buffer data available (during a poll or blocking read) has false positives then we want to avoid a situation where the subsequent read() returns EAGAIN (after a more accurate check) followed by a poll() immediately reporting the same false positive

[Intel-gfx] [PATCH 1/5] drm/i915/perf: fix gen7_append_oa_reports comment

If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 5/5] drm/i915/perf: improve tail race workaround

There's a HW race condition between OA unit tail pointer register updates and writes to memory whereby the tail pointer can sometimes get ahead of what's been written out to the OA buffer so far (in terms of what's visible to the CPU). Although this can be observed explicitly while copying

[Intel-gfx] [PATCH 0/5] drm/i915/perf: Improve handling of OA tail race

While I was updating the i915 perf patches for gen8+ I found I also needed to add a workaround for a tail pointer race, like we see for gen7 too. I was feeling guilty knowing there are a few limitations with the current workaround for gen7 and so want to address those before reusing the WA for

[Intel-gfx] [PATCH igt] igt/perf: improve robustness of polling/blocking tests

There were a couple of problems with both of these tests that could lead to false negatives addressed by this patch. 1) The upper limit for the number of iterations missed a +1 to consider that there might be a sample immediately available at the start of the loop. v2) The tests didn't

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add support for DP link training compliance

On Mon, Jan 23, 2017 at 12:50:07PM -0800, Manasi Navare wrote: > Thanks Jani for reviewing this patch and for your feedback. > Its very useful feedback and below are some of my comments: > > On Fri, Jan 20, 2017 at 05:05:03PM +0200, Jani Nikula wrote: > > On Fri, 20 Jan 2017, Manasi Navare

Re: [Intel-gfx] [PATCH v2] drm/i915/dp: do not proceed with autotests if we don't ACK them

Thanks for this patch. I have tested this on DPR 120 compliance test device and verified that it works as expected. Manasi On Fri, Jan 20, 2017 at 07:04:06PM +0200, Jani Nikula wrote: > There is no point in setting intel_dp->compliance.test_type, and > proceeding with the autotests, if we're

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move atomic state free from out of fence release

== Series Details == Series: drm/i915: Move atomic state free from out of fence release URL : https://patchwork.freedesktop.org/series/18431/ State : success == Summary == Series 18431v1 drm/i915: Move atomic state free from out of fence release

[Intel-gfx] [PATCH] drm/i915: Move atomic state free from out of fence release

Fences are required to support being released from under an atomic context. The drm_atomic_state struct may take a mutex when being released and so we cannot drop a reference to the drm_atomic_state from the fence release path directly, and so we need to defer that unreference to a worker. [

[Intel-gfx] [PATCH v2 00/13] coordinate cht i2c-pmic and i915-punit accesses

Hi All, Here is v2 of my cht i2c-pmic and i915-punit access coordination patchset. New in this version are some minor spelling / style fixes and more importantly the inclusion of 6 extra i2c-designware patches. These 6 patches are ready for merging, they have Wolfram's (the i2c maintainer's)

[Intel-gfx] [PATCH v2 06/13] i2c: designware-baytrail: Disallow the CPU to enter C6 or C7 while holding the punit semaphore

On my cherrytrail tablet with axp288 pmic, just doing a bunch of repeated reads from the pmic, e.g. "i2cdump -y 14 0x34" would lookup the tablet in 1 - 3 runs guaranteed. This seems to be causes by the cpu trying to enter C6 or C7 while we hold the punit bus semaphore, at which point everything

[Intel-gfx] [PATCH v2 01/13] x86/platform/intel/iosf_mbi: Add a mutex for P-Unit access

One some systems the P-Unit accesses the PMIC to change various voltages through the same bus as other kernel drivers use for e.g. battery monitoring. If a driver sends requests to the P-Unit which require the P-Unit to access the PMIC bus while another driver is also accessing the PMIC bus

[Intel-gfx] [PATCH v2 05/13] i2c: designware-baytrail: Only check iosf_mbi_available() for shared hosts

If (!shared_host) simply return 0, this avoids delaying the probe if iosf_mbi_available() returns false when an i2c bus is not using the punit semaphore. Also move the if (!iosf_mbi_available()) check to above the dev_info, so that we do not repeat the dev_info on every probe until

[Intel-gfx] [PATCH v2 11/13] drm/i915: Add intel_uncore_suspend / resume functions

Rename intel_uncore_early_sanitize to intel_uncore_resume, dropping the (always true) restore_forcewake argument and add a new intel_uncore_resume function to replace the intel_uncore_forcewake_reset(dev_priv, false) calls done from the suspend / runtime_suspend functions and make

[Intel-gfx] [PATCH v2 13/13] drm/i915: Acquire P-Unit access when modifying P-Unit settings

Make sure the P-Unit or the PMIC i2c bus is not in use when we send a request to the P-Unit by calling iosf_mbi_punit_acquire() / _release() around P-Unit write accesses. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=155241 Signed-off-by: Hans de Goede Tested-by:

[Intel-gfx] [PATCH v2 12/13] drm/i915: Listen for PMIC bus access notifications

Listen for PMIC bus access notifications and get FORCEWAKE_ALL while the bus is accessed to avoid needing to do any forcewakes, which need PMIC bus access, while the PMIC bus is busy: This fixes errors like these showing up in dmesg, usually followed by a gfx or system freeze:

[Intel-gfx] [PATCH v2 07/13] i2c: designware-baytrail: Fix race when resetting the semaphore

Use iosf_mbi_modify instead of iosf_mbi_read + iosf_mbi_write so that we keep the iosf_mbi_lock locked during the read-modify-write done to reset the semaphore. Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Acked-by: Jarkko

[Intel-gfx] [PATCH v2 08/13] i2c: designware-baytrail: Add support for cherrytrail

The cherrytrail punit has the pmic i2c bus access semaphore at a different register address. Signed-off-by: Hans de Goede Reviewed-by: Takashi Iwai Tested-by: Takashi Iwai Reviewed-by: Andy Shevchenko

[Intel-gfx] [PATCH v2 10/13] i2c: designware-baytrail: Call pmic_bus_access_notifier_chain

Call the iosf_mbi pmic_bus_access_notifier_chain on bus acquire / release. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=155241 Signed-off-by: Hans de Goede Tested-by: tagorereddy Reviewed-by: Andy Shevchenko

[Intel-gfx] [PATCH v2 09/13] i2c: designware-baytrail: Acquire P-Unit access on bus acquire

Acquire P-Unit access to stop others from accessing the P-Unit while the PMIC i2c bus is in use. This is necessary because accessing the P-Unit from the kernel may result in the P-Unit trying to access the PMIC i2c bus, which results in a hang when it happens while we own the PMIC i2c bus

[Intel-gfx] [PATCH v2 04/13] i2c: designware-baytrail: Pass dw_i2c_dev into helper functions

Pass dw_i2c_dev into the helper functions, this is a preparation patch for the punit semaphore fixes done in the other patches in this set. Signed-off-by: Hans de Goede Reviewed-by: Takashi Iwai Tested-by: Takashi Iwai Reviewed-by: Andy

[Intel-gfx] [PATCH v2 02/13] x86/platform/intel/iosf_mbi: Add a PMIC bus access notifier

Some drivers may need to acquire P-Unit managed resources from interrupt context, where they cannot call iosf_mbi_punit_acquire(). This commit adds a notifier chain which allows a driver to get notified (in a process context) before other drivers start accessing the PMIC bus, so that the driver

[Intel-gfx] [PATCH v2 03/13] i2c: designware: Rename accessor_flags to flags

Rename accessor_flags to flags, so that we can use the field for other flags too. This is a preparation patch for adding cherrytrail support to the punit semaphore code. Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Acked-by:

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.

Ander, can I carry your rv-b on this v2? Jani, with Ander confirmation can I merge these 2 patches? On Mon, Jan 23, 2017 at 11:24 AM, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915/kbl: Apply >

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add support for DP link training compliance

Thanks Jani for reviewing this patch and for your feedback. Its very useful feedback and below are some of my comments: On Fri, Jan 20, 2017 at 05:05:03PM +0200, Jani Nikula wrote: > On Fri, 20 Jan 2017, Manasi Navare wrote: > > This patch adds support to handle

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.

== Series Details == Series: series starting with [1/2] drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL. URL : https://patchwork.freedesktop.org/series/18421/ State : success == Summary == Series 18421v1 Series without cover letter

Re: [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6)

On Mon, Jan 23, 2017 at 09:05:02AM -0800, Manasi Navare wrote: > On Sat, Jan 21, 2017 at 05:16:42PM +0200, Jani Nikula wrote: > > On Sat, 21 Jan 2017, Manasi Navare wrote: > > > This patch series addresses all the review comments from the previous > > > series: > > >

[Intel-gfx] [PATCH 2/2] drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.

Along with GLK it was introduced the .is_lp and IS_GEN9_LP. So, following the same simplification standard we can put Skylake and Kabylake under the same bucket for most of the things. So let's add the IS_GEN9_BC for "Big Core" (non Atom based platforms). The i915_drv.c was let out of this patch

[Intel-gfx] [PATCH 1/2] drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.

According to wa_database this Wa persist on KBL as it was on SKL. Cc: Tim Gore Cc: Mika Kuoppala Cc: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Reviewed-by: Ander Conselvan de Oliveira

Re: [Intel-gfx] [PATCH 0/4] Add automation support for DP Compliance (Rev 6)

On Sat, Jan 21, 2017 at 05:16:42PM +0200, Jani Nikula wrote: > On Sat, 21 Jan 2017, Manasi Navare wrote: > > This patch series addresses all the review comments from the previous > > series: > > https://patchwork.freedesktop.org/series/18256/ > > It does not, and it

Re: [Intel-gfx] [PATCH] dim: Triple-check and tripe warning when merging patches that touch files outside i915.

On Fri, Jan 13, 2017 at 09:04:12AM +0200, Jani Nikula wrote: > On Fri, 13 Jan 2017, Rodrigo Vivi wrote: > > Most of commiters already knows that by heart and also dim already > > have this warning. So maybe this is just Bart writing to blackboard. Duh! > > > > Anyway for

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Add support for audio driver notifications

#include @@ -630,6 +631,10 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder, if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,

Re: [Intel-gfx] [PATCH] drm/i915: Fix not finding the VBT when it overlaps with OPREGION_ASLE_EXT

Hi, On 23-01-17 11:36, Jani Nikula wrote: On Fri, 20 Jan 2017, Hans de Goede wrote: Hi, On 31-12-16 17:00, Hans de Goede wrote: Hi, On 27-12-16 11:58, Jani Nikula wrote: On Sun, 25 Dec 2016, Hans de Goede wrote: If there is no OPREGION_ASLE_EXT

Re: [Intel-gfx] [PATCH] drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view

On Mon, Jan 23, 2017 at 03:01:20PM +, Matthew Auld wrote: > On 23 January 2017 at 14:52, Chris Wilson wrote: > > Since tweaking i915_vma_compare() we allowed constructors to skip > > clearing the ggtt_view believing that we didn't access the unused > > members. That,

Re: [Intel-gfx] [PATCH i-g-t v1 04/32] lib/igt_kms: Implement dynamic plane count support

On 2017-01-23 06:00 AM, Mika Kahola wrote: With this patch applied, I received couple of issues during the compilation igt_kms.c:332:5: warning: no previous prototype for ‘kmstest_pipe_to_index’ [-Wmissing-prototypes] int kmstest_pipe_to_index(char pipe) and kms_fence_pin_leak.c:118:41:

Re: [Intel-gfx] [PATCH i-g-t 5/5] tests/kms_test_only: Validate TEST_ONLY correctness against full atomic commit

Op 23-01-17 om 14:26 schreef Mika Kahola: > On Thu, 2017-01-12 at 12:37 +0100, Maarten Lankhorst wrote: >> Hey, >> >> Op 12-01-17 om 11:28 schreef Mika Kahola: >>> On Thu, 2017-01-12 at 11:11 +0100, Maarten Lankhorst wrote: Op 30-12-16 om 13:00 schreef Mika Kahola: > This test case adds

Re: [Intel-gfx] [PATCH] drm/i915: Assert that we don't submit to execlists whilst a preempt is pending

Chris Wilson writes: > To complement the check in execlists_elsp_ready(), also assert that we > don't submit the same context while it has a lite restore still pending. > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view

== Series Details == Series: drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view URL : https://patchwork.freedesktop.org/series/18414/ State : success == Summary == Series 18414v1 drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Only run execlist context-switch handler after an interrupt

Chris Wilson writes: > Mark when we run the execlist tasklet following the interrupt, so we > don't probe a potentially initialised register when submitting the > contexts multiple times. > > Signed-off-by: Chris Wilson > --- >

Re: [Intel-gfx] [PATCH] drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view

On 23 January 2017 at 14:52, Chris Wilson wrote: > Since tweaking i915_vma_compare() we allowed constructors to skip > clearing the ggtt_view believing that we didn't access the unused > members. That, as it turns out, was not entirely true. In particular, >

Re: [Intel-gfx] [PATCH] drm/i915: Use atomic page flip for intel again.

Op 27-12-16 om 15:48 schreef Daniel Vetter: > On Thu, Dec 22, 2016 at 11:33:23AM +0100, Maarten Lankhorst wrote: >> This reverts commit 527b6abe5fd2d2 >> (Revert "drm/i915: Use atomic commits for legacy page_flips") >> >> and reapplies commit ee042aa40b66d1. >> ("drm/i915: Use atomic commits for

[Intel-gfx] [PATCH] drm/i915: Pevent copying uninitialised garbage into vma->ggtt_view

Since tweaking i915_vma_compare() we allowed constructors to skip clearing the ggtt_view believing that we didn't access the unused members. That, as it turns out, was not entirely true. In particular, i915_gem_fault() uses ret = remap_io_mapping(area, area->vm_start +

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On Mon, Jan 23, 2017 at 02:39:03PM +, Chris Wilson wrote: > On Mon, Jan 23, 2017 at 02:22:38PM +, Matthew Auld wrote: > > On 23 January 2017 at 14:02, Chris Wilson wrote: > > > On Mon, Jan 23, 2017 at 01:51:54PM +, Matthew Auld wrote: > > >> On 14 January

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On Mon, Jan 23, 2017 at 02:22:38PM +, Matthew Auld wrote: > On 23 January 2017 at 14:02, Chris Wilson wrote: > > On Mon, Jan 23, 2017 at 01:51:54PM +, Matthew Auld wrote: > >> On 14 January 2017 at 00:28, Chris Wilson wrote: > >> > It

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

On Mon, Jan 23, 2017 at 01:52:02PM +, Chris Wilson wrote: > On Mon, Jan 23, 2017 at 03:43:27PM +0200, Ville Syrjälä wrote: > > On Mon, Jan 23, 2017 at 01:05:57PM +, Chris Wilson wrote: > > > This w/a was only used for preproduction hw, which is no longer in use. > > > Remove the workaround

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Assert that we don't submit to execlists whilst a preempt is pending

== Series Details == Series: drm/i915: Assert that we don't submit to execlists whilst a preempt is pending URL : https://patchwork.freedesktop.org/series/18407/ State : warning == Summary == Series 18407v1 drm/i915: Assert that we don't submit to execlists whilst a preempt is pending

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On 23 January 2017 at 14:02, Chris Wilson wrote: > On Mon, Jan 23, 2017 at 01:51:54PM +, Matthew Auld wrote: >> On 14 January 2017 at 00:28, Chris Wilson wrote: >> > It is only being used to clear a struct and set the type, after which it

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On Mon, Jan 23, 2017 at 01:51:54PM +, Matthew Auld wrote: > On 14 January 2017 at 00:28, Chris Wilson wrote: > > It is only being used to clear a struct and set the type, after which it > > is overwritten. Since we no longer check the unset bits of the union, > >

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On Mon, Jan 23, 2017 at 01:51:54PM +, Matthew Auld wrote: > On 14 January 2017 at 00:28, Chris Wilson wrote: > > It is only being used to clear a struct and set the type, after which it > > is overwritten. Since we no longer check the unset bits of the union, > >

Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: Only disable execlist preemption for the duration of the request

Chris Wilson writes: > We need to prevent resubmission of the context immediately following an > initial resubmit (which does a lite-restore preemption). Currently we do > this by disabling all submission whilst the context is still active, but > we can improve this by

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Remove disable_lite_restore_wa

== Series Details == Series: series starting with [1/6] drm/i915: Remove disable_lite_restore_wa URL : https://patchwork.freedesktop.org/series/18406/ State : success == Summary == Series 18406v1 Series without cover letter

Re: [Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On 14 January 2017 at 00:28, Chris Wilson wrote: > It is only being used to clear a struct and set the type, after which it > is overwritten. Since we no longer check the unset bits of the union, > skipping the clear is permissible. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

On Mon, Jan 23, 2017 at 03:43:27PM +0200, Ville Syrjälä wrote: > On Mon, Jan 23, 2017 at 01:05:57PM +, Chris Wilson wrote: > > This w/a was only used for preproduction hw, which is no longer in use. > > Remove the workaround to simplify the code. > > > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH] drm/i915: Assert that we don't submit to execlists whilst a preempt is pending

To complement the check in execlists_elsp_ready(), also assert that we don't submit the same context while it has a lite restore still pending. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

On Mon, Jan 23, 2017 at 01:05:57PM +, Chris Wilson wrote: > This w/a was only used for preproduction hw, which is no longer in use. > Remove the workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala >

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Remove BXT disable pixel mask clamping w/a

On ma, 2017-01-23 at 13:05 +, Chris Wilson wrote: > This w/a (WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken) was only > used for preproduction hw, which is no longer in use. Remove the > workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc:

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

On ma, 2017-01-23 at 13:05 +, Chris Wilson wrote: > This w/a was only used for preproduction hw, which is no longer in use. > Remove the workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Joonas

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Only run execlist context-switch handler after an interrupt

On Mon, Jan 23, 2017 at 12:14:26PM +, Chris Wilson wrote: > Mark when we run the execlist tasklet following the interrupt, so we > don't probe a potentially initialised register when submitting the s/initialised/uninitialised/! -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH i-g-t 5/5] tests/kms_test_only: Validate TEST_ONLY correctness against full atomic commit

On Thu, 2017-01-12 at 12:37 +0100, Maarten Lankhorst wrote: > Hey, > > Op 12-01-17 om 11:28 schreef Mika Kahola: > > > > On Thu, 2017-01-12 at 11:11 +0100, Maarten Lankhorst wrote: > > > > > > Op 30-12-16 om 13:00 schreef Mika Kahola: > > > > > > > > This test case adds TEST_ONLY flag to the

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915: Only disable execlist preemption for the duration of the request

== Series Details == Series: series starting with [v2,1/5] drm/i915: Only disable execlist preemption for the duration of the request URL : https://patchwork.freedesktop.org/series/18403/ State : success == Summary == Series 18403v1 Series without cover letter

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Remove BXT TDL state w/a

On ma, 2017-01-23 at 13:06 +, Chris Wilson wrote: > This w/a (WaClearTdlStateAckDirtyBits) was only used for preproduction hw, > which is no longer in use. Remove the workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

On Mon, Jan 23, 2017 at 01:05:56PM +, Chris Wilson wrote: > This w/a was only used for preproduction hw, which is no longer in use. > Remove the workaround to simplify the code. Note to self, remember to include WaEnableForceRestoreInCtxtDescForVCS -Chris -- Chris Wilson, Intel Open Source

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Remove BXT restore arbitration around ctx switch

On ma, 2017-01-23 at 13:05 +, Chris Wilson wrote: > This w/a (WaDisableCtxRestoreArbitration) was only used for preproduction > hw, which is no longer in use. Remove the workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

On ma, 2017-01-23 at 13:05 +, Chris Wilson wrote: > This w/a was only used for preproduction hw, which is no longer in use. > Remove the workaround to simplify the code. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Joonas

[Intel-gfx] [PATCH 5/6] drm/i915: Remove BXT TDL state w/a

This w/a (WaClearTdlStateAckDirtyBits) was only used for preproduction hw, which is no longer in use. Remove the workaround to simplify the code. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 4/6] drm/i915: Remove BXT disable pixel mask clamping w/a

This w/a (WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken) was only used for preproduction hw, which is no longer in use. Remove the workaround to simplify the code. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 3/6] drm/i915: Remove BXT restore arbitration around ctx switch

This w/a (WaDisableCtxRestoreArbitration) was only used for preproduction hw, which is no longer in use. Remove the workaround to simplify the code. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

This w/a was only used for preproduction hw, which is no longer in use. Remove the workaround to simplify the code. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 6/6] drm/i915: Remove unused per-bb wa_ctx for gen9

Stop creating and emitting the wa_ctx per-bb as it is no longer used. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 37 + 1 file changed, 13 insertions(+), 24 deletions(-) diff --git

[Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

This w/a was only used for preproduction hw, which is no longer in use. Remove the workaround to simplify the code. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: Only disable execlist preemption for the duration of the request

On Mon, Jan 23, 2017 at 02:33:20PM +0200, Mika Kuoppala wrote: > Chris Wilson writes: > > > On Mon, Jan 23, 2017 at 12:14:25PM +, Chris Wilson wrote: > >> @@ -558,7 +558,8 @@ static bool execlists_elsp_ready(struct > >> intel_engine_cs *engine) > >>int port; >

Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: Only disable execlist preemption for the duration of the request

Chris Wilson writes: > On Mon, Jan 23, 2017 at 12:14:25PM +, Chris Wilson wrote: >> @@ -558,7 +558,8 @@ static bool execlists_elsp_ready(struct intel_engine_cs >> *engine) >> int port; >> >> port = 1; /* wait for a free slot */ >> -if

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915: Assert that the kernel_context is hw-id 0

On Mon, Jan 23, 2017 at 12:22:52PM -, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/2] drm/i915: Assert that the > kernel_context is hw-id 0 > URL : https://patchwork.freedesktop.org/series/18402/ > State : warning > > == Summary == > > Series 18402v1

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Skip the execlists CSB scan and rewrite if the ring is untouched

On Mon, Jan 23, 2017 at 12:14:27PM +, Chris Wilson wrote: > If the CSB head/tail pointers are unchanged, we can skip the update of > the CSB register afterwards. > > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --

Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: Only disable execlist preemption for the duration of the request

On Mon, Jan 23, 2017 at 12:14:25PM +, Chris Wilson wrote: > @@ -558,7 +558,8 @@ static bool execlists_elsp_ready(struct intel_engine_cs > *engine) > int port; > > port = 1; /* wait for a free slot */ > - if (engine->disable_lite_restore_wa || engine->preempt_wa) > + if

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915: Assert that the kernel_context is hw-id 0

== Series Details == Series: series starting with [CI,1/2] drm/i915: Assert that the kernel_context is hw-id 0 URL : https://patchwork.freedesktop.org/series/18402/ State : warning == Summary == Series 18402v1 Series without cover letter

[Intel-gfx] [PATCH v2 3/5] drm/i915: Skip the execlists CSB scan and rewrite if the ring is untouched

If the CSB head/tail pointers are unchanged, we can skip the update of the CSB register afterwards. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH v2 5/5] drm/i915: Emit dma-fence (and execlists submit) first from signaler

When introduced, I thought that reducing client latency from the signaler was the priority. Since its inception the signaler has become responsible for keeping the execlists full, via the dma-fence. As this is very important to minimise overall execution time, signal the dma-fence first and then

[Intel-gfx] [PATCH v2 4/5] drm/i915: Dequeue execlists on a new request if any port is available

If the second ELSP port is available, schedule the execlists tasklet to see if the new request can occupy it. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin ---

[Intel-gfx] [PATCH v2 2/5] drm/i915: Only run execlist context-switch handler after an interrupt

Mark when we run the execlist tasklet following the interrupt, so we don't probe a potentially initialised register when submitting the contexts multiple times. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_irq.c | 7 +--

[Intel-gfx] [PATCH v2 1/5] drm/i915: Only disable execlist preemption for the duration of the request

We need to prevent resubmission of the context immediately following an initial resubmit (which does a lite-restore preemption). Currently we do this by disabling all submission whilst the context is still active, but we can improve this by limiting the restriction to only until we receive

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Split intel_engine allocation and initialisation

On ma, 2017-01-23 at 09:57 +, Chris Wilson wrote: > On Mon, Jan 23, 2017 at 11:41:12AM +0200, Joonas Lahtinen wrote: > > > > On la, 2017-01-21 at 14:50 +, Chris Wilson wrote: > > > > > > In order to reset the GPU early on in the module load sequence, we need > > > to allocate the basic

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Priority boost switching to an idle ring

On Mon, Jan 23, 2017 at 11:50:47AM +, Tvrtko Ursulin wrote: > > On 23/01/2017 11:16, Chris Wilson wrote: > >On Mon, Jan 23, 2017 at 10:51:28AM +, Tvrtko Ursulin wrote: > >> > >>On 21/01/2017 09:25, Chris Wilson wrote: > >>>In order to maximise concurrency between engines, if we queue a

Re: [Intel-gfx] [CI 2/2] drm/i915: Assert that the context-switch completion matches our context

On 23/01/2017 11:31, Chris Wilson wrote: When execlists signals the context completion, it also provides the context id for the status event. Assert that id matches the one we expect. v2: The upper dword of the context status is a duplicate of the upper dword from elsp submission (i.e.

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Priority boost for locked waits

On 23/01/2017 11:50, Chris Wilson wrote: On Mon, Jan 23, 2017 at 11:41:03AM +, Tvrtko Ursulin wrote: On 23/01/2017 10:51, Chris Wilson wrote: On Mon, Jan 23, 2017 at 10:43:10AM +, Tvrtko Ursulin wrote: @@ -3285,6 +3291,7 @@ int i915_gem_object_set_cache_level(struct

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/color: un-inline drm_color_lut_extract()

== Series Details == Series: drm/color: un-inline drm_color_lut_extract() URL : https://patchwork.freedesktop.org/series/18391/ State : failure == Summary == Series 18391v1 drm/color: un-inline drm_color_lut_extract() https://patchwork.freedesktop.org/api/1.0/series/18391/revisions/1/mbox/

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Priority boost switching to an idle ring

On 23/01/2017 11:16, Chris Wilson wrote: On Mon, Jan 23, 2017 at 10:51:28AM +, Tvrtko Ursulin wrote: On 21/01/2017 09:25, Chris Wilson wrote: In order to maximise concurrency between engines, if we queue a request to a current idle ring, reorder its dependencies to execute that request

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Priority boost for locked waits

On Mon, Jan 23, 2017 at 11:41:03AM +, Tvrtko Ursulin wrote: > > On 23/01/2017 10:51, Chris Wilson wrote: > >On Mon, Jan 23, 2017 at 10:43:10AM +, Tvrtko Ursulin wrote: > >>>@@ -3285,6 +3291,7 @@ int i915_gem_object_set_cache_level(struct > >>>drm_i915_gem_object *obj, > >>> ret

Re: [Intel-gfx] [CI 2/2] drm/i915: Assert that the context-switch completion matches our context

On ma, 2017-01-23 at 11:31 +, Chris Wilson wrote: > When execlists signals the context completion, it also provides the > context id for the status event. Assert that id matches the one we expect. > > v2: The upper dword of the context status is a duplicate of the upper > dword from elsp

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Skip the execlists CSB scan and rewrite if the ring is untouched

On Mon, Jan 23, 2017 at 01:33:32PM +0200, Joonas Lahtinen wrote: > On la, 2017-01-21 at 09:28 +, Chris Wilson wrote: > > If the CSB head/tail pointers are unchanged, we can skip the update of > > the CSB register afterwards. > > > > Signed-off-by: Chris Wilson > >

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Priority boost for locked waits

On 23/01/2017 10:51, Chris Wilson wrote: On Mon, Jan 23, 2017 at 10:43:10AM +, Tvrtko Ursulin wrote: @@ -3285,6 +3291,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, ret = i915_gem_object_wait(obj,

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Emit dma-fence (and execlists submit) first from signaler

On la, 2017-01-21 at 09:28 +, Chris Wilson wrote: > When introduced, I thought that reducing client latency from the > signaler was the priority. Since its inception the signaler has become > responsible for keeping the execlists full, via the dma-fence. As this > is very important to minimise

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