== Series Details ==
Series: drm/i915/gvt: dma-buf support for GVT-g (rev4)
URL : https://patchwork.freedesktop.org/series/23686/
State : failure
== Summary ==
Series 23686v4 drm/i915/gvt: dma-buf support for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/23686/revisions/4/mbox/
Test
On 22/05/17 10:59 PM, Daniel Vetter wrote:
> I failed to properly onion-wrap the unwind code: We acquire the vblank
> reference before we start with the wait-wound locking dance, hence we
> must make sure we retry before we drop the reference. Oops.
>
> v2: The vblank_put must be after the frambuf
User space will try to create a management fd for the dma-buf operation.
Using this management fd user can query the plane information and create
a dma-buf fd if necessary.
GVT-g will handle the life cycle of the management fd and will align the
life cycle of the fd with the vfio device.
User space
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/dr
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode
decode frambuffer attributes of primary, cursor and sprite plane
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 487 ++
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++
v3->v4:
1) fix bug while checking whether the gem obj is gvt's dma-buf when set
caching mode or doamins.
2) add more comments for patch set.
v2->v3:
1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save
the decoded plane information to avoid look up while need the plane info.
2)
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/intel_display.c
between commits:
1cecc830e6b6 ("drm/i915: Refactor CURBASE calculation")
024faac7d59b ("drm/i915: Support variable cursor height on ivb+")
from the drm-intel tree and commit:
== Series Details ==
Series: drm/i915: Disable GEN9LP decoupled mmio (rev2)
URL : https://patchwork.freedesktop.org/series/24803/
State : success
== Summary ==
Series 24803v2 drm/i915: Disable GEN9LP decoupled mmio
https://patchwork.freedesktop.org/api/1.0/series/24803/revisions/2/mbox/
Test
== Series Details ==
Series: drm/i915: Disable decoupled mmio for GEN9LP (rev4)
URL : https://patchwork.freedesktop.org/series/24470/
State : failure
== Summary ==
Series 24470v4 drm/i915: Disable decoupled mmio for GEN9LP
https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/4/mbox
From: Kai Chen
This change is used as a backport fix from top of drm-intel ([PATCH]
drm/i915: Disable decoupled mmio for GEN9LP) to disable decoupled mmio
on GEN9LP for those shipped kernels as a quick fix.
V2:
- Add signed-off-by
Signed-off-by: Kai Chen
---
drivers/gpu/drm/i915/i915_pci.c |
== Series Details ==
Series: drm/i915: Disable GEN9LP decoupled mmio
URL : https://patchwork.freedesktop.org/series/24803/
State : success
== Summary ==
Series 24803v1 drm/i915: Disable GEN9LP decoupled mmio
https://patchwork.freedesktop.org/api/1.0/series/24803/revisions/1/mbox/
Test kms_fli
From: Kai Chen
The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.
v2:
- Remove dead code related to GEN9LP decoupled mmio.
- Change backgrounds: In theory, decoupled mmio shou
On 22/05/17 15:07, Michał Winiarski wrote:
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission por
From: Kai Chen
This change is used as a backport fix from top of drm-intel ([PATCH]
drm/i915: Disable decoupled mmio for GEN9LP) to disable decoupled mmio
on GEN9LP for those shipped kernels as a quick fix.
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/dr
== Series Details ==
Series: drm/i915: Disable decoupled mmio for GEN9LP (rev3)
URL : https://patchwork.freedesktop.org/series/24470/
State : success
== Summary ==
Series 24470v3 drm/i915: Disable decoupled mmio for GEN9LP
https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/3/mbox
From: Kai Chen
The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.
v2:
- Remove dead code related to GEN9LP decoupled mmio.
- Change backgrounds: In theory, decoupled mmio shou
== Series Details ==
Series: series starting with [v2,1/8] drm/i915: Remove misleading comment in
request_alloc
URL : https://patchwork.freedesktop.org/series/24801/
State : failure
== Summary ==
Series 24801v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/24801
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, May 22, 2017 1:05 PM
> To: Bloomfield, Jon
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT
>
> On Mon, May 22, 2017 at 11:07:25AM -07
We'd like to reuse the priolist lookup in request resubmission path,
let's split insert_request to make that happen.
v2: Handle allocation error in lookup rather than in caller (Chris)
Cc: Chris Wilson
Cc: Jeff McGee
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Signed-off-by: Michał Winiarski
---
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e36..9dcc8a0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@
Now that we're able to unsubmit requests, we can take advantage of it
during reset. Rather than resubmitting the previous workload directly to
GuC/ELSP, we can simply move the requests back to priority queue,
submitting from the tasklet instead.
v2: Move the tasklet schedule out for legacy ringbuf
Now that we have an upper bound on the number of work items being sent
to GuC, we can remove the reservation.
v2: Multiply by number of engines in compile time assert (Daniele)
v3: Comment on reasoning behind the compile time assert (Chris)
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Jeff M
Since request can be unsubmitted, we need to avoid overriding its priority
during submission. Otherwise we won't be able to resubmit it with
correct priority.
v2: Limit DFS by excluding completed requests (Chris)
Cc: Chris Wilson
Cc: Jeff McGee
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Signed-of
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're
If port[0] is occupied and we're trying to dequeue request from
different context, we will inevitably hit BUG_ON in port_assign.
Let's skip it - similar to what we're doing in execlists counterpart.
Fixes: 77f0d0e925e8a0 ("drm/i915/execlists: Pack the count into the low bits of
the port.request")
Passing NULL ctx to request_alloc would lead to null-ptr-deref.
v2: Let's not replace the comment with a BUG_ON
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_request.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gp
On Fri, May 19, 2017 at 11:08:05AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 19/05/17 06:23, Michał Winiarski wrote:
> > To create an upper bound on number of GuC workitems, we need to change
> > the way that requests are being submitted. Rather than submitting each
> > request as an individu
Chris,
I tested this together with your v3 (Mark cache dirty...)
patch and verified tests are all passing.
Tested-by : Dongwon Kim
On Thu, May 18, 2017 at 10:46:17AM +0100, Chris Wilson wrote:
> For ease of use (i.e. avoiding a few checks and function calls), store
> the object's cache coheren
On Mon, May 22, 2017 at 11:07:25AM -0700, Jon Bloomfield wrote:
> BXT requires accesses to the GTT (i.e. PTE updates) to be serialized
> when IOMMU is enabled.
Serialised with what, since all writes are serialized already?
The reason is that you need to explain the hw model you are protecting,
fo
On Mon, May 22, 2017 at 10:50:28AM -0700, Daniele Ceraolo Spurio wrote:
> We're currently deleting the GuC logs if the FW fails to load, but those
> are still useful to understand why the loading failed. Keeping the
> object around allows us to access them after driver load is completed.
>
> v2: k
On Tue, May 16, 2017 at 12:10:42PM +0100, Chris Wilson wrote:
> Constructing the name takes the majority of the time for allocating a
> sync_file to wrap a fence, and the name is very rarely used (only via
> the sync_file status user interface). To reduce the impact on the common
> path (that of cr
On Thu, 2017-05-04 at 12:21 +0300, Andy Shevchenko wrote:
> acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16
> bytes. Instead we convert them to use uuid_le type. At the same time
> we
> convert current users.
>
> acpi_str_to_uuid() becomes useless after the conversion and it's
On 05/17, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
Hmm, are we not missing the GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS
part, so disabling slice/unslice clock ratio change reports, like we do
on all other gen9 platforms?
For the timestamp base are we just assuming it's the same
2017-05-22 16:59 GMT+03:00 Daniel Vetter :
> I failed to properly onion-wrap the unwind code: We acquire the vblank
> reference before we start with the wait-wound locking dance, hence we
> must make sure we retry before we drop the reference. Oops.
>
> v2: The vblank_put must be after the frambuff
On 22/05/17 11:21, Patchwork wrote:
== Series Details ==
Series: drm/i915/guc: capture GuC logs if FW fails to load (rev6)
URL : https://patchwork.freedesktop.org/series/23982/
State : warning
== Summary ==
Series 23982v6 drm/i915/guc: capture GuC logs if FW fails to load
https://patchwork
== Series Details ==
Series: drm/i915: Serialize GTT Updates on BXT
URL : https://patchwork.freedesktop.org/series/24793/
State : success
== Summary ==
Series 24793v1 drm/i915: Serialize GTT Updates on BXT
https://patchwork.freedesktop.org/api/1.0/series/24793/revisions/1/mbox/
Test gem_exec_
== Series Details ==
Series: drm/i915/guc: capture GuC logs if FW fails to load (rev6)
URL : https://patchwork.freedesktop.org/series/23982/
State : warning
== Summary ==
Series 23982v6 drm/i915/guc: capture GuC logs if FW fails to load
https://patchwork.freedesktop.org/api/1.0/series/23982/re
BXT requires accesses to the GTT (i.e. PTE updates) to be serialized
when IOMMU is enabled. This patch guarantees this by wrapping all
updates in stop_machine and using a flushing read to guarantee that
the GTT writes have reached their destination before restarting.
Signed-off-by: Jon Bloomfield
== Series Details ==
Series: Gen8+ engine-reset (rev11)
URL : https://patchwork.freedesktop.org/series/21868/
State : success
== Summary ==
Series 21868v11 Gen8+ engine-reset
https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/11/mbox/
Test kms_flip:
Subgroup basic-flip-v
On 22/05/17 17:51, Matthew Auld wrote:
On 05/17, Lionel Landwerlin wrote:
Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mech
We're currently deleting the GuC logs if the FW fails to load, but those
are still useful to understand why the loading failed. Keeping the
object around allows us to access them after driver load is completed.
v2: keep the object around instead of using kernel memory (chris)
don't store the l
intel_guc_reset sounds more like the microcontroller is the one performing
a reset, while in this case is the opposite. intel_reset_guc not only
makes it clearer, it follows the other intel_reset functions available.
v2: Print error message in English.
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursu
Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.
v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_start. Request space of
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
A follow-up patch will provide this information in debugfs.
v2: s/engine_reset/rese
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of registers that we want GuC to save and
restore. This is not an issue in case of engine reset as driver initializes
most of
For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).
This information should be in DWORD 9 of the GUC_CTL structure.
v2: Use guc_ggtt_offset (Chris).
Store the ggtt offset of the default ctx as we needed for
suspend/resume
Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.
To start the discussion, include just a total engine reset count. If it
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.
The recommended default watchdog threshold for video engines is 6 us,
*** General ***
Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to support this form of hang
We try to get the engines ready/idle before triggering the reset, but it
has been seen that sometimes the hw never acknowledges this.
If we miss the acknowledgment, carry on with the reset instead of
leaving the GPU in a wedged state.
The frequency of missed acknowledgment from hw is low, but it
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 6 +++---
dri
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission. With GuC submission these tasks
are shared between driver and GuC. i915 is still respo
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2
Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.
v2: rebase.
v3: use RESET_ENGINE_IN_PROGRESS flag.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 149 +++
1 file changed, 149 inse
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.
Hangchecker determines which engines are hung and invokes er
From: Daniele Ceraolo Spurio
The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
register the GuC can use to restore the provided whitelist when an
engine reset via GuC (which we still don't support) is triggered.
We're currently adding the mmio_base of the engine to the absolu
These patches add the reset-engine feature from Gen8. This is also
referred to as Timeout detection and recovery (TDR). This complements to
the full gpu reset feature available in i915 but it only allows to reset a
particular engine instead of all engines thus providing a light weight
engine reset
And store the active request so that we only search for it once.
v2: Check for request completion inside _prepare_engine, don't use
ECANCELED, remove unnecessary null checks (Chris).
v3: Capture active requests during reset_prepare and store it the
engine hangcheck obj.
v4: Rename commit, change
From firmware v8.8, GuC provides the count of media engine resets
(watchdog timeout). This information is available in the GuC shared
context data struct, which resides in the first page of the default
(kernel) lrc context.
Since GuC handled engine resets are transparent for kernel and user,
provi
Save the watchdog threshold (in us) as part of the engine state.
v2: Only do it for gen8+ (and prevent a missing-case warn).
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 12
2 files changed, 9 insertions(+),
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they are expected to trigger reset; these counts are checked before
and after the test to ensure the same.
v2: Include reset engine count in i915_engin
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at this point
because co
On 05/17, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
With a proper commit message:
Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
On 05/17, Lionel Landwerlin wrote:
> Gen8+ might have mux configurations per slices/subslices. Depending on
> whether slices/subslices have been fused off, only part of the
> configuration needs to be applied. This change reworks the mux
> configurations query mechanism to allow more than one set o
On Fri, May 19, 2017 at 04:50:17PM -0400, Robert Foss wrote:
> Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
> as a convenience.
>
> Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
> through the atomic API, but realizing that userspace is likely to take
> short
On 22 May 2017 at 13:21, Chris Wilson wrote:
> The compiler doesn't always spot the guard that object is allocated on
> the first pass, leading to:
>
> drivers/gpu/drm/i915/selftests/i915_gem_context.c: warning: 'obj' may be used
> uninitialized in this function [-Wuninitialized]: => 370:8
>
> R
== Series Details ==
Series: drm: Fix deadlock retry loop in page_flip_ioctl (rev2)
URL : https://patchwork.freedesktop.org/series/24773/
State : warning
== Summary ==
Series 24773v2 drm: Fix deadlock retry loop in page_flip_ioctl
https://patchwork.freedesktop.org/api/1.0/series/24773/revision
I failed to properly onion-wrap the unwind code: We acquire the vblank
reference before we start with the wait-wound locking dance, hence we
must make sure we retry before we drop the reference. Oops.
v2: The vblank_put must be after the frambuffer_put (Michel). I suck at
unwrapping code that does
On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
There is no confirmation if the DC5 to DC6 is available on CNL
though. But I could see DC3 to DC5 counter increasing reliably.
So let's at least add this one.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
1 file cha
== Series Details ==
Series: drm/i915/selftests: Silence compiler warning in igt_ctx_exec
URL : https://patchwork.freedesktop.org/series/24787/
State : warning
== Summary ==
Series 24787v1 drm/i915/selftests: Silence compiler warning in igt_ctx_exec
https://patchwork.freedesktop.org/api/1.0/se
The compiler doesn't always spot the guard that object is allocated on
the first pass, leading to:
drivers/gpu/drm/i915/selftests/i915_gem_context.c: warning: 'obj' may be used
uninitialized in this function [-Wuninitialized]: => 370:8
Reported-by: Geert Uytterhoeven
Fixes: 791ff39ae32a ("drm/
Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.
Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so
== Series Details ==
Series: Introduce buffer based cmd transport
URL : https://patchwork.freedesktop.org/series/24786/
State : success
== Summary ==
Series 24786v1 Introduce buffer based cmd transport
https://patchwork.freedesktop.org/api/1.0/series/24786/revisions/1/mbox/
fi-bdw-5557u t
Buffer based command transport can replace MMIO based mechanism.
It may be used to perform host-2-guc and guc-to-host communication.
Portions of this patch are based on work by:
Michel Thierry
Robert Beckett
Daniele Ceraolo Spurio
v2: use gem_object_pin_map (Chris)
don't use DEBUG_RATEL
This series is same as [1] but this time without enabling GuC
submission, as Guc submission is not working due to other changes.
[1] https://patchwork.freedesktop.org/series/24715/
Michal Wajdeczko (2):
drm/i915/guc: Disable send function on fini
drm/i915/guc: Introduce buffer based cmd trans
In earlier patch 789a625 we were enabling send function only
after successful init. For completeness, we should make sure
that we disable it on fini.
v2: don't group steps by submission flag (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
== Series Details ==
Series: drm/i915/gvt: dma-buf support for GVT-g (rev3)
URL : https://patchwork.freedesktop.org/series/23686/
State : failure
== Summary ==
Series 23686v3 drm/i915/gvt: dma-buf support for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/23686/revisions/3/mbox/
Test
On Mon, May 22, 2017 at 11:51:27AM +0100, Tvrtko Ursulin wrote:
>
> On 18/05/2017 10:46, Chris Wilson wrote:
> >Keep the recently freed context objects for reuse. This allows us to use
> >the current GGTT bindings and dma bound pages, avoiding any clflushes as
> >required. We mark the objects as p
== Series Details ==
Series: drm/i915/gvt: remove redundant -Wall
URL : https://patchwork.freedesktop.org/series/24779/
State : success
== Summary ==
Series 24779v1 drm/i915/gvt: remove redundant -Wall
https://patchwork.freedesktop.org/api/1.0/series/24779/revisions/1/mbox/
fi-bdw-5557u t
On 18/05/2017 10:46, Chris Wilson wrote:
Keep the recently freed context objects for reuse. This allows us to use
the current GGTT bindings and dma bound pages, avoiding any clflushes as
required. We mark the objects as purgeable under memory pressure, and
reap the list of freed objects as soon
On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
Since we have HAS_CSR tied to the platform definition
let's use this instead of checking per platform.
One less thing to worry when adding support to new platforms.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file ch
On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
From: Anusha Srivatsa
This patch loads the DMC on CNL.The firmware version
is 1.04.
v2: (Rodrigo) Remove MODULE_FIRMWARE.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
== Series Details ==
Series: drm/i915: mark wait_for_engine() __maybe_unused
URL : https://patchwork.freedesktop.org/series/24778/
State : success
== Summary ==
Series 24778v1 drm/i915: mark wait_for_engine() __maybe_unused
https://patchwork.freedesktop.org/api/1.0/series/24778/revisions/1/mbo
== Series Details ==
Series: drm/i915/gen3: Improve reset reliability
URL : https://patchwork.freedesktop.org/series/24777/
State : success
== Summary ==
Series 24777v1 drm/i915/gen3: Improve reset reliability
https://patchwork.freedesktop.org/api/1.0/series/24777/revisions/1/mbox/
Test gem_e
On 2017.05.19 23:35:03 +0800, Weinan Li wrote:
> I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
> In gvt environment, each vm only use the ballooned part of aperture, so we
> should return the correct available aperture size exclude the reserved part
> by balloon.
pls
On Mon, May 15, 2017 at 04:03:50PM +0200, Daniel Vetter wrote:
> What would probably help the CI folks is a gem testcase list that includes
> all the important stuff (so much more than BAT), but also completes in a
> reasonable amount of time (2h as a goal might be good). Atm not even
> excluding g
On Mon, May 15, 2017 at 04:03:50PM +0200, Daniel Vetter wrote:
> On Thu, May 11, 2017 at 12:13:44AM +0100, Chris Wilson wrote:
> > We have no coverage of sign-extended relocations in BAT, so provide
> > some.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Petri Latvala
>
> There's a metric ton of
User space will try to create a management fd for the dma-buf operation.
Using this management fd user can query the plane information and create
a dma-buf fd if necessary.
GVT-g will handle the life cycle of the management fd and will align the
life cycle of the fd with the vfio device.
User space
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/dr
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode
v2->v3:
1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save
the decoded plane information to avoid look up while need the plane info.
2) declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
to represent the gem obj for gvt's dma-buf. The tiling mode, caching m
decode frambuffer attributes of primary, cursor and sprite plane
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 487 ++
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++
On Tue, May 16, 2017 at 12:10:42PM +0100, Chris Wilson wrote:
> Constructing the name takes the majority of the time for allocating a
> sync_file to wrap a fence, and the name is very rarely used (only via
> the sync_file status user interface). To reduce the impact on the common
> path (that of cr
On Mon, May 22, 2017 at 12:02:44PM +0300, Mika Kuoppala wrote:
> We improved the reset reliablity on gen4 with
> stopping all engines before commencing reset, in
> commit 2c80353f3cd0 ("drm/i915/g4x: Improve gpu reset reliability")
>
> Evidence indicates that this same trick works with gen3.
Note
== Series Details ==
Series: drm/i915: Allow kswapd to pause the device whilst reaping
URL : https://patchwork.freedesktop.org/series/24776/
State : success
== Summary ==
Series 24776v1 drm/i915: Allow kswapd to pause the device whilst reaping
https://patchwork.freedesktop.org/api/1.0/series/2
On Mon, May 22, 2017 at 10:55:01AM +0200, Daniel Vetter wrote:
> On Wed, May 17, 2017 at 02:02:50PM +0100, Chris Wilson wrote:
> > Older gen use a physical address for the hardware status page, for which
> > we use cache-coherent writes. As the writes are into the cpu cache, we use
> > a normal WB
On Mon, May 22, 2017 at 09:51:22AM +0200, Daniel Vetter wrote:
> On Fri, May 19, 2017 at 04:50:17PM -0400, Robert Foss wrote:
> > Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
> > as a convenience.
> >
> > Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
> > thr
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