[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: dma-buf support for GVT-g (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: dma-buf support for GVT-g (rev4)
URL   : https://patchwork.freedesktop.org/series/23686/
State : failure

== Summary ==

Series 23686v4 drm/i915/gvt: dma-buf support for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/23686/revisions/4/mbox/

Test gem_busy:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
Subgroup basic-hang-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
Test gem_exec_basic:
Subgroup gtt-blt:

Re: [Intel-gfx] [PATCH] drm: Fix deadlock retry loop in page_flip_ioctl

[Michel Dänzer]

On 22/05/17 10:59 PM, Daniel Vetter wrote:
> I failed to properly onion-wrap the unwind code: We acquire the vblank
> reference before we start with the wait-wound locking dance, hence we
> must make sure we retry before we drop the reference. Oops.
> 
> v2: The vblank_put must be after the frambuffer_put (Michel). I suck at
> unwrapping code that doesn't use separate labels for each stage, but
> checks each pointer first ... While re-reading everything I also
> realized that we must clean up the fb refcounts, and specifically
> plane->old_fb before we drop the locks, either in the final unlocking,
> or in the w/w retry path. Hence the correct fix is to drop the
> vblank_put to the very bottom.
> 
> Fixes: 29dc0d1de182 ("drm: Roll out acquire context for the page_flip ioctl")
> Cc: Harry Wentland 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: David Airlie 
> Cc: dri-de...@lists.freedesktop.org
> Reported-by: Tommi Rantala 
> Cc: Tommi Rantala 
> Cc: Michel Dänzer 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/drm_plane.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index fedd4d60d9cd..5dc8c4350602 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -948,8 +948,6 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
>   }
>  
>  out:
> - if (ret && crtc->funcs->page_flip_target)
> - drm_crtc_vblank_put(crtc);
>   if (fb)
>   drm_framebuffer_put(fb);
>   if (crtc->primary->old_fb)
> @@ -964,5 +962,8 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
>   drm_modeset_drop_locks();
>   drm_modeset_acquire_fini();
>  
> + if (ret && crtc->funcs->page_flip_target)
> + drm_crtc_vblank_put(crtc);
> +
>   return ret;
>  }
> 

Reviewed-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
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[Intel-gfx] [PATCH v4 5/5] drm/i915/gvt: Adding interface so user space can get the dma-buf

[Xiaoguang Chen]

User space will try to create a management fd for the dma-buf operation.
Using this management fd user can query the plane information and create
a dma-buf fd if necessary.
GVT-g will handle the life cycle of the management fd and will align the
life cycle of the fd with the vfio device.
User space should handle the life cycle of the created dma-buf fd close
the dma-buf fd timely when finishing use.

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/dmabuf.c | 23 ++-
 drivers/gpu/drm/i915/gvt/dmabuf.h | 22 --
 drivers/gpu/drm/i915/gvt/gvt.c|  2 +
 drivers/gpu/drm/i915/gvt/gvt.h|  3 ++
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 87 +++
 include/uapi/linux/vfio.h | 36 
 6 files changed, 140 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index c9f283c..c74762f 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -29,6 +29,7 @@
 
 #include 
 #include 
+#include 
 
 #include "i915_drv.h"
 #include "gvt.h"
@@ -45,9 +46,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
int i, ret;
gen8_pte_t __iomem *gtt_entries;
unsigned int fb_gma = 0, fb_size = 0;
-   struct intel_vgpu_plane_info *plane_info;
+   struct plane_info *plane_info;
 
-   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   plane_info = (struct plane_info *)obj->gvt_plane_info;
if (WARN_ON(!plane_info))
return ERR_PTR(-EINVAL);
 
@@ -81,9 +82,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
 static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
 {
-   struct intel_vgpu_plane_info *plane_info;
+   struct plane_info *plane_info;
 
-   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   plane_info = (struct plane_info *)obj->gvt_plane_info;
if (WARN_ON(!plane_info))
return;
 
@@ -98,7 +99,7 @@ static const struct drm_i915_gem_object_ops 
intel_vgpu_gem_ops = {
 };
 
 static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device 
*dev,
-   struct intel_vgpu_plane_info *info)
+   struct plane_info *info)
 {
struct drm_i915_private *pri = dev->dev_private;
struct drm_i915_gem_object *obj;
@@ -141,14 +142,14 @@ static struct drm_i915_gem_object 
*intel_vgpu_create_gem(struct drm_device *dev,
return obj;
 }
 
-static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
+static struct plane_info *intel_vgpu_get_plane_info(
struct drm_device *dev,
struct intel_vgpu *vgpu, int plane_id)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_vgpu_primary_plane_format *p;
struct intel_vgpu_cursor_plane_format *c;
-   struct intel_vgpu_plane_info *info;
+   struct plane_info *info;
 
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info)
@@ -225,8 +226,8 @@ static struct intel_vgpu_plane_info 
*intel_vgpu_get_plane_info(
 int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args)
 {
struct drm_device *dev = >gvt->dev_priv->drm;
-   struct intel_vgpu_dmabuf *gvt_dmabuf = args;
-   struct intel_vgpu_plane_info *info;
+   struct dmabuf_info *gvt_dmabuf = args;
+   struct plane_info *info;
 
info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
if (info == NULL)
@@ -242,8 +243,8 @@ int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void 
*args)
struct dma_buf *dmabuf;
struct drm_i915_gem_object *obj;
struct drm_device *dev = >gvt->dev_priv->drm;
-   struct intel_vgpu_dmabuf *gvt_dmabuf = args;
-   struct intel_vgpu_plane_info *info;
+   struct dmabuf_info *gvt_dmabuf = args;
+   struct plane_info *info;
int ret;
 
info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h 
b/drivers/gpu/drm/i915/gvt/dmabuf.h
index c7ce642..0ddea78 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.h
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
@@ -26,28 +26,6 @@
 #ifndef _GVT_DMABUF_H_
 #define _GVT_DMABUF_H_
 
-struct intel_vgpu_plane_info {
-   uint32_t drm_format;
-   uint32_t width;
-   uint32_t height;
-   uint32_t stride;
-   uint32_t start;
-   uint32_t x_pos;
-   uint32_t y_pos;
-   uint32_t size;
-   uint64_t drm_format_mod;
-};
-
-#define INTEL_VGPU_QUERY_DMABUF0
-#define INTEL_VGPU_GENERATE_DMABUF 1
-
-struct intel_vgpu_dmabuf {
-   uint32_t plane_id;
-   /* out */
-   uint32_t fd;
-   struct intel_vgpu_plane_info plane_info;
-};
-
 int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args);
 int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
 

[Intel-gfx] [PATCH v4 2/5] drm/i915/gvt: OpRegion support for GVT-g

[Xiaoguang Chen]

OpRegion is needed to support display related operation for
intel vgpu.

A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.

Signed-off-by: Bing Niu 
Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c| 97 +
 drivers/gpu/drm/i915/gvt/opregion.c |  8 ++-
 2 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3c6a02b..389f072 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,6 +53,8 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
 struct vfio_region;
 struct intel_vgpu_regops {
size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
@@ -436,6 +438,92 @@ static void kvmgt_protect_table_del(struct 
kvmgt_guest_info *info,
}
 }
 
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite)
+{
+   unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+   VFIO_PCI_NUM_REGIONS;
+   void *base = vgpu->vdev.region[i].data;
+   loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+   if (pos >= vgpu->vdev.region[i].size || iswrite) {
+   gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+   return -EINVAL;
+   }
+   count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+   memcpy(buf, base + pos, count);
+
+   return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+   struct vfio_region *region)
+{
+   memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+   .rw = intel_vgpu_reg_rw_opregion,
+   .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+   unsigned int type, unsigned int subtype,
+   const struct intel_vgpu_regops *ops,
+   size_t size, u32 flags, void *data)
+{
+   struct vfio_region *region;
+
+   region = krealloc(vgpu->vdev.region,
+   (vgpu->vdev.num_regions + 1) * sizeof(*region),
+   GFP_KERNEL);
+   if (!region)
+   return -ENOMEM;
+
+   vgpu->vdev.region = region;
+   vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+   vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+   vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+   vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+   vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+   vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+   vgpu->vdev.num_regions++;
+
+   return 0;
+}
+
+static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
+{
+   unsigned int addr;
+   void *base;
+   int ret;
+
+   addr = vgpu->gvt->opregion.opregion_pa;
+   if (!addr || !(~addr))
+   return -ENODEV;
+
+   base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+   if (!base)
+   return -ENOMEM;
+
+   if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+   memunmap(base);
+   return -EINVAL;
+   }
+
+   ret = intel_vgpu_register_reg(vgpu,
+   PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
+   VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+   _vgpu_regops_opregion, OPREGION_SIZE,
+   VFIO_REGION_INFO_FLAG_READ, base);
+   if (ret) {
+   memunmap(base);
+   return ret;
+   }
+
+   return ret;
+}
+
 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 {
struct intel_vgpu *vgpu = NULL;
@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj, struct 
mdev_device *mdev)
vgpu->vdev.mdev = mdev;
mdev_set_drvdata(mdev, vgpu);
 
+   ret = intel_vgpu_reg_init_opregion(vgpu);
+   if (ret) {
+   gvt_vgpu_err("create OpRegion failed\n");
+   goto out;
+   }
+
+   gvt_dbg_core("create OpRegion succeeded for mdev:%s\n",
+   dev_name(mdev_dev(mdev)));
+
gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
 dev_name(mdev_dev(mdev)));
ret = 0;
diff --git a/drivers/gpu/drm/i915/gvt/opregion.c 
b/drivers/gpu/drm/i915/gvt/opregion.c
index 3117991..5c7496d 100644
--- a/drivers/gpu/drm/i915/gvt/opregion.c
+++ b/drivers/gpu/drm/i915/gvt/opregion.c
@@ -114,6 +114,7 @@ void 

[Intel-gfx] [PATCH v4 4/5] drm/i915/gvt: Dmabuf support for GVT-g

[Xiaoguang Chen]

dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.

Currently we provide query and create new dmabuf operations.

Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode, width, height etc.
When refresh the screen first query the currnet vgpu's frambuffer and
compare with the cached ones(address, size, tiling, width, height etc)
if found one then reuse the found dmabuf to gain performance improvment.

If there is no dmabuf created yet or not found in the cached dmabufs then
need to create a new dmabuf. To create a dmabuf first a gem object will
be created and the backing storage of this gem object is the vgpu's
framebuffer(primary/cursor).
Set caching mode, change tiling mode and set domains of this gem object
is not supported.
Then associate this gem object to a dmabuf and export this dmabuf.
A file descriptor will be generated for this dmabuf and this file
descriptor can be sent to user space to do display.

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/Makefile  |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 275 +
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  54 +++
 drivers/gpu/drm/i915/gvt/gvt.h |   1 +
 drivers/gpu/drm/i915/i915_gem.c|   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   3 +
 6 files changed, 342 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index 192ca26..e480f7d 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-   fb_decoder.o
+   fb_decoder.o dmabuf.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
new file mode 100644
index 000..c9f283c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Zhiyuan Lv 
+ *
+ * Contributors:
+ *Xiaoguang Chen 
+ */
+
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) \
+   ((dma_addr_t)(u64)pte) >> 12) & 0x7ffULL) << 12))
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+   struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+   struct sg_table *st;
+   struct scatterlist *sg;
+   int i, ret;
+   gen8_pte_t __iomem *gtt_entries;
+   unsigned int fb_gma = 0, fb_size = 0;
+   struct intel_vgpu_plane_info *plane_info;
+
+   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   if (WARN_ON(!plane_info))
+   return ERR_PTR(-EINVAL);
+
+   fb_gma = plane_info->start;
+   fb_size = plane_info->size;
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st) {
+   ret = -ENOMEM;
+   return ERR_PTR(ret);
+   }
+
+   ret = sg_alloc_table(st, fb_size, GFP_KERNEL);
+   if (ret) {
+   kfree(st);
+   return ERR_PTR(ret);
+   }
+   gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+   (fb_gma >> PAGE_SHIFT);
+   

[Intel-gfx] [PATCH v4 3/5] drm/i915/gvt: Frame buffer decoder support for GVT-g

[Xiaoguang Chen]

decode frambuffer attributes of primary, cursor and sprite plane

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/Makefile |   3 +-
 drivers/gpu/drm/i915/gvt/display.c|   2 +-
 drivers/gpu/drm/i915/gvt/display.h|   2 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 487 ++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 170 
 drivers/gpu/drm/i915/gvt/gvt.h|   1 +
 6 files changed, 663 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index b123c20..192ca26 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,8 @@
 GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+   fb_decoder.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index e0261fc..f5f63c5 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
return 1;
 }
 
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 {
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 
diff --git a/drivers/gpu/drm/i915/gvt/display.h 
b/drivers/gpu/drm/i915/gvt/display.h
index d73de22..b46b868 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 
resolution);
 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
 
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c 
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
new file mode 100644
index 000..954f047
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Kevin Tian 
+ *
+ * Contributors:
+ *Bing Niu 
+ *Xu Han 
+ *Ping Gao 
+ *Xiaoguang Chen 
+ *Yang Liu 
+ *
+ */
+
+#include 
+#include "i915_drv.h"
+#include "gvt.h"
+
+/* The below definitions are required by guest. */
+// [63:0] x:R:G:B 16:16:16:16 little endian
+#define DRM_FORMAT_XRGB161616_GVT  fourcc_code('X', 'R', '4', '8')
+// [63:0] x:B:G:R 16:16:16:16 little endian
+#define DRM_FORMAT_XBGR161616_GVT  fourcc_code('X', 'B', '4', '8')
+
+#define FORMAT_NUM 16
+struct pixel_format {
+   int drm_format; /* Pixel format in DRM definition */
+   int bpp;/* Bits per pixel, 0 indicates invalid */
+   char *desc; /* The description */
+};
+
+/* non-supported format has bpp default to 0 */
+static struct pixel_format primary_pixel_formats[FORMAT_NUM] = {
+   [0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+   [0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+   [0x6] = {DRM_FORMAT_XRGB, 32,
+   "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+   [0x8] = {DRM_FORMAT_XBGR2101010, 32,
+   "32-bit RGBX (2:10:10:10 

[Intel-gfx] [PATCH v4 1/5] drm/i915/gvt: Extend the GVT-g architecture to support vfio device region

[Xiaoguang Chen]

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,11 +53,21 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+struct vfio_region;
+struct intel_vgpu_regops {
+   size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite);
+   void (*release)(struct intel_vgpu *vgpu,
+   struct vfio_region *region);
+};
+
 struct vfio_region {
u32 type;
u32 subtype;
size_t  size;
u32 flags;
+   const struct intel_vgpu_regops  *ops;
+   void*data;
 };
 
 struct kvmgt_pgfn {
@@ -642,7 +652,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char 
*buf,
int ret = -EINVAL;
 
 
-   if (index >= VFIO_PCI_NUM_REGIONS) {
+   if (index >= VFIO_PCI_NUM_REGIONS + vgpu->vdev.num_regions) {
gvt_vgpu_err("invalid index: %u\n", index);
return -EINVAL;
}
@@ -676,8 +686,11 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, 
char *buf,
case VFIO_PCI_BAR5_REGION_INDEX:
case VFIO_PCI_VGA_REGION_INDEX:
case VFIO_PCI_ROM_REGION_INDEX:
+   break;
default:
-   gvt_vgpu_err("unsupported region: %u\n", index);
+   index -= VFIO_PCI_NUM_REGIONS;
+   return vgpu->vdev.region[index].ops->rw(vgpu, buf, count,
+   ppos, is_write);
}
 
return ret == 0 ? count : ret;
@@ -940,7 +953,8 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, 
unsigned int cmd,
 
info.flags = VFIO_DEVICE_FLAGS_PCI;
info.flags |= VFIO_DEVICE_FLAGS_RESET;
-   info.num_regions = VFIO_PCI_NUM_REGIONS;
+   info.num_regions = VFIO_PCI_NUM_REGIONS +
+   vgpu->vdev.num_regions;
info.num_irqs = VFIO_PCI_NUM_IRQS;
 
return copy_to_user((void __user *)arg, , minsz) ?
@@ -1061,6 +1075,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, 
unsigned int cmd,
}
 
if (caps.size) {
+   info.flags |= VFIO_REGION_INFO_FLAG_CAPS;
if (info.argsz < sizeof(info) + caps.size) {
info.argsz = sizeof(info) + caps.size;
info.cap_offset = 0;
-- 
2.7.4

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[Intel-gfx] [PATCH v4 0/5] drm/i915/gvt: Dma-buf support for GVT-g

[Xiaoguang Chen]

v3->v4:
1) fix bug while checking whether the gem obj is gvt's dma-buf when set
caching mode or doamins.
2) add more comments for patch set.

v2->v3:
1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save
the decoded plane information to avoid look up while need the plane info.
2) declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
to represent the gem obj for gvt's dma-buf. The tiling mode, caching mode
and domains can not be changed for this kind of gem object.
3) change dma-buf related information to be more generic. So other vendor
can use the same interface.

v1->v2:
1) create a management fd for dma-buf operations.
2) alloc gem object's backing storage in gem obj's get_pages() callback.

This patch set adds the dma-buf support for intel GVT-g.
dma-buf is a uniform mechanism to share DMA buffers across different
devices and sub-systems.
dma-buf for intel GVT-g is mainly used to share the vgpu's framebuffer
to other users or sub-systems so they can use the dma-buf to show the
desktop of a vm which uses intel vgpu.

The main idea is we create a gem object and set vgpu's framebuffer as
the backing storage of this gem object. And associate this gem obj
to a dma-buf object then export this dma-buf at the meantime
generate a file descriptor for this dma-buf. Finally deliver this file
descriptor to user space. And user can use this dma-buf fd to do render
or other operations.
User need to create a fd(for intel GVT-g dma-buf support it is a:dma-buf
management fd) then user can use this fd to query the plane information
or create a dma-buf. The life cycle of this fd is managed by GVT-g user
do not need to care about that.

We have an example program on how to use the dma-buf. You can download
the program to have a try. Good luck :)
git repo: https://github.com/01org/igvtg-qemu branch:kvmgt_dmabuf_example

Xiaoguang Chen (5):
  drm/i915/gvt: Extend the GVT-g architecture to support vfio device
region
  drm/i915/gvt: OpRegion support for GVT-g
  drm/i915/gvt: Frame buffer decoder support for GVT-g
  drm/i915/gvt: Dmabuf support for GVT-g
  drm/i915/gvt: Adding interface so user space can get the dma-buf

 drivers/gpu/drm/i915/gvt/Makefile  |   3 +-
 drivers/gpu/drm/i915/gvt/display.c |   2 +-
 drivers/gpu/drm/i915/gvt/display.h |   2 +
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 276 +++
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  32 +++
 drivers/gpu/drm/i915/gvt/fb_decoder.c  | 487 +
 drivers/gpu/drm/i915/gvt/fb_decoder.h  | 170 
 drivers/gpu/drm/i915/gvt/gvt.c |   2 +
 drivers/gpu/drm/i915/gvt/gvt.h |   5 +
 drivers/gpu/drm/i915/gvt/kvmgt.c   | 205 +-
 drivers/gpu/drm/i915/gvt/opregion.c|   8 +-
 drivers/gpu/drm/i915/i915_gem.c|   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   3 +
 include/uapi/linux/vfio.h  |  36 +++
 14 files changed, 1233 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

-- 
2.7.4

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[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm-intel tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the drm-misc tree got a conflict in:

  drivers/gpu/drm/i915/intel_display.c

between commits:

  1cecc830e6b6 ("drm/i915: Refactor CURBASE calculation")
  024faac7d59b ("drm/i915: Support variable cursor height on ivb+")

from the drm-intel tree and commit:

  c2c446ad2943 ("drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI")

from the drm-misc tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/intel_display.c
index 8217ed0e7132,6a037b856d96..
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -9144,102 -9138,6 +9144,102 @@@ out
return active;
  }
  
 +static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 +{
 +  struct drm_i915_private *dev_priv =
 +  to_i915(plane_state->base.plane->dev);
 +  const struct drm_framebuffer *fb = plane_state->base.fb;
 +  const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 +  u32 base;
 +
 +  if (INTEL_INFO(dev_priv)->cursor_needs_physical)
 +  base = obj->phys_handle->busaddr;
 +  else
 +  base = intel_plane_ggtt_offset(plane_state);
 +
 +  base += plane_state->main.offset;
 +
 +  /* ILK+ do this automagically */
 +  if (HAS_GMCH_DISPLAY(dev_priv) &&
-   plane_state->base.rotation & DRM_ROTATE_180)
++  plane_state->base.rotation & DRM_MODE_ROTATE_180)
 +  base += (plane_state->base.crtc_h *
 +   plane_state->base.crtc_w - 1) * fb->format->cpp[0];
 +
 +  return base;
 +}
 +
 +static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
 +{
 +  int x = plane_state->base.crtc_x;
 +  int y = plane_state->base.crtc_y;
 +  u32 pos = 0;
 +
 +  if (x < 0) {
 +  pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
 +  x = -x;
 +  }
 +  pos |= x << CURSOR_X_SHIFT;
 +
 +  if (y < 0) {
 +  pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
 +  y = -y;
 +  }
 +  pos |= y << CURSOR_Y_SHIFT;
 +
 +  return pos;
 +}
 +
 +static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
 +{
 +  const struct drm_mode_config *config =
 +  _state->base.plane->dev->mode_config;
 +  int width = plane_state->base.crtc_w;
 +  int height = plane_state->base.crtc_h;
 +
 +  return width > 0 && width <= config->cursor_width &&
 +  height > 0 && height <= config->cursor_height;
 +}
 +
 +static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 +struct intel_plane_state *plane_state)
 +{
 +  const struct drm_framebuffer *fb = plane_state->base.fb;
 +  int src_x, src_y;
 +  u32 offset;
 +  int ret;
 +
 +  ret = drm_plane_helper_check_state(_state->base,
 + _state->clip,
 + DRM_PLANE_HELPER_NO_SCALING,
 + DRM_PLANE_HELPER_NO_SCALING,
 + true, true);
 +  if (ret)
 +  return ret;
 +
 +  if (!fb)
 +  return 0;
 +
 +  if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
 +  DRM_DEBUG_KMS("cursor cannot be tiled\n");
 +  return -EINVAL;
 +  }
 +
 +  src_x = plane_state->base.src_x >> 16;
 +  src_y = plane_state->base.src_y >> 16;
 +
 +  intel_add_fb_offsets(_x, _y, plane_state, 0);
 +  offset = intel_compute_tile_offset(_x, _y, plane_state, 0);
 +
 +  if (src_x != 0 || src_y != 0) {
 +  DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
 +  return -EINVAL;
 +  }
 +
 +  plane_state->main.offset = offset;
 +
 +  return 0;
 +}
 +
  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
   const struct intel_plane_state *plane_state)
  {
@@@ -9389,154 -9245,116 +9389,154 @@@ static u32 i9xx_cursor_ctl(const struc
return cntl;
  }
  
 -static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
 - const struct intel_plane_state *plane_state)
 +static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
  {
 -  struct drm_device *dev = crtc->dev;
 -  struct drm_i915_private *dev_priv = to_i915(dev);
 -  struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 -  int pipe = intel_crtc->pipe;
 -  uint32_t cntl = 0;
 +  struct drm_i915_private *dev_priv =
 +  to_i915(plane_state->base.plane->dev);

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable GEN9LP decoupled mmio (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable GEN9LP decoupled mmio (rev2)
URL   : https://patchwork.freedesktop.org/series/24803/
State : success

== Summary ==

Series 24803v2 drm/i915: Disable GEN9LP decoupled mmio
https://patchwork.freedesktop.org/api/1.0/series/24803/revisions/2/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:436s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:433s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:586s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:515s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:490s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:484s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:423s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:409s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:422s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:492s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:467s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:461s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:576s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:458s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:576s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:465s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:499s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:438s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:408s
fi-snb-2520m failed to collect. IGT log at Patchwork_4780/fi-snb-2520m/igt.log

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
51394d1 drm/i915: Disable GEN9LP decoupled mmio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4780/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Disable decoupled mmio for GEN9LP (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable decoupled mmio for GEN9LP (rev4)
URL   : https://patchwork.freedesktop.org/series/24470/
State : failure

== Summary ==

Series 24470v4 drm/i915: Disable decoupled mmio for GEN9LP
https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/4/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-FAIL (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-skl-6700hq) fdo#100867
Subgroup basic-flip-vs-wf_vblank:
pass   -> SKIP   (fi-skl-6700hq) fdo#99739 +1
Subgroup basic-plain-flip:
pass   -> SKIP   (fi-skl-6700hq)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> SKIP   (fi-skl-6700hq)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup hang-read-crc-pipe-b:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup hang-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-b:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-c:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-b:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-c:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup read-crc-pipe-c-frame-sequence:
pass   -> FAIL   (fi-skl-6700hq)
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6700hq)
Test pm_backlight:
Subgroup basic-brightness:
pass   -> FAIL   (fi-skl-6700hq)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#100867 https://bugs.freedesktop.org/show_bug.cgi?id=100867
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:431s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:592s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:516s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:482s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:420s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:411s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:417s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:566s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:457s
fi-skl-6700hqtotal:278  pass:239  dwarn:0   dfail:1   fail:17  skip:21  
time:437s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:473s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:503s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:441s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time:406s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
c5da6a8 drm/i915: Disable decoupled mmio for GEN9LP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4779/

[Intel-gfx] [PATCH] drm/i915: Disable GEN9LP decoupled mmio

[kai . chen]

From: Kai Chen 

This change is used as a backport fix from top of drm-intel ([PATCH]
drm/i915: Disable decoupled mmio for GEN9LP) to disable decoupled mmio
on GEN9LP for those shipped kernels as a quick fix.

V2:
- Add signed-off-by

Signed-off-by: Kai Chen 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2c..cf43dc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -385,7 +385,6 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
-   .has_decoupled_mmio = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
-- 
2.9.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable GEN9LP decoupled mmio

[Patchwork]

== Series Details ==

Series: drm/i915: Disable GEN9LP decoupled mmio
URL   : https://patchwork.freedesktop.org/series/24803/
State : success

== Summary ==

Series 24803v1 drm/i915: Disable GEN9LP decoupled mmio
https://patchwork.freedesktop.org/api/1.0/series/24803/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:446s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:433s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:589s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:410s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:502s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:568s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:459s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:563s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:470s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:499s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:438s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:408s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
c4d1386 drm/i915: Disable GEN9LP decoupled mmio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4778/
___
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[Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP

[kai . chen]

From: Kai Chen 

The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.

v2:
- Remove dead code related to GEN9LP decoupled mmio.
- Change backgrounds: In theory, decoupled mmio should require less cycles
  for single read/write operation by avoiding frequent software forcewake.
  However, it turns out this design not to be true on HW practice and not to
  provide any decoupling benefit. It also introduces problems which cause
  failures in intel-gpu-tools (gem), and also cause driver code and debugging
  more complex.
- This change therefore reverts:

  commit 85ee17ebeedd1af0dccd98f82ab4e644e29d84c0
  Author: Praveen Paneri 
  Date:   Tue Nov 15 22:49:20 2016 +0530

  drm/i915/bxt: Broxton decoupled MMIO

V3:
- Remove HAS_DECOUPLED_MMIO macro and has_decoupled_mmio flag, as they are not
  needed, either.
- This patch will be on top with drm-intel.

V4:
- Add signed-off-by.

Signed-off-by: Kai Chen 
---
 drivers/gpu/drm/i915/i915_drv.h |   3 -
 drivers/gpu/drm/i915/i915_pci.c |   1 -
 drivers/gpu/drm/i915/i915_reg.h |   7 --
 drivers/gpu/drm/i915/intel_uncore.c | 126 
 4 files changed, 137 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f2047..41ff031 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -703,7 +703,6 @@ struct intel_csr {
func(has_aliasing_ppgtt); \
func(has_csr); \
func(has_ddi); \
-   func(has_decoupled_mmio); \
func(has_dp_mst); \
func(has_fbc); \
func(has_fpga_dbg); \
@@ -2944,8 +2943,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
-#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
-
 #include "i915_trace.h"
 
 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2c..cf43dc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -385,7 +385,6 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
-   .has_decoupled_mmio = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee144ec..78872f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7792,13 +7792,6 @@ enum {
 #define  SKL_FUSE_PG1_DIST_STATUS  (1<<26)
 #define  SKL_FUSE_PG2_DIST_STATUS  (1<<25)
 
-/* Decoupled MMIO register pair for kernel driver */
-#define GEN9_DECOUPLED_REG0_DW0_MMIO(0xF00)
-#define GEN9_DECOUPLED_REG0_DW1_MMIO(0xF04)
-#define GEN9_DECOUPLED_DW1_GO  (1<<31)
-#define GEN9_DECOUPLED_PD_SHIFT28
-#define GEN9_DECOUPLED_OP_SHIFT24
-
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A  0x60400
 #define _TRANS_DDI_FUNC_CTL_B  0x61400
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a9a6933..3901800 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -400,8 +400,6 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
  bool restore_forcewake)
 {
-   struct intel_device_info *info = mkwrite_device_info(dev_priv);
-
/* clear out unclaimed reg detection bit */
if (check_for_unclaimed_mmio(dev_priv))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
@@ -414,9 +412,6 @@ static void __intel_uncore_early_sanitize(struct 
drm_i915_private *dev_priv,
   GT_FIFO_CTL_RC6_POLICY_STALL);
}
 
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
-   info->has_decoupled_mmio = false;
-
intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 }
 
@@ -801,78 +796,6 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
__unclaimed_reg_debug(dev_priv, reg, read, before);
 }
 
-enum decoupled_power_domain {
-   GEN9_DECOUPLED_PD_BLITTER = 0,
-   GEN9_DECOUPLED_PD_RENDER,
-   GEN9_DECOUPLED_PD_MEDIA,
-   GEN9_DECOUPLED_PD_ALL
-};
-
-enum decoupled_ops {
-   GEN9_DECOUPLED_OP_WRITE = 0,
-   GEN9_DECOUPLED_OP_READ
-};
-
-static const enum decoupled_power_domain fw2dpd_domain[] = {
-   

Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/guc: Submit GuC workitems containing coalesced requests

[Daniele Ceraolo Spurio]

On 22/05/17 15:07, Michał Winiarski wrote:

To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition).

v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)

Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Jeff McGee 
Cc: Michal Wajdeczko 
Cc: Oscar Mateo 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 72 +++---
 1 file changed, 37 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e6e0c6e..2a0c3161 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -491,14 +491,12 @@ static void guc_wq_item_append(struct i915_guc_client 
*client,
 * workqueue buffer dw by dw.
 */
BUILD_BUG_ON(wqi_size != 16);
-   GEM_BUG_ON(client->wq_rsvd < wqi_size);

/* postincrement WQ tail for next time */
wq_off = client->wq_tail;
GEM_BUG_ON(wq_off & (wqi_size - 1));
client->wq_tail += wqi_size;
client->wq_tail &= client->wq_size - 1;
-   client->wq_rsvd -= wqi_size;

/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -580,7 +578,7 @@ static int guc_ring_doorbell(struct i915_guc_client *client)
 }

 /**
- * __i915_guc_submit() - Submit commands through GuC
+ * i915_guc_submit() - Submit commands through GuC
  * @rq:request associated with the commands
  *
  * The caller must have already called i915_guc_wq_reserve() above with
@@ -594,7 +592,7 @@ static int guc_ring_doorbell(struct i915_guc_client *client)
  * The only error here arises if the doorbell hardware isn't functioning
  * as expected, which really shouln't happen.
  */
-static void __i915_guc_submit(struct drm_i915_gem_request *rq)
+static void i915_guc_submit(struct drm_i915_gem_request *rq)
 {
struct drm_i915_private *dev_priv = rq->i915;
struct intel_engine_cs *engine = rq->engine;
@@ -618,12 +616,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
spin_unlock_irqrestore(>wq_lock, flags);
 }

-static void i915_guc_submit(struct drm_i915_gem_request *rq)
-{
-   __i915_gem_request_submit(rq);
-   __i915_guc_submit(rq);
-}
-
 static void nested_enable_signaling(struct drm_i915_gem_request *rq)
 {
/* If we use dma_fence_enable_sw_signaling() directly, lockdep
@@ -659,12 +651,15 @@ static void port_assign(struct execlist_port *port,
nested_enable_signaling(rq);
 }

-static bool i915_guc_dequeue(struct intel_engine_cs *engine)
+static void i915_guc_dequeue(struct intel_engine_cs *engine)
 {
struct execlist_port *port = engine->execlist_port;
-   struct drm_i915_gem_request *last = port_request(port);
-   struct rb_node *rb;
+   struct drm_i915_gem_request *last = NULL;
bool submit = false;
+   struct rb_node *rb;
+
+   if (port_request(port))
+   port++;

spin_lock_irq(>timeline->lock);
rb = engine->execlist_first;
@@ -681,18 +676,22 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
goto done;
}

-   if (submit)
+   if (submit) {
port_assign(port, last);
+   i915_guc_submit(last);
+   submit = false;
+   }
port++;
}

INIT_LIST_HEAD(>priotree.link);
rq->priotree.priority = INT_MAX;

-   i915_guc_submit(rq);
+   __i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port, engine));
last = rq;
submit = true;
+   i915_guc_wq_unreserve(rq);


Bikeshed: doesn't moving the removal of the reservation to before the 
actual WQ tail update actually theoretically introduce the possibility 
of racing over-reserving? It can't hurt anyway because of the 
coalescing, but it might be worth squashing the next patch into this one 
to make things cleaner.



}

rb = rb_next(rb);
@@ -703,11 +702,11 @@ static 

[Intel-gfx] [PATCH] drm/i915: Disable GEN9LP decoupled mmio

[kai . chen]

From: Kai Chen 

This change is used as a backport fix from top of drm-intel ([PATCH]
drm/i915: Disable decoupled mmio for GEN9LP) to disable decoupled mmio
on GEN9LP for those shipped kernels as a quick fix.
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2c..cf43dc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -385,7 +385,6 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
-   .has_decoupled_mmio = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
-- 
2.9.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable decoupled mmio for GEN9LP (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable decoupled mmio for GEN9LP (rev3)
URL   : https://patchwork.freedesktop.org/series/24470/
State : success

== Summary ==

Series 24470v3 drm/i915: Disable decoupled mmio for GEN9LP
https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/3/mbox/

Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:446s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:439s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:582s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:520s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:422s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:414s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:500s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:467s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:465s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:568s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:472s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time:573s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:466s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:504s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:439s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:531s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:410s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
b3c355a drm/i915: Disable decoupled mmio for GEN9LP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4777/
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[Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP

[kai . chen]

From: Kai Chen 

The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.

v2:
- Remove dead code related to GEN9LP decoupled mmio.
- Change backgrounds: In theory, decoupled mmio should require less cycles
  for single read/write operation by avoiding frequent software forcewake.
  However, it turns out this design not to be true on HW practice and not to
  provide any decoupling benefit. It also introduces problems which cause
  failures in intel-gpu-tools (gem), and also cause driver code and debugging
  more complex.
- This change therefore reverts:

  commit 85ee17ebeedd1af0dccd98f82ab4e644e29d84c0
  Author: Praveen Paneri 
  Date:   Tue Nov 15 22:49:20 2016 +0530

  drm/i915/bxt: Broxton decoupled MMIO

V3:
- Remove HAS_DECOUPLED_MMIO macro and has_decoupled_mmio flag, as they are not
  needed, either.
- This patch will be on top with drm-intel.
---
 drivers/gpu/drm/i915/i915_drv.h |   3 -
 drivers/gpu/drm/i915/i915_pci.c |   1 -
 drivers/gpu/drm/i915/i915_reg.h |   7 --
 drivers/gpu/drm/i915/intel_uncore.c | 126 
 4 files changed, 137 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f2047..41ff031 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -703,7 +703,6 @@ struct intel_csr {
func(has_aliasing_ppgtt); \
func(has_csr); \
func(has_ddi); \
-   func(has_decoupled_mmio); \
func(has_dp_mst); \
func(has_fbc); \
func(has_fpga_dbg); \
@@ -2944,8 +2943,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
-#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
-
 #include "i915_trace.h"
 
 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private 
*dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2c..cf43dc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -385,7 +385,6 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
-   .has_decoupled_mmio = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee144ec..78872f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7792,13 +7792,6 @@ enum {
 #define  SKL_FUSE_PG1_DIST_STATUS  (1<<26)
 #define  SKL_FUSE_PG2_DIST_STATUS  (1<<25)
 
-/* Decoupled MMIO register pair for kernel driver */
-#define GEN9_DECOUPLED_REG0_DW0_MMIO(0xF00)
-#define GEN9_DECOUPLED_REG0_DW1_MMIO(0xF04)
-#define GEN9_DECOUPLED_DW1_GO  (1<<31)
-#define GEN9_DECOUPLED_PD_SHIFT28
-#define GEN9_DECOUPLED_OP_SHIFT24
-
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A  0x60400
 #define _TRANS_DDI_FUNC_CTL_B  0x61400
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a9a6933..3901800 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -400,8 +400,6 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
  bool restore_forcewake)
 {
-   struct intel_device_info *info = mkwrite_device_info(dev_priv);
-
/* clear out unclaimed reg detection bit */
if (check_for_unclaimed_mmio(dev_priv))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
@@ -414,9 +412,6 @@ static void __intel_uncore_early_sanitize(struct 
drm_i915_private *dev_priv,
   GT_FIFO_CTL_RC6_POLICY_STALL);
}
 
-   if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
-   info->has_decoupled_mmio = false;
-
intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 }
 
@@ -801,78 +796,6 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
__unclaimed_reg_debug(dev_priv, reg, read, before);
 }
 
-enum decoupled_power_domain {
-   GEN9_DECOUPLED_PD_BLITTER = 0,
-   GEN9_DECOUPLED_PD_RENDER,
-   GEN9_DECOUPLED_PD_MEDIA,
-   GEN9_DECOUPLED_PD_ALL
-};
-
-enum decoupled_ops {
-   GEN9_DECOUPLED_OP_WRITE = 0,
-   GEN9_DECOUPLED_OP_READ
-};
-
-static const enum decoupled_power_domain fw2dpd_domain[] = {
-   GEN9_DECOUPLED_PD_RENDER,
-   GEN9_DECOUPLED_PD_BLITTER,
-   GEN9_DECOUPLED_PD_ALL,
-   

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/8] drm/i915: Remove misleading comment in request_alloc

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/8] drm/i915: Remove misleading comment in 
request_alloc
URL   : https://patchwork.freedesktop.org/series/24801/
State : failure

== Summary ==

Series 24801v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/24801/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_sync:
Subgroup basic-store-each:
pass   -> FAIL   (fi-kbl-7560u)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-bdw-5557u)
pass   -> INCOMPLETE (fi-bdw-gvtdvm)
Subgroup hang-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bsw-n3050)

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:220  pass:211  dwarn:0   dfail:0   fail:0   skip:8  
fi-bdw-gvtdvmtotal:220  pass:208  dwarn:2   dfail:0   fail:0   skip:9  
fi-bsw-n3050 total:222  pass:199  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:521s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:491s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:416s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:414s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:492s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:465s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:469s
fi-kbl-7560u total:278  pass:262  dwarn:5   dfail:0   fail:1   skip:10  
time:575s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:456s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:574s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:472s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:502s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:432s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time:404s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
e7be59c HAX: Enable GuC submission for CI
9486c76 drm/i915/scheduler: Use priorities when resubmitting after reset
8fa10e2 drm/i915/scheduler: Split insert_request
7314c03 drm/i915/scheduler: Remember request priority throughout its lifetime
b9887c1 drm/i915/guc: Remove GuC wq reservation
933c881 drm/i915/guc: Submit GuC workitems containing coalesced requests
0be4978 drm/i915/guc: Skip port assign on first iteration of GuC dequeue
f711323 drm/i915: Remove misleading comment in request_alloc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4776/
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Re: [Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT

[Bloomfield, Jon]

> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, May 22, 2017 1:05 PM
> To: Bloomfield, Jon 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT
> 
> On Mon, May 22, 2017 at 11:07:25AM -0700, Jon Bloomfield wrote:
> > BXT requires accesses to the GTT (i.e. PTE updates) to be serialized
> > when IOMMU is enabled.
> 
> Serialised with what, since all writes are serialized already?

Fair cop guv. I'll reword.

> 
> The reason is that you need to explain the hw model you are protecting, for
> example do clears need to be protected?
> 
> > This patch guarantees this by wrapping all updates in stop_machine and
> > using a flushing read to guarantee that the GTT writes have reached
> > their destination before restarting.
> 
> If you mention which patch you are reinstating (for a new problem) and cc
> the author, he might point out what has changed in the meantime.

I don't understand. I'm not re-instating any patches to my knowledge, so it's a 
bit hard to cc the author.

> 
> Note, the flush here is not about ensuring the GTT writes reach their
> destination.
> 
> > Signed-off-by: Jon Bloomfield 
> 
> If you are the author and sender, what is John's s-o-b doing afterwards?
This patch was previously signed off by John.

> 
> > Signed-off-by: John Harrison 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 106
> > 
> >  1 file changed, 106 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 7c769d7..6360d92 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -2191,6 +2191,100 @@ static void gen8_ggtt_clear_range(struct
> i915_address_space *vm,
> > gen8_set_pte(_base[i], scratch_pte);  }
> >
> > +#ifdef CONFIG_INTEL_IOMMU
> > +struct insert_page {
> > +   struct i915_address_space *vm;
> > +   dma_addr_t addr;
> > +   u64 offset;
> > +   enum i915_cache_level level;
> > +};
> > +
> > +static int gen8_ggtt_insert_page__cb(void *_arg) {
> > +   struct insert_page *arg = _arg;
> > +
> > +   struct drm_i915_private *dev_priv = arg->vm->i915;
> > +
> > +   gen8_ggtt_insert_page(arg->vm, arg->addr,
> > +   arg->offset, arg->level, 0);
> > +
> > +   POSTING_READ(GFX_FLSH_CNTL_GEN6);
> 
> This is now just a call to i915_ggtt_invalidate() because we are now also
> responsible for invalidating the guc tlbs as well as the chipset.
> And more importantly it is already done by gen8_ggtt_insert_page.
> 
> All the POSTING_READ(GFX_FLSH_CNTL_GEN6) are spurious.

Are you sure - The purpose of the register read is to ensure that all the PTE 
writes are flushed from the h/w queue
before we restart the machine. It is critical that all the PTE writes have left 
this queue before any other accesses are
allowed to begin.
Isn't the invalidate a posted write ? If so, it won't drain the queue.
Even if the invalidate is guaranteed to effect this pipeline flish, the 
clear_page path doesn't call invalidate, so it's
certainly required there.

> 
> >  static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> >   u64 start, u64 length)
> >  {
> > @@ -2789,6 +2883,18 @@ static int gen8_gmch_probe(struct i915_ggtt
> > *ggtt)
> >
> > ggtt->base.insert_entries = gen8_ggtt_insert_entries;
> >
> > +#ifdef CONFIG_INTEL_IOMMU
> > +   /* Serialize GTT updates on BXT if VT-d is on. */
> > +   if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped) {
> 
> Move to a header and don't ifdef out the users. A small cost in object side 
> for
> the benefit of keeping these ifdef out of code.
Move what to a header ? You mean create a macro for the test, the whole block, 
or something else ?

I was following the pattern used elsewhere in the code in the vain hope that by 
following established
convention we might avoid bike-shedding. Every single use of 
intel_iommu_gfx_mapped in this file is protected by
the #ifdef.

> -Chris
> 
> --
> Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH v2 6/8] drm/i915/scheduler: Split insert_request

[Michał Winiarski]

We'd like to reuse the priolist lookup in request resubmission path,
let's split insert_request to make that happen.

v2: Handle allocation error in lookup rather than in caller (Chris)

Cc: Chris Wilson 
Cc: Jeff McGee 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_lrc.c | 41 
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1255724..8fc852c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -627,20 +627,16 @@ static void intel_lrc_irq_handler(unsigned long data)
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
 }
 
-static bool
-insert_request(struct intel_engine_cs *engine,
-  struct i915_priotree *pt,
-  int prio)
+static struct i915_priolist *
+priolist_lookup(struct intel_engine_cs *engine, int prio, bool *first)
 {
struct i915_priolist *p;
struct rb_node **parent, *rb;
-   bool first = true;
 
+find_priolist:
if (unlikely(engine->no_priolist))
prio = I915_PRIORITY_NORMAL;
-
-find_priolist:
-   /* most positive priority is scheduled first, equal priorities fifo */
+   *first = true;
rb = NULL;
parent = >execlist_queue.rb_node;
while (*parent) {
@@ -650,10 +646,10 @@ insert_request(struct intel_engine_cs *engine,
parent = >rb_left;
} else if (prio < p->priority) {
parent = >rb_right;
-   first = false;
+   *first = false;
} else {
-   list_add_tail(>link, >requests);
-   return false;
+   *first = false;
+   return p;
}
}
 
@@ -661,10 +657,8 @@ insert_request(struct intel_engine_cs *engine,
p = >default_priolist;
} else {
p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
-   /* Convert an allocation failure to a priority bump */
-   if (unlikely(!p)) {
-   prio = I915_PRIORITY_NORMAL; /* recurses just once */
 
+   if (unlikely(!p)) {
/* To maintain ordering with all rendering, after an
 * allocation failure we have to disable all scheduling.
 * Requests will then be executed in fifo, and schedule
@@ -683,11 +677,26 @@ insert_request(struct intel_engine_cs *engine,
rb_insert_color(>node, >execlist_queue);
 
INIT_LIST_HEAD(>requests);
-   list_add_tail(>link, >requests);
 
-   if (first)
+   if (*first)
engine->execlist_first = >node;
 
+   return p;
+}
+
+static bool
+insert_request(struct intel_engine_cs *engine,
+  struct i915_priotree *pt,
+  int prio)
+{
+   struct i915_priolist *p;
+   bool first = false;
+
+   p = priolist_lookup(engine, prio, );
+
+   /* most positive priority is scheduled first, equal priorities fifo */
+   list_add_tail(>link, >requests);
+
return first;
 }
 
-- 
2.9.4

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[Intel-gfx] [PATCH 8/8] HAX: Enable GuC submission for CI

[Michał Winiarski]

---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e36..9dcc8a0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
-   .enable_guc_loading = 0,
-   .enable_guc_submission = 0,
+   .enable_guc_loading = 1,
+   .enable_guc_submission = 1,
.guc_log_level = -1,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
-- 
2.9.4

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[Intel-gfx] [PATCH v3 7/8] drm/i915/scheduler: Use priorities when resubmitting after reset

[Michał Winiarski]

Now that we're able to unsubmit requests, we can take advantage of it
during reset. Rather than resubmitting the previous workload directly to
GuC/ELSP, we can simply move the requests back to priority queue,
submitting from the tasklet instead.

v2: Move the tasklet schedule out for legacy ringbuffer submission
v3: Handle allocation error in lookup rather than in caller (Chris)

Cc: Chris Wilson 
Cc: Jeff McGee 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem.c|   6 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  15 +--
 drivers/gpu/drm/i915/intel_lrc.c   | 141 +
 drivers/gpu/drm/i915/intel_lrc.h   |   1 +
 4 files changed, 89 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a637cc0..28e21fd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3019,15 +3019,11 @@ static void engine_set_wedged(struct intel_engine_cs 
*engine)
 */
 
if (i915.enable_execlists) {
-   struct execlist_port *port = engine->execlist_port;
unsigned long flags;
-   unsigned int n;
 
spin_lock_irqsave(>timeline->lock, flags);
 
-   for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
-   i915_gem_request_put(port_request([n]));
-   memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
+   intel_lr_clear_execlist_ports(engine);
engine->execlist_queue = RB_ROOT;
engine->execlist_first = NULL;
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index f89718c..f6a1f6e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -534,21 +534,20 @@ static void i915_guc_submit(struct drm_i915_gem_request 
*rq)
unsigned int engine_id = engine->id;
struct intel_guc *guc = >i915->guc;
struct i915_guc_client *client = guc->execbuf_client;
-   unsigned long flags;
int b_ret;
 
/* WA to flush out the pending GMADR writes to ring buffer. */
if (i915_vma_is_map_and_fenceable(rq->ring->vma))
POSTING_READ_FW(GUC_STATUS);
 
-   spin_lock_irqsave(>wq_lock, flags);
+   spin_lock(>wq_lock);
 
guc_wq_item_append(client, rq);
b_ret = guc_ring_doorbell(client);
 
client->submissions[engine_id] += 1;
 
-   spin_unlock_irqrestore(>wq_lock, flags);
+   spin_unlock(>wq_lock);
 }
 
 static void nested_enable_signaling(struct drm_i915_gem_request *rq)
@@ -1189,9 +1188,6 @@ int i915_guc_submission_enable(struct drm_i915_private 
*dev_priv)
guc_interrupts_capture(dev_priv);
 
for_each_engine(engine, dev_priv, id) {
-   struct execlist_port *port = engine->execlist_port;
-   int n;
-
/* The tasklet was initialised by execlists, and may be in
 * a state of flux (across a reset) and so we just want to
 * take over the callback without changing any other state
@@ -1199,13 +1195,6 @@ int i915_guc_submission_enable(struct drm_i915_private 
*dev_priv)
 */
engine->irq_tasklet.func = i915_guc_irq_handler;
clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
-
-   for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
-   if (!port_isset([n]))
-   break;
-
-   i915_guc_submit(port_request([n]));
-   }
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8fc852c..356a6d2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -291,6 +291,26 @@ uint64_t intel_lr_context_descriptor(struct 
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
 }
 
+static inline struct execlist_port *
+execlists_last_port(struct intel_engine_cs *engine)
+{
+   return >execlist_port[ARRAY_SIZE(engine->execlist_port) - 1];
+}
+
+void intel_lr_clear_execlist_ports(struct intel_engine_cs *engine)
+{
+   struct execlist_port *port = engine->execlist_port;
+   struct drm_i915_gem_request *rq;
+
+   while ((rq = port_request(port))) {
+   i915_gem_request_put(rq);
+   if (port == execlists_last_port(engine))
+   break;
+   port++;
+   }
+   memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
+}
+
 static inline void
 execlists_context_status_change(struct drm_i915_gem_request *rq,
unsigned long status)
@@ -952,6 +972,36 @@ 

[Intel-gfx] [PATCH v3 4/8] drm/i915/guc: Remove GuC wq reservation

[Michał Winiarski]

Now that we have an upper bound on the number of work items being sent
to GuC, we can remove the reservation.

v2: Multiply by number of engines in compile time assert (Daniele)
v3: Comment on reasoning behind the compile time assert (Chris)

Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Jeff McGee 
Cc: Michal Wajdeczko 
Cc: Oscar Mateo 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  2 -
 drivers/gpu/drm/i915/i915_guc_submission.c | 89 +-
 drivers/gpu/drm/i915/intel_lrc.c   | 25 +
 drivers/gpu/drm/i915/intel_uc.h|  8 ---
 4 files changed, 17 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0969b8d..83366a4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2481,8 +2481,6 @@ static void i915_guc_client_info(struct seq_file *m,
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
client->wq_size, client->wq_offset, client->wq_tail);
 
-   seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-
for_each_engine(engine, dev_priv, id) {
u64 submissions = client->submissions[id];
tot += submissions;
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 2a0c3161..66d8eaf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -406,63 +406,6 @@ static void guc_stage_desc_fini(struct intel_guc *guc,
memset(desc, 0, sizeof(*desc));
 }
 
-/**
- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
- * @request:   request associated with the commands
- *
- * Return: 0 if space is available
- * -EAGAIN if space is not currently available
- *
- * This function must be called (and must return 0) before a request
- * is submitted to the GuC via i915_guc_submit() below. Once a result
- * of 0 has been returned, it must be balanced by a corresponding
- * call to submit().
- *
- * Reservation allows the caller to determine in advance that space
- * will be available for the next submission before committing resources
- * to it, and helps avoid late failures with complicated recovery paths.
- */
-int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
-{
-   const size_t wqi_size = sizeof(struct guc_wq_item);
-   struct i915_guc_client *client = request->i915->guc.execbuf_client;
-   struct guc_process_desc *desc = __get_process_desc(client);
-   u32 freespace;
-   int ret;
-
-   spin_lock_irq(>wq_lock);
-   freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
-   freespace -= client->wq_rsvd;
-   if (likely(freespace >= wqi_size)) {
-   client->wq_rsvd += wqi_size;
-   ret = 0;
-   } else {
-   client->no_wq_space++;
-   ret = -EAGAIN;
-   }
-   spin_unlock_irq(>wq_lock);
-
-   return ret;
-}
-
-static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
-{
-   unsigned long flags;
-
-   spin_lock_irqsave(>wq_lock, flags);
-   client->wq_rsvd += size;
-   spin_unlock_irqrestore(>wq_lock, flags);
-}
-
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
-{
-   const int wqi_size = sizeof(struct guc_wq_item);
-   struct i915_guc_client *client = request->i915->guc.execbuf_client;
-
-   GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
-   guc_client_update_wq_rsvd(client, -wqi_size);
-}
-
 /* Construct a Work Item and append it to the GuC's Work Queue */
 static void guc_wq_item_append(struct i915_guc_client *client,
   struct drm_i915_gem_request *rq)
@@ -475,7 +418,7 @@ static void guc_wq_item_append(struct i915_guc_client 
*client,
struct guc_wq_item *wqi;
u32 freespace, tail, wq_off;
 
-   /* Free space is guaranteed, see i915_guc_wq_reserve() above */
+   /* Free space is guaranteed */
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
GEM_BUG_ON(freespace < wqi_size);
 
@@ -581,14 +524,6 @@ static int guc_ring_doorbell(struct i915_guc_client 
*client)
  * i915_guc_submit() - Submit commands through GuC
  * @rq:request associated with the commands
  *
- * The caller must have already called i915_guc_wq_reserve() above with
- * a result of 0 (success), guaranteeing that there is space in the work
- * queue for the new request, so enqueuing the item cannot fail.
- *
- * Bad Things Will Happen if the caller violates this protocol e.g. calls
- * submit() when _reserve() says there's no space, or calls _submit()
- * a different number of times from 

[Intel-gfx] [PATCH v2 5/8] drm/i915/scheduler: Remember request priority throughout its lifetime

[Michał Winiarski]

Since request can be unsubmitted, we need to avoid overriding its priority
during submission. Otherwise we won't be able to resubmit it with
correct priority.

v2: Limit DFS by excluding completed requests (Chris)

Cc: Chris Wilson 
Cc: Jeff McGee 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  1 -
 drivers/gpu/drm/i915/intel_lrc.c   | 13 ++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 66d8eaf..f89718c 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -620,7 +620,6 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
}
 
INIT_LIST_HEAD(>priotree.link);
-   rq->priotree.priority = INT_MAX;
 
__i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port, engine));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5d4f23c..1255724 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -487,7 +487,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
INIT_LIST_HEAD(>priotree.link);
-   rq->priotree.priority = INT_MAX;
 
__i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port, engine));
@@ -771,9 +770,17 @@ static void execlists_schedule(struct drm_i915_gem_request 
*request, int prio)
 * engines.
 */
list_for_each_entry(p, >signalers_list, signal_link) {
+   struct drm_i915_gem_request *s =
+   container_of(p->signaler, typeof(*s), priotree);
+
GEM_BUG_ON(p->signaler->priority < pt->priority);
-   if (prio > READ_ONCE(p->signaler->priority))
-   list_move_tail(>dfs_link, );
+   if (prio <= READ_ONCE(p->signaler->priority))
+   continue;
+
+   if (i915_gem_request_completed(s))
+   continue;
+
+   list_move_tail(>dfs_link, );
}
 
list_safe_reset_next(dep, p, dfs_link);
-- 
2.9.4

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[Intel-gfx] [PATCH v3 3/8] drm/i915/guc: Submit GuC workitems containing coalesced requests

[Michał Winiarski]

To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition).

v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)

Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Jeff McGee 
Cc: Michal Wajdeczko 
Cc: Oscar Mateo 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 72 +++---
 1 file changed, 37 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index e6e0c6e..2a0c3161 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -491,14 +491,12 @@ static void guc_wq_item_append(struct i915_guc_client 
*client,
 * workqueue buffer dw by dw.
 */
BUILD_BUG_ON(wqi_size != 16);
-   GEM_BUG_ON(client->wq_rsvd < wqi_size);
 
/* postincrement WQ tail for next time */
wq_off = client->wq_tail;
GEM_BUG_ON(wq_off & (wqi_size - 1));
client->wq_tail += wqi_size;
client->wq_tail &= client->wq_size - 1;
-   client->wq_rsvd -= wqi_size;
 
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -580,7 +578,7 @@ static int guc_ring_doorbell(struct i915_guc_client *client)
 }
 
 /**
- * __i915_guc_submit() - Submit commands through GuC
+ * i915_guc_submit() - Submit commands through GuC
  * @rq:request associated with the commands
  *
  * The caller must have already called i915_guc_wq_reserve() above with
@@ -594,7 +592,7 @@ static int guc_ring_doorbell(struct i915_guc_client *client)
  * The only error here arises if the doorbell hardware isn't functioning
  * as expected, which really shouln't happen.
  */
-static void __i915_guc_submit(struct drm_i915_gem_request *rq)
+static void i915_guc_submit(struct drm_i915_gem_request *rq)
 {
struct drm_i915_private *dev_priv = rq->i915;
struct intel_engine_cs *engine = rq->engine;
@@ -618,12 +616,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request 
*rq)
spin_unlock_irqrestore(>wq_lock, flags);
 }
 
-static void i915_guc_submit(struct drm_i915_gem_request *rq)
-{
-   __i915_gem_request_submit(rq);
-   __i915_guc_submit(rq);
-}
-
 static void nested_enable_signaling(struct drm_i915_gem_request *rq)
 {
/* If we use dma_fence_enable_sw_signaling() directly, lockdep
@@ -659,12 +651,15 @@ static void port_assign(struct execlist_port *port,
nested_enable_signaling(rq);
 }
 
-static bool i915_guc_dequeue(struct intel_engine_cs *engine)
+static void i915_guc_dequeue(struct intel_engine_cs *engine)
 {
struct execlist_port *port = engine->execlist_port;
-   struct drm_i915_gem_request *last = port_request(port);
-   struct rb_node *rb;
+   struct drm_i915_gem_request *last = NULL;
bool submit = false;
+   struct rb_node *rb;
+
+   if (port_request(port))
+   port++;
 
spin_lock_irq(>timeline->lock);
rb = engine->execlist_first;
@@ -681,18 +676,22 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
goto done;
}
 
-   if (submit)
+   if (submit) {
port_assign(port, last);
+   i915_guc_submit(last);
+   submit = false;
+   }
port++;
}
 
INIT_LIST_HEAD(>priotree.link);
rq->priotree.priority = INT_MAX;
 
-   i915_guc_submit(rq);
+   __i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port, engine));
last = rq;
submit = true;
+   i915_guc_wq_unreserve(rq);
}
 
rb = rb_next(rb);
@@ -703,11 +702,11 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
*engine)
}
 done:
engine->execlist_first = rb;
-   if (submit)
+   if (submit) {
port_assign(port, last);
+   i915_guc_submit(last);
+   }
spin_unlock_irq(>timeline->lock);
-
-   return submit;
 }
 
 static void 

[Intel-gfx] [PATCH 2/8] drm/i915/guc: Skip port assign on first iteration of GuC dequeue

[Michał Winiarski]

If port[0] is occupied and we're trying to dequeue request from
different context, we will inevitably hit BUG_ON in port_assign.
Let's skip it - similar to what we're doing in execlists counterpart.

Fixes: 77f0d0e925e8a0 ("drm/i915/execlists: Pack the count into the low bits of 
the port.request")
Cc: Chris Wilson 
Cc: Michał Wajdeczko 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 777f48e..e6e0c6e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -681,7 +681,8 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
goto done;
}
 
-   port_assign(port, last);
+   if (submit)
+   port_assign(port, last);
port++;
}
 
-- 
2.9.4

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[Intel-gfx] [PATCH v2 1/8] drm/i915: Remove misleading comment in request_alloc

[Michał Winiarski]

Passing NULL ctx to request_alloc would lead to null-ptr-deref.

v2: Let's not replace the comment with a BUG_ON

Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 1ccf252..0d1e0d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -538,9 +538,6 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
  *
  * @engine: engine that we wish to issue the request on.
  * @ctx: context that the request will be associated with.
- *   This can be NULL if the request is not directly related to
- *   any specific user context, in which case this function will
- *   choose an appropriate context to use.
  *
  * Returns a pointer to the allocated request if successful,
  * or an error code if not.
-- 
2.9.4

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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Submit GuC workitems containing coalesced requests

[Michał Winiarski]

On Fri, May 19, 2017 at 11:08:05AM -0700, Daniele Ceraolo Spurio wrote:
> 
> 
> On 19/05/17 06:23, Michał Winiarski wrote:
> > To create an upper bound on number of GuC workitems, we need to change
> > the way that requests are being submitted. Rather than submitting each
> > request as an individual workitem, we can do coalescing in a similar way
> > we're handlig execlist submission ports. We also need to stop pretending
> > that we're doing "lite-restore" in GuC submission (we would create a
> > workitem each time we hit this condition).
> > 
> > v2: Also coalesce when replaying on reset (Daniele)
> > 
> > Cc: Chris Wilson 
> > Cc: Daniele Ceraolo Spurio 
> > Cc: Michal Wajdeczko 
> > Cc: Oscar Mateo 
> > Signed-off-by: Michał Winiarski 
> > ---
> >  drivers/gpu/drm/i915/i915_guc_submission.c | 68 
> > --
> >  1 file changed, 36 insertions(+), 32 deletions(-)
> > 

[SNIP]

> > @@ -689,12 +686,16 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
> > *engine)
> > 
> > port_assign(port, last);
> > port++;
> > +   if (submit) {
> > +   i915_guc_submit(last);
> > +   submit = false;
> > +   }
> > }
> > 
> > INIT_LIST_HEAD(>priotree.link);
> > rq->priotree.priority = INT_MAX;
> > 
> > -   i915_guc_submit(rq);
> > +   __i915_gem_request_submit(rq);
> > trace_i915_gem_request_in(rq, port_index(port, engine));
> > last = rq;
> > submit = true;
> > @@ -708,11 +709,11 @@ static bool i915_guc_dequeue(struct intel_engine_cs 
> > *engine)
> > }
> >  done:
> > engine->execlist_first = rb;
> > -   if (submit)
> > +   if (submit) {
> > port_assign(port, last);
> > +   i915_guc_submit(last);
> > +   }
> 
> Since now we only call both port_assign and i915_guc_submit once per port,
> can we move both usages in the loop, before the break, and remove it from
> here? i.e.:
> 
> if (last && rq->ctx != last->ctx) {
> 
> if (submit) {
> port_assign(port, last);
> i915_guc_submit(last);
> }
> if (port != engine->execlist_port) {
> __list_del_many(>requests,
> >priotree.link);
> goto done;
> }
> port++;
> }
> 
> Or do we have issues with the ordering of operations?

No, not with the ordering, it's just that we won't handle the case where we've
ran out of request (we're done iterating through the list, but we still have to
submit "last" request). Still, I think moving port_assign and port++ under
submit conditional makes the code a bit easier on the reader - I'll do that in
next version.

> 
> 
> > spin_unlock_irq(>timeline->lock);
> > -
> > -   return submit;
> >  }
> > 
> >  static void i915_guc_irq_handler(unsigned long data)
> > @@ -720,24 +721,20 @@ static void i915_guc_irq_handler(unsigned long data)
> > struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
> > struct execlist_port *port = engine->execlist_port;
> > struct drm_i915_gem_request *rq;
> > -   bool submit;
> > 
> > -   do {
> > -   rq = port_request([0]);
> > -   while (rq && i915_gem_request_completed(rq)) {
> > -   trace_i915_gem_request_out(rq);
> > -   i915_gem_request_put(rq);
> > +   rq = port_request([0]);
> > +   while (rq && i915_gem_request_completed(rq)) {
> > +   trace_i915_gem_request_out(rq);
> > +   i915_gem_request_put(rq);
> > 
> > -   port[0] = port[1];
> > -   memset([1], 0, sizeof(port[1]));
> > +   port[0] = port[1];
> > +   memset([1], 0, sizeof(port[1]));
> > 
> > -   rq = port_request([0]);
> > -   }
> > +   rq = port_request([0]);
> > +   }
> > 
> > -   submit = false;
> > -   if (!port_count([1]))
> > -   submit = i915_guc_dequeue(engine);
> > -   } while (submit);
> > +   if (!port_isset([1]))
> > +   i915_guc_dequeue(engine);
> >  }
> > 
> >  /*
> > @@ -1255,6 +1252,8 @@ int i915_guc_submission_enable(struct 
> > drm_i915_private *dev_priv)
> > for_each_engine(engine, dev_priv, id) {
> > const int wqi_size = sizeof(struct guc_wq_item);
> > struct drm_i915_gem_request *rq;
> > +   struct execlist_port *port = engine->execlist_port;
> > +   int n;
> > 
> > /* The tasklet was initialised by execlists, and may be in
> >  * a state of flux (across a reset) and so we just want to
> > @@ -1266,11 +1265,16 @@ int 

Re: [Intel-gfx] [PATCH 03/24] drm/i915: Store i915_gem_object_is_coherent() as a bit next to cache-dirty

[Dongwon Kim]

Chris, 

I tested this together with your v3 (Mark cache dirty...)
patch and verified tests are all passing.

Tested-by : Dongwon Kim 

On Thu, May 18, 2017 at 10:46:17AM +0100, Chris Wilson wrote:
> For ease of use (i.e. avoiding a few checks and function calls), store
> the object's cache coherency next to the cache is dirty bit.
> 
> Signed-off-by: Chris Wilson 
> Cc: Dongwon Kim 
> Cc: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_gem.c  | 14 +++---
>  drivers/gpu/drm/i915/i915_gem_clflush.c  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c   |  2 +-
>  drivers/gpu/drm/i915/i915_gem_internal.c |  3 ++-
>  drivers/gpu/drm/i915/i915_gem_object.h   |  1 +
>  drivers/gpu/drm/i915/i915_gem_stolen.c   |  1 +
>  drivers/gpu/drm/i915/i915_gem_userptr.c  |  3 ++-
>  drivers/gpu/drm/i915/selftests/huge_gem_object.c |  3 ++-
>  8 files changed, 17 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 155dd52f2d18..870659c13de3 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -52,7 +52,7 @@ static bool cpu_write_needs_clflush(struct 
> drm_i915_gem_object *obj)
>   if (obj->cache_dirty)
>   return false;
>  
> - if (!i915_gem_object_is_coherent(obj))
> + if (!obj->cache_coherent)
>   return true;
>  
>   return obj->pin_display;
> @@ -253,7 +253,7 @@ __i915_gem_object_release_shmem(struct 
> drm_i915_gem_object *obj,
>  
>   if (needs_clflush &&
>   (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
> - !i915_gem_object_is_coherent(obj))
> + !obj->cache_coherent)
>   drm_clflush_sg(pages);
>  
>   __start_cpu_write(obj);
> @@ -856,8 +856,7 @@ int i915_gem_obj_prepare_shmem_read(struct 
> drm_i915_gem_object *obj,
>   if (ret)
>   return ret;
>  
> - if (i915_gem_object_is_coherent(obj) ||
> - !static_cpu_has(X86_FEATURE_CLFLUSH)) {
> + if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
>   ret = i915_gem_object_set_to_cpu_domain(obj, false);
>   if (ret)
>   goto err_unpin;
> @@ -909,8 +908,7 @@ int i915_gem_obj_prepare_shmem_write(struct 
> drm_i915_gem_object *obj,
>   if (ret)
>   return ret;
>  
> - if (i915_gem_object_is_coherent(obj) ||
> - !static_cpu_has(X86_FEATURE_CLFLUSH)) {
> + if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
>   ret = i915_gem_object_set_to_cpu_domain(obj, true);
>   if (ret)
>   goto err_unpin;
> @@ -3661,6 +3659,7 @@ int i915_gem_object_set_cache_level(struct 
> drm_i915_gem_object *obj,
>   list_for_each_entry(vma, >vma_list, obj_link)
>   vma->node.color = cache_level;
>   obj->cache_level = cache_level;
> + obj->cache_coherent = i915_gem_object_is_coherent(obj);
>   obj->cache_dirty = true; /* Always invalidate stale cachelines */
>  
>   return 0;
> @@ -4320,7 +4319,8 @@ i915_gem_object_create(struct drm_i915_private 
> *dev_priv, u64 size)
>   } else
>   obj->cache_level = I915_CACHE_NONE;
>  
> - obj->cache_dirty = !i915_gem_object_is_coherent(obj);
> + obj->cache_coherent = i915_gem_object_is_coherent(obj);
> + obj->cache_dirty = !obj->cache_coherent;
>  
>   trace_i915_gem_object_create(obj);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c 
> b/drivers/gpu/drm/i915/i915_gem_clflush.c
> index 17b207e963c2..152f16c11878 100644
> --- a/drivers/gpu/drm/i915/i915_gem_clflush.c
> +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c
> @@ -139,7 +139,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object 
> *obj,
>* snooping behaviour occurs naturally as the result of our domain
>* tracking.
>*/
> - if (!(flags & I915_CLFLUSH_FORCE) && i915_gem_object_is_coherent(obj))
> + if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
>   return;
>  
>   trace_i915_gem_object_clflush(obj);
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 0b8ae0f56675..2e5f513087a8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1129,7 +1129,7 @@ i915_gem_execbuffer_move_to_gpu(struct 
> drm_i915_gem_request *req,
>   if (vma->exec_entry->flags & EXEC_OBJECT_ASYNC)
>   continue;
>  
> - if (obj->cache_dirty)
> + if (obj->cache_dirty & ~obj->cache_coherent)
>   i915_gem_clflush_object(obj, 0);
>  
>   ret = i915_gem_request_await_object
> diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c 
> 

Re: [Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT

[Chris Wilson]

On Mon, May 22, 2017 at 11:07:25AM -0700, Jon Bloomfield wrote:
> BXT requires accesses to the GTT (i.e. PTE updates) to be serialized
> when IOMMU is enabled.

Serialised with what, since all writes are serialized already?

The reason is that you need to explain the hw model you are protecting,
for example do clears need to be protected?

> This patch guarantees this by wrapping all
> updates in stop_machine and using a flushing read to guarantee that
> the GTT writes have reached their destination before restarting.

If you mention which patch you are reinstating (for a new problem) and
cc the author, he might point out what has changed in the meantime.

Note, the flush here is not about ensuring the GTT writes reach their
destination.
 
> Signed-off-by: Jon Bloomfield 

If you are the author and sender, what is John's s-o-b doing afterwards?

> Signed-off-by: John Harrison 
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 106 
> 
>  1 file changed, 106 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7c769d7..6360d92 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2191,6 +2191,100 @@ static void gen8_ggtt_clear_range(struct 
> i915_address_space *vm,
>   gen8_set_pte(_base[i], scratch_pte);
>  }
>  
> +#ifdef CONFIG_INTEL_IOMMU
> +struct insert_page {
> + struct i915_address_space *vm;
> + dma_addr_t addr;
> + u64 offset;
> + enum i915_cache_level level;
> +};
> +
> +static int gen8_ggtt_insert_page__cb(void *_arg)
> +{
> + struct insert_page *arg = _arg;
> +
> + struct drm_i915_private *dev_priv = arg->vm->i915;
> +
> + gen8_ggtt_insert_page(arg->vm, arg->addr,
> + arg->offset, arg->level, 0);
> +
> + POSTING_READ(GFX_FLSH_CNTL_GEN6);

This is now just a call to i915_ggtt_invalidate() because we are now
also responsible for invalidating the guc tlbs as well as the chipset.
And more importantly it is already done by gen8_ggtt_insert_page.

All the POSTING_READ(GFX_FLSH_CNTL_GEN6) are spurious.

>  static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> u64 start, u64 length)
>  {
> @@ -2789,6 +2883,18 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>  
>   ggtt->base.insert_entries = gen8_ggtt_insert_entries;
>  
> +#ifdef CONFIG_INTEL_IOMMU
> + /* Serialize GTT updates on BXT if VT-d is on. */
> + if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped) {

Move to a header and don't ifdef out the users. A small cost in object
side for the benefit of keeping these ifdef out of code.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH v6] drm/i915/guc: capture GuC logs if FW fails to load

[Michal Wajdeczko]

On Mon, May 22, 2017 at 10:50:28AM -0700, Daniele Ceraolo Spurio wrote:
> We're currently deleting the GuC logs if the FW fails to load, but those
> are still useful to understand why the loading failed. Keeping the
> object around allows us to access them after driver load is completed.
> 
> v2: keep the object around instead of using kernel memory (chris)
> don't store the logs in the gpu_error struct (Chris)
> add a check on guc_log_level to avoid snapshotting empty logs
> 
> v3: use separate debugfs for error log (Chris)
> 
> v4: rebased
> 
> v5: clean up obj selection, move err_load inside guc_log, move err_load
> cleanup, rename functions (Michal)
> 
> v6: move obj back to intel_guc, move functions to intel_uc.c, don't
> clear obj on new GuC load, free object only if enable_guc_loading
> is set (Michal)
> 
> Cc: Chris Wilson 
> Cc: Oscar Mateo 
> Cc: Michal Wajdeczko 
> Signed-off-by: Daniele Ceraolo Spurio 
> ---

Reviewed-by: Michal Wajdeczko 

Regards,
Michal
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Re: [Intel-gfx] [PATCH v5] dma-buf/sync-file: Defer creation of sync_file->name

[Daniel Vetter]

On Tue, May 16, 2017 at 12:10:42PM +0100, Chris Wilson wrote:
> Constructing the name takes the majority of the time for allocating a
> sync_file to wrap a fence, and the name is very rarely used (only via
> the sync_file status user interface). To reduce the impact on the common
> path (that of creating sync_file to pass around), defer the construction
> of the name until it is first used.
> 
> v2: Update kerneldoc (kbuild test robot)
> v3: sync_debug.c was peeking at the name
> v4: Comment upon the potential race between two users of
> sync_file_get_name() and claim that such a race is below the level of
> notice. However, to prevent any future nuisance, use a global spinlock
> to serialize the assignment of the name.
> v5: Completely avoid the read/write race by only storing the name passed
> in from the user inside sync_file->user_name and passing in a buffer to
> dynamically construct the name otherwise.
> 
> Signed-off-by: Chris Wilson 
> Cc: Sumit Semwal 
> Cc: Gustavo Padovan 
> Cc: Daniel Vetter 
> Cc: David Herrmann 
> ---
>  drivers/dma-buf/sync_debug.c |  4 +++-
>  drivers/dma-buf/sync_file.c  | 39 ---
>  include/linux/sync_file.h|  5 +++--
>  3 files changed, 38 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c
> index 4b1731ee7458..59a3b2f8ee91 100644
> --- a/drivers/dma-buf/sync_debug.c
> +++ b/drivers/dma-buf/sync_debug.c
> @@ -132,9 +132,11 @@ static void sync_print_obj(struct seq_file *s, struct 
> sync_timeline *obj)
>  static void sync_print_sync_file(struct seq_file *s,
> struct sync_file *sync_file)
>  {
> + char buf[128];
>   int i;
>  
> - seq_printf(s, "[%p] %s: %s\n", sync_file, sync_file->name,
> + seq_printf(s, "[%p] %s: %s\n", sync_file,
> +sync_file_get_name(sync_file, buf, sizeof(buf)),
>  sync_status_str(dma_fence_get_status(sync_file->fence)));
>  
>   if (dma_fence_is_array(sync_file->fence)) {
> diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
> index c9eb4997cfcc..d7e219d2669d 100644
> --- a/drivers/dma-buf/sync_file.c
> +++ b/drivers/dma-buf/sync_file.c
> @@ -80,11 +80,6 @@ struct sync_file *sync_file_create(struct dma_fence *fence)
>  
>   sync_file->fence = dma_fence_get(fence);
>  
> - snprintf(sync_file->name, sizeof(sync_file->name), "%s-%s%llu-%d",
> -  fence->ops->get_driver_name(fence),
> -  fence->ops->get_timeline_name(fence), fence->context,
> -  fence->seqno);
> -
>   return sync_file;
>  }
>  EXPORT_SYMBOL(sync_file_create);
> @@ -129,6 +124,36 @@ struct dma_fence *sync_file_get_fence(int fd)
>  }
>  EXPORT_SYMBOL(sync_file_get_fence);
>  
> +/**
> + * sync_file_get_name - get the name of the sync_file
> + * @sync_file:   sync_file to get the fence from
> + * @buf: destination buffer to copy sync_file name into
> + * @len: available size of destination buffer.
> + *
> + * Each sync_file may have a name assigned either by the user (when merging
> + * sync_files together) or created from the fence it contains. In the latter
> + * case construction of the name is deferred until use, and so requires
> + * sync_file_get_name().
> + *
> + * Returns: a string representing the name.
> + */
> +char *sync_file_get_name(struct sync_file *sync_file, char *buf, int len)
> +{
> + if (sync_file->user_name[0]) {
> + strlcpy(buf, sync_file->user_name, len);
> + } else {
> + struct dma_fence *fence = sync_file->fence;
> +
> + snprintf(buf, len, "%s-%s%llu-%d",
> +  fence->ops->get_driver_name(fence),
> +  fence->ops->get_timeline_name(fence),
> +  fence->context,
> +  fence->seqno);
> + }
> +
> + return buf;
> +}
> +
>  static int sync_file_set_fence(struct sync_file *sync_file,
>  struct dma_fence **fences, int num_fences)
>  {
> @@ -266,7 +291,7 @@ static struct sync_file *sync_file_merge(const char 
> *name, struct sync_file *a,
>   goto err;
>   }
>  
> - strlcpy(sync_file->name, name, sizeof(sync_file->name));
> + strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name));
>   return sync_file;
>  
>  err:
> @@ -419,7 +444,7 @@ static long sync_file_ioctl_fence_info(struct sync_file 
> *sync_file,
>   }
>  
>  no_fences:
> - strlcpy(info.name, sync_file->name, sizeof(info.name));
> + sync_file_get_name(sync_file, info.name, sizeof(info.name));
>   info.status = dma_fence_is_signaled(sync_file->fence);
>   info.num_fences = num_fences;
>  
> diff --git a/include/linux/sync_file.h b/include/linux/sync_file.h
> index d37beefdfbd5..5226d62ae91b 100644
> --- 

Re: [Intel-gfx] [PATCH v1] ACPI: Switch to use generic UUID API

[Andy Shevchenko]

On Thu, 2017-05-04 at 12:21 +0300, Andy Shevchenko wrote:
> acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16
> bytes. Instead we convert them to use uuid_le type. At the same time
> we
> convert current users.
> 
> acpi_str_to_uuid() becomes useless after the conversion and it's safe
> to
> get rid of it.
> 
> The conversion fixes a potential bug in int340x_thermal as well since
> we have to use memcmp() on binary data.
> 
> Cc: Rafael J. Wysocki 
> Cc: Mika Westerberg 
> Cc: Borislav Petkov 
> Cc: Dan Williams 
> Cc: Amir Goldstein 
> Cc: Jarkko Sakkinen 
> Cc: Jani Nikula 
> Cc: Ben Skeggs 
> Cc: Benjamin Tissoires 
> Cc: Joerg Roedel 
> Cc: Adrian Hunter 
> Cc: Yisen Zhuang 
> Cc: Bjorn Helgaas 
> Cc: Zhang Rui 
> Cc: Felipe Balbi 
> Cc: Mathias Nyman 
> Cc: Heikki Krogerus 
> Cc: Liam Girdwood 
> Cc: Mark Brown 
> Signed-off-by: Andy Shevchenko 

Thank you everyone who gave a tag to this.

I'm going to split and rebase on top of Christoph's branch
http://git.infradead.org/users/hch/vfs.git/shortlog/refs/heads/uuid-type
s

followed by changing types and API calls accordingly (without changing a
logic!).

So, I would like to keep tags in place. If there is any objection, speak
up now!
 
Thanks!

-- 
Andy Shevchenko 
Intel Finland Oy
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Re: [Intel-gfx] [PATCH 14/14] drm/i915/perf: add GLK support

[Matthew Auld]

On 05/17, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 

Hmm, are we not missing the GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS
part, so disabling slice/unslice clock ratio change reports, like we do
on all other gen9 platforms?

For the timestamp base are we just assuming it's the same as BXT, or did
you find it somewhere in the bspec, because I had no such luck?

Otherwise assuming the configs are indeed correct and with a proper
commit message:

Reviewed-by: Matthew Auld 

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Re: [Intel-gfx] [PATCH] drm: Fix deadlock retry loop in page_flip_ioctl

[Tommi Rantala]

2017-05-22 16:59 GMT+03:00 Daniel Vetter :
> I failed to properly onion-wrap the unwind code: We acquire the vblank
> reference before we start with the wait-wound locking dance, hence we
> must make sure we retry before we drop the reference. Oops.
>
> v2: The vblank_put must be after the frambuffer_put (Michel). I suck at
> unwrapping code that doesn't use separate labels for each stage, but
> checks each pointer first ... While re-reading everything I also
> realized that we must clean up the fb refcounts, and specifically
> plane->old_fb before we drop the locks, either in the final unlocking,
> or in the w/w retry path. Hence the correct fix is to drop the
> vblank_put to the very bottom.
>
> Fixes: 29dc0d1de182 ("drm: Roll out acquire context for the page_flip ioctl")
> Cc: Harry Wentland 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: David Airlie 
> Cc: dri-de...@lists.freedesktop.org
> Reported-by: Tommi Rantala 
> Cc: Tommi Rantala 
> Cc: Michel Dänzer 
> Signed-off-by: Daniel Vetter 

Thanks, confirmed that this fixes the warning that I was seeing!

Tested-by: Tommi Rantala 

> ---
>  drivers/gpu/drm/drm_plane.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index fedd4d60d9cd..5dc8c4350602 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -948,8 +948,6 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> }
>
>  out:
> -   if (ret && crtc->funcs->page_flip_target)
> -   drm_crtc_vblank_put(crtc);
> if (fb)
> drm_framebuffer_put(fb);
> if (crtc->primary->old_fb)
> @@ -964,5 +962,8 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> drm_modeset_drop_locks();
> drm_modeset_acquire_fini();
>
> +   if (ret && crtc->funcs->page_flip_target)
> +   drm_crtc_vblank_put(crtc);
> +
> return ret;
>  }
> --
> 2.11.0
>
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/guc: capture GuC logs if FW fails to load (rev6)

[Daniele Ceraolo Spurio]

On 22/05/17 11:21, Patchwork wrote:

== Series Details ==

Series: drm/i915/guc: capture GuC logs if FW fails to load (rev6)
URL   : https://patchwork.freedesktop.org/series/23982/
State : warning

== Summary ==

Series 23982v6 drm/i915/guc: capture GuC logs if FW fails to load
https://patchwork.freedesktop.org/api/1.0/series/23982/revisions/6/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-snb-2600)


this is: https://bugs.freedesktop.org/show_bug.cgi?id=100125

Regards,
Daniele


Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:434s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:582s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:487s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:412s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:495s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:467s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:573s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:457s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:581s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:463s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:532s
fi-snb-2600  total:278  pass:248  dwarn:1   dfail:0   fail:0   skip:29  
time:416s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
8ddb7a7 drm/i915/guc: capture GuC logs if FW fails to load

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4774/


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Serialize GTT Updates on BXT

[Patchwork]

== Series Details ==

Series: drm/i915: Serialize GTT Updates on BXT
URL   : https://patchwork.freedesktop.org/series/24793/
State : success

== Summary ==

Series 24793v1 drm/i915: Serialize GTT Updates on BXT
https://patchwork.freedesktop.org/api/1.0/series/24793/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:447s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:440s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:585s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:512s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:495s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:488s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:419s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:465s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:570s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:458s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:574s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:465s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:505s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:436s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time:414s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
1d67986 drm/i915: Serialize GTT Updates on BXT

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4775/
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/guc: capture GuC logs if FW fails to load (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: capture GuC logs if FW fails to load (rev6)
URL   : https://patchwork.freedesktop.org/series/23982/
State : warning

== Summary ==

Series 23982v6 drm/i915/guc: capture GuC logs if FW fails to load
https://patchwork.freedesktop.org/api/1.0/series/23982/revisions/6/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-snb-2600)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:434s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:582s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:519s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:487s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:412s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:495s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:467s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:573s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:457s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:581s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:463s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:532s
fi-snb-2600  total:278  pass:248  dwarn:1   dfail:0   fail:0   skip:29  
time:416s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
8ddb7a7 drm/i915/guc: capture GuC logs if FW fails to load

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4774/
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[Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT

[Jon Bloomfield]

BXT requires accesses to the GTT (i.e. PTE updates) to be serialized
when IOMMU is enabled. This patch guarantees this by wrapping all
updates in stop_machine and using a flushing read to guarantee that
the GTT writes have reached their destination before restarting.

Signed-off-by: Jon Bloomfield 
Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 106 
 1 file changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7c769d7..6360d92 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2191,6 +2191,100 @@ static void gen8_ggtt_clear_range(struct 
i915_address_space *vm,
gen8_set_pte(_base[i], scratch_pte);
 }
 
+#ifdef CONFIG_INTEL_IOMMU
+struct insert_page {
+   struct i915_address_space *vm;
+   dma_addr_t addr;
+   u64 offset;
+   enum i915_cache_level level;
+};
+
+static int gen8_ggtt_insert_page__cb(void *_arg)
+{
+   struct insert_page *arg = _arg;
+
+   struct drm_i915_private *dev_priv = arg->vm->i915;
+
+   gen8_ggtt_insert_page(arg->vm, arg->addr,
+   arg->offset, arg->level, 0);
+
+   POSTING_READ(GFX_FLSH_CNTL_GEN6);
+
+   return 0;
+}
+
+static void gen8_ggtt_insert_page__BKL(struct i915_address_space *vm,
+  dma_addr_t addr,
+  u64 offset,
+  enum i915_cache_level level,
+  u32 unused)
+{
+   struct insert_page arg = { vm, addr, offset, level };
+
+   stop_machine(gen8_ggtt_insert_page__cb, , NULL);
+}
+
+
+struct insert_entries {
+   struct i915_address_space *vm;
+   struct sg_table *st;
+   u64 start;
+   enum i915_cache_level level;
+};
+
+static int gen8_ggtt_insert_entries__cb(void *_arg)
+{
+   struct insert_entries *arg = _arg;
+
+   struct drm_i915_private *dev_priv = arg->vm->i915;
+
+   gen8_ggtt_insert_entries(arg->vm, arg->st,
+   arg->start, arg->level, 0);
+
+   POSTING_READ(GFX_FLSH_CNTL_GEN6);
+
+   return 0;
+}
+
+static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
+ struct sg_table *st,
+ u64 start,
+ enum i915_cache_level level,
+ u32 unused)
+{
+   struct insert_entries arg = { vm, st, start, level };
+
+   stop_machine(gen8_ggtt_insert_entries__cb, , NULL);
+}
+
+struct clear_range {
+   struct i915_address_space *vm;
+   u64 start;
+   u64 length;
+};
+
+static int gen8_ggtt_clear_range__cb(void *_arg)
+{
+   struct clear_range *arg = _arg;
+
+   struct drm_i915_private *dev_priv = arg->vm->i915;
+
+   gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
+
+   POSTING_READ(GFX_FLSH_CNTL_GEN6);
+
+   return 0;
+}
+
+static void gen8_ggtt_clear_range__BKL(struct i915_address_space *vm,
+   u64 start,
+   u64 length)
+{
+   struct clear_range arg = { vm, start, length };
+   stop_machine(gen8_ggtt_clear_range__cb, , NULL);
+}
+#endif
+
 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
  u64 start, u64 length)
 {
@@ -2789,6 +2883,18 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
ggtt->base.insert_entries = gen8_ggtt_insert_entries;
 
+#ifdef CONFIG_INTEL_IOMMU
+   /* Serialize GTT updates on BXT if VT-d is on. */
+   if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped) {
+   ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
+   ggtt->base.insert_page= gen8_ggtt_insert_page__BKL;
+   if (!USES_FULL_PPGTT(dev_priv) ||
+   intel_scanout_needs_vtd_wa(dev_priv)) {
+   ggtt->base.clear_range = gen8_ggtt_clear_range__BKL;
+   }
+   }
+#endif
+
ggtt->invalidate = gen6_ggtt_invalidate;
 
return ggtt_probe_common(ggtt, size);
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.BAT: success for Gen8+ engine-reset (rev11)

[Patchwork]

== Series Details ==

Series: Gen8+ engine-reset (rev11)
URL   : https://patchwork.freedesktop.org/series/21868/
State : success

== Summary ==

Series 21868v11 Gen8+ engine-reset
https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/11/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:441s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:438s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:590s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:516s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:485s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:417s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:413s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:495s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:566s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:475s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:574s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:464s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:497s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:436s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:407s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
1b35e7e drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs
55b2a8a drm/i915: Watchdog timeout: Include threshold value in error state
6b3b3a9 drm/i915: Watchdog timeout: DRM kernel interface to set the timeout
7c8e3b2 drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+
2d0df1b drm/i915: Watchdog timeout: IRQ handler for gen8+
057fcc9 drm/i915: Watchdog timeout: Pass GuC shared data structure during param 
load
c992439 drm/i915/guc: Add support for reset engine using GuC commands
dd0958f drm/i915/guc: Rename the function that resets the GuC
d6fee33 drm/i915/guc: Provide register list to be saved/restored during engine 
reset
072b5a0 drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder
be5c46e drm/i915/selftests: reset engine self tests
6b31b7c drm/i915: Add engine reset count in get-reset-stats ioctl
8d68656 drm/i915: Enable Engine reset and recovery support
d2e1dcc drm/i915: Carry on with reset even if hw engine is not ready
6b5864d drm/i915: Export per-engine reset count info to debugfs
b7021f1 drm/i915: Add engine reset count to error state
4edfcaf drm/i915: Add support for per engine reset recovery
1317a93 drm/i915: Modify error handler for per engine hang recovery
7ac0078 drm/i915: Update i915.reset to handle engine resets
88e47d5 drm/i915: Look for active requests earlier in the reset path

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4773/
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Re: [Intel-gfx] [PATCH 06/14] drm/i915/perf: rework mux configurations queries

[Lionel Landwerlin]

On 22/05/17 17:51, Matthew Auld wrote:

On 05/17, Lionel Landwerlin wrote:

Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mechanism to allow more than one set of registers
to be programmed.

So the previous behaviour of applying only one mux config depending on
the slices/sublices was wrong? Since now we seem to concatenate the mux
configs.


Yes that was incorrect previously.




Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_drv.h|   5 +-
  drivers/gpu/drm/i915/i915_oa_hsw.c | 211 -
  drivers/gpu/drm/i915/i915_perf.c   |   7 +-
  3 files changed, 144 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18e12e61949b..56ed5a0651e2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2353,8 +2353,9 @@ struct drm_i915_private {
  
  			int metrics_set;
  
-			const struct i915_oa_reg *mux_regs;

-   int mux_regs_len;
+   const struct i915_oa_reg *mux_regs[1];
+   int mux_regs_lens[1];
+   int n_mux_regs;

So this is more like n_mux_configs ?


Sure, thanks for looking through those patches again :)



Reviewed-by: Matthew Auld 


const struct i915_oa_reg *b_counter_regs;
int b_counter_regs_len;
  
diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c

index 4ddf756add31..ccd6e5124992 100644
--- a/drivers/gpu/drm/i915/i915_oa_hsw.c
+++ b/drivers/gpu/drm/i915/i915_oa_hsw.c
@@ -109,12 +109,21 @@ static const struct i915_oa_reg mux_config_render_basic[] 
= {
{ _MMIO(0x25428), 0x00042049 },
  };
  
-static const struct i915_oa_reg *

+static int
  get_render_basic_mux_config(struct drm_i915_private *dev_priv,
-   int *len)
+   const struct i915_oa_reg **regs,
+   int *lens)
  {
-   *len = ARRAY_SIZE(mux_config_render_basic);
-   return mux_config_render_basic;
+   int n = 0;
+
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+   regs[n] = mux_config_render_basic;
+   lens[n] = ARRAY_SIZE(mux_config_render_basic);
+   n++;
+
+   return n;
  }
  
  static const struct i915_oa_reg b_counter_config_compute_basic[] = {

@@ -172,12 +181,21 @@ static const struct i915_oa_reg 
mux_config_compute_basic[] = {
{ _MMIO(0x25428), 0x0c03 },
  };
  
-static const struct i915_oa_reg *

+static int
  get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
-int *len)
+const struct i915_oa_reg **regs,
+int *lens)
  {
-   *len = ARRAY_SIZE(mux_config_compute_basic);
-   return mux_config_compute_basic;
+   int n = 0;
+
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+   regs[n] = mux_config_compute_basic;
+   lens[n] = ARRAY_SIZE(mux_config_compute_basic);
+   n++;
+
+   return n;
  }
  
  static const struct i915_oa_reg b_counter_config_compute_extended[] = {

@@ -221,12 +239,21 @@ static const struct i915_oa_reg 
mux_config_compute_extended[] = {
{ _MMIO(0x25428), 0x },
  };
  
-static const struct i915_oa_reg *

+static int
  get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
-   int *len)
+   const struct i915_oa_reg **regs,
+   int *lens)
  {
-   *len = ARRAY_SIZE(mux_config_compute_extended);
-   return mux_config_compute_extended;
+   int n = 0;
+
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+   regs[n] = mux_config_compute_extended;
+   lens[n] = ARRAY_SIZE(mux_config_compute_extended);
+   n++;
+
+   return n;
  }
  
  static const struct i915_oa_reg b_counter_config_memory_reads[] = {

@@ -281,12 +308,21 @@ static const struct i915_oa_reg mux_config_memory_reads[] 
= {
{ _MMIO(0x25428), 0x },
  };
  
-static const struct i915_oa_reg *

+static int
  get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
-   int *len)
+   const struct i915_oa_reg **regs,
+   int *lens)
  {
-   *len = ARRAY_SIZE(mux_config_memory_reads);
-   return mux_config_memory_reads;
+   int n = 0;
+
+   BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);

[Intel-gfx] [PATCH v6] drm/i915/guc: capture GuC logs if FW fails to load

[Daniele Ceraolo Spurio]

We're currently deleting the GuC logs if the FW fails to load, but those
are still useful to understand why the loading failed. Keeping the
object around allows us to access them after driver load is completed.

v2: keep the object around instead of using kernel memory (chris)
don't store the logs in the gpu_error struct (Chris)
add a check on guc_log_level to avoid snapshotting empty logs

v3: use separate debugfs for error log (Chris)

v4: rebased

v5: clean up obj selection, move err_load inside guc_log, move err_load
cleanup, rename functions (Michal)

v6: move obj back to intel_guc, move functions to intel_uc.c, don't
clear obj on new GuC load, free object only if enable_guc_loading
is set (Michal)

Cc: Chris Wilson 
Cc: Oscar Mateo 
Cc: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 39 -
 drivers/gpu/drm/i915/intel_uc.c | 25 ++--
 drivers/gpu/drm/i915/intel_uc.h |  3 +++
 3 files changed, 51 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index c08a6d8..7e0816c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2586,27 +2586,37 @@ static int i915_guc_stage_pool(struct seq_file *m, void 
*data)
 
 static int i915_guc_log_dump(struct seq_file *m, void *data)
 {
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_i915_gem_object *obj;
-   int i = 0, pg;
-
-   if (!dev_priv->guc.log.vma)
-   return 0;
+   struct drm_info_node *node = m->private;
+   struct drm_i915_private *dev_priv = node_to_i915(node);
+   bool dump_load_err = !!node->info_ent->data;
+   struct drm_i915_gem_object *obj = NULL;
+   u32 *log;
+   int i = 0;
 
-   obj = dev_priv->guc.log.vma->obj;
-   for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
-   u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
+   if (dump_load_err)
+   obj = dev_priv->guc.load_err_log;
+   else if (dev_priv->guc.log.vma)
+   obj = dev_priv->guc.log.vma->obj;
 
-   for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
-   seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
-  *(log + i), *(log + i + 1),
-  *(log + i + 2), *(log + i + 3));
+   if (!obj)
+   return 0;
 
-   kunmap_atomic(log);
+   log = i915_gem_object_pin_map(obj, I915_MAP_WC);
+   if (IS_ERR(log)) {
+   DRM_DEBUG("Failed to pin object\n");
+   seq_puts(m, "(log data unaccessible)\n");
+   return PTR_ERR(log);
}
 
+   for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
+   seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
+  *(log + i), *(log + i + 1),
+  *(log + i + 2), *(log + i + 3));
+
seq_putc(m, '\n');
 
+   i915_gem_object_unpin_map(obj);
+
return 0;
 }
 
@@ -4791,6 +4801,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, 
struct file *file)
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+   {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index d27b527..e6e913f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -286,6 +286,23 @@ static void guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
 }
 
+static void guc_capture_load_err_log(struct intel_guc *guc)
+{
+   if (!guc->log.vma || i915.guc_log_level < 0)
+   return;
+
+   if (!guc->load_err_log)
+   guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
+
+   return;
+}
+
+static void guc_free_load_err_log(struct intel_guc *guc)
+{
+   if (guc->load_err_log)
+   i915_gem_object_put(guc->load_err_log);
+}
+
 static int guc_enable_communication(struct intel_guc *guc)
 {
/* XXX: placeholder for alternate setup */
@@ -355,11 +372,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 
/* Did we succeded or run out of retries? */
if (ret)
-   goto err_submission;
+   goto err_log_capture;
 
ret = guc_enable_communication(guc);
if (ret)
-   goto err_submission;
+   goto 

[Intel-gfx] [PATCH v8 13/20] drm/i915/guc: Rename the function that resets the GuC

[Michel Thierry]

intel_guc_reset sounds more like the microcontroller is the one performing
a reset, while in this case is the opposite. intel_reset_guc not only
makes it clearer, it follows the other intel_reset functions available.

v2: Print error message in English.

Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_uc.c | 4 ++--
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28f48678c91f..d2709dd361b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3053,7 +3053,7 @@ extern bool intel_has_gpu_reset(struct drm_i915_private 
*dev_priv);
 extern void i915_reset(struct drm_i915_private *dev_priv);
 extern int i915_reset_engine(struct intel_engine_cs *engine);
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
-extern int intel_guc_reset(struct drm_i915_private *dev_priv);
+extern int intel_reset_guc(struct drm_i915_private *dev_priv);
 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index d27b5277901c..735ace31ca8f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -46,9 +46,9 @@ static int __intel_uc_reset_hw(struct drm_i915_private 
*dev_priv)
int ret;
u32 guc_status;
 
-   ret = intel_guc_reset(dev_priv);
+   ret = intel_reset_guc(dev_priv);
if (ret) {
-   DRM_ERROR("GuC reset failed, ret = %d\n", ret);
+   DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
return ret;
}
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a89738655460..56fd3e9d3fbf 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1851,7 +1851,7 @@ bool intel_has_reset_engine(struct drm_i915_private 
*dev_priv)
i915.reset >= 2);
 }
 
-int intel_guc_reset(struct drm_i915_private *dev_priv)
+int intel_reset_guc(struct drm_i915_private *dev_priv)
 {
int ret;
 
-- 
2.11.0

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[Intel-gfx] [PATCH v8 17/20] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+

[Michel Thierry]

Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.

v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_start. Request space of
combined start_watchdog, bb_start and stop_watchdog to avoid any error
after emitting bb_start.

v3: There were too many req->engine in emit_bb_start.
Use GEM_BUG_ON instead of returning a very late EINVAL in the remote
case of watchdog misprogramming; set correct LRI cmd size in
emit_stop_watchdog. (Chris)

Cc: Chris Wilson 
Signed-off-by: Tomas Elf 
Signed-off-by: Ian Lister 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem_context.h |  4 ++
 drivers/gpu/drm/i915/intel_lrc.c| 85 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++
 3 files changed, 89 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94558b..88700bdbb4e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -150,6 +150,10 @@ struct i915_gem_context {
u32 *lrc_reg_state;
u64 lrc_desc;
int pin_count;
+   /** watchdog_threshold: hw watchdog threshold value,
+* in clock counts
+*/
+   u32 watchdog_threshold;
bool initialised;
} engine[I915_NUM_ENGINES];
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 144bb9abd400..d7a6ba48cd18 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1386,7 +1386,10 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
  u64 offset, u32 len,
  const unsigned int flags)
 {
+   struct intel_engine_cs *engine = req->engine;
u32 *cs;
+   u32 num_dwords;
+   bool watchdog_running = false;
int ret;
 
/* Don't rely in hw updating PDPs, specially in lite-restore.
@@ -1396,20 +1399,38 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
 * not idle). PML4 is allocated during ppgtt init so this is
 * not needed in 48-bit.*/
if (req->ctx->ppgtt &&
-   (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) 
&&
+   (intel_engine_flag(engine) & req->ctx->ppgtt->pd_dirty_rings) &&
!i915_vm_is_48bit(>ctx->ppgtt->base) &&
!intel_vgpu_active(req->i915)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
 
-   req->ctx->ppgtt->pd_dirty_rings &= 
~intel_engine_flag(req->engine);
+   req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
+   }
+
+   /* bb_start only */
+   num_dwords = 4;
+
+   /* check if watchdog will be required */
+   if (req->ctx->engine[engine->id].watchdog_threshold != 0) {
+   GEM_BUG_ON(!engine->emit_start_watchdog ||
+  !engine->emit_stop_watchdog);
+
+   /* + start_watchdog (6) + stop_watchdog (4) */
+   num_dwords += 10;
+   watchdog_running = true;
}
 
-   cs = intel_ring_begin(req, 4);
+   cs = intel_ring_begin(req, num_dwords);
if (IS_ERR(cs))
return PTR_ERR(cs);
 
+   if (watchdog_running) {
+   /* Start watchdog timer */
+   cs = engine->emit_start_watchdog(req, cs);
+   }
+
/* FIXME(BDW): Address space and security selectors. */
*cs++ = MI_BATCH_BUFFER_START_GEN8 |
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
@@ -1417,8 +1438,13 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
*cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
 
+   if (watchdog_running) {
+   /* Cancel watchdog timer */
+   cs = engine->emit_stop_watchdog(req, cs);
+   }
+
+   intel_ring_advance(req, cs);
return 0;
 }
 
@@ -1585,6 +1611,49 @@ static void gen8_watchdog_irq_handler(unsigned long data)
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
 }
 
+static u32 *gen8_emit_start_watchdog(struct drm_i915_gem_request *req, u32 *cs)
+{
+   struct intel_engine_cs *engine = req->engine;
+   struct i915_gem_context *ctx = req->ctx;
+   struct intel_context *ce = >engine[engine->id];
+
+   /* XXX: no watchdog support in BCS engine */
+   GEM_BUG_ON(engine->id == BCS);
+
+   /*
+* watchdog register must never be 

[Intel-gfx] [PATCH v8 05/20] drm/i915: Add engine reset count to error state

[Michel Thierry]

Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.

A follow-up patch will provide this information in debugfs.

v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c   |  3 +++
 drivers/gpu/drm/i915/i915_drv.h   | 10 ++
 drivers/gpu/drm/i915/i915_gpu_error.c |  3 +++
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7925e103c8bd..51663abda5db 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1925,7 +1925,10 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 * process to program RING_MODE, HWSP and re-enable submission.
 */
ret = engine->init_hw(engine);
+   if (ret)
+   goto out;
 
+   error->reset_engine_count[engine->id]++;
 out:
return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9fd849dab8b..ada9e2cc969c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -920,6 +920,7 @@ struct i915_gpu_state {
enum intel_engine_hangcheck_action hangcheck_action;
struct i915_address_space *vm;
int num_requests;
+   u32 reset_count;
 
/* position of active request inside the ring */
u32 rq_head, rq_post, rq_tail;
@@ -1562,6 +1563,9 @@ struct i915_gpu_error {
 #define I915_RESET_ENGINE_IN_PROGRESS  2
 #define I915_WEDGED(BITS_PER_LONG - 1)
 
+   /** Number of times an engine has been reset */
+   u32 reset_engine_count[I915_NUM_ENGINES];
+
/**
 * Waitqueue to signal when a hang is detected. Used to for waiters
 * to release the struct_mutex for the reset to procede.
@@ -3417,6 +3421,12 @@ static inline u32 i915_reset_count(struct i915_gpu_error 
*error)
return READ_ONCE(error->reset_count);
 }
 
+static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
+ struct intel_engine_cs *engine)
+{
+   return READ_ONCE(error->reset_engine_count[engine->id]);
+}
+
 struct drm_i915_gem_request *
 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 762685ba86da..ebd5501ec134 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -463,6 +463,7 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,
err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
   ee->hangcheck_timestamp,
   jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
+   err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 
error_print_request(m, "  ELSP[0]: ", >execlist[0]);
error_print_request(m, "  ELSP[1]: ", >execlist[1]);
@@ -1244,6 +1245,8 @@ static void error_record_engine_registers(struct 
i915_gpu_state *error,
ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
ee->hangcheck_action = engine->hangcheck.action;
ee->hangcheck_stalled = engine->hangcheck.stalled;
+   ee->reset_count = i915_reset_engine_count(_priv->gpu_error,
+ engine);
 
if (USES_PPGTT(dev_priv)) {
int i;
-- 
2.11.0

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[Intel-gfx] [PATCH v8 12/20] drm/i915/guc: Provide register list to be saved/restored during engine reset

[Michel Thierry]

GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of registers that we want GuC to save and
restore. This is not an issue in case of engine reset as driver initializes
most of them following an engine reset, but in case of media reset (aka
watchdog reset) which is completely internal to GuC (including resubmission
of hung workload), it is necessary to provide this list, otherwise GuC won't
be able to schedule further workloads after a reset. This is the minimal
set of registers identified for things to work as expected but if we see
any new issues, this register list can be expanded.

In order to not loose any existing workarounds, we have to let GuC know
the registers and its values. These will be reapplied after the reset.
Note that we can't just read the current value because most of these
registers are masked (so we have a workaround for a workaround for a
workaround).

v2: REGSET_MASKED is too difficult for GuC, use REGSET_SAVE_DEFAULT_VALUE
and current value from RING_MODE reg instead; no need to preserve
head/tail either, be extra paranoid and save whitelisted registers (Daniele).

v3: Workarounds added only once during _init_workarounds also have to
been restored, or we risk loosing them after internal GuC reset
(Daniele).

v4: Rename macro used to keep track the workaround registers we will
have to restore after reset (s/I915_GUC_REG_WRITE/WA_REG_WR_GUC_RESTORE).

v5: Only ask guc to reapply workarounds in case of render reset (Daniele).

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Arun Siluvery 
Signed-off-by: Jeff McGee 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h|  3 ++
 drivers/gpu/drm/i915/i915_guc_submission.c | 70 +-
 drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++-
 3 files changed, 116 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ada9e2cc969c..28f48678c91f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1869,7 +1869,10 @@ struct i915_wa_reg {
 
 struct i915_workarounds {
struct i915_wa_reg reg[I915_MAX_WA_REGS];
+   /* list of registers (and their values) that GuC will have to restore */
+   struct i915_wa_reg guc_reg[GUC_REGSET_MAX_REGISTERS];
u32 count;
+   u32 guc_count;
u32 hw_whitelist_count[I915_NUM_ENGINES];
 };
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 50d3e5aaf566..8650b6ec2f2d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1017,6 +1017,24 @@ static void guc_policies_init(struct guc_policies 
*policies)
policies->is_valid = 1;
 }
 
+/*
+ * In this macro it is highly unlikely to exceed max value but even if we did
+ * it is not an error so just throw a warning and continue. Only side effect
+ * in continuing further means some registers won't be added to save/restore
+ * list.
+ */
+#define GUC_ADD_MMIO_REG_ADS(node, reg_addr, _flags, defvalue) \
+   do {\
+   u32 __count = node->number_of_registers;\
+   if (WARN_ON(__count >= GUC_REGSET_MAX_REGISTERS))   \
+   continue;   \
+   node->registers[__count].offset = reg_addr.reg; \
+   node->registers[__count].flags = (_flags);  \
+   if (defvalue)   \
+   node->registers[__count].value = (defvalue);\
+   node->number_of_registers++;\
+   } while (0)
+
 static int guc_ads_create(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1030,6 +1048,7 @@ static int guc_ads_create(struct intel_guc *guc)
u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
} __packed *blob;
struct intel_engine_cs *engine;
+   struct i915_workarounds *workarounds = _priv->workarounds;
enum intel_engine_id id;
u32 base;
 
@@ -1049,6 +1068,49 @@ static int guc_ads_create(struct intel_guc *guc)
 
/* MMIO reg state */
for_each_engine(engine, dev_priv, id) {
+   u32 i;
+   struct guc_mmio_regset *eng_reg =
+   >reg_state.engine_reg[engine->guc_id];
+
+   /*
+* Provide a list of registers to be saved/restored during gpu
+* reset. This is mainly required for Media reset (aka watchdog
+* timeout) which is completely under the 

[Intel-gfx] [PATCH v8 15/20] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load

[Michel Thierry]

For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).

This information should be in DWORD 9 of the GUC_CTL structure.

v2: Use guc_ggtt_offset (Chris).
Store the ggtt offset of the default ctx as we needed for
suspend/resume/reset (Daniele).

Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 21 ++---
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 11 +++
 drivers/gpu/drm/i915/intel_uc.h|  2 ++
 4 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 66bf521e5007..80da01a907cf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1387,7 +1387,6 @@ void i915_guc_submission_reenable_engine(struct 
intel_engine_cs *engine)
 int intel_guc_suspend(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
u32 data[3];
 
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -1395,13 +1394,11 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 
gen9_disable_guc_interrupts(dev_priv);
 
-   ctx = dev_priv->kernel_context;
-
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
data[1] = GUC_POWER_D1;
-   /* first page is shared data with GuC */
-   data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+   /* first page of default ctx is shared data with GuC */
+   data[2] = guc->shared_data_offset;
 
return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -1413,7 +1410,6 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 int intel_guc_resume(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
u32 data[3];
 
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -1422,12 +1418,10 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
 
-   ctx = dev_priv->kernel_context;
-
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
-   /* first page is shared data with GuC */
-   data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+   /* first page of default ctx is shared data with GuC */
+   data[2] = guc->shared_data_offset;
 
return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -1436,14 +1430,11 @@ int i915_guc_reset_engine(struct intel_engine_cs 
*engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
u32 data[7];
 
if (!i915.enable_guc_submission)
return 0;
 
-   ctx = dev_priv->kernel_context;
-
/*
 * The affected context report is populated by GuC and is provided
 * to the driver using the shared page. We request for it but don't
@@ -1455,8 +1446,8 @@ int i915_guc_reset_engine(struct intel_engine_cs *engine)
data[3] = 0;
data[4] = 0;
data[5] = guc->execbuf_client->stage_id;
-   /* first page is shared data with GuC */
-   data[6] = guc_ggtt_offset(ctx->engine[RCS].state);
+   /* first page of default ctx is shared data with GuC */
+   data[6] = guc->shared_data_offset;
 
return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 081f2cf614e6..a2d0cba2f8b9 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -135,7 +135,7 @@
 #define   GUC_ADS_ADDR_SHIFT   11
 #define   GUC_ADS_ADDR_MASK0xf800
 
-#define GUC_CTL_RSRVD  9
+#define GUC_CTL_SHARED_DATA9
 
 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index d9045b6e897b..8cd5c2bf9510 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -108,6 +108,7 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
 {
struct intel_guc *guc = _priv->guc;
u32 params[GUC_CTL_MAX_DWORDS];
+   struct i915_gem_context *ctx;
int i;
 
memset(, 0, sizeof(params));
@@ -156,6 +157,16 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 

[Intel-gfx] [PATCH v8 09/20] drm/i915: Add engine reset count in get-reset-stats ioctl

[Michel Thierry]

Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.

To start the discussion, include just a total engine reset count. If it
is deemed useful, it can be extended to report each engine separately.

v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 14 +++---
 include/uapi/drm/i915_drm.h |  6 +-
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index c5d1666d7071..210d6638e97b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1029,9 +1029,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_reset_stats *args = data;
struct i915_gem_context *ctx;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
int ret;
 
-   if (args->flags || args->pad)
+   if (args->flags)
return -EINVAL;
 
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
@@ -1047,10 +1049,16 @@ int i915_gem_context_reset_stats_ioctl(struct 
drm_device *dev,
return PTR_ERR(ctx);
}
 
-   if (capable(CAP_SYS_ADMIN))
+   if (capable(CAP_SYS_ADMIN)) {
args->reset_count = i915_reset_count(_priv->gpu_error);
-   else
+   for_each_engine(engine, dev_priv, id)
+   args->reset_engine_count +=
+   i915_reset_engine_count(_priv->gpu_error,
+   engine);
+   } else {
args->reset_count = 0;
+   args->reset_engine_count = 0;
+   }
 
args->batch_active = ctx->guilty_count;
args->batch_pending = ctx->active_count;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f24a80d2d42e..fadedefba6db 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1278,7 +1278,11 @@ struct drm_i915_reset_stats {
/* Number of batches lost pending for execution, for this context */
__u32 batch_pending;
 
-   __u32 pad;
+   union {
+   __u32 pad;
+   /* Engine resets since boot/module reload, for all contexts */
+   __u32 reset_engine_count;
+   };
 };
 
 struct drm_i915_gem_userptr {
-- 
2.11.0

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[Intel-gfx] [PATCH v8 18/20] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

[Michel Thierry]

Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.

The recommended default watchdog threshold for video engines is 6 us,
since this has been _empirically determined_ to be a good compromise for
low-latency requirements and low rate of false positives. The default
register value is ~106000us and the theoretical max value (all 1s) is
353 seconds.

Note, UABI engine ids and i915 engine ids are different, and this patch
uses the i915 ones. Some kind of mapping table [1] is required if we
decide to use the UABI engine ids.

[1] 
http://patchwork.freedesktop.org/patch/msgid/20170329135831.30254-2-ch...@chris-wilson.co.uk

v2: Fixed get api to return values in microseconds. Threshold updated to
be per context engine. Check for u32 overflow. Capture ctx threshold
value in error state.

v3: Add a way to get array size, short-cut to disable all thresholds,
return EFAULT / EINVAL as needed. Move the capture of the threshold
value in the error state into a new patch. BXT has a different
timestamp base (because why not?).

v4: Checking if watchdog is available should be the first thing to
do, instead of giving false hopes to abi users; remove unnecessary & in
set_watchdog; ignore args->size in getparam.

v5: GEN9-LP platforms have a different crystal clock frequency, use the
right timestamp base for them (magic 8-ball predicts this will change
again later on, so future-proof it). (Daniele)

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h | 56 +++
 drivers/gpu/drm/i915/i915_gem_context.c | 95 +
 drivers/gpu/drm/i915/intel_lrc.c|  5 +-
 include/uapi/drm/i915_drm.h |  1 +
 4 files changed, 155 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7141d65c3a9..3a757ef7dec0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2191,6 +2191,9 @@ struct drm_i915_private {
struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 
965 */
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
+   /* Command stream timestamp base - helps define watchdog threshold */
+   u32 cs_timestamp_base;
+
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
unsigned int max_cdclk_freq;
@@ -3554,6 +3557,59 @@ i915_gem_context_lookup_timeline(struct i915_gem_context 
*ctx,
return >timeline.engine[engine->id];
 }
 
+/*
+ * BDW, CHV & SKL+ Timestamp timer resolution = 0.080 uSec,
+ * or 1250 counts per second, or ~12 counts per microsecond.
+ *
+ * But BXT/GLK Timestamp timer resolution is different, 0.052 uSec,
+ * or 1920 counts per second, or ~19 counts per microsecond.
+ *
+ * Future-proofing, some day it won't be as simple as just GEN & IS_LP.
+ */
+#define GEN8_TIMESTAMP_CNTS_PER_USEC 12
+#define GEN9_LP_TIMESTAMP_CNTS_PER_USEC 19
+static inline u32 cs_timestamp_in_us(struct drm_i915_private *dev_priv)
+{
+   u32 cs_timestamp_base = dev_priv->cs_timestamp_base;
+
+   if (cs_timestamp_base)
+   return cs_timestamp_base;
+
+   switch (INTEL_GEN(dev_priv)) {
+   default:
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   /* fall through */
+   case 9:
+   cs_timestamp_base = IS_GEN9_LP(dev_priv) ?
+   GEN9_LP_TIMESTAMP_CNTS_PER_USEC :
+   GEN8_TIMESTAMP_CNTS_PER_USEC;
+   break;
+   case 8:
+   cs_timestamp_base = GEN8_TIMESTAMP_CNTS_PER_USEC;
+   break;
+   }
+
+   dev_priv->cs_timestamp_base = cs_timestamp_base;
+   return cs_timestamp_base;
+}
+
+static inline u32
+watchdog_to_us(struct drm_i915_private *dev_priv, u32 value_in_clock_counts)
+{
+   return value_in_clock_counts / cs_timestamp_in_us(dev_priv);
+}
+
+static inline u32
+watchdog_to_clock_counts(struct drm_i915_private *dev_priv, u64 value_in_us)
+{
+   u64 threshold = value_in_us * cs_timestamp_in_us(dev_priv);
+
+   if (overflows_type(threshold, u32))
+   return -EINVAL;
+
+   return threshold;
+}
+
 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 210d6638e97b..a56e79430082 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -337,6 +337,95 @@ i915_gem_context_create_gvt(struct drm_device *dev)

[Intel-gfx] [PATCH v8 16/20] drm/i915: Watchdog timeout: IRQ handler for gen8+

[Michel Thierry]

*** General ***

Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to support this form of hang detection
is to implement the interrupt handling support as well as watchdog command
emission before and after the emitted batch buffer start instruction in the
ring buffer.

The principle of the hang detection mechanism is as follows:

1. Once the decision has been made to enable watchdog timeout for a
particular batch buffer and the driver is in the process of emitting the
batch buffer start instruction into the ring buffer it also emits a
watchdog timer start instruction before and a watchdog timer cancellation
instruction after the batch buffer start instruction in the ring buffer.

2. Once the GPU execution reaches the watchdog timer start instruction
the hardware watchdog counter is started by the hardware. The counter
keeps counting until either reaching a previously configured threshold
value or the timer cancellation instruction is executed.

2a. If the counter reaches the threshold value the hardware fires a
watchdog interrupt that is picked up by the watchdog interrupt handler.
This means that a hang has been detected and the driver needs to deal with
it the same way it would deal with a engine hang detected by the periodic
hang checker. The only difference between the two is that we already blamed
the active request (to ensure an engine reset).

2b. If the batch buffer completes and the execution reaches the watchdog
cancellation instruction before the watchdog counter reaches its
threshold value the watchdog is cancelled and nothing more comes of it.
No hang is detected.

Note about future interaction with preemption: Preemption could happen
in a command sequence prior to watchdog counter getting disabled,
resulting in watchdog being triggered following preemption (e.g. when
watchdog had been enabled in the low priority batch). The driver will
need to explicitly disable the watchdog counter as part of the
preemption sequence.

*** This patch introduces: ***

1. IRQ handler code for watchdog timeout allowing direct hang recovery
based on hardware-driven hang detection, which then integrates directly
with the hang recovery path. This is independent of having per-engine reset
or just full gpu reset.

2. Watchdog specific register information.

Currently the render engine and all available media engines support
watchdog timeout (VECS is only supported in GEN9). The specifications elude
to the BCS engine being supported but that is currently not supported by
this commit.

Note that the value to stop the counter is different between render and
non-render engines in GEN8; GEN9 onwards it's the same.

v2: Move irq handler to tasklet, arm watchdog for a 2nd time to check
against false-positives.

v3: Don't use high priority tasklet, use engine_last_submit while
checking for false-positives. From GEN9 onwards, the stop counter bit is
the same for all engines.

v4: Remove unnecessary brackets, use current_seqno to mark the request
as guilty in the hangcheck/capture code.

Signed-off-by: Tomas Elf 
Signed-off-by: Ian Lister 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h |  4 ++
 drivers/gpu/drm/i915/i915_irq.c | 12 +-
 drivers/gpu/drm/i915/i915_reg.h |  6 +++
 drivers/gpu/drm/i915/intel_hangcheck.c  | 13 +--
 drivers/gpu/drm/i915/intel_lrc.c| 69 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++
 6 files changed, 103 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7fba5cf4db1b..d7141d65c3a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1552,6 +1552,9 @@ struct i915_gpu_error {
 * acquire the struct_mutex to reset an engine, we need an explicit
 * flag to prevent two concurrent reset-engine attempts.
 *
+* #I915_RESET_WATCHDOG - When hw detects a hang before us, we can use
+* I915_RESET_WATCHDOG to report the hang detection cause accurately.
+*
 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
 * i915_gem_request_alloc(), this bit is checked and the sequence
@@ -1561,6 +1564,7 @@ struct i915_gpu_error {
 #define I915_RESET_BACKOFF 0
 #define I915_RESET_HANDOFF 1
 #define I915_RESET_ENGINE_IN_PROGRESS  2
+#define I915_RESET_WATCHDOG3
 #define I915_WEDGED(BITS_PER_LONG - 1)
 
/** Number of times an engine has been reset */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [PATCH v8 07/20] drm/i915: Carry on with reset even if hw engine is not ready

[Michel Thierry]

We try to get the engines ready/idle before triggering the reset, but it
has been seen that sometimes the hw never acknowledges this.

If we miss the acknowledgment, carry on with the reset instead of
leaving the GPU in a wedged state.

The frequency of missed acknowledgment from hw is low, but it has been
seen at least once in CI.

References: https://intel-gfx-ci.01.org/CI/Trybot_831/
Reported-by: Antonio Argenziano 
Cc: Mika Kuoppala 
Cc: Chris Wilson 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index fdfd8c66c956..a89738655460 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1747,8 +1747,12 @@ static int gen8_reset_engine_start(struct 
intel_engine_cs *engine)
 RESET_CTL_READY_TO_RESET,
 RESET_CTL_READY_TO_RESET,
 700);
-   if (ret)
-   DRM_ERROR("%s: reset request timeout\n", engine->name);
+   if (GEM_WARN_ON(ret)) {
+   /* hw did not ack ready-to-reset, reset anyway */
+   DRM_DEBUG_DRIVER("%s: reset request timeout, continue\n",
+engine->name);
+   ret = 0;
+   }
 
return ret;
 }
-- 
2.11.0

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[Intel-gfx] [PATCH v8 02/20] drm/i915: Update i915.reset to handle engine resets

[Michel Thierry]

In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_params.c | 6 +++---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e363d076..045cadb77285 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.load_detect_test = 0,
.force_reset_modeset_test = 0,
-   .reset = true,
+   .reset = 1,
.error_capture = true,
.invert_brightness = 0,
.disable_display = 0,
@@ -115,8 +115,8 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"Override/Ignore selection of SDVO panel mode in the VBT "
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
-module_param_named_unsafe(reset, i915.reset, bool, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
+module_param_named_unsafe(reset, i915.reset, int, 0600);
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset 
[default], 2=engine reset)");
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 module_param_named(error_capture, i915.error_capture, bool, 0600);
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 34148cc8637c..febbfdbd30bd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -51,6 +51,7 @@
func(int, use_mmio_flip); \
func(int, mmio_debug); \
func(int, edp_vswing); \
+   func(int, reset); \
func(unsigned int, inject_load_failure); \
/* leave bools at the end to not create holes */ \
func(bool, alpha_support); \
@@ -60,7 +61,6 @@
func(bool, prefault_disable); \
func(bool, load_detect_test); \
func(bool, force_reset_modeset_test); \
-   func(bool, reset); \
func(bool, error_capture); \
func(bool, disable_display); \
func(bool, verbose_state_checks); \
-- 
2.11.0

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[Intel-gfx] [PATCH v8 14/20] drm/i915/guc: Add support for reset engine using GuC commands

[Michel Thierry]

This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.

In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission. With GuC submission these tasks
are shared between driver and GuC. i915 is still responsible for detecting
a hang, and when it does it only requests GuC to reset that Engine. GuC
internally manages acquiring forcewake and idling the engine before actually
resetting it.

Once the reset is successful, i915 takes over again and handles resubmission.
The scheduler in i915 knows which requests are pending so after resetting
a engine, pending workloads/requests are resubmitted again.

v2: s/i915_guc_request_engine_reset/i915_guc_reset_engine/ to match the
non-guc funtion names.

v3: Removed debug message about engine restarting from which request,
since the new baseline do it regardless of submission mode. (Chris)

Signed-off-by: Arun Siluvery 
Signed-off-by: Jeff McGee 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c| 24 +++
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 48 ++
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  6 
 drivers/gpu/drm/i915/intel_uc.h|  1 +
 drivers/gpu/drm/i915/intel_uncore.c|  5 
 6 files changed, 75 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 51663abda5db..50c6d4cdecee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1910,11 +1910,21 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 */
i915_gem_reset_engine(engine, active_request);
 
-   /* finally, reset engine */
-   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
-   if (ret) {
-   DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
-   goto out;
+   if (!dev_priv->guc.execbuf_client) {
+   /* finally, reset engine */
+   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
+   if (ret) {
+   DRM_ERROR("Failed to reset %s, ret=%d\n",
+ engine->name, ret);
+   goto out;
+   }
+   } else {
+   ret = i915_guc_reset_engine(engine);
+   if (ret) {
+   DRM_ERROR("GuC failed to reset %s, ret=%d\n",
+ engine->name, ret);
+   goto out;
+   }
}
 
i915_gem_reset_finish_engine(engine);
@@ -1928,6 +1938,10 @@ int i915_reset_engine(struct intel_engine_cs *engine)
if (ret)
goto out;
 
+   /* for guc too */
+   if (dev_priv->guc.execbuf_client)
+   i915_guc_submission_reenable_engine(engine);
+
error->reset_engine_count[engine->id]++;
 out:
return ret;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d2709dd361b4..7fba5cf4db1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3054,6 +3054,7 @@ extern void i915_reset(struct drm_i915_private *dev_priv);
 extern int i915_reset_engine(struct intel_engine_cs *engine);
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
+extern int i915_guc_reset_engine(struct intel_engine_cs *engine);
 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 8650b6ec2f2d..66bf521e5007 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1361,6 +1361,25 @@ void i915_guc_submission_disable(struct drm_i915_private 
*dev_priv)
guc->execbuf_client = NULL;
 }
 
+void i915_guc_submission_reenable_engine(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct intel_guc *guc = _priv->guc;
+   struct i915_guc_client *client = guc->execbuf_client;
+   const int wqi_size = sizeof(struct guc_wq_item);
+   struct drm_i915_gem_request *rq;
+
+   GEM_BUG_ON(!client);
+   intel_guc_sample_forcewake(guc);
+
+   spin_lock_irq(>timeline->lock);
+   list_for_each_entry(rq, >timeline->requests, link) {
+   guc_client_update_wq_rsvd(client, wqi_size);
+   __i915_guc_submit(rq);
+   }
+   spin_unlock_irq(>timeline->lock);
+}
+
 /**
  * intel_guc_suspend() - notify GuC entering suspend state
  * @dev_priv:  i915 

[Intel-gfx] [PATCH v8 08/20] drm/i915: Enable Engine reset and recovery support

[Michel Thierry]

This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 045cadb77285..14e2c2e57f96 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.load_detect_test = 0,
.force_reset_modeset_test = 0,
-   .reset = 1,
+   .reset = 2,
.error_capture = true,
.invert_brightness = 0,
.disable_display = 0,
@@ -116,7 +116,7 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
 module_param_named_unsafe(reset, i915.reset, int, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset 
[default], 2=engine reset)");
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 
2=engine reset [default])");
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 module_param_named(error_capture, i915.error_capture, bool, 0600);
-- 
2.11.0

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[Intel-gfx] [PATCH v8 10/20] drm/i915/selftests: reset engine self tests

[Michel Thierry]

Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.

v2: rebase.
v3: use RESET_ENGINE_IN_PROGRESS flag.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 149 +++
 1 file changed, 149 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index aa31d6c0cdfb..8a3edb8bd440 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -322,6 +322,56 @@ static int igt_global_reset(void *arg)
return err;
 }
 
+static int igt_reset_engine(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   unsigned int reset_count, reset_engine_count;
+   int err = 0;
+
+   /* Check that we can issue a global GPU and engine reset */
+
+   if (!intel_has_gpu_reset(i915))
+   return 0;
+
+   if (!intel_has_reset_engine(i915))
+   return 0;
+
+   set_bit(I915_RESET_ENGINE_IN_PROGRESS, >gpu_error.flags);
+
+   for_each_engine(engine, i915, id) {
+   reset_count = i915_reset_count(>gpu_error);
+   reset_engine_count = i915_reset_engine_count(>gpu_error,
+engine);
+
+   err = i915_reset_engine(engine);
+   if (err) {
+   pr_err("i915_reset_engine failed\n");
+   break;
+   }
+
+   if (i915_reset_count(>gpu_error) != reset_count) {
+   pr_err("Full GPU reset recorded! (engine reset 
expected)\n");
+   err = -EINVAL;
+   break;
+   }
+
+   if (i915_reset_engine_count(>gpu_error, engine) ==
+   reset_engine_count) {
+   pr_err("No %s engine reset recorded!\n", engine->name);
+   err = -EINVAL;
+   break;
+   }
+   }
+
+   clear_bit(I915_RESET_ENGINE_IN_PROGRESS, >gpu_error.flags);
+   if (i915_terminally_wedged(>gpu_error))
+   err = -EIO;
+
+   return err;
+}
+
 static u32 fake_hangcheck(struct drm_i915_gem_request *rq)
 {
u32 reset_count;
@@ -526,13 +576,112 @@ static int igt_reset_queue(void *arg)
return err;
 }
 
+static int igt_render_engine_reset_fallback(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine = i915->engine[RCS];
+   struct hang h;
+   struct drm_i915_gem_request *rq;
+   unsigned int reset_count, reset_engine_count;
+   int err = 0;
+
+   /* Check that we can issue a global GPU and engine reset */
+
+   if (!intel_has_gpu_reset(i915))
+   return 0;
+
+   if (!intel_has_reset_engine(i915))
+   return 0;
+
+   set_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+   mutex_lock(>drm.struct_mutex);
+
+   err = hang_init(, i915);
+   if (err)
+   goto unlock;
+
+   rq = hang_create_request(, engine, i915->kernel_context);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   goto fini;
+   }
+
+   i915_gem_request_get(rq);
+   __i915_add_request(rq, true);
+
+   /* make reset engine fail */
+   rq->fence.error = -EIO;
+
+   if (!wait_for_hang(, rq)) {
+   pr_err("Failed to start request %x\n", rq->fence.seqno);
+   err = -EIO;
+   goto fini;
+   }
+
+   reset_engine_count = i915_reset_engine_count(>gpu_error, engine);
+   reset_count = fake_hangcheck(rq);
+
+   /* unlock since we'll call handle_error */
+   mutex_unlock(>drm.struct_mutex);
+   clear_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+
+   i915_handle_error(i915, intel_engine_flag(engine), "live test");
+
+   if (i915_reset_engine_count(>gpu_error, engine) !=
+   reset_engine_count) {
+   pr_err("render engine reset recorded! (full reset expected)\n");
+   err = -EINVAL;
+   goto fini;
+   }
+
+   if (i915_reset_count(>gpu_error) == reset_count) {
+   pr_err("No full GPU reset recorded!\n");
+   err = -EINVAL;
+   goto fini;
+   }
+
+   /*
+* by using fence.error = -EIO, full reset sets the wedged flag, do one
+* more full reset to re-enable the hw.
+*/
+   if (i915_terminally_wedged(>gpu_error)) {
+   set_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+   mutex_lock(>drm.struct_mutex);
+   rq->fence.error = 0;
+
+   set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
+   i915_reset(i915);
+   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
+   

[Intel-gfx] [PATCH v8 04/20] drm/i915: Add support for per engine reset recovery

[Michel Thierry]

This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.

Hangchecker determines which engines are hung and invokes error handler to
recover from it. Error handler schedules recovery for each of those engines
that are hung. The recovery procedure is as follows,
 - identifies the request that caused the hang and it is dropped
 - force engine to idle: this is done by issuing a reset request
 - reset the engine
 - re-init the engine to resume submissions.

If engine reset fails then we fall back to heavy weight full gpu reset
which resets all engines and reinitiazes complete state of HW and SW.

v2: Rebase.
v3: s/*engine_reset*/*reset_engine*/; freeze engine and irqs before
calling i915_gem_reset_engine (Chris).
v4: Rebase, modify i915_gem_reset_prepare to use a ring mask and
reuse the function for reset_engine.
v5: intel_reset_engine_start/cancel instead of request/unrequest_reset.
v6: Clean up reset_engine function to not require mutex, i.e. no need to call
revoke/restore_fences and _retire_requests (Chris).
v7: Remove leftovers from v5, i.e. no need to disable irq, hold
forcewake or wakeup the handoff bit (Chris).
v8: engine_retire_requests should be (and it was) static; explain that
we have to re-init the engine after reset, which is why the init_hw call
is needed; check reset-in-progress flag (Chris).
v9: Rebase, include code to pass the active request to gem_reset_engine
(as it is already done in full reset). Remove unnecessary
intel_reset_engine_start/cancel, these are executed as part of the
reset.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c | 48 -
 drivers/gpu/drm/i915/i915_drv.h |  5 +++
 drivers/gpu/drm/i915/i915_gem.c | 96 +
 3 files changed, 109 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f49f9d9273f2..7925e103c8bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1879,11 +1879,55 @@ void i915_reset(struct drm_i915_private *dev_priv)
  *
  * Reset a specific GPU engine. Useful if a hang is detected.
  * Returns zero on successful reset or otherwise an error code.
+ *
+ * Procedure is:
+ *  - identifies the request that caused the hang and it is dropped
+ *  - reset engine (which will force the engine to idle)
+ *  - re-init/configure engine
  */
 int i915_reset_engine(struct intel_engine_cs *engine)
 {
-   /* FIXME: replace me with engine reset sequence */
-   return -ENODEV;
+   int ret;
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_gpu_error *error = _priv->gpu_error;
+   struct drm_i915_gem_request *active_request;
+
+   GEM_BUG_ON(!test_bit(I915_RESET_ENGINE_IN_PROGRESS, >flags));
+
+   DRM_DEBUG_DRIVER("resetting %s\n", engine->name);
+
+   active_request = i915_gem_reset_prepare_engine(engine);
+   if (IS_ERR(active_request)) {
+   DRM_DEBUG_DRIVER("Previous reset failed, promote to full 
reset\n");
+   ret = PTR_ERR(active_request);
+   goto out;
+   }
+
+   /*
+* the request that caused the hang is stuck on elsp, we know the
+* active request and can drop it, adjust head to skip the offending
+* request to resume executing remaining requests in the queue.
+*/
+   i915_gem_reset_engine(engine, active_request);
+
+   /* finally, reset engine */
+   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
+   if (ret) {
+   DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
+   goto out;
+   }
+
+   i915_gem_reset_finish_engine(engine);
+
+   /*
+* The engine and its registers (and workarounds in case of render)
+* have been reset to their default values. Follow the init_ring
+* process to program RING_MODE, HWSP and re-enable submission.
+*/
+   ret = engine->init_hw(engine);
+
+out:
+   return ret;
 }
 
 static int i915_pm_suspend(struct device *kdev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6848ed75611d..f9fd849dab8b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3417,11 +3417,16 @@ static inline u32 i915_reset_count(struct 
i915_gpu_error *error)
return READ_ONCE(error->reset_count);
 }
 
+struct drm_i915_gem_request *
+i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
 void 

[Intel-gfx] [PATCH v8 11/20] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

[Michel Thierry]

From: Daniele Ceraolo Spurio 

The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
register the GuC can use to restore the provided whitelist when an
engine reset via GuC (which we still don't support) is triggered.

We're currently adding the mmio_base of the engine to the absolute
address of the RCS version of the register, which results in the wrong
offset. Fix it by using the definition we already have instead of
re-defining it in the GuC FW header.

Also add a comment to avoid future issues with FORCE_TO_NONPRIV
registers, which are also used by the workaround framework.

v2: improve comment (Michal), move comment about save/restore because it
is not related to the mmio_white_list field.

v3: rebase/resurrect.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michał Winiarski 
Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Cc: Oscar Mateo 
Reviewed-by: Michał Winiarski  (v2)
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 11 +--
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  1 -
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 777f48e9bb33..50d3e5aaf566 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1050,10 +1050,17 @@ static int guc_ads_create(struct intel_guc *guc)
/* MMIO reg state */
for_each_engine(engine, dev_priv, id) {
blob->reg_state.white_list[engine->guc_id].mmio_start =
-   engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
+   
i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(engine->mmio_base, 0));
 
-   /* Nothing to be saved or restored for now. */
+   /*
+* Note: if the GuC whitelist management is enabled, the values
+* should be filled using the workaround framework to avoid
+* inconsistencies with the handling of FORCE_TO_NONPRIV
+* registers.
+*/
blob->reg_state.white_list[engine->guc_id].count = 0;
+
+   /* Nothing to be saved or restored for now. */
}
 
/*
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 6156845641a3..e6f8079df94a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -394,7 +394,6 @@ struct guc_policies {
 #define GUC_REGSET_SAVE_CURRENT_VALUE  0x10
 
 #define GUC_REGSET_MAX_REGISTERS   25
-#define GUC_MMIO_WHITE_LIST_START  0x24d0
 #define GUC_MMIO_WHITE_LIST_MAX12
 #define GUC_S3_SAVE_SPACE_PAGES10
 
-- 
2.11.0

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[Intel-gfx] [PATCH v8 06/20] drm/i915: Export per-engine reset count info to debugfs

[Michel Thierry]

A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they are expected to trigger reset; these counts are checked before
and after the test to ensure the same.

v2: Include reset engine count in i915_engine_info too (Chris).

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index c08a6d8a4e07..01d6758d33d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1403,6 +1403,23 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_reset_info(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct i915_gpu_error *error = _priv->gpu_error;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+
+   for_each_engine(engine, dev_priv, id) {
+   seq_printf(m, "%s = %u\n", engine->name,
+  i915_reset_engine_count(error, engine));
+   }
+
+   return 0;
+}
+
 static int ironlake_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -3259,6 +3276,7 @@ static int i915_display_info(struct seq_file *m, void 
*unused)
 static int i915_engine_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct i915_gpu_error *error = _priv->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
@@ -3282,6 +3300,8 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos);
+   seq_printf(m, "\tReset count: %d\n",
+  i915_reset_engine_count(error, engine));
 
rcu_read_lock();
 
@@ -4795,6 +4815,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
+   {"i915_reset_info", i915_reset_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
{"i915_emon_status", i915_emon_status, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
-- 
2.11.0

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[Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

[Michel Thierry]

This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at this point
because core implementation is lacking) and continue recovery using legacy
full gpu reset.

A helper function is also added to query the availability of engine
reset.

The error events behaviour that are used to notify user of reset are
adapted to engine reset such that it doesn't break users listening to these
events. In legacy we report an error event, a reset event before resetting
the gpu and a reset done event marking the completion of reset. The same
behaviour is adapted but reset event is only dispatched once even when
multiple engines are hung. Finally once reset is complete we send reset
done event as usual.

Note that this implementation of engine reset is for i915 directly
submitting to the ELSP, where the driver manages the hang detection,
recovery and resubmission. With GuC submission these tasks are shared
between driver and firmware; i915 will still responsible for detecting a
hang, and when it does it will have to request GuC to reset that Engine and
remind the firmware about the outstanding submissions. This will be
added in different patch.

v2: rebase, advertise engine reset availability in platform definition,
add note about GuC submission.
v3: s/*engine_reset*/*reset_engine*/. (Chris)
Handle reset as 2 level resets, by first going to engine only and fall
backing to full/chip reset as needed, i.e. reset_engine will need the
struct_mutex.
v4: Pass the engine mask to i915_reset. (Chris)
v5: Rebase, update selftests.
v6: Rebase, prepare for mutex-less reset engine.
v7: Pass reset_engine mask as a function parameter, and iterate over the
engine mask for reset_engine. (Chris)
v8: Use i915.reset >=2 in has_reset_engine; remove redundant reset
logging; add a reset-engine-in-progress flag to prevent concurrent
resets, and avoid dual purposing of reset-backoff. (Chris)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Ian Lister 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c | 13 +
 drivers/gpu/drm/i915/i915_drv.h |  8 
 drivers/gpu/drm/i915/i915_irq.c | 24 
 drivers/gpu/drm/i915/i915_pci.c |  5 -
 drivers/gpu/drm/i915/intel_uncore.c | 11 +++
 5 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d703897786e9..f49f9d9273f2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1873,6 +1873,19 @@ void i915_reset(struct drm_i915_private *dev_priv)
goto finish;
 }
 
+/**
+ * i915_reset_engine - reset GPU engine to recover from a hang
+ * @engine: engine to reset
+ *
+ * Reset a specific GPU engine. Useful if a hang is detected.
+ * Returns zero on successful reset or otherwise an error code.
+ */
+int i915_reset_engine(struct intel_engine_cs *engine)
+{
+   /* FIXME: replace me with engine reset sequence */
+   return -ENODEV;
+}
+
 static int i915_pm_suspend(struct device *kdev)
 {
struct pci_dev *pdev = to_pci_dev(kdev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2a01bc04168..6848ed75611d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -753,6 +753,7 @@ struct intel_csr {
func(has_ddi); \
func(has_decoupled_mmio); \
func(has_dp_mst); \
+   func(has_reset_engine); \
func(has_fbc); \
func(has_fpga_dbg); \
func(has_full_ppgtt); \
@@ -1546,6 +1547,10 @@ struct i915_gpu_error {
 * inspect the bit and do the reset directly, otherwise the worker
 * waits for the struct_mutex.
 *
+* #I915_RESET_ENGINE_IN_PROGRESS - Since the driver doesn't need to
+* acquire the struct_mutex to reset an engine, we need an explicit
+* flag to prevent two concurrent reset-engine attempts.
+*
 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
 * i915_gem_request_alloc(), this bit is checked and the sequence
@@ -1554,6 +1559,7 @@ struct i915_gpu_error {
unsigned long flags;
 #define I915_RESET_BACKOFF 0
 #define I915_RESET_HANDOFF 1
+#define I915_RESET_ENGINE_IN_PROGRESS  2
 #define I915_WEDGED(BITS_PER_LONG - 1)
 
/**
@@ -3038,6 +3044,8 @@ extern void i915_driver_unload(struct drm_device *dev);
 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
 

[Intel-gfx] [PATCH v8 00/20] Gen8+ engine-reset

[Michel Thierry]

These patches add the reset-engine feature from Gen8. This is also
referred to as Timeout detection and recovery (TDR). This complements to
the full gpu reset feature available in i915 but it only allows to reset a
particular engine instead of all engines thus providing a light weight
engine reset and recovery mechanism.

Thanks to recent changes merged, this implementation is now not only for
execlists, but for GuC based submission too; it is still limited from
Gen8 onwards. I have also included the changes for watchdog timeout
detection. The GuC related patches are functional, but can be seen as RFC.

Timeout detection relies on the existing hangcheck, which remains the same;
main changes are to the recovery mechanism. Once we detect a hang on a
particular engine we identify the request that caused the hang, skip the
request and adjust head pointers to allow the execution to proceed
normally. After some cleanup, submissions are restarted to process
remaining work queued to that engine.

If engine reset fails to recover engine correctly then we fallback to full
gpu reset.

We can argue about the effectiveness of reset-engine vs full reset when
more than one ring is hung, but the benefits of just resetting one engine
are reduced when the driver has to do it multiple times.

v2: ELSP queue request tracking and reset path changes to handle incomplete
requests during reset. Thanks to Chris Wilson for providing these patches.

v3: Let the waiter keep handling the full gpu reset if it already has the
lock; point out that GuC submission needs a different method to restart
workloads after the engine reset completes.

v4: Handle reset as 2 level resets, by first going to engine only and fall
backing to full/chip reset as needed, i.e. reset_engine will need the
struct_mutex.

v5: Rebased after reset flag split in 2, add GuC support, include watchdog
detection patches, addressing comments from prev RFC.

v6: Mutex-less reset engine. Updates in watchdog abi and guc whitelist &
register-restore fixes (including an old patch from Daniele).

v7: Removed leftovers from v5; review comments; ability to cancel the reset
if there's no active request.

v8: Moved patch looking for active request at the beginning of these series;
drop patch to request the engine's reset readinnes earlier since this is
done during the reset flow too; warn if hw fails to acknowledge reset
_readiness_.

Daniele Ceraolo Spurio (1):
  drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

Michel Thierry (19):
  drm/i915: Look for active requests earlier in the reset path
  drm/i915: Update i915.reset to handle engine resets
  drm/i915: Modify error handler for per engine hang recovery
  drm/i915: Add support for per engine reset recovery
  drm/i915: Add engine reset count to error state
  drm/i915: Export per-engine reset count info to debugfs
  drm/i915: Carry on with reset even if hw engine is not ready
  drm/i915: Enable Engine reset and recovery support
  drm/i915: Add engine reset count in get-reset-stats ioctl
  drm/i915/selftests: reset engine self tests
  drm/i915/guc: Provide register list to be saved/restored during engine
reset
  drm/i915/guc: Rename the function that resets the GuC
  drm/i915/guc: Add support for reset engine using GuC commands
  drm/i915: Watchdog timeout: Pass GuC shared data structure during
param load
  drm/i915: Watchdog timeout: IRQ handler for gen8+
  drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+
  drm/i915: Watchdog timeout: DRM kernel interface to set the timeout
  drm/i915: Watchdog timeout: Include threshold value in error state
  drm/i915: Watchdog timeout: Export media reset count from GuC to
debugfs

 drivers/gpu/drm/i915/i915_debugfs.c  |  43 +++
 drivers/gpu/drm/i915/i915_drv.c  |  74 +++
 drivers/gpu/drm/i915/i915_drv.h  |  90 -
 drivers/gpu/drm/i915/i915_gem.c  | 104 +--
 drivers/gpu/drm/i915/i915_gem_context.c  | 109 +++-
 drivers/gpu/drm/i915/i915_gem_context.h  |   4 +
 drivers/gpu/drm/i915/i915_gpu_error.c|  15 ++-
 drivers/gpu/drm/i915/i915_guc_submission.c   | 138 ++--
 drivers/gpu/drm/i915/i915_irq.c  |  36 +-
 drivers/gpu/drm/i915/i915_params.c   |   6 +-
 drivers/gpu/drm/i915/i915_params.h   |   2 +-
 drivers/gpu/drm/i915/i915_pci.c  |   5 +-
 drivers/gpu/drm/i915/i915_reg.h  |   6 +
 drivers/gpu/drm/i915/intel_engine_cs.c   |  65 +++---
 drivers/gpu/drm/i915/intel_guc_fwif.h|  27 +++-
 drivers/gpu/drm/i915/intel_guc_loader.c  |  11 ++
 drivers/gpu/drm/i915/intel_hangcheck.c   |  13 +-
 drivers/gpu/drm/i915/intel_lrc.c | 155 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   9 ++
 drivers/gpu/drm/i915/intel_uc.c  |   4 +-
 

[Intel-gfx] [PATCH v8 01/20] drm/i915: Look for active requests earlier in the reset path

[Michel Thierry]

And store the active request so that we only search for it once.

v2: Check for request completion inside _prepare_engine, don't use
ECANCELED, remove unnecessary null checks (Chris).

v3: Capture active requests during reset_prepare and store it the
engine hangcheck obj.

v4: Rename commit, change i915_gem_reset_request to just confirm the
active_request is still incomplete, instead of engine_stalled (Chris).

v5: With style; pass the active request to gem_reset_engine, keep single
return in reset_prepare_engine (Chris).

v6: Moved before reset-engine code appears (Chris)

Suggested-by: Chris Wilson 
Reviewed-by: Chris Wilson  (v5)
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem.c | 14 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a637cc05cc4a..8207476b0c35 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2801,7 +2801,7 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
 
/* Ensure irq handler finishes, and not run again. */
for_each_engine(engine, dev_priv, id) {
-   struct drm_i915_gem_request *request;
+   struct drm_i915_gem_request *request = NULL;
 
/* Prevent the signaler thread from updating the request
 * state (by calling dma_fence_signal) as we are processing
@@ -2833,6 +2833,8 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
if (request && request->fence.error == -EIO)
err = -EIO; /* Previous reset failed! */
}
+
+   engine->hangcheck.active_request = request;
}
 
i915_gem_revoke_fences(dev_priv);
@@ -2886,7 +2888,7 @@ static void engine_skip_context(struct 
drm_i915_gem_request *request)
 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
 {
/* Read once and return the resolution */
-   const bool guilty = engine_stalled(request->engine);
+   const bool guilty = !i915_gem_request_completed(request);
 
/* The guilty request will get skipped on a hung engine.
 *
@@ -2920,11 +2922,9 @@ static bool i915_gem_reset_request(struct 
drm_i915_gem_request *request)
return guilty;
 }
 
-static void i915_gem_reset_engine(struct intel_engine_cs *engine)
+static void i915_gem_reset_engine(struct intel_engine_cs *engine,
+ struct drm_i915_gem_request *request)
 {
-   struct drm_i915_gem_request *request;
-
-   request = i915_gem_find_active_request(engine);
if (request && i915_gem_reset_request(request)) {
DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 
0x%x\n",
 engine->name, request->global_seqno);
@@ -2950,7 +2950,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
for_each_engine(engine, dev_priv, id) {
struct i915_gem_context *ctx;
 
-   i915_gem_reset_engine(engine);
+   i915_gem_reset_engine(engine, engine->hangcheck.active_request);
ctx = fetch_and_zero(>last_retired_context);
if (ctx)
engine->context_unpin(engine, ctx);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6aa20ac8cde3..d33c93444c0d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -121,6 +121,7 @@ struct intel_engine_hangcheck {
unsigned long action_timestamp;
int deadlock;
struct intel_instdone instdone;
+   struct drm_i915_gem_request *active_request;
bool stalled;
 };
 
-- 
2.11.0

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[Intel-gfx] [PATCH v8 20/20] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs

[Michel Thierry]

From firmware v8.8, GuC provides the count of media engine resets
(watchdog timeout). This information is available in the GuC shared
context data struct, which resides in the first page of the default
(kernel) lrc context.

Since GuC handled engine resets are transparent for kernel and user,
provide a simple debugfs entry to see the number of times media reset
has happened.

v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic;
use READ_ONCE. (Chris)

Cc: Chris Wilson 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 22 ++
 drivers/gpu/drm/i915/intel_guc_fwif.h | 18 ++
 2 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 01d6758d33d7..b38e8512fb95 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1403,6 +1403,26 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static u32 i915_watchdog_reset_count(struct drm_i915_private *dev_priv)
+{
+   struct i915_gem_context *ctx;
+   struct page *page;
+   struct guc_shared_ctx_data *guc_shared_data;
+   u32 guc_media_reset_count;
+
+   if (!i915.enable_guc_submission)
+   return 0;
+
+   ctx = dev_priv->kernel_context;
+   page = i915_gem_object_get_page(ctx->engine[RCS].state->obj,
+   LRC_GUCSHR_PN);
+   guc_shared_data = kmap(page);
+   guc_media_reset_count = READ_ONCE(guc_shared_data->media_reset_count);
+   kunmap(page);
+
+   return guc_media_reset_count;
+}
+
 static int i915_reset_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1411,6 +1431,8 @@ static int i915_reset_info(struct seq_file *m, void 
*unused)
enum intel_engine_id id;
 
seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+   seq_printf(m, "GuC watchdog/media reset = %u\n",
+  i915_watchdog_reset_count(dev_priv));
 
for_each_engine(engine, dev_priv, id) {
seq_printf(m, "%s = %u\n", engine->name,
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index a2d0cba2f8b9..e45987f7aa50 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -502,6 +502,24 @@ union guc_log_control {
u32 value;
 } __packed;
 
+/* GuC Shared Context Data Struct */
+struct guc_shared_ctx_data {
+   u32 addr_of_last_preempted_data_low;
+   u32 addr_of_last_preempted_data_high;
+   u32 addr_of_last_preempted_data_high_tmp;
+   u32 padding;
+   u32 is_mapped_to_proxy;
+   u32 proxy_ctx_id;
+   u32 engine_reset_ctx_id;
+   u32 media_reset_count;
+   u32 reserved[8];
+   u32 uk_last_ctx_switch_reason;
+   u32 was_reset;
+   u32 lrca_gpu_addr;
+   u32 execlist_ctx;
+   u32 reserved1[32];
+} __packed;
+
 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
 enum intel_guc_action {
INTEL_GUC_ACTION_DEFAULT = 0x0,
-- 
2.11.0

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[Intel-gfx] [PATCH v8 19/20] drm/i915: Watchdog timeout: Include threshold value in error state

[Michel Thierry]

Save the watchdog threshold (in us) as part of the engine state.

v2: Only do it for gen8+ (and prevent a missing-case warn).

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/i915_gpu_error.c | 12 
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a757ef7dec0..677c59dd8ae1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -960,6 +960,7 @@ struct i915_gpu_state {
int ban_score;
int active;
int guilty;
+   int watchdog_threshold;
} context;
 
struct drm_i915_error_object {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index ebd5501ec134..515fedb61751 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -388,9 +388,11 @@ static void error_print_context(struct 
drm_i915_error_state_buf *m,
const char *header,
const struct drm_i915_error_context *ctx)
 {
-   err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d 
active %d\n",
+   err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d 
active %d, watchdog %dus\n",
   header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
-  ctx->ban_score, ctx->guilty, ctx->active);
+  ctx->ban_score, ctx->guilty, ctx->active,
+  INTEL_GEN(m->i915) >= 8 ?
+   watchdog_to_us(m->i915, ctx->watchdog_threshold) : 0);
 }
 
 static void error_print_engine(struct drm_i915_error_state_buf *m,
@@ -1349,7 +1351,8 @@ static void error_record_engine_execlists(struct 
intel_engine_cs *engine,
 }
 
 static void record_context(struct drm_i915_error_context *e,
-  struct i915_gem_context *ctx)
+  struct i915_gem_context *ctx,
+  u32 engine_id)
 {
if (ctx->pid) {
struct task_struct *task;
@@ -1368,6 +1371,7 @@ static void record_context(struct drm_i915_error_context 
*e,
e->ban_score = ctx->ban_score;
e->guilty = ctx->guilty_count;
e->active = ctx->active_count;
+   e->watchdog_threshold = ctx->engine[engine_id].watchdog_threshold;
 }
 
 static void request_record_user_bo(struct drm_i915_gem_request *request,
@@ -1431,7 +1435,7 @@ static void i915_gem_record_rings(struct drm_i915_private 
*dev_priv,
ee->vm = request->ctx->ppgtt ?
>ctx->ppgtt->base : >base;
 
-   record_context(>context, request->ctx);
+   record_context(>context, request->ctx, engine->id);
 
/* We need to copy these to an anonymous buffer
 * as the simplest method to avoid being overwritten
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 12/14] drm/i915: add KBL GT2/GT3 check macros

[Matthew Auld]

On 05/17, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 
With a proper commit message:

Reviewed-by: Matthew Auld 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7b9fd9d0f5b8..1d9c75caa26a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2758,6 +2758,10 @@ intel_info(const struct drm_i915_private *dev_priv)
>(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
>  #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
>(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
> +#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
> +  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
> +#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
> +  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
>  
>  #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>  
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH 06/14] drm/i915/perf: rework mux configurations queries

[Matthew Auld]

On 05/17, Lionel Landwerlin wrote:
> Gen8+ might have mux configurations per slices/subslices. Depending on
> whether slices/subslices have been fused off, only part of the
> configuration needs to be applied. This change reworks the mux
> configurations query mechanism to allow more than one set of registers
> to be programmed.
So the previous behaviour of applying only one mux config depending on
the slices/sublices was wrong? Since now we seem to concatenate the mux
configs.

> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h|   5 +-
>  drivers/gpu/drm/i915/i915_oa_hsw.c | 211 
> -
>  drivers/gpu/drm/i915/i915_perf.c   |   7 +-
>  3 files changed, 144 insertions(+), 79 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18e12e61949b..56ed5a0651e2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2353,8 +2353,9 @@ struct drm_i915_private {
>  
>   int metrics_set;
>  
> - const struct i915_oa_reg *mux_regs;
> - int mux_regs_len;
> + const struct i915_oa_reg *mux_regs[1];
> + int mux_regs_lens[1];
> + int n_mux_regs;
So this is more like n_mux_configs ?

Reviewed-by: Matthew Auld 

>   const struct i915_oa_reg *b_counter_regs;
>   int b_counter_regs_len;
>  
> diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c 
> b/drivers/gpu/drm/i915/i915_oa_hsw.c
> index 4ddf756add31..ccd6e5124992 100644
> --- a/drivers/gpu/drm/i915/i915_oa_hsw.c
> +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c
> @@ -109,12 +109,21 @@ static const struct i915_oa_reg 
> mux_config_render_basic[] = {
>   { _MMIO(0x25428), 0x00042049 },
>  };
>  
> -static const struct i915_oa_reg *
> +static int
>  get_render_basic_mux_config(struct drm_i915_private *dev_priv,
> - int *len)
> + const struct i915_oa_reg **regs,
> + int *lens)
>  {
> - *len = ARRAY_SIZE(mux_config_render_basic);
> - return mux_config_render_basic;
> + int n = 0;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
> +
> + regs[n] = mux_config_render_basic;
> + lens[n] = ARRAY_SIZE(mux_config_render_basic);
> + n++;
> +
> + return n;
>  }
>  
>  static const struct i915_oa_reg b_counter_config_compute_basic[] = {
> @@ -172,12 +181,21 @@ static const struct i915_oa_reg 
> mux_config_compute_basic[] = {
>   { _MMIO(0x25428), 0x0c03 },
>  };
>  
> -static const struct i915_oa_reg *
> +static int
>  get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
> -  int *len)
> +  const struct i915_oa_reg **regs,
> +  int *lens)
>  {
> - *len = ARRAY_SIZE(mux_config_compute_basic);
> - return mux_config_compute_basic;
> + int n = 0;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
> +
> + regs[n] = mux_config_compute_basic;
> + lens[n] = ARRAY_SIZE(mux_config_compute_basic);
> + n++;
> +
> + return n;
>  }
>  
>  static const struct i915_oa_reg b_counter_config_compute_extended[] = {
> @@ -221,12 +239,21 @@ static const struct i915_oa_reg 
> mux_config_compute_extended[] = {
>   { _MMIO(0x25428), 0x },
>  };
>  
> -static const struct i915_oa_reg *
> +static int
>  get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
> - int *len)
> + const struct i915_oa_reg **regs,
> + int *lens)
>  {
> - *len = ARRAY_SIZE(mux_config_compute_extended);
> - return mux_config_compute_extended;
> + int n = 0;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
> + BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
> +
> + regs[n] = mux_config_compute_extended;
> + lens[n] = ARRAY_SIZE(mux_config_compute_extended);
> + n++;
> +
> + return n;
>  }
>  
>  static const struct i915_oa_reg b_counter_config_memory_reads[] = {
> @@ -281,12 +308,21 @@ static const struct i915_oa_reg 
> mux_config_memory_reads[] = {
>   { _MMIO(0x25428), 0x },
>  };
>  
> -static const struct i915_oa_reg *
> +static int
>  get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
> - int *len)
> + const struct i915_oa_reg **regs,
> + int *lens)
>  {
> - *len = ARRAY_SIZE(mux_config_memory_reads);
> - return mux_config_memory_reads;
> + int n = 0;
> +
> + 

Re: [Intel-gfx] [PATCH v4 2/2] drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI

[Ville Syrjälä]

On Fri, May 19, 2017 at 04:50:17PM -0400, Robert Foss wrote:
> Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
> as a convenience.
> 
> Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
> through the atomic API, but realizing that userspace is likely to take
> shortcuts and assume that the enum values are what is sent over the
> wire.
> 
> As a result these defines are provided purely as a convenience to
> userspace applications.
> 
> Signed-off-by: Robert Foss 
> Reviewed-by: Emil Velikov 
> Reviewed-by: Sinclair Yeh 
> Acked-by: Liviu Dudau 
> ---
> Changes since v3:
>  - Switched away from past tense in comments
>  - Add define name change to previously mis-spelled DRM_REFLECT_X comment
>  - Improved the comment for the DRM_MODE_REFLECT_ comment
> 
> Changes since v2:
>  - Changed define prefix from DRM_MODE_PROP_ to DRM_MODE_
>  - Fix compilation errors
>  - Changed comment formatting
>  - Deduplicated comment lines
>  - Clarified DRM_MODE_PROP_REFLECT_ comment
> 
> Changes since v1:
>  - Moved defines from drm.h to drm_mode.h
>  - Changed define prefix from DRM_ to DRM_MODE_PROP_ 
>  - Updated uses of the defines to the new prefix
>  - Removed include from drm_rect.c
>  - Stopped using the BIT() macro 
> 
>  drivers/gpu/drm/arm/malidp_drv.h|  2 +-
>  drivers/gpu/drm/arm/malidp_planes.c | 18 -
>  drivers/gpu/drm/armada/armada_overlay.c |  2 +-
>  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 20 +-
>  drivers/gpu/drm/drm_atomic.c|  2 +-
>  drivers/gpu/drm/drm_atomic_helper.c |  2 +-
>  drivers/gpu/drm/drm_blend.c | 45 +++---
>  drivers/gpu/drm/drm_fb_helper.c |  4 +-
>  drivers/gpu/drm/drm_plane_helper.c  |  2 +-
>  drivers/gpu/drm/drm_rect.c  | 36 +-
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++
>  drivers/gpu/drm/i915/intel_atomic_plane.c   |  6 +--
>  drivers/gpu/drm/i915/intel_display.c| 50 
> -
>  drivers/gpu/drm/i915/intel_fbc.c|  2 +-
>  drivers/gpu/drm/i915/intel_fbdev.c  |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c | 20 +-
>  drivers/gpu/drm/imx/ipuv3-plane.c   |  2 +-
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 30 +++
>  drivers/gpu/drm/nouveau/nv50_display.c  |  2 +-
>  drivers/gpu/drm/omapdrm/omap_drv.c  |  4 +-
>  drivers/gpu/drm/omapdrm/omap_fb.c   | 18 -
>  drivers/gpu/drm/omapdrm/omap_plane.c| 16 
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  4 +-
>  include/drm/drm_blend.h | 21 +--
>  include/uapi/drm/drm_mode.h | 49 +++-
>  25 files changed, 202 insertions(+), 171 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arm/malidp_drv.h 
> b/drivers/gpu/drm/arm/malidp_drv.h
> index 040311ffcaec..2e2033140efc 100644
> --- a/drivers/gpu/drm/arm/malidp_drv.h
> +++ b/drivers/gpu/drm/arm/malidp_drv.h
> @@ -65,6 +65,6 @@ void malidp_de_planes_destroy(struct drm_device *drm);
>  int malidp_crtc_init(struct drm_device *drm);
>  
>  /* often used combination of rotational bits */
> -#define MALIDP_ROTATED_MASK  (DRM_ROTATE_90 | DRM_ROTATE_270)
> +#define MALIDP_ROTATED_MASK  (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)
>  
>  #endif  /* __MALIDP_DRV_H__ */
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
> b/drivers/gpu/drm/arm/malidp_planes.c
> index 814fda23cead..063a8d2b0be3 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -80,7 +80,7 @@ static void malidp_plane_reset(struct drm_plane *plane)
>   state = kzalloc(sizeof(*state), GFP_KERNEL);
>   if (state) {
>   state->base.plane = plane;
> - state->base.rotation = DRM_ROTATE_0;
> + state->base.rotation = DRM_MODE_ROTATE_0;
>   plane->state = >base;
>   }
>  }
> @@ -221,7 +221,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
>   return ret;
>  
>   /* packed RGB888 / BGR888 can't be rotated or flipped */
> - if (state->rotation != DRM_ROTATE_0 &&
> + if (state->rotation != DRM_MODE_ROTATE_0 &&
>   (fb->format->format == DRM_FORMAT_RGB888 ||
>fb->format->format == DRM_FORMAT_BGR888))
>   return -EINVAL;
> @@ -315,12 +315,12 @@ static void malidp_de_plane_update(struct drm_plane 
> *plane,
>   val &= ~LAYER_ROT_MASK;
>  
>   /* setup the rotation and axis flip bits */
> - if (plane->state->rotation & DRM_ROTATE_MASK)
> - val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) <<
> + if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
> + val |= 

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Silence compiler warning in igt_ctx_exec

[Matthew Auld]

On 22 May 2017 at 13:21, Chris Wilson  wrote:
> The compiler doesn't always spot the guard that object is allocated on
> the first pass, leading to:
>
> drivers/gpu/drm/i915/selftests/i915_gem_context.c: warning: 'obj' may be used 
> uninitialized in this function [-Wuninitialized]:  => 370:8
>
> Reported-by: Geert Uytterhoeven 
> Fixes: 791ff39ae32a ("drm/i915: Live testing for context execution")
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Tvrtko Ursulin 
> Cc: Matthew Auld 
> c:  # v4.12-rc1+
Cc:  # v4.12-rc1+

Reviewed-by: Matthew Auld 
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm: Fix deadlock retry loop in page_flip_ioctl (rev2)

[Patchwork]

== Series Details ==

Series: drm: Fix deadlock retry loop in page_flip_ioctl (rev2)
URL   : https://patchwork.freedesktop.org/series/24773/
State : warning

== Summary ==

Series 24773v2 drm: Fix deadlock retry loop in page_flip_ioctl
https://patchwork.freedesktop.org/api/1.0/series/24773/revisions/2/mbox/

Test kms_busy:
Subgroup basic-flip-default-a:
pass   -> DMESG-WARN (fi-skl-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-skl-6770hq) fdo#99739

fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:438s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:580s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:516s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:484s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:418s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:408s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:501s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:466s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7560u total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  
time:576s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:459s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:577s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:464s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:508s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:436s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:534s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:411s

5c5ce2ab8183e4bd85a603169e260cc938837e2c drm-tip: 2017y-05m-22d-13h-42m-03s UTC 
integration manifest
e8da648 drm: Fix deadlock retry loop in page_flip_ioctl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4772/
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[Intel-gfx] [PATCH] drm: Fix deadlock retry loop in page_flip_ioctl

[Daniel Vetter]

I failed to properly onion-wrap the unwind code: We acquire the vblank
reference before we start with the wait-wound locking dance, hence we
must make sure we retry before we drop the reference. Oops.

v2: The vblank_put must be after the frambuffer_put (Michel). I suck at
unwrapping code that doesn't use separate labels for each stage, but
checks each pointer first ... While re-reading everything I also
realized that we must clean up the fb refcounts, and specifically
plane->old_fb before we drop the locks, either in the final unlocking,
or in the w/w retry path. Hence the correct fix is to drop the
vblank_put to the very bottom.

Fixes: 29dc0d1de182 ("drm: Roll out acquire context for the page_flip ioctl")
Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Jani Nikula 
Cc: Sean Paul 
Cc: David Airlie 
Cc: dri-de...@lists.freedesktop.org
Reported-by: Tommi Rantala 
Cc: Tommi Rantala 
Cc: Michel Dänzer 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_plane.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index fedd4d60d9cd..5dc8c4350602 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -948,8 +948,6 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
}
 
 out:
-   if (ret && crtc->funcs->page_flip_target)
-   drm_crtc_vblank_put(crtc);
if (fb)
drm_framebuffer_put(fb);
if (crtc->primary->old_fb)
@@ -964,5 +962,8 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
drm_modeset_drop_locks();
drm_modeset_acquire_fini();
 
+   if (ret && crtc->funcs->page_flip_target)
+   drm_crtc_vblank_put(crtc);
+
return ret;
 }
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL.

[Animesh Manna]

On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:

There is no confirmation if the DC5 to DC6 is available on CNL
though. But I could see DC3 to DC5 counter increasing reliably.
So let's at least add this one.

Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d07257b..2ae79a6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2859,7 +2859,10 @@ static int i915_dmc_info(struct seq_file *m, void 
*unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
   CSR_VERSION_MINOR(csr->version));
  
-	if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {

+   if (IS_CANNONLAKE(dev_priv)) {
+   seq_printf(m, "DC3 -> DC5 count: %d\n",
+  I915_READ(SKL_CSR_DC3_DC5_COUNT));


Have not found any info regarding DC5/DC6-counter in bspec for CNL.
I assume H/W team stop exposing these counter as I can not see DC5/DC6 counter 
details for other platform other than gen9(skl/bxt).
Not sure is it ok to rely on something which is not confirmed.

Regards,
Animesh


+   } else if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
   I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",


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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/selftests: Silence compiler warning in igt_ctx_exec

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Silence compiler warning in igt_ctx_exec
URL   : https://patchwork.freedesktop.org/series/24787/
State : warning

== Summary ==

Series 24787v1 drm/i915/selftests: Silence compiler warning in igt_ctx_exec
https://patchwork.freedesktop.org/api/1.0/series/24787/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-snb-2600)
Test drv_module_reload:
Subgroup basic-reload-final:
pass   -> DMESG-WARN (fi-skl-6770hq) fdo#100248

fdo#100248 https://bugs.freedesktop.org/show_bug.cgi?id=100248

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:434s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:586s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:513s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:421s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:409s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:416s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:460s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:579s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:473s
fi-skl-6770hqtotal:278  pass:267  dwarn:1   dfail:0   fail:0   skip:10  
time:501s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:437s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-snb-2600  total:278  pass:248  dwarn:1   dfail:0   fail:0   skip:29  
time:412s
fi-kbl-7560u failed to collect. IGT log at Patchwork_4771/fi-kbl-7560u/igt.log

ec077216f6939248d037dc27dc6e0b56f7121d2b drm-tip: 2017y-05m-22d-10h-46m-27s UTC 
integration manifest
744abe7 drm/i915/selftests: Silence compiler warning in igt_ctx_exec

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4771/
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[Intel-gfx] [PATCH] drm/i915/selftests: Silence compiler warning in igt_ctx_exec

[Chris Wilson]

The compiler doesn't always spot the guard that object is allocated on
the first pass, leading to:

drivers/gpu/drm/i915/selftests/i915_gem_context.c: warning: 'obj' may be used 
uninitialized in this function [-Wuninitialized]:  => 370:8

Reported-by: Geert Uytterhoeven 
Fixes: 791ff39ae32a ("drm/i915: Live testing for context execution")
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Matthew Auld 
c:  # v4.12-rc1+
---
 drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 1afb8b06e3e1..4b38134eafd2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -320,7 +320,7 @@ static unsigned long max_dwords(struct drm_i915_gem_object 
*obj)
 static int igt_ctx_exec(void *arg)
 {
struct drm_i915_private *i915 = arg;
-   struct drm_i915_gem_object *obj;
+   struct drm_i915_gem_object *uninitialized_var(obj);
struct drm_file *file;
IGT_TIMEOUT(end_time);
LIST_HEAD(objects);
-- 
2.11.0

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[Intel-gfx] [PATCH v3] drm/i915: Use a cached mapping for the physical HWS

[Chris Wilson]

Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.

Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so far have not reoccurred with this patch. How reliable that
evidence is remains to be seen.

v2: Explicitly pass the expected physical address to the hw
v3: Also remember the wild writes we once had for HWS above 4G.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 -
 drivers/gpu/drm/i915/intel_ringbuffer.c | 29 +++--
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90787e0084f2..1a7961ef4399 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2109,7 +2109,6 @@ struct drm_i915_private {
struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
 
-   struct drm_dma_handle *status_page_dmah;
struct resource mch_res;
 
/* protects the irq masks */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c32a4ba9579f..26808f2bf748 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -340,11 +340,14 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, 
u32 mode)
 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
+   struct page *page = virt_to_page(engine->status_page.page_addr);
+   phys_addr_t phys = PFN_PHYS(page_to_pfn(page));
u32 addr;
 
-   addr = dev_priv->status_page_dmah->busaddr;
+   addr = lower_32_bits(phys);
if (INTEL_GEN(dev_priv) >= 4)
-   addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
+   addr |= (phys >> 28) & 0xf0;
+
I915_WRITE(HWS_PGA, addr);
 }
 
@@ -1000,12 +1003,10 @@ i915_emit_bb_start(struct drm_i915_gem_request *req,
 
 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
 {
-   struct drm_i915_private *dev_priv = engine->i915;
-
-   if (!dev_priv->status_page_dmah)
+   if (!engine->status_page.page_addr)
return;
 
-   drm_pci_free(_priv->drm, dev_priv->status_page_dmah);
+   __free_page(virt_to_page(engine->status_page.page_addr));
engine->status_page.page_addr = NULL;
 }
 
@@ -1091,17 +1092,17 @@ static int init_status_page(struct intel_engine_cs 
*engine)
 
 static int init_phys_status_page(struct intel_engine_cs *engine)
 {
-   struct drm_i915_private *dev_priv = engine->i915;
-
-   GEM_BUG_ON(engine->id != RCS);
+   struct page *page;
 
-   dev_priv->status_page_dmah =
-   drm_pci_alloc(_priv->drm, PAGE_SIZE, PAGE_SIZE);
-   if (!dev_priv->status_page_dmah)
+   /* Though the HWS register does support 36bit addresses, historically
+* we have had hangs and corruption reported due to wild writes if
+* the HWS is placed above 4G.
+*/
+   page = alloc_page(GFP_KERNEL | __GFP_DMA32 | __GFP_ZERO);
+   if (!page)
return -ENOMEM;
 
-   engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
-   memset(engine->status_page.page_addr, 0, PAGE_SIZE);
+   engine->status_page.page_addr = page_address(page);
 
return 0;
 }
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce buffer based cmd transport

[Patchwork]

== Series Details ==

Series: Introduce buffer based cmd transport
URL   : https://patchwork.freedesktop.org/series/24786/
State : success

== Summary ==

Series 24786v1 Introduce buffer based cmd transport
https://patchwork.freedesktop.org/api/1.0/series/24786/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:437s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:584s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:526s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:488s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:411s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:411s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:428s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:497s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:464s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:464s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:466s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:576s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:466s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:501s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:438s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:407s

ec077216f6939248d037dc27dc6e0b56f7121d2b drm-tip: 2017y-05m-22d-10h-46m-27s UTC 
integration manifest
51d991b drm/i915/guc: Introduce buffer based cmd transport
0ee5a8e drm/i915/guc: Disable send function on fini

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4769/
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[Intel-gfx] [CI v2 2/2] drm/i915/guc: Introduce buffer based cmd transport

[Michal Wajdeczko]

Buffer based command transport can replace MMIO based mechanism.
It may be used to perform host-2-guc and guc-to-host communication.

Portions of this patch are based on work by:
 Michel Thierry 
 Robert Beckett 
 Daniele Ceraolo Spurio 

v2: use gem_object_pin_map (Chris)
don't use DEBUG_RATELIMITED (Chris)
don't track action stats (Chris)
simplify next fence (Chris)
use READ_ONCE (Chris)
move blob allocation to new function (Chris)

Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Oscar Mateo 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.c   |   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/intel_guc_ct.c   | 468 ++
 drivers/gpu/drm/i915/intel_guc_ct.h   |  97 +++
 drivers/gpu/drm/i915/intel_guc_fwif.h |  44 
 drivers/gpu/drm/i915/intel_uc.c   |  25 +-
 drivers/gpu/drm/i915/intel_uc.h   |   4 +-
 8 files changed, 641 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ct.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ct.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7b05fb8..16dccf5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -58,6 +58,7 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
+ intel_guc_ct.o \
  intel_guc_log.o \
  intel_guc_loader.o \
  intel_huc.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d703897..6c78469 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -869,6 +869,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
i915_workqueues_cleanup(dev_priv);
 err_engines:
i915_engines_cleanup(dev_priv);
+   intel_uc_cleanup(dev_priv);
return ret;
 }
 
@@ -883,6 +884,7 @@ static void i915_driver_cleanup_early(struct 
drm_i915_private *dev_priv)
intel_irq_fini(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
+   intel_uc_cleanup(dev_priv);
 }
 
 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17883a8..453eea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -760,6 +760,7 @@ struct intel_csr {
func(has_gmbus_irq); \
func(has_gmch_display); \
func(has_guc); \
+   func(has_guc_ct); \
func(has_hotplug); \
func(has_l3_dpf); \
func(has_llc); \
@@ -2947,6 +2948,7 @@ intel_info(const struct drm_i915_private *dev_priv)
  * properties, so we have separate macros to test them.
  */
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
+#define HAS_GUC_CT(dev_priv)   ((dev_priv)->info.has_guc_ct)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c 
b/drivers/gpu/drm/i915/intel_guc_ct.c
new file mode 100644
index 000..869a7ad
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright © 2016-2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "i915_drv.h"
+#include "intel_guc_ct.h"
+
+enum { CTB_SEND = 0, CTB_RECV = 1 };
+
+static inline const char *guc_ct_buffer_type_to_str(u32 type)
+{
+   switch (type) {
+   case 

[Intel-gfx] [CI v2 0/2] Introduce buffer based cmd transport

[Michal Wajdeczko]

This series is same as [1] but this time without enabling GuC
submission, as Guc submission is not working due to other changes.

[1] https://patchwork.freedesktop.org/series/24715/

Michal Wajdeczko (2):
  drm/i915/guc: Disable send function on fini
  drm/i915/guc: Introduce buffer based cmd transport

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.c   |   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/intel_guc_ct.c   | 468 ++
 drivers/gpu/drm/i915/intel_guc_ct.h   |  97 +++
 drivers/gpu/drm/i915/intel_guc_fwif.h |  44 
 drivers/gpu/drm/i915/intel_uc.c   |  32 ++-
 drivers/gpu/drm/i915/intel_uc.h   |   4 +-
 8 files changed, 647 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ct.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ct.h

-- 
2.7.4

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[Intel-gfx] [CI v2 1/2] drm/i915/guc: Disable send function on fini

[Michal Wajdeczko]

In earlier patch 789a625 we were enabling send function only
after successful init. For completeness, we should make sure
that we disable it on fini.

v2: don't group steps by submission flag (Chris)

Signed-off-by: Michal Wajdeczko 
Cc: Joonas Lahtinen 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uc.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index d27b527..31dc8c3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -410,11 +410,16 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (!i915.enable_guc_loading)
return;
 
-   if (i915.enable_guc_submission) {
+   if (i915.enable_guc_submission)
i915_guc_submission_disable(dev_priv);
+
+   guc_disable_communication(_priv->guc);
+
+   if (i915.enable_guc_submission) {
gen9_disable_guc_interrupts(dev_priv);
i915_guc_submission_fini(dev_priv);
}
+
i915_ggtt_disable_guc(dev_priv);
 }
 
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: dma-buf support for GVT-g (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: dma-buf support for GVT-g (rev3)
URL   : https://patchwork.freedesktop.org/series/23686/
State : failure

== Summary ==

Series 23686v3 drm/i915/gvt: dma-buf support for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/23686/revisions/3/mbox/

Test gem_busy:
Subgroup basic-busy-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
Subgroup basic-hang-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> FAIL   (fi-ilk-650)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-byt-n2820)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bdw-gvtdvm)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700hq)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-gvtdvm)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
Test gem_exec_basic:
Subgroup gtt-blt:
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
  

Re: [Intel-gfx] [PATCH 23/24] drm/i915: Keep a recent cache of freed contexts objects for reuse

[Chris Wilson]

On Mon, May 22, 2017 at 11:51:27AM +0100, Tvrtko Ursulin wrote:
> 
> On 18/05/2017 10:46, Chris Wilson wrote:
> >Keep the recently freed context objects for reuse. This allows us to use
> >the current GGTT bindings and dma bound pages, avoiding any clflushes as
> >required. We mark the objects as purgeable under memory pressure, and
> >reap the list of freed objects as soon as the device is idle.
> 
> One additional thought - how about making the batch pool more
> generic, or more precisely extracting a layer from it to be called
> object pool, and then having batch pool and context pool on top of
> that?
> 
> There would be some details to flesh out, like do we want to
> strictly split internal from shmemfs backed objects, or can allow
> batch pool to get either, the API and similar.

That was the big difference; different object types that shouldn't be
mixed. So you going to have different lists for the the different
classes and behaviours.

On top of this, there's also the question of whether to keep old objects
around for userspace. Userspace caching is still more efficient for
userspace, but there are classes of objects that are cycled between
processes and discarded instead of being recycled in userspace. The
tricky part is making sure that the object state, after alloc from
cache, doesn't surprise the user.

> But if it could be done with not a lot of code it may be
> preferential to have one implementation of the similar basic idea.

No denying that, just not enough in common yet and still mostly
searching for the problem to be solved. (Outside of unrealistic
benchmarks and test cases.)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: remove redundant -Wall

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: remove redundant -Wall
URL   : https://patchwork.freedesktop.org/series/24779/
State : success

== Summary ==

Series 24779v1 drm/i915/gvt: remove redundant -Wall
https://patchwork.freedesktop.org/api/1.0/series/24779/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:442s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:432s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:581s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:513s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:491s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:413s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:412s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:466s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:468s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:465s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:566s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:469s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:510s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:437s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:532s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:417s

f20cc05633fee08ea2a99cf544524735057592a1 drm-tip: 2017y-05m-22d-09h-11m-14s UTC 
integration manifest
5d2077c drm/i915/gvt: remove redundant -Wall

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4767/
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Re: [Intel-gfx] [PATCH 23/24] drm/i915: Keep a recent cache of freed contexts objects for reuse

[Tvrtko Ursulin]

On 18/05/2017 10:46, Chris Wilson wrote:

Keep the recently freed context objects for reuse. This allows us to use
the current GGTT bindings and dma bound pages, avoiding any clflushes as
required. We mark the objects as purgeable under memory pressure, and
reap the list of freed objects as soon as the device is idle.


One additional thought - how about making the batch pool more generic, 
or more precisely extracting a layer from it to be called object pool, 
and then having batch pool and context pool on top of that?


There would be some details to flesh out, like do we want to strictly 
split internal from shmemfs backed objects, or can allow batch pool to 
get either, the API and similar.


But if it could be done with not a lot of code it may be preferential to 
have one implementation of the similar basic idea.


Regards,

Tvrtko


Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 +
 drivers/gpu/drm/i915/i915_gem.c  |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c  | 59 ++--
 drivers/gpu/drm/i915/i915_gem_context.h  |  5 ++
 drivers/gpu/drm/i915/intel_lrc.c |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  2 +-
 drivers/gpu/drm/i915/selftests/mock_context.c|  1 +
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  1 +
 8 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1d55bbde68df..1fa1e7d48f02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2316,6 +2316,8 @@ struct drm_i915_private {
struct llist_head free_list;
struct work_struct free_work;

+   struct list_head freed_objects;
+
/* The hw wants to have a stable context identifier for the
 * lifetime of the context (for OA, PASID, faults, etc).
 * This is limited in execlists to 21 bits.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c044b5dbdb66..f482c320d810 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3212,6 +3212,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
DRM_ERROR("Timeout waiting for engines to idle\n");

intel_engines_mark_idle(dev_priv);
+   i915_gem_contexts_mark_idle(dev_priv);
i915_gem_timelines_mark_idle(dev_priv);

GEM_BUG_ON(!dev_priv->gt.awake);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 198b0064a3d3..1e51fd36f355 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -96,6 +96,48 @@
 /* Initial size (as log2) to preallocate the handle->object hashtable */
 #define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */

+struct drm_i915_gem_object *
+i915_gem_context_create_object(struct drm_i915_private *i915,
+  unsigned long size)
+{
+   struct drm_i915_gem_object *obj, *on;
+
+   lockdep_assert_held(>drm.struct_mutex);
+
+   list_for_each_entry_safe(obj, on,
+>contexts.freed_objects,
+batch_pool_link) {
+   if (obj->mm.madv != I915_MADV_DONTNEED) {
+   /* Purge the heretic! */
+   list_del(>batch_pool_link);
+   i915_gem_object_put(obj);
+   continue;
+   }
+
+   if (obj->base.size == size) {
+   list_del(>batch_pool_link);
+   obj->mm.madv = I915_MADV_WILLNEED;
+   return obj;
+   }
+   }
+
+   return i915_gem_object_create(i915, size);
+}
+
+void i915_gem_contexts_mark_idle(struct drm_i915_private *i915)
+{
+   struct drm_i915_gem_object *obj, *on;
+
+   lockdep_assert_held(>drm.struct_mutex);
+
+   list_for_each_entry_safe(obj, on,
+>contexts.freed_objects,
+batch_pool_link) {
+   list_del(>batch_pool_link);
+   i915_gem_object_put(obj);
+   }
+}
+
 static void resize_vma_ht(struct work_struct *work)
 {
struct i915_gem_context_vma_lut *lut =
@@ -160,9 +202,10 @@ static void vma_lut_free(struct i915_gem_context *ctx)

 static void i915_gem_context_free(struct i915_gem_context *ctx)
 {
+   struct drm_i915_private *i915 = ctx->i915;
int i;

-   lockdep_assert_held(>i915->drm.struct_mutex);
+   lockdep_assert_held(>drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));

vma_lut_free(ctx);
@@ -178,7 +221,11 @@ static void i915_gem_context_free(struct i915_gem_context 
*ctx)
if (ce->ring)
intel_ring_free(ce->ring);

-   

Re: [Intel-gfx] [PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load.

[Animesh Manna]

On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:

Since we have HAS_CSR tied to the platform definition
let's use this instead of checking per platform.

One less thing to worry when adding support to new platforms.

Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/intel_csr.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 496a965..eecee65 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -241,7 +241,7 @@ void intel_csr_load_program(struct drm_i915_private 
*dev_priv)
u32 *payload = dev_priv->csr.dmc_payload;
uint32_t i, fw_size;
  
-	if (!IS_GEN9(dev_priv)) {

+   if (!HAS_CSR(dev_priv)) {
DRM_ERROR("No CSR support available for this platform\n");
return;
}


Changes looks good to me.

Reviewed-by: Animesh Manna

Regards,

Animesh


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Re: [Intel-gfx] [PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL

[Animesh Manna]

On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:

From: Anusha Srivatsa 

This patch loads the DMC on CNL.The firmware version
is 1.04.

v2: (Rodrigo) Remove MODULE_FIRMWARE.

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_pci.c  |  1 +
  drivers/gpu/drm/i915/intel_csr.c | 11 +--
  2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c84ef7c..bace848 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -437,6 +437,7 @@
.platform = INTEL_CANNONLAKE,
.gen = 10,
.ddb_size = 1024,
+   .has_csr = 1,
  };
  
  /*

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1575bde..496a965 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -37,6 +37,9 @@
  #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
  #define GLK_CSR_VERSION_REQUIRED  CSR_VERSION(1, 4)
  
+#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"

+#define CNL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 4)
+
  #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
  MODULE_FIRMWARE(I915_CSR_KBL);
  #define KBL_CSR_VERSION_REQUIRED  CSR_VERSION(1, 1)
@@ -289,7 +292,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private 
*dev_priv,
  
  	csr->version = css_header->version;
  
-	if (IS_GEMINILAKE(dev_priv)) {

+   if (IS_CANNONLAKE(dev_priv)) {
+   required_version = CNL_CSR_VERSION_REQUIRED;
+   } else if (IS_GEMINILAKE(dev_priv)) {
required_version = GLK_CSR_VERSION_REQUIRED;
} else if (IS_KABYLAKE(dev_priv)) {
required_version = KBL_CSR_VERSION_REQUIRED;
@@ -438,7 +443,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (!HAS_CSR(dev_priv))
return;
  
-	if (IS_GEMINILAKE(dev_priv))

+   if (IS_CANNONLAKE(dev_priv))
+   csr->fw_path = I915_CSR_CNL;
+   else if (IS_GEMINILAKE(dev_priv))
csr->fw_path = I915_CSR_GLK;
else if (IS_KABYLAKE(dev_priv))
csr->fw_path = I915_CSR_KBL;


Changes looks good to me.

Reviewed-by: Animesh Manna 

Regards,

Animesh


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: mark wait_for_engine() __maybe_unused

[Patchwork]

== Series Details ==

Series: drm/i915: mark wait_for_engine() __maybe_unused
URL   : https://patchwork.freedesktop.org/series/24778/
State : success

== Summary ==

Series 24778v1 drm/i915: mark wait_for_engine() __maybe_unused
https://patchwork.freedesktop.org/api/1.0/series/24778/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:436s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:590s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:512s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:489s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:425s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:409s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:418s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:494s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:469s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:462s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:576s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:467s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:495s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:442s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-snb-2600  total:278  pass:247  dwarn:0   dfail:0   fail:2   skip:29  
time:409s

f20cc05633fee08ea2a99cf544524735057592a1 drm-tip: 2017y-05m-22d-09h-11m-14s UTC 
integration manifest
e19d196 drm/i915: mark wait_for_engine() __maybe_unused

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4766/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen3: Improve reset reliability

[Patchwork]

== Series Details ==

Series: drm/i915/gen3: Improve reset reliability
URL   : https://patchwork.freedesktop.org/series/24777/
State : success

== Summary ==

Series 24777v1 drm/i915/gen3: Improve reset reliability
https://patchwork.freedesktop.org/api/1.0/series/24777/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:436s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:585s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:509s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:484s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:419s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:409s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:493s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:466s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:464s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:461s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:573s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:468s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:506s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:437s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:531s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time:408s

f20cc05633fee08ea2a99cf544524735057592a1 drm-tip: 2017y-05m-22d-09h-11m-14s UTC 
integration manifest
e3fabc8 drm/i915/gen3: Improve reset reliability

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4765/
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Re: [Intel-gfx] [PATCH v5] drm/i915/gvt: return the correct usable aperture size under gvt environment

[Zhenyu Wang]

On 2017.05.19 23:35:03 +0800, Weinan Li wrote:
> I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
> In gvt environment, each vm only use the ballooned part of aperture, so we
> should return the correct available aperture size exclude the reserved part
> by balloon.

pls fix up patch title as this is for "drm/i915: ..." change although has
gvt impact, and I think should be applied through i915 tree. Thanks.

> 
> v2: add 'reserved' in struct i915_address_space to record the reserved size
> in ggtt (Chris)
> 
> v3: remain aper_size as total, adjust aper_available_size exclude reserved
> and pinned. UMD driver need to adjust the max allocation size according to
> the available aperture size but not total size. KMD return the correct
> usable aperture size any time (Chris, Joonas)
> 
> v4: decrease reserved in deballoon (Joonas)
> 
> v5: add onion teardown in balloon, add vgt_deballoon_space (Joonas)
> 
> Suggested-by: Chris Wilson 
> Suggested-by: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Signed-off-by: Weinan Li 
> ---
>  drivers/gpu/drm/i915/i915_gem.c |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
>  drivers/gpu/drm/i915/i915_vgpu.c| 44 
> ++---
>  3 files changed, 34 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 02adf82..fd2a87d 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -156,8 +156,8 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
>   mutex_unlock(>struct_mutex);
>  
>   args->aper_size = ggtt->base.total;
> - args->aper_available_size = args->aper_size - pinned;
> -
> + args->aper_available_size = args->aper_size -
> + ggtt->base.reserved - pinned;
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index fb15684..da9aa9f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -255,6 +255,7 @@ struct i915_address_space {
>   struct drm_i915_file_private *file;
>   struct list_head global_link;
>   u64 total;  /* size addr space maps (ex. 2GB for ggtt) */
> + u64 reserved;   /* size addr space reserved */
>  
>   bool closed;
>  
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c 
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index 4ab8a97..647ccad 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -92,6 +92,17 @@ struct _balloon_info_ {
>  
>  static struct _balloon_info_ bl_info;
>  
> +static void vgt_deballoon_space(struct i915_ggtt *ggtt,
> +  struct drm_mm_node *node)
> +{
> + DRM_INFO("deballoon space: range [ 0x%llx - 0x%llx ] %llu KiB.\n",
> +  node->start, node->start + node->size, node->size / 1024);
> +
> + ggtt->base.reserved -= node->size;
> + drm_mm_remove_node(node);
> + memset(node, 0, sizeof(*node));
> +}
> +
>  /**
>   * intel_vgt_deballoon - deballoon reserved graphics address trunks
>   * @dev_priv: i915 device private data
> @@ -108,18 +119,15 @@ void intel_vgt_deballoon(struct drm_i915_private 
> *dev_priv)
>  
>   DRM_DEBUG("VGT deballoon.\n");
>  
> - for (i = 0; i < 4; i++) {
> - if (bl_info.space[i].allocated)
> - drm_mm_remove_node(_info.space[i]);
> - }
> -
> - memset(_info, 0, sizeof(bl_info));
> + for (i = 0; i < 4; i++)
> + vgt_deballoon_space(_priv->ggtt, _info.space[i]);
>  }
>  
>  static int vgt_balloon_space(struct i915_ggtt *ggtt,
>struct drm_mm_node *node,
>unsigned long start, unsigned long end)
>  {
> + int ret;
>   unsigned long size = end - start;
>  
>   if (start >= end)
> @@ -127,9 +135,14 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
>  
>   DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
>start, end, size / 1024);
> - return i915_gem_gtt_reserve(>base, node,
> + ret = i915_gem_gtt_reserve(>base, node,
>   size, start, I915_COLOR_UNEVICTABLE,
>   0);
> + if (!ret)
> + ggtt->base.reserved += size;
> + else
> + memset(node, 0, sizeof(*node));
> + return ret;
>  }
>  
>  /**
> @@ -215,14 +228,14 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
>   ggtt->mappable_end, unmappable_base);
>  
>   if (ret)
> - goto err;
> + goto err_out;
>   }
>  
>   if (unmappable_end < ggtt_end) {
>   ret = vgt_balloon_space(ggtt, _info.space[3],
>  

Re: [Intel-gfx] [PATCH igt] intel-ci: Add gem_exec_reloc/basic-range to BAT

[Chris Wilson]

On Mon, May 15, 2017 at 04:03:50PM +0200, Daniel Vetter wrote:
> What would probably help the CI folks is a gem testcase list that includes
> all the important stuff (so much more than BAT), but also completes in a
> reasonable amount of time (2h as a goal might be good). Atm not even
> excluding gem_concurrent_* (which really is a shame, since it has lots of
> correctness tests among all the combinatorial stress) doesn't get us
> there, with Mexico reporting it takes over 10h to just run that.

To reiterate myself, such a constrained test suite can and should be
generated automatically.
-Chris

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Re: [Intel-gfx] [PATCH igt] intel-ci: Add gem_exec_reloc/basic-range to BAT

[Chris Wilson]

On Mon, May 15, 2017 at 04:03:50PM +0200, Daniel Vetter wrote:
> On Thu, May 11, 2017 at 12:13:44AM +0100, Chris Wilson wrote:
> > We have no coverage of sign-extended relocations in BAT, so provide
> > some.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Petri Latvala 
> 
> There's a metric ton of simple abi checks we should add to pre-merge
> testing, adding them all to BAT imo doesn't work. And the reloc test here
> doesn't feel especially special that we need to have it in BAT.

No, this exercises something completely missed before and both together take
approximately 1ms.
-Chris

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[Intel-gfx] [PATCH v3 5/5] drm/i915/gvt: Adding interface so user space can get the dma-buf

[Xiaoguang Chen]

User space will try to create a management fd for the dma-buf operation.
Using this management fd user can query the plane information and create
a dma-buf fd if necessary.
GVT-g will handle the life cycle of the management fd and will align the
life cycle of the fd with the vfio device.
User space should handle the life cycle of the created dma-buf fd close
the dma-buf fd timely when finishing use.

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/dmabuf.c | 23 ++-
 drivers/gpu/drm/i915/gvt/dmabuf.h | 22 --
 drivers/gpu/drm/i915/gvt/gvt.c|  2 +
 drivers/gpu/drm/i915/gvt/gvt.h|  3 ++
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 87 +++
 include/uapi/linux/vfio.h | 36 
 6 files changed, 140 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index c9f283c..c74762f 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -29,6 +29,7 @@
 
 #include 
 #include 
+#include 
 
 #include "i915_drv.h"
 #include "gvt.h"
@@ -45,9 +46,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
int i, ret;
gen8_pte_t __iomem *gtt_entries;
unsigned int fb_gma = 0, fb_size = 0;
-   struct intel_vgpu_plane_info *plane_info;
+   struct plane_info *plane_info;
 
-   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   plane_info = (struct plane_info *)obj->gvt_plane_info;
if (WARN_ON(!plane_info))
return ERR_PTR(-EINVAL);
 
@@ -81,9 +82,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
 static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
 {
-   struct intel_vgpu_plane_info *plane_info;
+   struct plane_info *plane_info;
 
-   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   plane_info = (struct plane_info *)obj->gvt_plane_info;
if (WARN_ON(!plane_info))
return;
 
@@ -98,7 +99,7 @@ static const struct drm_i915_gem_object_ops 
intel_vgpu_gem_ops = {
 };
 
 static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device 
*dev,
-   struct intel_vgpu_plane_info *info)
+   struct plane_info *info)
 {
struct drm_i915_private *pri = dev->dev_private;
struct drm_i915_gem_object *obj;
@@ -141,14 +142,14 @@ static struct drm_i915_gem_object 
*intel_vgpu_create_gem(struct drm_device *dev,
return obj;
 }
 
-static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
+static struct plane_info *intel_vgpu_get_plane_info(
struct drm_device *dev,
struct intel_vgpu *vgpu, int plane_id)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_vgpu_primary_plane_format *p;
struct intel_vgpu_cursor_plane_format *c;
-   struct intel_vgpu_plane_info *info;
+   struct plane_info *info;
 
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info)
@@ -225,8 +226,8 @@ static struct intel_vgpu_plane_info 
*intel_vgpu_get_plane_info(
 int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args)
 {
struct drm_device *dev = >gvt->dev_priv->drm;
-   struct intel_vgpu_dmabuf *gvt_dmabuf = args;
-   struct intel_vgpu_plane_info *info;
+   struct dmabuf_info *gvt_dmabuf = args;
+   struct plane_info *info;
 
info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
if (info == NULL)
@@ -242,8 +243,8 @@ int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void 
*args)
struct dma_buf *dmabuf;
struct drm_i915_gem_object *obj;
struct drm_device *dev = >gvt->dev_priv->drm;
-   struct intel_vgpu_dmabuf *gvt_dmabuf = args;
-   struct intel_vgpu_plane_info *info;
+   struct dmabuf_info *gvt_dmabuf = args;
+   struct plane_info *info;
int ret;
 
info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h 
b/drivers/gpu/drm/i915/gvt/dmabuf.h
index c7ce642..0ddea78 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.h
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
@@ -26,28 +26,6 @@
 #ifndef _GVT_DMABUF_H_
 #define _GVT_DMABUF_H_
 
-struct intel_vgpu_plane_info {
-   uint32_t drm_format;
-   uint32_t width;
-   uint32_t height;
-   uint32_t stride;
-   uint32_t start;
-   uint32_t x_pos;
-   uint32_t y_pos;
-   uint32_t size;
-   uint64_t drm_format_mod;
-};
-
-#define INTEL_VGPU_QUERY_DMABUF0
-#define INTEL_VGPU_GENERATE_DMABUF 1
-
-struct intel_vgpu_dmabuf {
-   uint32_t plane_id;
-   /* out */
-   uint32_t fd;
-   struct intel_vgpu_plane_info plane_info;
-};
-
 int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args);
 int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
 

[Intel-gfx] [PATCH v3 2/5] drm/i915/gvt: OpRegion support for GVT-g

[Xiaoguang Chen]

OpRegion is needed to support display related operation for
intel vgpu.

A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.

Signed-off-by: Bing Niu 
Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c| 97 +
 drivers/gpu/drm/i915/gvt/opregion.c |  8 ++-
 2 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3c6a02b..389f072 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,6 +53,8 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
 struct vfio_region;
 struct intel_vgpu_regops {
size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
@@ -436,6 +438,92 @@ static void kvmgt_protect_table_del(struct 
kvmgt_guest_info *info,
}
 }
 
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite)
+{
+   unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+   VFIO_PCI_NUM_REGIONS;
+   void *base = vgpu->vdev.region[i].data;
+   loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+   if (pos >= vgpu->vdev.region[i].size || iswrite) {
+   gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+   return -EINVAL;
+   }
+   count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+   memcpy(buf, base + pos, count);
+
+   return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+   struct vfio_region *region)
+{
+   memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+   .rw = intel_vgpu_reg_rw_opregion,
+   .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+   unsigned int type, unsigned int subtype,
+   const struct intel_vgpu_regops *ops,
+   size_t size, u32 flags, void *data)
+{
+   struct vfio_region *region;
+
+   region = krealloc(vgpu->vdev.region,
+   (vgpu->vdev.num_regions + 1) * sizeof(*region),
+   GFP_KERNEL);
+   if (!region)
+   return -ENOMEM;
+
+   vgpu->vdev.region = region;
+   vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+   vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+   vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+   vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+   vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+   vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+   vgpu->vdev.num_regions++;
+
+   return 0;
+}
+
+static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
+{
+   unsigned int addr;
+   void *base;
+   int ret;
+
+   addr = vgpu->gvt->opregion.opregion_pa;
+   if (!addr || !(~addr))
+   return -ENODEV;
+
+   base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+   if (!base)
+   return -ENOMEM;
+
+   if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+   memunmap(base);
+   return -EINVAL;
+   }
+
+   ret = intel_vgpu_register_reg(vgpu,
+   PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
+   VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+   _vgpu_regops_opregion, OPREGION_SIZE,
+   VFIO_REGION_INFO_FLAG_READ, base);
+   if (ret) {
+   memunmap(base);
+   return ret;
+   }
+
+   return ret;
+}
+
 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 {
struct intel_vgpu *vgpu = NULL;
@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj, struct 
mdev_device *mdev)
vgpu->vdev.mdev = mdev;
mdev_set_drvdata(mdev, vgpu);
 
+   ret = intel_vgpu_reg_init_opregion(vgpu);
+   if (ret) {
+   gvt_vgpu_err("create OpRegion failed\n");
+   goto out;
+   }
+
+   gvt_dbg_core("create OpRegion succeeded for mdev:%s\n",
+   dev_name(mdev_dev(mdev)));
+
gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
 dev_name(mdev_dev(mdev)));
ret = 0;
diff --git a/drivers/gpu/drm/i915/gvt/opregion.c 
b/drivers/gpu/drm/i915/gvt/opregion.c
index 3117991..5c7496d 100644
--- a/drivers/gpu/drm/i915/gvt/opregion.c
+++ b/drivers/gpu/drm/i915/gvt/opregion.c
@@ -114,6 +114,7 @@ void 

[Intel-gfx] [PATCH v3 4/5] drm/i915/gvt: Dmabuf support for GVT-g

[Xiaoguang Chen]

dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.

Currently we provide query and create new dmabuf operations.

Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode, width, height etc.
When refresh the screen first query the currnet vgpu's frambuffer and
compare with the cached ones(address, size, tiling, width, height etc)
if found one then reuse the found dmabuf to gain performance improvment.

If there is no dmabuf created yet or not found in the cached dmabufs then
need to create a new dmabuf. To create a dmabuf first a gem object will
be created and the backing storage of this gem object is the vgpu's
framebuffer(primary/cursor). Then associate this gem object to a dmabuf
and export this dmabuf. A file descriptor will be generated for this
dmabuf and this file descriptor can be sent to user space to do display.

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/Makefile  |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 275 +
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  54 +++
 drivers/gpu/drm/i915/gvt/gvt.h |   3 +
 drivers/gpu/drm/i915/i915_gem.c|   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   3 +
 6 files changed, 344 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index 192ca26..e480f7d 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-   fb_decoder.o
+   fb_decoder.o dmabuf.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c 
b/drivers/gpu/drm/i915/gvt/dmabuf.c
new file mode 100644
index 000..c9f283c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Zhiyuan Lv 
+ *
+ * Contributors:
+ *Xiaoguang Chen 
+ */
+
+#include 
+#include 
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) \
+   ((dma_addr_t)(u64)pte) >> 12) & 0x7ffULL) << 12))
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+   struct drm_i915_gem_object *obj)
+{
+   struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+   struct sg_table *st;
+   struct scatterlist *sg;
+   int i, ret;
+   gen8_pte_t __iomem *gtt_entries;
+   unsigned int fb_gma = 0, fb_size = 0;
+   struct intel_vgpu_plane_info *plane_info;
+
+   plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+   if (WARN_ON(!plane_info))
+   return ERR_PTR(-EINVAL);
+
+   fb_gma = plane_info->start;
+   fb_size = plane_info->size;
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st) {
+   ret = -ENOMEM;
+   return ERR_PTR(ret);
+   }
+
+   ret = sg_alloc_table(st, fb_size, GFP_KERNEL);
+   if (ret) {
+   kfree(st);
+   return ERR_PTR(ret);
+   }
+   gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+   (fb_gma >> PAGE_SHIFT);
+   for_each_sg(st->sgl, sg, fb_size, i) {
+   sg->offset = 0;
+   sg->length = 

[Intel-gfx] [PATCH v3 0/5] drm/i915/gvt: Dma-buf support for GVT-g

[Xiaoguang Chen]

v2->v3:
1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save
the decoded plane information to avoid look up while need the plane info.
2) declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
to represent the gem obj for gvt's dma-buf. The tiling mode, caching mode
and domains can not be changed for this kind of gem object.
3) change dma-buf related information to be more generic. So other vendor
can use the same interface.

v1->v2:
1) create a management fd for dma-buf operations.
2) alloc gem object's backing storage in gem obj's get_pages() callback.

This patch set adds the dma-buf support for intel GVT-g.
dma-buf is a uniform mechanism to share DMA buffers across different
devices and sub-systems.
dma-buf for intel GVT-g is mainly used to share the vgpu's framebuffer
to other users or sub-systems so they can use the dma-buf to show the
desktop of a vm which uses intel vgpu.

The main idea is we create a gem object and set vgpu's framebuffer as
the backing storage of this gem object. And associate this gem obj
to a dma-buf object then export this dma-buf at the meantime
generate a file descriptor for this dma-buf. Finally deliver this file
descriptor to user space. And user can use this dma-buf fd to do render
or other operations.
User need to create a fd(for intel GVT-g dma-buf support it is a:dma-buf
management fd) then user can use this fd to query the plane information
or create a dma-buf. The life cycle of this fd is managed by GVT-g user
do not need to care about that.

We have an example program on how to use the dma-buf. You can download
the program to have a try. Good luck :)
git repo: https://github.com/01org/igvtg-qemu branch:kvmgt_dmabuf_example

Xiaoguang Chen (5):
  drm/i915/gvt: Extend the GVT-g architecture to support vfio device
region
  drm/i915/gvt: OpRegion support for GVT-g
  drm/i915/gvt: Frame buffer decoder support for GVT-g
  drm/i915/gvt: Dmabuf support for GVT-g
  drm/i915/gvt: Adding interface so user space can get the dma-buf

 drivers/gpu/drm/i915/gvt/Makefile  |   3 +-
 drivers/gpu/drm/i915/gvt/display.c |   2 +-
 drivers/gpu/drm/i915/gvt/display.h |   2 +
 drivers/gpu/drm/i915/gvt/dmabuf.c  | 276 +++
 drivers/gpu/drm/i915/gvt/dmabuf.h  |  32 +++
 drivers/gpu/drm/i915/gvt/fb_decoder.c  | 487 +
 drivers/gpu/drm/i915/gvt/fb_decoder.h  | 170 
 drivers/gpu/drm/i915/gvt/gvt.c |   2 +
 drivers/gpu/drm/i915/gvt/gvt.h |   7 +
 drivers/gpu/drm/i915/gvt/kvmgt.c   | 205 +-
 drivers/gpu/drm/i915/gvt/opregion.c|   8 +-
 drivers/gpu/drm/i915/i915_gem.c|   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   3 +
 include/uapi/linux/vfio.h  |  36 +++
 14 files changed, 1235 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

-- 
2.7.4

___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH v3 3/5] drm/i915/gvt: Frame buffer decoder support for GVT-g

[Xiaoguang Chen]

decode frambuffer attributes of primary, cursor and sprite plane

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/Makefile |   3 +-
 drivers/gpu/drm/i915/gvt/display.c|   2 +-
 drivers/gpu/drm/i915/gvt/display.h|   2 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 487 ++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 170 
 drivers/gpu/drm/i915/gvt/gvt.h|   1 +
 6 files changed, 663 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
index b123c20..192ca26 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,8 @@
 GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+   execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+   fb_decoder.o
 
 ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y += $(addprefix $(GVT_DIR)/, 
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index e0261fc..f5f63c5 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
return 1;
 }
 
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 {
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 
diff --git a/drivers/gpu/drm/i915/gvt/display.h 
b/drivers/gpu/drm/i915/gvt/display.h
index d73de22..b46b868 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 
resolution);
 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
 
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c 
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
new file mode 100644
index 000..954f047
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Kevin Tian 
+ *
+ * Contributors:
+ *Bing Niu 
+ *Xu Han 
+ *Ping Gao 
+ *Xiaoguang Chen 
+ *Yang Liu 
+ *
+ */
+
+#include 
+#include "i915_drv.h"
+#include "gvt.h"
+
+/* The below definitions are required by guest. */
+// [63:0] x:R:G:B 16:16:16:16 little endian
+#define DRM_FORMAT_XRGB161616_GVT  fourcc_code('X', 'R', '4', '8')
+// [63:0] x:B:G:R 16:16:16:16 little endian
+#define DRM_FORMAT_XBGR161616_GVT  fourcc_code('X', 'B', '4', '8')
+
+#define FORMAT_NUM 16
+struct pixel_format {
+   int drm_format; /* Pixel format in DRM definition */
+   int bpp;/* Bits per pixel, 0 indicates invalid */
+   char *desc; /* The description */
+};
+
+/* non-supported format has bpp default to 0 */
+static struct pixel_format primary_pixel_formats[FORMAT_NUM] = {
+   [0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+   [0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+   [0x6] = {DRM_FORMAT_XRGB, 32,
+   "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+   [0x8] = {DRM_FORMAT_XBGR2101010, 32,
+   "32-bit RGBX (2:10:10:10 

[Intel-gfx] [PATCH v3 1/5] drm/i915/gvt: Extend the GVT-g architecture to support vfio device region

[Xiaoguang Chen]

Signed-off-by: Xiaoguang Chen 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,11 +53,21 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+struct vfio_region;
+struct intel_vgpu_regops {
+   size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
+   size_t count, loff_t *ppos, bool iswrite);
+   void (*release)(struct intel_vgpu *vgpu,
+   struct vfio_region *region);
+};
+
 struct vfio_region {
u32 type;
u32 subtype;
size_t  size;
u32 flags;
+   const struct intel_vgpu_regops  *ops;
+   void*data;
 };
 
 struct kvmgt_pgfn {
@@ -642,7 +652,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char 
*buf,
int ret = -EINVAL;
 
 
-   if (index >= VFIO_PCI_NUM_REGIONS) {
+   if (index >= VFIO_PCI_NUM_REGIONS + vgpu->vdev.num_regions) {
gvt_vgpu_err("invalid index: %u\n", index);
return -EINVAL;
}
@@ -676,8 +686,11 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, 
char *buf,
case VFIO_PCI_BAR5_REGION_INDEX:
case VFIO_PCI_VGA_REGION_INDEX:
case VFIO_PCI_ROM_REGION_INDEX:
+   break;
default:
-   gvt_vgpu_err("unsupported region: %u\n", index);
+   index -= VFIO_PCI_NUM_REGIONS;
+   return vgpu->vdev.region[index].ops->rw(vgpu, buf, count,
+   ppos, is_write);
}
 
return ret == 0 ? count : ret;
@@ -940,7 +953,8 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, 
unsigned int cmd,
 
info.flags = VFIO_DEVICE_FLAGS_PCI;
info.flags |= VFIO_DEVICE_FLAGS_RESET;
-   info.num_regions = VFIO_PCI_NUM_REGIONS;
+   info.num_regions = VFIO_PCI_NUM_REGIONS +
+   vgpu->vdev.num_regions;
info.num_irqs = VFIO_PCI_NUM_IRQS;
 
return copy_to_user((void __user *)arg, , minsz) ?
@@ -1061,6 +1075,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, 
unsigned int cmd,
}
 
if (caps.size) {
+   info.flags |= VFIO_REGION_INFO_FLAG_CAPS;
if (info.argsz < sizeof(info) + caps.size) {
info.argsz = sizeof(info) + caps.size;
info.cap_offset = 0;
-- 
2.7.4

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Re: [Intel-gfx] [PATCH v5] dma-buf/sync-file: Defer creation of sync_file->name

[Chris Wilson]

On Tue, May 16, 2017 at 12:10:42PM +0100, Chris Wilson wrote:
> Constructing the name takes the majority of the time for allocating a
> sync_file to wrap a fence, and the name is very rarely used (only via
> the sync_file status user interface). To reduce the impact on the common
> path (that of creating sync_file to pass around), defer the construction
> of the name until it is first used.
> 
> v2: Update kerneldoc (kbuild test robot)
> v3: sync_debug.c was peeking at the name
> v4: Comment upon the potential race between two users of
> sync_file_get_name() and claim that such a race is below the level of
> notice. However, to prevent any future nuisance, use a global spinlock
> to serialize the assignment of the name.
> v5: Completely avoid the read/write race by only storing the name passed
> in from the user inside sync_file->user_name and passing in a buffer to
> dynamically construct the name otherwise.
> 
> Signed-off-by: Chris Wilson 
> Cc: Sumit Semwal 
> Cc: Gustavo Padovan 
> Cc: Daniel Vetter 
> Cc: David Herrmann 

Any thoughts on this one? It should completely avoid the race, with
the presumption that unless the user sets a name when merging the best
response is to show the fence name.

It may be interesting to actually show both; the encoded
sync_file->fence name and the user's identifier.
-Chris

> ---
>  drivers/dma-buf/sync_debug.c |  4 +++-
>  drivers/dma-buf/sync_file.c  | 39 ---
>  include/linux/sync_file.h|  5 +++--
>  3 files changed, 38 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c
> index 4b1731ee7458..59a3b2f8ee91 100644
> --- a/drivers/dma-buf/sync_debug.c
> +++ b/drivers/dma-buf/sync_debug.c
> @@ -132,9 +132,11 @@ static void sync_print_obj(struct seq_file *s, struct 
> sync_timeline *obj)
>  static void sync_print_sync_file(struct seq_file *s,
> struct sync_file *sync_file)
>  {
> + char buf[128];
>   int i;
>  
> - seq_printf(s, "[%p] %s: %s\n", sync_file, sync_file->name,
> + seq_printf(s, "[%p] %s: %s\n", sync_file,
> +sync_file_get_name(sync_file, buf, sizeof(buf)),
>  sync_status_str(dma_fence_get_status(sync_file->fence)));
>  
>   if (dma_fence_is_array(sync_file->fence)) {
> diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
> index c9eb4997cfcc..d7e219d2669d 100644
> --- a/drivers/dma-buf/sync_file.c
> +++ b/drivers/dma-buf/sync_file.c
> @@ -80,11 +80,6 @@ struct sync_file *sync_file_create(struct dma_fence *fence)
>  
>   sync_file->fence = dma_fence_get(fence);
>  
> - snprintf(sync_file->name, sizeof(sync_file->name), "%s-%s%llu-%d",
> -  fence->ops->get_driver_name(fence),
> -  fence->ops->get_timeline_name(fence), fence->context,
> -  fence->seqno);
> -
>   return sync_file;
>  }
>  EXPORT_SYMBOL(sync_file_create);
> @@ -129,6 +124,36 @@ struct dma_fence *sync_file_get_fence(int fd)
>  }
>  EXPORT_SYMBOL(sync_file_get_fence);
>  
> +/**
> + * sync_file_get_name - get the name of the sync_file
> + * @sync_file:   sync_file to get the fence from
> + * @buf: destination buffer to copy sync_file name into
> + * @len: available size of destination buffer.
> + *
> + * Each sync_file may have a name assigned either by the user (when merging
> + * sync_files together) or created from the fence it contains. In the latter
> + * case construction of the name is deferred until use, and so requires
> + * sync_file_get_name().
> + *
> + * Returns: a string representing the name.
> + */
> +char *sync_file_get_name(struct sync_file *sync_file, char *buf, int len)
> +{
> + if (sync_file->user_name[0]) {
> + strlcpy(buf, sync_file->user_name, len);
> + } else {
> + struct dma_fence *fence = sync_file->fence;
> +
> + snprintf(buf, len, "%s-%s%llu-%d",
> +  fence->ops->get_driver_name(fence),
> +  fence->ops->get_timeline_name(fence),
> +  fence->context,
> +  fence->seqno);
> + }
> +
> + return buf;
> +}
> +
>  static int sync_file_set_fence(struct sync_file *sync_file,
>  struct dma_fence **fences, int num_fences)
>  {
> @@ -266,7 +291,7 @@ static struct sync_file *sync_file_merge(const char 
> *name, struct sync_file *a,
>   goto err;
>   }
>  
> - strlcpy(sync_file->name, name, sizeof(sync_file->name));
> + strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name));
>   return sync_file;
>  
>  err:
> @@ -419,7 +444,7 @@ static long sync_file_ioctl_fence_info(struct sync_file 
> *sync_file,
>   }
>  
>  no_fences:
> - strlcpy(info.name, sync_file->name, sizeof(info.name));
> +  

Re: [Intel-gfx] [PATCH] drm/i915/gen3: Improve reset reliability

[Chris Wilson]

On Mon, May 22, 2017 at 12:02:44PM +0300, Mika Kuoppala wrote:
> We improved the reset reliablity on gen4 with
> stopping all engines before commencing reset, in
> commit 2c80353f3cd0 ("drm/i915/g4x: Improve gpu reset reliability")
> 
> Evidence indicates that this same trick works with gen3.

Note this is g33 which is a close cousin to g4x, not ye olde gen3
itself.

> Testcase: igt/gem_busy/*-hang #blb-e6850
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 
> Cc: Tomi Sarvela 
> Signed-off-by: Mika Kuoppala 
Acked-by: Chris Wilson 
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow kswapd to pause the device whilst reaping

[Patchwork]

== Series Details ==

Series: drm/i915: Allow kswapd to pause the device whilst reaping
URL   : https://patchwork.freedesktop.org/series/24776/
State : success

== Summary ==

Series 24776v1 drm/i915: Allow kswapd to pause the device whilst reaping
https://patchwork.freedesktop.org/api/1.0/series/24776/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time:433s
fi-bsw-n3050 total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  
time:587s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time:515s
fi-byt-j1900 total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:491s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:412s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time:411s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time:420s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:500s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time:463s
fi-kbl-7500u total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  
time:462s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:470s
fi-skl-6700hqtotal:278  pass:260  dwarn:1   dfail:0   fail:0   skip:17  
time:580s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time:463s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time:497s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time:530s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time:409s

721575dc73081f09673be35c8a7aa82224446cd1 drm-tip: 2017y-05m-22d-06h-50m-56s UTC 
integration manifest
afa24df drm/i915: Allow kswapd to pause the device whilst reaping

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4764/
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Re: [Intel-gfx] [PATCH] drm/i915: Use a cached mapping for the physical HWS

[Chris Wilson]

On Mon, May 22, 2017 at 10:55:01AM +0200, Daniel Vetter wrote:
> On Wed, May 17, 2017 at 02:02:50PM +0100, Chris Wilson wrote:
> > Older gen use a physical address for the hardware status page, for which
> > we use cache-coherent writes. As the writes are into the cpu cache, we use
> > a normal WB mapped page to read the HWS, used for our seqno tracking.
> > 
> > Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
> > which so far have not reoccurred with this patch. How reliable that
> > evidence is remains to be seen.
> > 
> > Signed-off-by: Chris Wilson 
> 
> dma is assumed to be coherent, so this should give you the same thing in
> the end.

Hmm, DMA historically hasn't been coherent, to get coherency required
UC - being able to snoop was an ability of the GMCH, I thought. Looking
at drivers/base/dma-coherent.c it is allocating UC (WC if you are
lucky) from a device region, though I'm lost working out how the dynamic
allocaton is treated.

> Except that dma_map_page can use bounce buffers, whereas
> dma_alloc_coherent will make sure you're not doing that.

Hmm, on these machines we don't have DMAR, we really should be feeding
in physical addresses. That was probably being too polite. Fancy
without?
-Chris

-- 
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Re: [Intel-gfx] [PATCH v4 2/2] drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI

[Daniel Vetter]

On Mon, May 22, 2017 at 09:51:22AM +0200, Daniel Vetter wrote:
> On Fri, May 19, 2017 at 04:50:17PM -0400, Robert Foss wrote:
> > Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
> > as a convenience.
> > 
> > Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
> > through the atomic API, but realizing that userspace is likely to take
> > shortcuts and assume that the enum values are what is sent over the
> > wire.
> > 
> > As a result these defines are provided purely as a convenience to
> > userspace applications.
> > 
> > Signed-off-by: Robert Foss 
> > Reviewed-by: Emil Velikov 
> > Reviewed-by: Sinclair Yeh 
> > Acked-by: Liviu Dudau 
> > ---
> > Changes since v3:
> >  - Switched away from past tense in comments
> >  - Add define name change to previously mis-spelled DRM_REFLECT_X comment
> >  - Improved the comment for the DRM_MODE_REFLECT_ comment
> > 
> > Changes since v2:
> >  - Changed define prefix from DRM_MODE_PROP_ to DRM_MODE_
> >  - Fix compilation errors
> >  - Changed comment formatting
> >  - Deduplicated comment lines
> >  - Clarified DRM_MODE_PROP_REFLECT_ comment
> > 
> > Changes since v1:
> >  - Moved defines from drm.h to drm_mode.h
> >  - Changed define prefix from DRM_ to DRM_MODE_PROP_ 
> >  - Updated uses of the defines to the new prefix
> >  - Removed include from drm_rect.c
> >  - Stopped using the BIT() macro 
> 
> I know everyone else is different, but I like to keep these in the commit
> message (even better when they're annotated with the names of reviewers
> who made the suggestion). So added it to the commit.
> 
> Anyway applied, thanks.

Ok, this turns into a mess because drm-intel isn't in sync and oh the fun.
But I guess I'll survive :-)
-Daniel

> -Daniel
> 
> > 
> >  drivers/gpu/drm/arm/malidp_drv.h|  2 +-
> >  drivers/gpu/drm/arm/malidp_planes.c | 18 -
> >  drivers/gpu/drm/armada/armada_overlay.c |  2 +-
> >  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 20 +-
> >  drivers/gpu/drm/drm_atomic.c|  2 +-
> >  drivers/gpu/drm/drm_atomic_helper.c |  2 +-
> >  drivers/gpu/drm/drm_blend.c | 45 +++---
> >  drivers/gpu/drm/drm_fb_helper.c |  4 +-
> >  drivers/gpu/drm/drm_plane_helper.c  |  2 +-
> >  drivers/gpu/drm/drm_rect.c  | 36 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++
> >  drivers/gpu/drm/i915/intel_atomic_plane.c   |  6 +--
> >  drivers/gpu/drm/i915/intel_display.c| 50 
> > -
> >  drivers/gpu/drm/i915/intel_fbc.c|  2 +-
> >  drivers/gpu/drm/i915/intel_fbdev.c  |  2 +-
> >  drivers/gpu/drm/i915/intel_sprite.c | 20 +-
> >  drivers/gpu/drm/imx/ipuv3-plane.c   |  2 +-
> >  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 30 +++
> >  drivers/gpu/drm/nouveau/nv50_display.c  |  2 +-
> >  drivers/gpu/drm/omapdrm/omap_drv.c  |  4 +-
> >  drivers/gpu/drm/omapdrm/omap_fb.c   | 18 -
> >  drivers/gpu/drm/omapdrm/omap_plane.c| 16 
> >  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  4 +-
> >  include/drm/drm_blend.h | 21 +--
> >  include/uapi/drm/drm_mode.h | 49 
> > +++-
> >  25 files changed, 202 insertions(+), 171 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/arm/malidp_drv.h 
> > b/drivers/gpu/drm/arm/malidp_drv.h
> > index 040311ffcaec..2e2033140efc 100644
> > --- a/drivers/gpu/drm/arm/malidp_drv.h
> > +++ b/drivers/gpu/drm/arm/malidp_drv.h
> > @@ -65,6 +65,6 @@ void malidp_de_planes_destroy(struct drm_device *drm);
> >  int malidp_crtc_init(struct drm_device *drm);
> >  
> >  /* often used combination of rotational bits */
> > -#define MALIDP_ROTATED_MASK(DRM_ROTATE_90 | DRM_ROTATE_270)
> > +#define MALIDP_ROTATED_MASK(DRM_MODE_ROTATE_90 | 
> > DRM_MODE_ROTATE_270)
> >  
> >  #endif  /* __MALIDP_DRV_H__ */
> > diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
> > b/drivers/gpu/drm/arm/malidp_planes.c
> > index 814fda23cead..063a8d2b0be3 100644
> > --- a/drivers/gpu/drm/arm/malidp_planes.c
> > +++ b/drivers/gpu/drm/arm/malidp_planes.c
> > @@ -80,7 +80,7 @@ static void malidp_plane_reset(struct drm_plane *plane)
> > state = kzalloc(sizeof(*state), GFP_KERNEL);
> > if (state) {
> > state->base.plane = plane;
> > -   state->base.rotation = DRM_ROTATE_0;
> > +   state->base.rotation = DRM_MODE_ROTATE_0;
> > plane->state = >base;
> > }
> >  }
> > @@ -221,7 +221,7 @@ static int malidp_de_plane_check(struct drm_plane 
> > *plane,
> > return ret;
> >  
> > /* packed RGB888 / BGR888 can't be rotated or flipped */
> > -   if