Re: [Intel-gfx] [PULL] drm-intel-fixes

On 20 September 2017 at 15:43, Dave Airlie wrote: > On 20 September 2017 at 09:03, Rodrigo Vivi wrote: >> Hi Dave, > > Hi Rodrigo, > > This pull request is generated wrongly, it contains some commits from > drm-next in it. Sorry contains some commits

Re: [Intel-gfx] [PULL] drm-intel-fixes

On 20 September 2017 at 09:03, Rodrigo Vivi wrote: > Hi Dave, Hi Rodrigo, This pull request is generated wrongly, it contains some commits from drm-next in it. Please regenerate it, I'm assuming you generated against 4.14-rc1 and not against drm-next. Dave.

[Intel-gfx] ✗ Fi.CI.IGT: failure for tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)

== Series Details == Series: tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2) URL : https://patchwork.freedesktop.org/series/30564/ State : failure == Summary == Test gem_eio: Subgroup in-flight-external: dmesg-warn -> PASS (shard-hsw)

Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

> On Sep 19, 2017, at 6:26 PM, Pandiyan, Dhinakaran > wrote: > > >> On Fri, 2017-09-15 at 17:00 -0700, Radhakrishna Sripada wrote: >> Platforms do not support psr and drrs simultaneously. >> Adding a subtest to make the check. >> >> Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly

On Wed, 2017-09-20 at 05:46 +0800, Zhenyu Wang wrote: > On 2017.09.19 16:55:34 +0100, Colin King wrote: > > From: Colin Ian King > > > > An earlier fix changed the return type from find_bb_size however the > > integer return is being assigned to a unsigned int so the

[Intel-gfx] ✗ Fi.CI.IGT: failure for tools_test: Clean up and fix sysfs_l3_parity

== Series Details == Series: tools_test: Clean up and fix sysfs_l3_parity URL : https://patchwork.freedesktop.org/series/30583/ State : failure == Summary == Test drv_hangman: Subgroup error-state-capture-render: pass -> SKIP (shard-hsw) Test

Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/gvt: Add gvt_debug in i915_params for GVT-g log classification

On Wed 20.Sep'17 at 4:45:31 +0800, Zhenyu Wang wrote: On 2017.09.19 18:17:04 +0800, Shuo Liu wrote: On Tue 19.Sep'17 at 10:22:16 +0100, Chris Wilson wrote: > Quoting Shuo Liu (2017-09-19 08:54:43) > > Signed-off-by: Shuo Liu > > --- > >

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

== Series Details == Series: drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug URL : https://patchwork.freedesktop.org/series/30626/ State : warning == Summary == Test kms_flip: Subgroup rcs-wf_vblank-vs-dpms: dmesg-warn -> PASS (shard-hsw) Test perf:

Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

On Fri, 2017-09-15 at 17:00 -0700, Radhakrishna Sripada wrote: > Platforms do not support psr and drrs simultaneously. > Adding a subtest to make the check. > > Cc: Rodrigo Vivi > Cc: Daniel Vetter > Signed-off-by: Radhakrishna Sripada

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skylake plane update/disable unifications [v5]

== Series Details == Series: drm/i915: Skylake plane update/disable unifications [v5] URL : https://patchwork.freedesktop.org/series/30622/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 Test kms_flip:

[Intel-gfx] ✓ Fi.CI.BAT: success for tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)

== Series Details == Series: tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2) URL : https://patchwork.freedesktop.org/series/30564/ State : success == Summary == IGT patchset tested on top of latest successful build da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add

[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/kms_rotation_crc : Remove flip tests for sprite plane

== Series Details == Series: igt/kms_rotation_crc : Remove flip tests for sprite plane URL : https://patchwork.freedesktop.org/series/30588/ State : failure == Summary == IGT patchset tested on top of latest successful build da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another

[Intel-gfx] ✗ Fi.CI.IGT: warning for GuC code restructuring and fixes (rev3)

== Series Details == Series: GuC code restructuring and fixes (rev3) URL : https://patchwork.freedesktop.org/series/30351/ State : warning == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_flip: Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for tools_test: Clean up and fix sysfs_l3_parity

== Series Details == Series: tools_test: Clean up and fix sysfs_l3_parity URL : https://patchwork.freedesktop.org/series/30583/ State : success == Summary == IGT patchset tested on top of latest successful build da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another variant of

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: ensure -ve return value is handled correctly

== Series Details == Series: drm/i915/gvt: ensure -ve return value is handled correctly URL : https://patchwork.freedesktop.org/series/30604/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 +1 Test kms_flip:

Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

On Tue, Sep 19, 2017 at 09:41:36AM +, Petri Latvala wrote: > On Mon, Sep 18, 2017 at 12:51:07PM -0700, Rodrigo Vivi wrote: > > > Reviewed-by: Rodrigo Vivi > > > > merged to master. thanks for the patch,. > > > Obligatory scolding: You forgot to add your R-b to the

Re: [Intel-gfx] [PATCH] drm/i915/cfl: Remove alpha support protection.

On Fri, Sep 08, 2017 at 01:45:59AM +, Pandiyan, Dhinakaran wrote: > On Thu, 2017-09-07 at 16:06 -0700, Rodrigo Vivi wrote: > > We now have Coffee Lake on our CI systems. > > > > Coffee Lake is at this point in same stage as Kaby Lake. > > > > And it seems that we don't have any risk of bad

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

On Tue, Sep 19, 2017 at 09:57:03PM +, Rodrigo Vivi wrote: > "CNL PCH chance of hang when software accesses south display > registers after hotplug is enabled. > Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling > south display hotplug detection." > > "Workaround only needs to be

[Intel-gfx] ✗ Fi.CI.BAT: failure for tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy

== Series Details == Series: tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy URL : https://patchwork.freedesktop.org/series/30582/ State : failure == Summary == IGT patchset tested on top of latest successful build da197b5f3cb516aaaea72d0d60b0f5c1c81081dd

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Here are drm/i915 the fixes for 4.14-rc1. Couple fixes for stable: - Fix MIPI panels on BXT. - Fix PCI BARs information on GVT. Plus other fixes: - Fix minimal brightness for BXT, GLK, CFL and CNL. - Fix compilation warning: unused in_vbl - Fix error handling in

[Intel-gfx] [PATCH i-g-t v2] tests/psr: Don't strcmp CRCs that are not NULL terminated.

Switched to strncmp. v2: increased buffer size to account for NULL character. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- tests/kms_psr_sink_crc.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs URL : https://patchwork.freedesktop.org/series/30629/ State : warning == Summary == Series 30629v1 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Stop engines before reset (rev2)

== Series Details == Series: drm/i915: Stop engines before reset (rev2) URL : https://patchwork.freedesktop.org/series/30357/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 Test kms_flip: Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

== Series Details == Series: drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug URL : https://patchwork.freedesktop.org/series/30626/ State : success == Summary == Series 30626v1 drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of the die instead of other slices or anything like

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by avoiding [1][2] and [2][2]. - Inclusion of EU Per

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/edp: Be less aggressive about changing link config on eDP (rev4)

== Series Details == Series: drm/i915/edp: Be less aggressive about changing link config on eDP (rev4) URL : https://patchwork.freedesktop.org/series/28588/ State : failure == Summary == Series 28588v4 drm/i915/edp: Be less aggressive about changing link config on eDP

[Intel-gfx] [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

"CNL PCH chance of hang when software accesses south display registers after hotplug is enabled. Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling south display hotplug detection." "Workaround only needs to be applied to pre-production steppings used in graphics capable SKUs, but it is

Re: [Intel-gfx] [PATCH 0/6] Adding NV12 support

On Mon, Aug 28, 2017 at 3:17 PM, Daniel Vetter wrote: > On Mon, Aug 28, 2017 at 04:22:16PM +0530, Vidya Srinivas wrote: >> This patch series is adding NV12 support for Broxton display after >> rebasing on latest drm-intel-nightly. Initial series of the patches >> can be found

Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly

On 2017.09.19 16:55:34 +0100, Colin King wrote: > From: Colin Ian King > > An earlier fix changed the return type from find_bb_size however the > integer return is being assigned to a unsigned int so the -ve error > check will never be detected. Make bb_size an int to

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)

On Tue, Sep 19, 2017 at 08:28:16PM +, Patchwork wrote: > == Series Details == > > Series: series starting with drm/i915/cnp: Display Wa #1179: > WaHardHangonHotPlug (rev3) > URL : https://patchwork.freedesktop.org/series/30067/ > State : failure > > == Summary == > > CHK

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3.

== Series Details == Series: series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3. URL : https://patchwork.freedesktop.org/series/30587/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2) URL : https://patchwork.freedesktop.org/series/30549/ State : failure == Summary == Series 30549v2 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu

[Intel-gfx] [PATCH v8] drm/i915/edp: Be less aggressive about changing link config on eDP

This set of changes has some history to them. There were several attempts to add what was called "fast link training" to i915, which actually wasn't fast link training as per the DP spec. These changes were: commit 5fa836a9d859 ("drm/i915: DP link training optimization") commit 4e96c97742f4

Re: [Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

On Tue, Sep 19, 2017 at 12:55:24PM -0700, Rodrigo Vivi wrote: > On Fri, Sep 15, 2017 at 06:19:12PM +, Manasi Navare wrote: > > The patch looks good for eDP link training optimizations. > > > > Reviewed-by: Manasi Navare > > I haven't merged this patch yet because

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

On 09/19/2017 02:02 PM, Rodrigo Vivi wrote: From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skylake plane update/disable unifications [v5]

== Series Details == Series: drm/i915: Skylake plane update/disable unifications [v5] URL : https://patchwork.freedesktop.org/series/30622/ State : success == Summary == Series 30622v1 drm/i915: Skylake plane update/disable unifications [v5]

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of the die instead of other slices or anything like

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by avoiding [1][2] and [2][2]. - Inclusion of EU Per

[Intel-gfx] ✓ Fi.CI.IGT: success for i915 PMU and engine busy stats (rev10)

== Series Details == Series: i915 PMU and engine busy stats (rev10) URL : https://patchwork.freedesktop.org/series/27488/ State : success == Summary == Test kms_flip: Subgroup rcs-wf_vblank-vs-dpms: dmesg-warn -> PASS (shard-hsw) Test perf: Subgroup

Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/gvt: Add gvt_debug in i915_params for GVT-g log classification

On 2017.09.19 18:17:04 +0800, Shuo Liu wrote: > On Tue 19.Sep'17 at 10:22:16 +0100, Chris Wilson wrote: > > Quoting Shuo Liu (2017-09-19 08:54:43) > > > Signed-off-by: Shuo Liu > > > --- > > > drivers/gpu/drm/i915/i915_params.c | 13 + > > >

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v6,1/3] drm/i915: Rename global i915 to i915_modparams

== Series Details == Series: series starting with [v6,1/3] drm/i915: Rename global i915 to i915_modparams URL : https://patchwork.freedesktop.org/series/30621/ State : warning == Summary == Series 30621v1 series starting with [v6,1/3] drm/i915: Rename global i915 to i915_modparams

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote: From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote: CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Create intel_uc_init_mmio to initialize MMIO interface prior to uc init

On Tue, 19 Sep 2017 19:27:39 +0200, Sagar Arun Kamble wrote: This patch adds new function intel_uc_init_mmio which will initialize MMIO access related variables prior to uc load/init. v2: Removed unnecessary export of guc_send_init_regs. Created intel_uc_init_mmio

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)

== Series Details == Series: series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3) URL : https://patchwork.freedesktop.org/series/30067/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

[Intel-gfx] ✓ Fi.CI.BAT: success for GuC code restructuring and fixes (rev3)

== Series Details == Series: GuC code restructuring and fixes (rev3) URL : https://patchwork.freedesktop.org/series/30351/ State : success == Summary == Series 30351v3 GuC code restructuring and fixes https://patchwork.freedesktop.org/api/1.0/series/30351/revisions/3/mbox/ Test

Re: [Intel-gfx] [PATCH 01/14] drm/i915/guc: Pass intel_guc struct as parameter to intel_guc_wopcm_size

On Tue, 19 Sep 2017 19:27:38 +0200, Sagar Arun Kamble wrote: Pass intel_guc struct as parameter to intel_guc_wopcm_size instead of drm_i915_private. intel_guc_suspend/resume parameters are not updated in this patch as those functions are updated in the upcoming

Re: [Intel-gfx] [PATCH 00/14] GuC code restructuring and fixes

On Tue, 19 Sep 2017 19:27:37 +0200, Sagar Arun Kamble wrote: This series is based on reviews from https://patchwork.freedesktop.org/series/30502/. Cc: Michal Wajdeczko Cc: Michał Winiarski Sagar Arun

Re: [Intel-gfx] [RFC 10/11] drm/i915: Export engine stats API to other users

On Tue, 2017-09-19 at 12:50 -0700, Ben Widawsky wrote: > On 17-09-15 10:49:56, Tvrtko Ursulin wrote: > > > >On 14/09/2017 21:26, Chris Wilson wrote: > >>Quoting Tvrtko Ursulin (2017-09-11 16:25:58) > >>>From: Tvrtko Ursulin > >>> > >>>Other kernel users might want to

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: ensure -ve return value is handled correctly

== Series Details == Series: drm/i915/gvt: ensure -ve return value is handled correctly URL : https://patchwork.freedesktop.org/series/30604/ State : success == Summary == Series 30604v1 drm/i915/gvt: ensure -ve return value is handled correctly

Re: [Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

On Fri, Sep 15, 2017 at 06:19:12PM +, Manasi Navare wrote: > The patch looks good for eDP link training optimizations. > > Reviewed-by: Manasi Navare I haven't merged this patch yet because I'd like an Ack from Jani. Also I'd like to hear from Mika if he believes

Re: [Intel-gfx] [RFC 10/11] drm/i915: Export engine stats API to other users

On 17-09-15 10:49:56, Tvrtko Ursulin wrote: On 14/09/2017 21:26, Chris Wilson wrote: Quoting Tvrtko Ursulin (2017-09-11 16:25:58) From: Tvrtko Ursulin Other kernel users might want to look at total GPU busyness in order to implement things like package power

[Intel-gfx] [PATCH 0/5] drm/i915: Skylake plane update/disable unifications [v5]

[v5] use clipped y coordinate at get_crtc_fence_y_offset() (ville syrjälä) [v4] rebase [v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä) [v2] Fixed missed references which were brough on rebase. /Juha-Pekka Juha-Pekka Heikkila (5): drm/i915: move adjusted_x/y from

[Intel-gfx] [PATCH 3/5] drm/i915: Unify skylake plane disable

Don't handle skylake primary plane separately as it is similar plane as the others. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_display.c | 21 ++--- drivers/gpu/drm/i915/intel_drv.h | 1 +

[Intel-gfx] [PATCH 5/5] drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y

This is to use clipped y coordinate here. I left get_crtc_fence_y_offset() function itself in place as oneliner to maintain comment above it why this is done. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_drv.h | 2 ++

[Intel-gfx] [PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_drv.h | 8 drivers/gpu/drm/i915/intel_display.c | 10 ++ drivers/gpu/drm/i915/intel_drv.h | 2 -- drivers/gpu/drm/i915/intel_fbc.c | 11 --- 4 files changed, 22

[Intel-gfx] [PATCH 2/5] drm/i915: Unify skylake plane update

Don't handle skylake primary plane separately as it is similar plane as the others. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_display.c | 82 +--- drivers/gpu/drm/i915/intel_drv.h | 3 ++

[Intel-gfx] [PATCH 4/5] drm/i915: dspaddr_offset doesn't need to be more than local variable

Move u32 dspaddr_offset from struct intel_crtc member into local variable in i9xx_update_primary_plane() Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_display.c | 12 ++-- drivers/gpu/drm/i915/intel_drv.h | 5 - 2 files changed,

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: always update ELD connector type after get modes

== Series Details == Series: drm/i915: always update ELD connector type after get modes URL : https://patchwork.freedesktop.org/series/30602/ State : warning == Summary == Series 30602v1 drm/i915: always update ELD connector type after get modes

[Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

We should discourage developers from modifying modparams. Introduce special macro for easier tracking of changes done in modparams and enforce its use by defining existing modparams members as const. Note that defining whole modparams struct as const makes checkpatch unhappy. v2: rebased

[Intel-gfx] [PATCH v6 1/3] drm/i915: Rename global i915 to i915_modparams

Our global struct with params is named exactly the same way as new preferred name for the drm_i915_private function parameter. To avoid such name reuse lets use different name for the global. v5: pure rename v6: fix Credits-to: Coccinelle @@ identifier n; @@ ( - i915.n +

[Intel-gfx] [PATCH v6 2/3] drm/i915: Prepare error capture to work with const modparams

We are planning to enforce "read_mostly" access to modparams. Let start handle modparams as it was already defined as const. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_gpu_error.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

Re: [Intel-gfx] [PATCH 8/9] drm/i915/dp: Protect link training with connection mutex

On Tue, 2017-09-19 at 15:42 +0300, Ville Syrjälä wrote: > On Mon, Sep 18, 2017 at 09:50:30PM +, Pandiyan, Dhinakaran wrote: > > On Fri, 2017-09-15 at 13:10 +0300, Ville Syrjälä wrote: > > > On Tue, Sep 12, 2017 at 04:57:29PM -0700, Dhinakaran Pandiyan wrote: > > > > The other instances of

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/3] drm/i915: Rename global i915 to i915_modparams

== Series Details == Series: series starting with [v5,1/3] drm/i915: Rename global i915 to i915_modparams URL : https://patchwork.freedesktop.org/series/30600/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop engines before reset (rev2)

== Series Details == Series: drm/i915: Stop engines before reset (rev2) URL : https://patchwork.freedesktop.org/series/30357/ State : success == Summary == Series 30357v2 drm/i915: Stop engines before reset https://patchwork.freedesktop.org/api/1.0/series/30357/revisions/2/mbox/ Test

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3.

== Series Details == Series: series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3. URL : https://patchwork.freedesktop.org/series/30587/ State : success == Summary == Series 30587v1 series starting with [1/2] drm/i915: Unset legacy_cursor_update

[Intel-gfx] ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev10)

== Series Details == Series: i915 PMU and engine busy stats (rev10) URL : https://patchwork.freedesktop.org/series/27488/ State : success == Summary == Series 27488v10 i915 PMU and engine busy stats https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/10/mbox/ Test chamelium:

Re: [Intel-gfx] [PATCH] Idleness DRRS:

On Tue, Sep 19, 2017 at 10:46:49AM +, Ramalingam C wrote: > > > On Tuesday 19 September 2017 01:24 AM, Rodrigo Vivi wrote: > > On Mon, Sep 18, 2017 at 08:52:12AM +, wrote: > > > From: Lohith BS > > > > > > By default the DRRS state will be at DRRS_HIGH_RR. When

Re: [Intel-gfx] [PATCH v2] drm/i915/mst: Use MST sideband message transactions for dpms control

On Wed, 2017-09-13 at 13:06 -0700, Dhinakaran Pandiyan wrote: > Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to > set power states for downstream sinks. Apart from giving us the ability > to set power state for individual sinks, this fixes the below test for > me. > > $

[Intel-gfx] [PATCH] dim: Accept author x signed-off based on email, but warn.

It seems Patchwork or SMTP servers are messing some patches and changing the original git's author name on git per "Last, First". So we end up with a mismatch were signed-off uses one name format and author is using another format. So, let's check for email addresses instead. However let's

[Intel-gfx] [PATCH 29/31] drm/i915/slpc: Add Broxton SLPC support

From: Tom O'Rourke Adds has_slpc to broxton info. v1: Adjusted slpc version check for major version 8. Added message if version mismatch happens for easier debug. (Sagar) v2-v3: Rebase. v4: Commit message update. v5: Rebase. Updated check in sanitize_slpc_option.

[Intel-gfx] [PATCH 25/31] drm/i915/slpc: Add enable/disable controls for SLPC tasks

From: Tom O'Rourke Adds debugfs hooks for enabling/disabling each SLPC task. The enable/disable debugfs files are i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc. Each of these can take the values: "default", "enabled", or "disabled" v1: update for SLPC

[Intel-gfx] [PATCH 31/31] drm/i915/slpc: Add Geminilake SLPC support

Adds has_slpc to geminilake info. Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d89d6fc..738e214 100644 ---

[Intel-gfx] [PATCH 30/31] drm/i915/slpc: Add Kabylake SLPC support

Adds has_slpc to kabylake info. Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_slpc.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c

[Intel-gfx] [PATCH 11/31] drm/i915: Introduce separate status variable for RC6 and Ring frequency setup

Defined new struct intel_rc6 to hold RC6 specific state and intel_ring_pstate to hold ring specific state. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.c | 2 +-

[Intel-gfx] [PATCH 13/31] drm/i915/slpc: Add has_slpc capability flag

From: Tom O'Rourke Add has_slpc capablity flag to indicate GuC firmware supports single loop power control (SLPC). SLPC is a replacement for some host-based power management features. v1: fix whitespace (Sagar) Reviewed-by: David Weinehall

[Intel-gfx] [PATCH 20/31] drm/i915/slpc: Add parameter set/unset/get, task control/status functions

SLPC behavior can be changed through set of parameters. These parameters can be updated and queried from i915 though Host to GuC SLPC events. This patch adds parameter update events for setting/unsetting/getting parameters. SLPC has various tasks for controlling different controls. This patch adds

[Intel-gfx] [PATCH 21/31] drm/i915/slpc: Send RESET event to enable SLPC during Load/TDR

Send host2guc SLPC reset event to GuC post GuC load. Post this, i915 can ascertain if SLPC has started running successfully through shared data. This check is done during intel_init_gt_powersave. This allows to get initial configuration setup by SLPC and if needed move to Host RPS if SLPC runs

[Intel-gfx] [PATCH 22/31] drm/i915/slpc: Send SHUTDOWN event

From: Tom O'Rourke Send SLPC shutdown event during disable, suspend, and reset operations. Sending shutdown event while already shutdown is OK. v1: Return void instead of ignored error code (Paulo) Removed WARN_ON for checking msb of gtt address of shared gem

[Intel-gfx] [PATCH 17/31] drm/i915/slpc: Enable SLPC in GuC if supported

From: Tom O'Rourke If slpc enabled, then add enable SLPC flag to guc control parameter during guc load. v1: Use intel_slpc_enabled() (Paulo) v2-v4: Rebase. v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar) v6: Changed i915.enable_slpc to

[Intel-gfx] [PATCH 27/31] drm/i915/slpc: Add SLPC banner to RPS debugfs interfaces.

When SLPC is controlling frequency requests, RPS state related to autotuning is no longer valid. Make user aware through banner upfront. Value read from register RPNSWREQ likely has the frequency requested last by GuC SLPC. v1: Replace HAS_SLPC with intel_slpc_active (Paulo) Avoid magic

[Intel-gfx] [PATCH 26/31] drm/i915/slpc: Add i915_slpc_info to debugfs

From: Tom O'Rourke i915_slpc_info shows the contents of SLPC shared data parsed into text format. v1: Reformat slpc info (Radek) squashed query task state info in slpc info, kunmap before seq_print (Paulo) return void instead of ignored return value (Paulo)

[Intel-gfx] [PATCH 24/31] drm/i915/slpc: Add debugfs support to read/write/revert the parameters

This patch adds two debugfs interfaces: 1. i915_slpc_paramlist: List of all parameters that Host can configure. Currently listing id and description of each. 2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is: echo "write " > i915_slpc_param_ctl. echo "read " >

[Intel-gfx] [PATCH 23/31] drm/i915/slpc: Add support for min/max frequency control

Update sysfs and debugfs functions to set SLPC parameters when setting max/min frequency. v1: Update for SLPC 2015.2.4 (params for both slice and unslice) Replace HAS_SLPC with intel_slpc_active() (Paulo) v2-v4: Rebase. v5: Removed typecasting the frequency values to u32. (Chris)

[Intel-gfx] [PATCH 28/31] drm/i915/slpc: Add SKL SLPC Support

From: Tom O'Rourke This patch adds has_slpc to skylake info. The SLPC interface has changed and could continue to change. Only GuC versions known to be compatible are supported here. v1: Move slpc_version_check to intel_guc_ucode_init. fix whitespace (Sagar)

[Intel-gfx] [PATCH 18/31] drm/i915/slpc: Add SLPC communication interfaces

Communication with SLPC is via Host to GuC interrupt through shared data and parameters. This patch defines the structure of shared data, parameters, data structure to be passed as input and received as output from SLPC. This patch also defines the events to be sent as input and status values

[Intel-gfx] [PATCH 15/31] drm/i915/slpc: Sanitize GuC version

From: Tom O'Rourke The SLPC interface is dependent on GuC version. Only GuC versions known to be compatible are supported here. SLPC with GuC firmware v9 is supported with this series. v1: Updated with modified sanitize_slpc_option in earlier patch. v2-v3: Rebase. v4:

[Intel-gfx] [PATCH 19/31] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

Populate SLPC shared data with required default values for Slice count, Power source/plan, IA Perf MSRs. v1: Update for SLPC interface version 2015.2.4 intel_slpc_active() returns 1 if slpc initialized (Paulo) change default host_os to "Windows" Spelling fixes (Sagar Kamble and Nick

[Intel-gfx] [PATCH 14/31] drm/i915/slpc: Add enable_slpc module parameter

From: Tom O'Rourke i915.enable_slpc is used to override the default for slpc usage. The expected values are -1=auto, 0=disabled [default], 1=enabled. Sanitize i915.enable_slpc to either 0 or 1 based on HAS_SLPC() and GuC load and submission options. v1: Add early call

[Intel-gfx] [PATCH 10/31] drm/i915: Create generic functions to control RC6, RPS

Prepared generic functions intel_enable_rc6, intel_disable_rc6, intel_enable_rps and intel_disable_rps functions to setup RC6/RPS based on platforms. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble ---

[Intel-gfx] [PATCH 16/31] drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers

SLPC operates based on parameters setup in shared data between i915 and GuC SLPC. This is to be created/initialized in intel_slpc_init. From there onwards i915 can control the SLPC operations by Enabling, Disabling complete SLPC or changing SLPC parameters. During cleanup SLPC shared data has to

[Intel-gfx] [PATCH 12/31] drm/i915: Define RPS idle, busy, boost function pointers

These will allow to define nop functions when SLPC is in use. Initialized with gen6_rps_idle, gen6_rps_busy and gen6_rps_boost during intel_enable_rps. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble ---

[Intel-gfx] [PATCH 07/31] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "pm"

Prepared substructure rps for RPS related state. autoenable_work and pcu_lock are used for RC6 hence they are defined outside rps structure. Renamed the RPS lock as pcu_lock. Cc: Chris Wilson Cc: Imre Deak Signed-off-by: Sagar Arun Kamble

[Intel-gfx] [PATCH 08/31] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

This function gives the status of RC6, whether disabled or if enabled then which state. intel_enable_rc6 will be used for enabling RC6 in the next patch. Cc: Chris Wilson Cc: Imre Deak Signed-off-by: Sagar Arun Kamble ---

[Intel-gfx] [PATCH 02/31] drm/i915: Separate RPS and RC6 handling for gen6+

This patch separates enable/disable of RC6 and RPS for gen6+ platforms prior to VLV. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 17 +++---

[Intel-gfx] [PATCH 05/31] drm/i915: Separate RPS and RC6 handling for CHV

This patch separates enable/disable of RC6 and RPS for CHV. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_pm.c | 29 - 1 file changed, 24

[Intel-gfx] [PATCH 06/31] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"

Will be using pm for state containing RPS/RC6 state in the next patch. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.c | 8

[Intel-gfx] [PATCH 09/31] drm/i915: Create generic function to setup ring frequency table

Prepared intel_update_ring_freq function to setup ring frequency for applicable platforms determined by macro - NEEDS_RING_FREQ_UPDATE Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble ---

[Intel-gfx] [PATCH 04/31] drm/i915: Separate RPS and RC6 handling for VLV

This patch separates enable/disable of RC6 and RPS for VLV. Cc: Imre Deak Cc: Chris Wilson Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 12 +--- drivers/gpu/drm/i915/intel_pm.c | 57

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