Re: [Intel-gfx] [PATCH v13 04/21] drm/i915/guc: Remove enable_guc_submission dependency for invoking GuC log functions

[Sagar Arun Kamble]

On 10/11/2017 9:10 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:59 +0200, Sagar Arun Kamble 
 wrote:



With guc_log_level parameter sanitized and GuC interrupts control
functions made self sufficient w.r.t interrupts state, we can remove
the enable_guc_submission checks from flush_guc_logs and
i915_guc_log_register/unregister and intel_uc_fini_hw.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 9 ++---
 drivers/gpu/drm/i915/intel_uc.c  | 3 +--
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c

index 0f201c0..fb5eb2b9 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,7 @@ static void guc_flush_logs(struct intel_guc *guc)
 {
 struct drm_i915_private *dev_priv = guc_to_i915(guc);
-    if (!i915_guc_submission_enabled(guc) ||
-    i915_modparams.guc_log_level < 0)
+    if (i915_modparams.guc_log_level < 0)
 return;
/* First disable the interrupts, will be renabled afterwards */
@@ -646,8 +645,7 @@ int i915_guc_log_control(struct drm_i915_private 
*dev_priv, u64 control_val)

void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-    if (!i915_guc_submission_enabled(_priv->guc) ||
-    i915_modparams.guc_log_level < 0)
+    if (i915_modparams.guc_log_level < 0)


I would expect above two fixes in patch 2/21
Since there are multiple places needing the update and for better 
division I had created separate patches.

Will keep same for now.



 return;
mutex_lock(_priv->drm.struct_mutex);
@@ -657,9 +655,6 @@ void i915_guc_log_register(struct 
drm_i915_private *dev_priv)

void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-    if (!i915_guc_submission_enabled(_priv->guc))
-    return;


Hmm, as i915_guc_log_unregister() is called unconditionally by
i915_driver_unregister so maybe here we should have at least

if (i915_modparams.guc_log_level < 0)
    return;

Yes. Will add this.



-
 mutex_lock(_priv->drm.struct_mutex);
 /* GuC logging is currently the only user of Guc2Host interrupts */
 gen9_disable_guc_interrupts(dev_priv);


What about dropping this gen9_disable_guc_interrupts from here
and rely on the intel_uc_fini_hw() that will do the same?

This needs to be handled separately as if we remove it from here we will 
have to synchronize the logging irq

with relay runtime destruction. Will defer this for now.
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 3cf3cbd..974434e 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -280,8 +280,7 @@ void intel_uc_fini_hw(struct drm_i915_private 
*dev_priv)

guc_disable_communication(guc);
-    if (i915_guc_submission_enabled(guc))
-    gen9_disable_guc_interrupts(dev_priv);
+    gen9_disable_guc_interrupts(dev_priv);
 i915_guc_submission_fini(dev_priv);
i915_ggtt_disable_guc(dev_priv);




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Re: [Intel-gfx] [PATCH v13 03/21] drm/i915/guc: Add status checks to enable/disable_guc_interrupts

[Sagar Arun Kamble]

On 10/11/2017 8:50 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:58 +0200, Sagar Arun Kamble 
 wrote:


GuC interrupts are currently enabled by Logging and disabled in 
different

scenarios. Make disabling check whether interrupts were already disabled
and similar for enable path. This will remove the state tracking for the
callers of these functions based on kernel parameters.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_irq.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c 
b/drivers/gpu/drm/i915/i915_irq.c

index a3de408..6cf417c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -455,18 +455,22 @@ void gen9_reset_guc_interrupts(struct 
drm_i915_private *dev_priv)

void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+    if (READ_ONCE(dev_priv->guc.interrupts_enabled))


Hmm, I don't like that functions from irq.c read and modify guc internal
members directly. I would expect that functions here just do their job
and any state is maintained by the helper function(s) in guc.c.

Sure will move to guc.c.


Also note that this change will not help scenario where one client will
try to disable irqs while other client still depends on them.


Will add refcounting then.

Michal


+    return;
+
 spin_lock_irq(_priv->irq_lock);
-    if (!dev_priv->guc.interrupts_enabled) {
-    WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-   dev_priv->pm_guc_events);
-    dev_priv->guc.interrupts_enabled = true;
-    gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-    }
+    WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+   dev_priv->pm_guc_events);
+    dev_priv->guc.interrupts_enabled = true;
+    gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 spin_unlock_irq(_priv->irq_lock);
 }
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+    if (!READ_ONCE(dev_priv->guc.interrupts_enabled))
+    return;
+
 spin_lock_irq(_priv->irq_lock);
 dev_priv->guc.interrupts_enabled = false;


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Re: [Intel-gfx] [PATCH v13 02/21] drm/i915/guc: Sanitize module parameter guc_log_level

[Sagar Arun Kamble]

On 10/11/2017 8:21 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:57 +0200, Sagar Arun Kamble 
 wrote:



Parameter guc_log_level needs to be sanitized based on GuC support and
enable_guc_loading parameter since it depends on them like
enable_guc_submission. This will make GuC logging paths independent of
enable_guc_submission parameter in further patches.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index b33d469..3cf3cbd 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -56,6 +56,7 @@ void intel_uc_sanitize_options(struct 
drm_i915_private *dev_priv)


Btw, I think the message "Ignoring GuC options, no hardware\n" is also
applicable when user specified guc_log_level>=0. Please update condition
that controls that message.


Yes. Will update that condition.

    i915_modparams.enable_guc_loading = 0;
 i915_modparams.enable_guc_submission = 0;
+    i915_modparams.guc_log_level = -1;
 return;
 }
@@ -72,9 +73,11 @@ void intel_uc_sanitize_options(struct 
drm_i915_private *dev_priv)

 i915_modparams.enable_guc_loading = 0;
 }
-    /* Can't enable guc submission without guc loaded */
-    if (!i915_modparams.enable_guc_loading)
+    /* Can't enable guc submission and logging without guc loaded */
+    if (!i915_modparams.enable_guc_loading) {
 i915_modparams.enable_guc_submission = 0;
+    i915_modparams.guc_log_level = -1;
+    }
/* A negative value means "use platform default" */
 if (i915_modparams.enable_guc_submission < 0)


Looks good, but please also update condition in i915_guc_log_register()
as we may now rely only on sanitized guc_log_level:

void i915_guc_log_register(struct drm_i915_private *dev_priv)
{
if (!i915_modparams.enable_guc_submission ||
 
    (i915_modparams.guc_log_level < 0))
    return;


This is updated in the later patches in the series.

Also, maybe it is worth to update DOC in intel_guc_log.c and param
description in i915_params.c to indicate (obvious) dependency on guc.


Sure. Will add this.

Michal


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[Intel-gfx] ✗ Fi.CI.BAT: failure for enable virtual HWSP in GVT-g (rev2)

[Patchwork]

== Series Details ==

Series: enable virtual HWSP in GVT-g (rev2)
URL   : https://patchwork.freedesktop.org/series/31217/
State : failure

== Summary ==

Series 31217 revision 2 was fully merged or fully failed: no git log

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[Intel-gfx] [PATCH v3 0/2] enable virtual HWSP in GVT-g

[Weinan Li]

v2 : clean merge confict

v3 :
 remove unnecessary comments
 add address audit in HWSP address update

Weinan Li (2):
  drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP
  drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g
VM

 drivers/gpu/drm/i915/gvt/execlist.c| 17 +
 drivers/gpu/drm/i915/gvt/gvt.h |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c| 45 +-
 drivers/gpu/drm/i915/gvt/vgpu.c|  8 ++
 drivers/gpu/drm/i915/i915_pvinfo.h |  1 +
 drivers/gpu/drm/i915/i915_vgpu.c   |  5 
 drivers/gpu/drm/i915/i915_vgpu.h   |  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c |  8 +++---
 drivers/gpu/drm/i915/intel_lrc.c   |  1 -
 9 files changed, 81 insertions(+), 6 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v3 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

[Weinan Li]

The engine provides a mirror of the CSB and CSB write pointer in the HWSP.
Read these status from virtual HWSP in VM can reduce CPU utilization while
applications have much more short GPU workloads. Here we update the
corresponding data in virtual HWSP as it in virtual MMIO.

Before read these status from HWSP in GVT-g VM, please ensure the host
support it by checking the BIT(3) of caps in PVINFO.

Virtual HWSP only support GEN8+ platform, since the HWSP MMIO may change
follow the platform update, please add the corresponding MMIO emulation
when enable new platforms in GVT-g.

v3 : Add address audit in HWSP address update.

Signed-off-by: Weinan Li 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gvt/execlist.c | 17 ++
 drivers/gpu/drm/i915/gvt/gvt.h  |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c | 45 -
 drivers/gpu/drm/i915/gvt/vgpu.c |  8 +++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  1 +
 5 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/execlist.c 
b/drivers/gpu/drm/i915/gvt/execlist.c
index 5c966ed..7bc7286 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -133,6 +133,8 @@ static void emulate_csb_update(struct intel_vgpu_execlist 
*execlist,
struct execlist_context_status_pointer_format ctx_status_ptr;
u32 write_pointer;
u32 ctx_status_ptr_reg, ctx_status_buf_reg, offset;
+   unsigned long hwsp_gpa;
+   struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 
ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
_EL_OFFSET_STATUS_PTR);
@@ -158,6 +160,21 @@ static void emulate_csb_update(struct intel_vgpu_execlist 
*execlist,
ctx_status_ptr.write_ptr = write_pointer;
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
 
+   /* Update the CSB and CSB write pointer in HWSP */
+   if (INTEL_INFO(dev_priv)->gen >= 8) {
+   hwsp_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
+vgpu->hws_pga[ring_id]);
+   if (hwsp_gpa != INTEL_GVT_INVALID_ADDR) {
+   intel_gvt_hypervisor_write_gpa(vgpu,
+   hwsp_gpa + I915_HWS_CSB_BUF0_INDEX * 4 +
+   write_pointer * 8,
+   status, 8);
+   intel_gvt_hypervisor_write_gpa(vgpu,
+   hwsp_gpa +
+   intel_hws_csb_write_index(dev_priv) * 4,
+   _pointer, 4);
+   }
+   }
gvt_dbg_el("vgpu%d: w pointer %u reg %x csb l %x csb h %x\n",
vgpu->id, write_pointer, offset, status->ldw, status->udw);
 
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index f08d194..27e8186 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -189,6 +189,7 @@ struct intel_vgpu {
struct intel_vgpu_opregion opregion;
struct intel_vgpu_display display;
struct intel_vgpu_submission submission;
+   u32 hws_pga[I915_NUM_ENGINES];
 
struct dentry *debugfs;
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 8ef7db3..6313f0e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1380,6 +1380,49 @@ static int mailbox_write(struct intel_vgpu *vgpu, 
unsigned int offset,
return intel_vgpu_default_mmio_write(vgpu, offset, , bytes);
 }
 
+static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
+   void *p_data, unsigned int bytes)
+{
+   u32 value = *(u32 *)p_data;
+
+   if (!intel_gvt_ggtt_validate_range(vgpu, value, GTT_PAGE_SIZE)) {
+   gvt_vgpu_err("VM(%d) write invalid HWSP address, reg:0x%x, 
value:0x%x\n",
+ vgpu->id, offset, value);
+   return -EINVAL;
+   }
+   /*
+* Need to emulate all the HWSP register write to ensure host can
+* update the VM CSB status correctly. Here listed registers can
+* support BDW, SKL or other platforms with same HWSP registers.
+*/
+   switch (offset) {
+   case 0x2080:
+   vgpu->hws_pga[RCS] = value;
+   break;
+   case 0x12080:
+   vgpu->hws_pga[VCS] = value;
+   break;
+   case 0x1c080:
+   vgpu->hws_pga[VCS2] = value;
+   break;
+   case 0x1a080:
+   vgpu->hws_pga[VECS] = value;
+   break;
+   case 0x22080:
+   vgpu->hws_pga[BCS] = value;
+   break;
+   default:
+   gvt_vgpu_err("VM(%d) access unknown hardware status page 
register:0x%x\n",
+vgpu->id, offset);
+   return -EINVAL;
+

[Intel-gfx] [PATCH v3 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

[Weinan Li]

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.

v3 : Remove unnecessary comments.

Signed-off-by: Weinan Li 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_vgpu.c   | 5 +
 drivers/gpu/drm/i915/i915_vgpu.h   | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 8 
 drivers/gpu/drm/i915/intel_lrc.c   | 1 -
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5fe9f3f..6f713c5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -86,6 +86,11 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private 
*dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
 }
 
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
+{
+   return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
+}
+
 struct _balloon_info_ {
/*
 * There are up to 2 regions per mappable/unmappable graphic
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index b72bd29..cec0ec1 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -29,6 +29,7 @@
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
 
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 807a7aa..93478c2 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -23,6 +23,7 @@
  */
 
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
@@ -384,10 +385,6 @@ static void intel_engine_init_timeline(struct 
intel_engine_cs *engine)
 
 static bool csb_force_mmio(struct drm_i915_private *i915)
 {
-   /* GVT emulation depends upon intercepting CSB mmio */
-   if (intel_vgpu_active(i915))
-   return true;
-
/*
 * IOMMU adds unpredictable latency causing the CSB write (from the
 * GPU into the HWSP) to only be visible some time after the interrupt
@@ -396,6 +393,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
if (intel_vtd_active())
return true;
 
+   if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
+   return true;
+
return false;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 721432d..3c91971 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -793,7 +793,6 @@ static void intel_lrc_irq_handler(unsigned long data)
>status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
unsigned int head, tail;
 
-   /* However GVT emulation depends upon intercepting CSB mmio */
if (unlikely(execlists->csb_use_mmio)) {
buf = (u32 * __force)
(dev_priv->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/vblank: Fix flip event vblank count

[Patchwork]

== Series Details ==

Series: drm/vblank: Fix flip event vblank count
URL   : https://patchwork.freedesktop.org/series/31761/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2552 pass:1440 dwarn:0   dfail:0   fail:9   skip:1103 
time:9680s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5998/shards.html
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[Intel-gfx] linux-firmware pull request

[Srivatsa, Anusha]

Hi,

Please consider pulling i915 updates to linux-firmware.git

The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30:

  WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100)

are available in the git repository at:

  https://github.com/anushasr/linux-firmware.git master

for you to fetch changes up to 8e7c787fad2181eda916b570113fdd3c08c08436:

  linux-firmware/i915: Add Geminilake DMC version 1.04 (2017-10-11 17:05:52 
-0700)


Anusha Srivatsa (1):
  linux-firmware/i915: Add Geminilake DMC version 1.04

 WHENCE   |   3 +++
 i915/glk_dmc_ver1_04.bin | Bin 0 -> 8800 bytes
 2 files changed, 3 insertions(+)
 create mode 100644 i915/glk_dmc_ver1_04.bin


Thanks,
Anusha



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[Intel-gfx] linux-firmware pull request

[Srivatsa, Anusha]

Hi,

Please consider pulling i915 updates o linux-firmware.git.

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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_gt: Allow non-default contexts to hang non-render rings (rev4)

[Patchwork]

== Series Details ==

Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev4)
URL   : https://patchwork.freedesktop.org/series/31693/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don't close the 
timeline early in wait_snapshot

with latest DRM-Tip kernel build CI_DRM_3220
6a96415ec560 drm-tip: 2017y-10m-11d-19h-08m-29s UTC integration manifest

No testlist changes.

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:458s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:475s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:392s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:574s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:285s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:522s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:527s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:543s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:525s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:561s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:436s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:274s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:608s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:441s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:505s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:587s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:492s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:665s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:655s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:538s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:513s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:470s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:581s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:432s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_333/
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[Intel-gfx] [PATCH i-g-t v4] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Vinay Belgaumkar]

This limitation does not exist in latest kernel. It was removed by this patch-

commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding 
gens(Chris Wilson)
v4: Optimize the if block (Daniele)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
 lib/igt_gt.c | 44 ++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..555e4df 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -209,11 +209,51 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
 }
 
 /**
+ * has_ctx_exec:
+ * @fd: open i915 drm file descriptor
+ * @ring: execbuf ring flag
+ *
+ * This helper function checks if non default context submission is allowed
+ * on a ring.
+ *
+ * Returns:
+ * True if allowed
+ *
+ */
+bool has_ctx_exec(int fd, unsigned ring)
+{
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_exec_object2 exec;
+   bool supported;
+
+   /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+   if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
+   if (ring & (3 << 13) && !gem_has_bsd2(fd))
+   return false;
+   }
+
+   memset(, 0, sizeof(exec));
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.flags = ring;
+   execbuf.rsvd1 = gem_context_create(fd);
+   /* If context submission is not allowed, this will return EINVAL
+* Otherwise, this will return ENOENT on account of no gem obj
+* being submitted */
+   supported = __gem_execbuf(fd, ) == -ENOENT;
+   gem_context_destroy(fd, execbuf.rsvd1);
+
+   return supported;
+}
+
+/**
  * igt_hang_ring_ctx:
  * @fd: open i915 drm file descriptor
  * @ctx: the contxt specifier
  * @ring: execbuf ring flag
  * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
  *
  * This helper function injects a hanging batch associated with @ctx into 
@ring.
  * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +279,8 @@ igt_hang_t igt_hang_ctx(int fd,
 
igt_require_hang_ring(fd, ring);
 
-   /* One day the kernel ABI will be fixed! */
-   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   /* check if non-default ctx submission is allowed */
+   igt_require(ctx == 0 || (has_ctx_exec(fd, ring)));
 
param.context = ctx;
param.size = 0;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH i-g-t v3] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Belgaumkar, Vinay]

On 10/11/2017 4:23 PM, Daniele Ceraolo Spurio wrote:



On 11/10/17 14:31, Vinay Belgaumkar wrote:

This limitation does not exist in latest kernel. It was removed by
this patch-

commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding
gens(Chris Wilson)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
  lib/igt_gt.c | 47 +--
  1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..183d8bb 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -209,11 +209,51 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
  }
/**
+ * has_ctx_exec:
+ * @fd: open i915 drm file descriptor
+ * @ring: execbuf ring flag
+ *
+ * This helper function checks if non default context submission is
allowed
+ * on a ring.
+ *
+ * Returns:
+ * True if allowed
+ *
+ */
+bool has_ctx_exec(int fd, unsigned ring)
+{
+struct drm_i915_gem_execbuffer2 execbuf;
+struct drm_i915_gem_exec_object2 exec;
+bool supported;
+
+/* silly ABI, the kernel thinks everyone who has BSD also has
BSD2 */
+if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
+if (ring & (3 << 13) && !gem_has_bsd2(fd))
+return false;
+}
+
+memset(, 0, sizeof(exec));
+memset(, 0, sizeof(execbuf));
+execbuf.buffers_ptr = to_user_pointer();
+execbuf.buffer_count = 1;
+execbuf.flags = ring;
+execbuf.rsvd1 = gem_context_create(fd);
+/* If context submission is not allowed, this will return EINVAL
+ * Otherwise, this will return ENOENT on account of no gem obj
+ * being submitted */
+supported = __gem_execbuf(fd, ) == -ENOENT;
+gem_context_destroy(fd, execbuf.rsvd1);
+
+return supported;
+}
+
+/**
   * igt_hang_ring_ctx:
   * @fd: open i915 drm file descriptor
   * @ctx: the contxt specifier
   * @ring: execbuf ring flag
   * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
   *
   * This helper function injects a hanging batch associated with @ctx
into @ring.
   * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +279,11 @@ igt_hang_t igt_hang_ctx(int fd,
igt_require_hang_ring(fd, ring);
  -/* One day the kernel ABI will be fixed! */
-igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+/* check if non-default ctx submission is allowed */
+if (!(has_ctx_exec(fd, ring)))
+{
+igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+}



Wouldn't

igt_require(ctx == 0 || has_ctx_exec(fd, ring));

suffice here instead of the whole if block?

-Daniele


True, will make the change.




  param.context = ctx;
  param.size = 0;


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: Do not do link training fallback or prune modes on EDP

[Patchwork]

== Series Details ==

Series: drm/i915/edp: Do not do link training fallback or prune modes on EDP
URL   : https://patchwork.freedesktop.org/series/31776/
State : success

== Summary ==

Series 31776v1 drm/i915/edp: Do not do link training fallback or prune modes on 
EDP
https://patchwork.freedesktop.org/api/1.0/series/31776/revisions/1/mbox/

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_exec_parallel:
Subgroup basic:
pass   -> FAIL   (fi-ilk-650) fdo#101735
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)

fdo#101735 https://bugs.freedesktop.org/show_bug.cgi?id=101735
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:458s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:474s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:396s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:568s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:288s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:541s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:526s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:563s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:276s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:598s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:445s
fi-ilk-650   total:289  pass:227  dwarn:0   dfail:0   fail:1   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:508s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:584s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:491s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:665s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:470s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:659s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:532s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:568s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:471s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:594s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:431s

6a96415ec560527f41089b246c06e7fd75991791 drm-tip: 2017y-10m-11d-19h-08m-29s UTC 
integration manifest
cddc893fb88c drm/i915/edp: Do not do link training fallback or prune modes on 
EDP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6000/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane assert/readout cleanups etc.

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc.
URL   : https://patchwork.freedesktop.org/series/31758/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check:
pass   -> FAIL   (shard-hsw) fdo#100368

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-hswtotal:2552 pass:1439 dwarn:0   dfail:0   fail:10  skip:1103 
time:9644s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5997/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for Lib: Move __gem_context_create to common ioctl wrapper library.

[Patchwork]

== Series Details ==

Series: Lib: Move __gem_context_create to common ioctl wrapper library.
URL   : https://patchwork.freedesktop.org/series/31775/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don't close the 
timeline early in wait_snapshot

with latest DRM-Tip kernel build CI_DRM_3220
6a96415ec560 drm-tip: 2017y-10m-11d-19h-08m-29s UTC integration manifest

No testlist changes.

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:457s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:393s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:583s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:288s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:532s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:529s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:537s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:526s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:563s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:274s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:602s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:441s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:466s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:502s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:486s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:661s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:660s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:542s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:517s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:590s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:434s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_332/
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Re: [Intel-gfx] [PATCH i-g-t v3] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Daniele Ceraolo Spurio]

On 11/10/17 14:31, Vinay Belgaumkar wrote:

This limitation does not exist in latest kernel. It was removed by this patch-

commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding 
gens(Chris Wilson)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
  lib/igt_gt.c | 47 +--
  1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..183d8bb 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -209,11 +209,51 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
  }
  
  /**

+ * has_ctx_exec:
+ * @fd: open i915 drm file descriptor
+ * @ring: execbuf ring flag
+ *
+ * This helper function checks if non default context submission is allowed
+ * on a ring.
+ *
+ * Returns:
+ * True if allowed
+ *
+ */
+bool has_ctx_exec(int fd, unsigned ring)
+{
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_exec_object2 exec;
+   bool supported;
+
+   /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+   if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
+   if (ring & (3 << 13) && !gem_has_bsd2(fd))
+   return false;
+   }
+
+   memset(, 0, sizeof(exec));
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.flags = ring;
+   execbuf.rsvd1 = gem_context_create(fd);
+   /* If context submission is not allowed, this will return EINVAL
+* Otherwise, this will return ENOENT on account of no gem obj
+* being submitted */
+   supported = __gem_execbuf(fd, ) == -ENOENT;
+   gem_context_destroy(fd, execbuf.rsvd1);
+
+   return supported;
+}
+
+/**
   * igt_hang_ring_ctx:
   * @fd: open i915 drm file descriptor
   * @ctx: the contxt specifier
   * @ring: execbuf ring flag
   * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
   *
   * This helper function injects a hanging batch associated with @ctx into 
@ring.
   * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +279,11 @@ igt_hang_t igt_hang_ctx(int fd,
  
  	igt_require_hang_ring(fd, ring);
  
-	/* One day the kernel ABI will be fixed! */

-   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   /* check if non-default ctx submission is allowed */
+   if (!(has_ctx_exec(fd, ring)))
+   {
+   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   }
  


Wouldn't

igt_require(ctx == 0 || has_ctx_exec(fd, ring));

suffice here instead of the whole if block?

-Daniele


param.context = ctx;
param.size = 0;


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[Intel-gfx] [PATCH] drm/i915/edp: Do not do link training fallback or prune modes on EDP

[Manasi Navare]

In case of eDP because the panel has a fixed mode, the link rate
and lane count at which it is trained corresponds to the link BW
required to support the native resolution of the panel. In case of
panles with lower resolutions where fewer lanes are hooked up internally,
that number is reflected in the MAX_LANE_COUNT DPCD register of the panel.
So it is pointless to fallback to lower link rate/lane count in case
of link training failure on eDP connector since the lower link BW
will not support the native resolution of the panel and we cannot
prune the preferred mode on the eDP connector.

In case of Link training failure on the eDP panel, something is wrong
in the HW internally and hence driver errors out with a loud
and clear DRM_ERROR message.

Cc: Clinton Taylor 
Cc: Jim Bride 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Dave Airlie 
Cc: Daniel Vetter 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..bcccef1 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -328,14 +328,21 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
return;
 
  failure_handling:
-   DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = 
%d, lane count = %d",
- intel_connector->base.base.id,
- intel_connector->base.name,
- intel_dp->link_rate, intel_dp->lane_count);
-   if (!intel_dp_get_link_train_fallback_values(intel_dp,
-intel_dp->link_rate,
-intel_dp->lane_count))
-   /* Schedule a Hotplug Uevent to userspace to start modeset */
-   schedule_work(_connector->modeset_retry_work);
+   /* Dont fallback and prune modes if its eDP */
+   if (!intel_dp_is_edp(intel_dp)) {
+   DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link 
rate = %d, lane count = %d",
+ intel_connector->base.base.id,
+ intel_connector->base.name,
+ intel_dp->link_rate, intel_dp->lane_count);
+   if (!intel_dp_get_link_train_fallback_values(intel_dp,
+
intel_dp->link_rate,
+
intel_dp->lane_count))
+   /* Schedule a Hotplug Uevent to userspace to start 
modeset */
+   schedule_work(_connector->modeset_retry_work);
+   } else
+   DRM_ERROR("eDP [CONNECTOR:%d:%s] Link Training failed at link 
rate = %d, lane count = %d",
+ intel_connector->base.base.id,
+ intel_connector->base.name,
+ intel_dp->link_rate, intel_dp->lane_count);
return;
 }
-- 
2.1.4

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[Intel-gfx] [PATCH i-g-t] Lib: Move __gem_context_create to common ioctl wrapper library.

[Antonio Argenziano]

This patch adds a context creation ioctl wrapper that returns the error
for the caller to consume. Multiple tests that implemented this already,
have been changed to use the new library function.

Signed-off-by: Antonio Argenziano 
---
 benchmarks/gem_exec_ctx.c   | 16 
 benchmarks/gem_exec_trace.c |  9 +
 lib/ioctl_wrappers.c| 33 +++--
 lib/ioctl_wrappers.h|  1 +
 tests/gem_ctx_create.c  | 13 ++---
 tests/gem_ctx_switch.c  | 13 -
 tests/gem_eio.c | 13 +
 tests/gem_exec_await.c  | 14 ++
 tests/gem_exec_nop.c| 13 -
 tests/gem_exec_parallel.c   | 15 +++
 tests/gem_exec_reuse.c  | 13 -
 tests/gem_exec_whisper.c| 13 -
 12 files changed, 41 insertions(+), 125 deletions(-)

diff --git a/benchmarks/gem_exec_ctx.c b/benchmarks/gem_exec_ctx.c
index 0eac04b0..b41eb204 100644
--- a/benchmarks/gem_exec_ctx.c
+++ b/benchmarks/gem_exec_ctx.c
@@ -64,16 +64,6 @@ static uint32_t batch(int fd)
return handle;
 }
 
-static uint32_t __gem_context_create(int fd)
-{
-   struct drm_i915_gem_context_create create;
-
-   memset(, 0, sizeof(create));
-   drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, );
-
-   return create.ctx_id;
-}
-
 static int loop(unsigned ring,
int reps,
enum mode mode,
@@ -84,6 +74,7 @@ static int loop(unsigned ring,
struct drm_i915_gem_exec_object2 obj;
double *shared;
int fds[2], fd;
+   uint32_t ctx_id = 0;
 
shared = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 
@@ -101,7 +92,8 @@ static int loop(unsigned ring,
execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
if (mode != DEFAULT) {
-   execbuf.rsvd1 = __gem_context_create(fd);
+   __gem_context_create(fd, _id);
+   execbuf.rsvd1 = ctx_id;
if (execbuf.rsvd1 == 0)
return 77;
}
@@ -125,7 +117,7 @@ static int loop(unsigned ring,
uint32_t ctx = 0;
 
if (mode != DEFAULT && mode != NOP) {
-   execbuf.rsvd1 = __gem_context_create(fd);
+   execbuf.rsvd1 = gem_context_create(fd);
ctx = gem_context_create(fd);
}
 
diff --git a/benchmarks/gem_exec_trace.c b/benchmarks/gem_exec_trace.c
index 12577649..eebd6872 100644
--- a/benchmarks/gem_exec_trace.c
+++ b/benchmarks/gem_exec_trace.c
@@ -105,13 +105,6 @@ static double elapsed(const struct timespec *start, const 
struct timespec *end)
return 1e3*(end->tv_sec - start->tv_sec) + 1e-6*(end->tv_nsec - 
start->tv_nsec);
 }
 
-static uint32_t __gem_context_create(int fd)
-{
-   struct drm_i915_gem_context_create arg = {};
-   drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, );
-   return arg.ctx_id;
-}
-
 static double replay(const char *filename, long nop, long range)
 {
struct timespec t_start, t_end;
@@ -216,7 +209,7 @@ static double replay(const char *filename, long nop, long 
range)
num_ctx = new_ctx;
}
 
-   ctx[t->handle] = __gem_context_create(fd);
+   ctx[t->handle] = gem_context_create(fd);
break;
}
case DEL_CTX:
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 87511fc6..561e2bb7 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -894,6 +894,21 @@ int gem_madvise(int fd, uint32_t handle, int state)
return madv.retained;
 }
 
+int __gem_context_create(int fd, uint32_t *ctx_id)
+{
+   struct drm_i915_gem_context_create create;
+   int err = 0;
+
+   memset(, 0, sizeof(create));
+   if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, ) == 0)
+   *ctx_id = create.ctx_id;
+   else
+   err = -errno;
+
+   errno = 0;
+   return err;
+}
+
 /**
  * gem_context_create:
  * @fd: open i915 drm file descriptor
@@ -906,18 +921,16 @@ int gem_madvise(int fd, uint32_t handle, int state)
  */
 uint32_t gem_context_create(int fd)
 {
-   struct drm_i915_gem_context_create create;
+   uint32_t ctx_id;
+   int ret;
 
-   memset(, 0, sizeof(create));
-   if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, )) {
-   int err = -errno;
-   igt_skip_on(err == -ENODEV || errno == -EINVAL);
-   igt_assert_eq(err, 0);
-   }
-   igt_assert(create.ctx_id != 0);
-   errno = 0;
+   ret = __gem_context_create(fd, _id);
+
+   igt_skip_on(ret == -ENODEV || errno == -EINVAL);
+   igt_assert_eq(ret, 0);
+   igt_assert(ctx_id != 0);
 
-   return create.ctx_id;
+   return ctx_id;

Re: [Intel-gfx] [P v4 02/11] drm/i915/guc: Move GuC boot param initialization out of xfer

[Daniele Ceraolo Spurio]

On 10/10/17 07:51, Michal Wajdeczko wrote:

We want to keep ucode xfer functions separate from other
initialization. Once separated, add explicit forcewake.

Suggested-by: Joonas Lahtinen 
Signed-off-by: Michal Wajdeczko 
Cc: Joonas Lahtinen 
Cc: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/intel_guc.c| 88 +
  drivers/gpu/drm/i915/intel_guc.h|  1 +
  drivers/gpu/drm/i915/intel_guc_loader.c | 85 ---
  drivers/gpu/drm/i915/intel_uc.c |  1 +
  4 files changed, 90 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 90c3dd8..d75515c 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -67,6 +67,94 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->notify = gen8_guc_raise_irq;
  }
  
+static u32 get_gttype(struct drm_i915_private *dev_priv)

+{
+   /* XXX: GT type based on PCI device ID? field seems unused by fw */
+   return 0;
+}
+
+static u32 get_core_family(struct drm_i915_private *dev_priv)
+{
+   u32 gen = INTEL_GEN(dev_priv);
+
+   switch (gen) {
+   case 9:
+   return GUC_CORE_FAMILY_GEN9;
+
+   default:
+   MISSING_CASE(gen);
+   return GUC_CORE_FAMILY_UNKNOWN;
+   }
+}
+
+/*
+ * Initialise the GuC parameter block before starting the firmware
+ * transfer. These parameters are read by the firmware on startup
+ * and cannot be changed thereafter.
+ */
+void intel_guc_init_params(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   u32 params[GUC_CTL_MAX_DWORDS];
+   int i;
+
+   memset(, 0, sizeof(params));
+
+   params[GUC_CTL_DEVICE_INFO] |=
+   (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
+   (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
+
+   /*
+* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
+* second. This ARAR is calculated by:
+* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 10 / 10
+*/
+   params[GUC_CTL_ARAT_HIGH] = 0;
+   params[GUC_CTL_ARAT_LOW] = 1;
+
+   params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
+
+   params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
+   GUC_CTL_VCS2_ENABLED;
+
+   params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
+
+   if (i915_modparams.guc_log_level >= 0) {
+   params[GUC_CTL_DEBUG] =
+   i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
+   } else
+   params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
+
+   /* If GuC submission is enabled, set up additional parameters here */
+   if (i915_modparams.enable_guc_submission) {
+   u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
+   u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+   u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
+
+   params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
+   params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
+
+   pgs >>= PAGE_SHIFT;
+   params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
+   (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
+
+   params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
+
+   /* Unmask this bit to enable the GuC's internal scheduler */
+   params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
+   }
+
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);


I don't think we need this explicit forcewake if we use I915_WRITE(), 
because that should already wake the required wells. If you want to 
explicitly take forcewake then we can use I915_WRITE_FW(). Also, 
FORCEWAKE_BLITTER should be enough.
I'd also add a comment to say that the register are power context saved 
so it's ok to release forcewake here and take it again at xfer time.



+
+   I915_WRITE(SOFT_SCRATCH(0), 0);
+
+   for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
+   I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+}
+
  int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
  {
WARN(1, "Unexpected send: action=%#x\n", *action);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index aa9a7b5..8b44165 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -95,6 +95,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
  
  void intel_guc_init_early(struct intel_guc *guc);

  void intel_guc_init_send_regs(struct intel_guc *guc);
+void intel_guc_init_params(struct intel_guc *guc);
  int intel_guc_send_nop(struct intel_guc 

[Intel-gfx] ✗ Fi.CI.BAT: warning for lib/igt_gt: Allow non-default contexts to hang non-render rings (rev3)

[Patchwork]

== Series Details ==

Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev3)
URL   : https://patchwork.freedesktop.org/series/31693/
State : warning

== Summary ==

IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don't close the 
timeline early in wait_snapshot

with latest DRM-Tip kernel build CI_DRM_3220
6a96415ec560 drm-tip: 2017y-10m-11d-19h-08m-29s UTC integration manifest

No testlist changes.

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> SKIP   (fi-blb-e6850) fdo#101600 +1
pass   -> SKIP   (fi-elk-e7500)
pass   -> SKIP   (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:0   dfail:0   fail:0   skip:66  
time:376s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:580s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:287s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:522s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:523s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:539s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:520s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:564s
fi-elk-e7500 total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:413s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:282s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:597s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-ilk-650   total:289  pass:227  dwarn:0   dfail:0   fail:0   skip:62  
time:453s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:506s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:494s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-pnv-d510  total:289  pass:222  dwarn:0   dfail:0   fail:0   skip:67  
time:659s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:657s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:519s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:584s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:432s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_331/
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[Intel-gfx] [PATCH i-g-t v3] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Vinay Belgaumkar]

This limitation does not exist in latest kernel. It was removed by this patch-

commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding 
gens(Chris Wilson)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
 lib/igt_gt.c | 47 +--
 1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..183d8bb 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -209,11 +209,51 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
 }
 
 /**
+ * has_ctx_exec:
+ * @fd: open i915 drm file descriptor
+ * @ring: execbuf ring flag
+ *
+ * This helper function checks if non default context submission is allowed
+ * on a ring.
+ *
+ * Returns:
+ * True if allowed
+ *
+ */
+bool has_ctx_exec(int fd, unsigned ring)
+{
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_exec_object2 exec;
+   bool supported;
+
+   /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+   if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
+   if (ring & (3 << 13) && !gem_has_bsd2(fd))
+   return false;
+   }
+
+   memset(, 0, sizeof(exec));
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.flags = ring;
+   execbuf.rsvd1 = gem_context_create(fd);
+   /* If context submission is not allowed, this will return EINVAL
+* Otherwise, this will return ENOENT on account of no gem obj
+* being submitted */
+   supported = __gem_execbuf(fd, ) == -ENOENT;
+   gem_context_destroy(fd, execbuf.rsvd1);
+
+   return supported;
+}
+
+/**
  * igt_hang_ring_ctx:
  * @fd: open i915 drm file descriptor
  * @ctx: the contxt specifier
  * @ring: execbuf ring flag
  * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
  *
  * This helper function injects a hanging batch associated with @ctx into 
@ring.
  * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +279,11 @@ igt_hang_t igt_hang_ctx(int fd,
 
igt_require_hang_ring(fd, ring);
 
-   /* One day the kernel ABI will be fixed! */
-   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   /* check if non-default ctx submission is allowed */
+   if (!(has_ctx_exec(fd, ring)))
+   {
+   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   }
 
param.context = ctx;
param.size = 0;
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/userptr: Drop struct_mutex before cleanup

[Patchwork]

== Series Details ==

Series: drm/i915/userptr: Drop struct_mutex before cleanup
URL   : https://patchwork.freedesktop.org/series/31748/
State : warning

== Summary ==

Test pm_rpm:
Subgroup basic-rte:
pass   -> SKIP   (shard-hsw)
Subgroup universal-planes:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887

shard-hswtotal:2552 pass:1432 dwarn:5   dfail:0   fail:10  skip:1105 
time:9575s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5994/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for IGT PMU support (rev12)

[Patchwork]

== Series Details ==

Series: IGT PMU support (rev12)
URL   : https://patchwork.freedesktop.org/series/28253/
State : failure

== Summary ==

Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS   (shard-hsw) fdo#102886 +1
Test gem_tiled_swapping:
Subgroup non-threaded:
pass   -> DMESG-WARN (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_atomic:
Subgroup atomic_invalid_params:
pass   -> SKIP   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-indfb-fliptrack:
pass   -> SKIP   (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-C-64x64-bottom-edge:
pass   -> SKIP   (shard-hsw)
Test gem_flink_race:
Subgroup flink_close:
pass   -> FAIL   (shard-hsw) fdo#102655
Test gem_exec_store:
Subgroup pages-render:
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-rmfb:
pass   -> DMESG-WARN (shard-hsw)

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655

shard-hswtotal:2581 pass:1396 dwarn:7   dfail:0   fail:10  skip:1168 
time:9317s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_329/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for lib/igt_gt: Allow non-default contexts to hang non-render rings (rev2)

[Patchwork]

== Series Details ==

Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev2)
URL   : https://patchwork.freedesktop.org/series/31693/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don't close the 
timeline early in wait_snapshot

with latest DRM-Tip kernel build CI_DRM_3220
6a96415ec560 drm-tip: 2017y-10m-11d-19h-08m-29s UTC integration manifest

No testlist changes.

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_exec_reloc:
Subgroup basic-gtt-active:
pass   -> FAIL   (fi-gdg-551) fdo#102582 +4
Subgroup basic-write-cpu-active:
pass   -> FAIL   (fi-gdg-551)
Subgroup basic-write-gtt-active:
pass   -> FAIL   (fi-gdg-551)
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> SKIP   (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705

fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:463s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:470s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:393s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:567s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:285s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:526s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:522s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:540s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:532s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:570s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:438s
fi-gdg-551   total:289  pass:171  dwarn:1   dfail:0   fail:8   skip:109 
time:274s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:601s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:422s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:505s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:490s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:661s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:482s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:657s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:538s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:512s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:477s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:578s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:436s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_330/
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[Intel-gfx] ✓ Fi.CI.IGT: success for igt/prime_mmap_coherency: Only assert correct usage of sync API

[Patchwork]

== Series Details ==

Series: igt/prime_mmap_coherency: Only assert correct usage of sync API
URL   : https://patchwork.freedesktop.org/series/31729/
State : success

== Summary ==

Test gem_flink_race:
Subgroup flink_close:
pass   -> FAIL   (shard-hsw) fdo#102655

fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655

shard-hswtotal:2550 pass:1434 dwarn:5   dfail:0   fail:10  skip:1101 
time:9645s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_327/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use a cached mapping for the physical HWS (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Use a cached mapping for the physical HWS (rev3)
URL   : https://patchwork.freedesktop.org/series/24562/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_cursor_legacy:
Subgroup cursorA-vs-flipA-atomic-transitions:
pass   -> FAIL   (shard-hsw) fdo#102723

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102723 https://bugs.freedesktop.org/show_bug.cgi?id=102723

shard-hswtotal:2552 pass:1435 dwarn:5   dfail:0   fail:9   skip:1103 
time:9625s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5991/shards.html
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Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Split intel_enable_ddi() into DP and HDMI variants

[Jani Nikula]

On Tue, 10 Oct 2017, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Untangle intel_enable_ddi() by splitting it into DP and HDMI specific
> variants.
>
> v2: Keep using intel_ddi_get_encoder_port() for now
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 86 
> +++-
>  1 file changed, 49 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 49cf8d9d2bc1..18bf06c7e43f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2369,45 +2369,57 @@ void intel_ddi_fdi_post_disable(struct intel_encoder 
> *encoder,
>   I915_WRITE(FDI_RX_CTL(PIPE_A), val);
>  }
>  
> -static void intel_enable_ddi(struct intel_encoder *intel_encoder,
> -  const struct intel_crtc_state *pipe_config,
> +static void intel_enable_ddi_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> + enum port port = intel_ddi_get_encoder_port(encoder);
> +
> + if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
> + intel_dp_stop_link_train(intel_dp);
> +
> + intel_edp_backlight_on(crtc_state, conn_state);
> + intel_psr_enable(intel_dp, crtc_state);

This is broken without edp check.

BR,
Jani.


> + intel_edp_drrs_enable(intel_dp, crtc_state);
> +
> + if (crtc_state->has_audio)
> + intel_audio_codec_enable(encoder, crtc_state, conn_state);
> +}
> +
> +static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> +   const struct intel_crtc_state *crtc_state,
> +   const struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> + enum port port = intel_ddi_get_encoder_port(encoder);
> +
> + intel_hdmi_handle_sink_scrambling(encoder,
> +   conn_state->connector,
> +   
> crtc_state->hdmi_high_tmds_clock_ratio,
> +   crtc_state->hdmi_scrambling);
> +
> + /* In HDMI/DVI mode, the port width, and swing/emphasis values
> +  * are ignored so nothing special needs to be done besides
> +  * enabling the port.
> +  */
> + I915_WRITE(DDI_BUF_CTL(port),
> +dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
> +
> + if (crtc_state->has_audio)
> + intel_audio_codec_enable(encoder, crtc_state, conn_state);
> +}
> +
> +static void intel_enable_ddi(struct intel_encoder *encoder,
> +  const struct intel_crtc_state *crtc_state,
>const struct drm_connector_state *conn_state)
>  {
> - struct drm_encoder *encoder = _encoder->base;
> - struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
> - int type = intel_encoder->type;
> -
> - if (type == INTEL_OUTPUT_HDMI) {
> - struct intel_digital_port *intel_dig_port =
> - enc_to_dig_port(encoder);
> - bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
> - bool scrambling = pipe_config->hdmi_scrambling;
> -
> - intel_hdmi_handle_sink_scrambling(intel_encoder,
> -   conn_state->connector,
> -   clock_ratio, scrambling);
> -
> - /* In HDMI/DVI mode, the port width, and swing/emphasis values
> -  * are ignored so nothing special needs to be done besides
> -  * enabling the port.
> -  */
> - I915_WRITE(DDI_BUF_CTL(port),
> -intel_dig_port->saved_port_bits |
> -DDI_BUF_CTL_ENABLE);
> - } else if (type == INTEL_OUTPUT_EDP) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
> - intel_dp_stop_link_train(intel_dp);
> -
> - intel_edp_backlight_on(pipe_config, conn_state);
> - intel_psr_enable(intel_dp, pipe_config);
> - intel_edp_drrs_enable(intel_dp, pipe_config);
> - }
> -
> - if (pipe_config->has_audio)
> - intel_audio_codec_enable(intel_encoder, pipe_config, 
> conn_state);
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
> + 

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Split intel_disable_ddi() into DP vs. HDMI variants

[Jani Nikula]

On Tue, 10 Oct 2017, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Untangle intel_disable_ddi() by splitting it into DP and HDMI specific
> variants.
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 51 
> 
>  1 file changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 945980e71697..c930ef0338c5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2424,29 +2424,40 @@ static void intel_enable_ddi(struct intel_encoder 
> *intel_encoder,
>   intel_audio_codec_enable(intel_encoder, pipe_config, 
> conn_state);
>  }
>  
> -static void intel_disable_ddi(struct intel_encoder *intel_encoder,
> +static void intel_disable_ddi_dp(struct intel_encoder *encoder,
> +  const struct intel_crtc_state *old_crtc_state,
> +  const struct drm_connector_state 
> *old_conn_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> +
> + if (old_crtc_state->has_audio)
> + intel_audio_codec_disable(encoder);
> +

You remove the eDP check here, and...

> + intel_edp_drrs_disable(intel_dp, old_crtc_state);

...this will now depend on old_crtc_state->has_drrs which is probably
fine, but...

> + intel_psr_disable(intel_dp, old_crtc_state);

...but this will be wrong. I don't mind adding the edp check within.

> + intel_edp_backlight_off(old_conn_state);

This is ok.

I guess easiest would be to keep the type == INTEL_OUTPUT_EDP check and
clean up afterwards.

Otherwise LGTM.

BR,
Jani.



> +}
> +
> +static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
> +const struct intel_crtc_state 
> *old_crtc_state,
> +const struct drm_connector_state 
> *old_conn_state)
> +{
> + if (old_crtc_state->has_audio)
> + intel_audio_codec_disable(encoder);
> +
> + intel_hdmi_handle_sink_scrambling(encoder,
> +   old_conn_state->connector,
> +   false, false);
> +}
> +
> +static void intel_disable_ddi(struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state *old_conn_state)
>  {
> - struct drm_encoder *encoder = _encoder->base;
> - int type = intel_encoder->type;
> -
> - if (old_crtc_state->has_audio)
> - intel_audio_codec_disable(intel_encoder);
> -
> - if (type == INTEL_OUTPUT_HDMI) {
> - intel_hdmi_handle_sink_scrambling(intel_encoder,
> -   old_conn_state->connector,
> -   false, false);
> - }
> -
> - if (type == INTEL_OUTPUT_EDP) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - intel_edp_drrs_disable(intel_dp, old_crtc_state);
> - intel_psr_disable(intel_dp, old_crtc_state);
> - intel_edp_backlight_off(old_conn_state);
> - }
> + if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
> + intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
> + else
> + intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
>  }
>  
>  static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,

-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.BAT: warning for Refactor HW workaround code (rev2)

[Patchwork]

== Series Details ==

Series: Refactor HW workaround code (rev2)
URL   : https://patchwork.freedesktop.org/series/31611/
State : warning

== Summary ==

Series 31611v2 Refactor HW workaround code
https://patchwork.freedesktop.org/api/1.0/series/31611/revisions/2/mbox/

Test gem_close_race:
Subgroup basic-threads:
dmesg-warn -> PASS   (fi-snb-2520m)
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-blb-e6850) fdo#101600
Test gem_workarounds:
Subgroup basic-read:
pass   -> SKIP   (fi-bdw-5557u)
pass   -> SKIP   (fi-bdw-gvtdvm)
pass   -> SKIP   (fi-bsw-n3050)
pass   -> SKIP   (fi-skl-6260u)
pass   -> SKIP   (fi-skl-6700hq)
pass   -> SKIP   (fi-skl-6700k)
pass   -> SKIP   (fi-skl-6770hq)
pass   -> SKIP   (fi-skl-gvtdvm)
pass   -> SKIP   (fi-bxt-dsi)
pass   -> SKIP   (fi-bxt-j4205)
pass   -> SKIP   (fi-kbl-7500u)
pass   -> SKIP   (fi-kbl-7560u)
pass   -> SKIP   (fi-kbl-7567u)
pass   -> SKIP   (fi-kbl-r)
pass   -> SKIP   (fi-glk-1)
pass   -> SKIP   (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7567u)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-bsw-n3050)
Subgroup basic-no-display:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-bsw-n3050)
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-bdw-5557u)
pass   -> DMESG-WARN (fi-bdw-gvtdvm)
pass   -> DMESG-WARN (fi-bsw-n3050)
dmesg-warn -> INCOMPLETE (fi-cfl-s) fdo#103206

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#103206 https://bugs.freedesktop.org/show_bug.cgi?id=103206

fi-bdw-5557u total:289  pass:264  dwarn:3   dfail:0   fail:0   skip:22  
time:456s
fi-bdw-gvtdvmtotal:289  pass:261  dwarn:3   dfail:0   fail:0   skip:25  
time:465s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:392s
fi-bsw-n3050 total:289  pass:239  dwarn:3   dfail:0   fail:0   skip:47  
time:563s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:283s
fi-bxt-dsi   total:289  pass:258  dwarn:0   dfail:0   fail:0   skip:31  
time:519s
fi-bxt-j4205 total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:520s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:531s
fi-cfl-s total:288  pass:252  dwarn:3   dfail:0   fail:0   skip:32 
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:434s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:270s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:596s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:459s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:498s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:0   skip:25  
time:505s
fi-kbl-7560u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:580s
fi-kbl-7567u total:289  pass:264  dwarn:4   dfail:0   fail:0   skip:21  
time:494s
fi-kbl-r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:591s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:655s
fi-skl-6260u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:466s
fi-skl-6700hqtotal:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:653s
fi-skl-6700k total:289  pass:264  dwarn:0   dfail:0   fail:0   skip:25  
time:538s
fi-skl-6770hqtotal:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:515s
fi-skl-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:470s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:581s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:433s
fi-byt-n2820 failed to connect after reboot

6a96415ec560527f41089b246c06e7fd75991791 drm-tip: 2017y-10m-11d-19h-08m-29s UTC 
integration manifest
58a6a0a07fa3 drm/i915: Remove Gen9 WAs 

[Intel-gfx] [PULL] drm-misc-fixes

[Sean Paul]

Hi Dave,
Here's the latest from -misc-fixes. We have fixes for a reference leak, and a
race.

Following Jani's lead, I've setup dim to sign my pull requests. You can find my
public key at https://pgp.key-server.io/0x732C002572DCAF79


drm-misc-fixes-2017-10-11:
Core Changes:
- sync_file: Fix race in SYNC_IOC_FILE_INFO (John)
- atomic_helper: Give up reference taken in suspend helper (Jeffy)

Cc: John Einar Reitan 
Cc: Jeffy Chen 

Cheers, Sean


The following changes since commit 8a5776a5f49812d29fe4b2d0a2d71675c3facf3f:

  Linux 4.14-rc4 (2017-10-08 20:53:29 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2017-10-11

for you to fetch changes up to f7974880cf869ddbd0ba9a8e2ab11dff4a667f96:

  sync_file: Return consistent status in SYNC_IOC_FILE_INFO (2017-10-09 
13:09:19 -0300)


Core Changes:
- sync_file: Fix race in SYNC_IOC_FILE_INFO (John)
- atomic_helper: Give up reference taken in suspend helper (Jeffy)

Cc: John Einar Reitan 
Cc: Jeffy Chen 


Jeffy Chen (1):
  drm/atomic: Unref duplicated drm_atomic_state in 
drm_atomic_helper_resume()

John Einar Reitan (1):
  sync_file: Return consistent status in SYNC_IOC_FILE_INFO

 drivers/dma-buf/sync_file.c | 17 -
 drivers/gpu/drm/drm_atomic_helper.c |  1 +
 2 files changed, 13 insertions(+), 5 deletions(-)

-- 
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Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Extract intel_disable_ddi_buf()

[Jani Nikula]

On Tue, 10 Oct 2017, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Extract the code to disable the DDI_BUF_CTL into small helper. This
> will allows us to detangle the encoder type mess in
> intel_ddi_post_disable().
>
> v2: Keep using intel_ddi_get_encoder_port() for now
>
> Reviewed-by: Jani Nikula  #v1

Holds for v2

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 41 
> +++-
>  1 file changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 1cc61ba48e3a..e4d1d934231b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2257,17 +2257,37 @@ static void intel_ddi_pre_enable(struct intel_encoder 
> *encoder,
>   }
>  }
>  
> +static void intel_disable_ddi_buf(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum port port = intel_ddi_get_encoder_port(encoder);
> + bool wait = false;
> + u32 val;
> +
> + val = I915_READ(DDI_BUF_CTL(port));
> + if (val & DDI_BUF_CTL_ENABLE) {
> + val &= ~DDI_BUF_CTL_ENABLE;
> + I915_WRITE(DDI_BUF_CTL(port), val);
> + wait = true;
> + }
> +
> + val = I915_READ(DP_TP_CTL(port));
> + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(DP_TP_CTL(port), val);
> +
> + if (wait)
> + intel_wait_ddi_buf_idle(dev_priv, port);
> +}
> +
>  static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
>  const struct intel_crtc_state 
> *old_crtc_state,
>  const struct drm_connector_state 
> *old_conn_state)
>  {
>   struct drm_encoder *encoder = _encoder->base;
>   struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> - enum port port = intel_ddi_get_encoder_port(intel_encoder);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   int type = intel_encoder->type;
> - uint32_t val;
> - bool wait = false;
>  
>   if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
>   /*
> @@ -2286,20 +2306,7 @@ static void intel_ddi_post_disable(struct 
> intel_encoder *intel_encoder,
>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>   }
>  
> - val = I915_READ(DDI_BUF_CTL(port));
> - if (val & DDI_BUF_CTL_ENABLE) {
> - val &= ~DDI_BUF_CTL_ENABLE;
> - I915_WRITE(DDI_BUF_CTL(port), val);
> - wait = true;
> - }
> -
> - val = I915_READ(DP_TP_CTL(port));
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(DP_TP_CTL(port), val);
> -
> - if (wait)
> - intel_wait_ddi_buf_idle(dev_priv, port);
> + intel_disable_ddi_buf(intel_encoder);
>  
>   if (type == INTEL_OUTPUT_HDMI) {
>   dig_port->set_infoframes(encoder, false,

-- 
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Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Extract intel_ddi_clk_disable()

[Jani Nikula]

On Tue, 10 Oct 2017, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Pull the code to disable the port clock into a function. We already have
> the intel_ddi_clk_select() counterpart.
>
> v2: Keep using intel_ddi_get_encoder_port() for now (Chris)
>
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 24 
>  1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b307b6fe1ce3..1cc61ba48e3a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2141,6 +2141,21 @@ static void intel_ddi_clk_select(struct intel_encoder 
> *encoder,
>   }
>  }
>  
> +static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum port port = intel_ddi_get_encoder_port(encoder);
> +
> + if (IS_CANNONLAKE(dev_priv))
> + I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> +DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> + else if (IS_GEN9_BC(dev_priv))
> + I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
> +DPLL_CTRL2_DDI_CLK_OFF(port));
> + else if (INTEL_GEN(dev_priv) < 9)
> + I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> +}
> +
>  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>   int link_rate, uint32_t lane_count,
>   struct intel_shared_dpll *pll,
> @@ -2301,14 +2316,7 @@ static void intel_ddi_post_disable(struct 
> intel_encoder *intel_encoder,
>   if (dig_port)
>   intel_display_power_put(dev_priv, 
> dig_port->ddi_io_power_domain);
>  
> - if (IS_CANNONLAKE(dev_priv))
> - I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> -DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> - else if (IS_GEN9_BC(dev_priv))
> - I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> - DPLL_CTRL2_DDI_CLK_OFF(port)));
> - else if (INTEL_GEN(dev_priv) < 9)
> - I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> + intel_ddi_clk_disable(intel_encoder);
>  
>   if (type == INTEL_OUTPUT_HDMI) {
>   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

-- 
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Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Dump 'output_types' in crtc state dump

[Jani Nikula]

On Tue, 10 Oct 2017, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> To make it easier to debug things let's dump the output types bitmask in
> the crtc state dump. And to make life that much better, let's pretty
> print it as a a human reaadable string as well.
>
> v2: Have the caller pass in the buffer (Chris)
> #undef OUTPUT_TYPE (Jani)
>
> Cc: Chris Wilson 
> Cc: Jani Nikula 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 51 
> 
>  1 file changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 45d6e57fbe89..4938c23a3fc1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10674,6 +10674,52 @@ intel_dump_m_n_config(struct intel_crtc_state 
> *pipe_config, char *id,
> m_n->link_m, m_n->link_n, m_n->tu);
>  }
>  
> +#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> +
> +static const char * const output_type_str[] = {
> + OUTPUT_TYPE(UNUSED),
> + OUTPUT_TYPE(ANALOG),
> + OUTPUT_TYPE(DVO),
> + OUTPUT_TYPE(SDVO),
> + OUTPUT_TYPE(LVDS),
> + OUTPUT_TYPE(TVOUT),
> + OUTPUT_TYPE(HDMI),
> + OUTPUT_TYPE(DP),
> + OUTPUT_TYPE(EDP),
> + OUTPUT_TYPE(DSI),
> + OUTPUT_TYPE(UNKNOWN),
> + OUTPUT_TYPE(DP_MST),
> +};
> +
> +#undef OUTPUT_TYPE
> +
> +static void snprintf_output_types(char *buf, size_t len,
> +   unsigned int output_types)
> +{
> + char *str = buf;
> + int i;
> +
> + str[0] = '\0';
> +
> + for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
> + int r;
> +
> + if ((output_types & BIT(i)) == 0)
> + continue;
> +
> + r = snprintf(str, len, "%s%s",
> +  str != buf ? "," : "", output_type_str[i]);
> + if (r >= len)
> + break;
> + str += r;
> + len -= r;

Ugh, what a minefield this is, but AFAICT you avoided them all.

Reviewed-by: Jani Nikula 


> +
> + output_types &= ~BIT(i);
> + }
> +
> + WARN_ON_ONCE(output_types != 0);
> +}
> +
>  static void intel_dump_pipe_config(struct intel_crtc *crtc,
>  struct intel_crtc_state *pipe_config,
>  const char *context)
> @@ -10684,10 +10730,15 @@ static void intel_dump_pipe_config(struct 
> intel_crtc *crtc,
>   struct intel_plane *intel_plane;
>   struct intel_plane_state *state;
>   struct drm_framebuffer *fb;
> + char buf[64];
>  
>   DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
> crtc->base.base.id, crtc->base.name, context);
>  
> + snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> + DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
> +   buf, pipe_config->output_types);
> +
>   DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> transcoder_name(pipe_config->cpu_transcoder),
> pipe_config->pipe_bpp, pipe_config->dither);

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/dp: WARN about invalid/unknown link rates and bw codes

[Jani Nikula]

On Mon, 09 Oct 2017, Patchwork  wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/dp: WARN about invalid/unknown link 
> rates and bw codes
> URL   : https://patchwork.freedesktop.org/series/31579/
> State : failure
>
> == Summary ==
>
> Test kms_atomic_transition:
> Subgroup plane-all-transition-nonblocking:
> pass   -> FAIL   (shard-hsw) fdo#102671
> Test gem_wait:
> Subgroup write-wait-bsd:
> pass   -> SKIP   (shard-hsw)
> Test kms_frontbuffer_tracking:
> Subgroup psr-1p-primscrn-indfb-pgflip-blt:
> skip   -> INCOMPLETE (shard-hsw)

Pretty hard to see how this could be related to patches at hand. Pushed
2-3 to dinq, thanks for the review.

BR,
Jani.

>
> fdo#102671 https://bugs.freedesktop.org/show_bug.cgi?id=102671
>
> shard-hswtotal:2392 pass:1297 dwarn:6   dfail:0   fail:9   skip:1079 
> time:9699s
>
> == Logs ==
>
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5948/shards.html

-- 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/vblank: Fix flip event vblank count

[Patchwork]

== Series Details ==

Series: drm/vblank: Fix flip event vblank count
URL   : https://patchwork.freedesktop.org/series/31761/
State : success

== Summary ==

Series 31761v1 drm/vblank: Fix flip event vblank count
https://patchwork.freedesktop.org/api/1.0/series/31761/revisions/1/mbox/

Test drv_module_reload:
Subgroup basic-no-display:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#103206

fdo#103206 https://bugs.freedesktop.org/show_bug.cgi?id=103206

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:452s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:470s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:389s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:571s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:283s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:520s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:520s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:533s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:516s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:564s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:599s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:466s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:500s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:511s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:585s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:492s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:664s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:665s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:532s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:514s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:471s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:579s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:428s
fi-cnl-y failed to connect after reboot
fi-gdg-551 failed to connect after reboot

326dc1cd4339ecca36f58baf7ddec72f4d1fe0b7 drm-tip: 2017y-10m-11d-17h-34m-40s UTC 
integration manifest
840df9133ba2 drm/vblank: Fix flip event vblank count

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5998/
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Allow PCH platforms fall back to BIOS LVDS mode

[Ville Syrjälä]

On Wed, Oct 11, 2017 at 07:06:45PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-10-09 17:19:51)
> > From: Ville Syrjälä 
> > 
> > With intel_encoder_current_mode() using the normal state readout code it
> > actually works on PCH platforms as well. So let's nuke the PCH check from
> > intel_lvds_init(). I suppose there aren't any machines that actually
> > need this, but at least we get to eliminate a few lines of code, and one
> > FIXME.
> > 
> > Signed-off-by: Ville Syrjälä 
> 
> I have to admit the FIXME comment confused me utterly.

It does seem to be something not quite English.

> Having read the
> function, this should now work given the conversion of
> intel_encoder_current_mode() to use the common encoder->get_hw_state()
> routine.
> 
> Reviewed-by: Chris Wilson 

Thanks. Pushed this one as well.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 08/11] drm/i915: Print all workaround types correctly in debugfs

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:18)
> Let's try to make sure that all WAs are applied correctly and survive
> resumes, resets, etc... (with some help from a companion i-g-t patch).
> 
> Signed-off-by: Oscar Mateo 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 48 
> ++---
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f108f53..fb49eac 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3399,6 +3399,20 @@ static int i915_shared_dplls_info(struct seq_file *m, 
> void *unused)
> return 0;
>  }
>  
> +static void check_wa_register(struct seq_file *m, struct i915_wa_reg *wa_reg)
> +{
> +   struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +   u32 read;
> +   bool ok;
> +
> +   read = I915_READ(wa_reg->addr);
> +   ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask);
> +   seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: 
> %s\n",
> +  i915_mmio_reg_offset(wa_reg->addr),
> +  wa_reg->value, wa_reg->mask, read,
> +  ok ? "OK" : "FAIL");

So one thing I've been considering is adding the Wa name for easier
cross-referencing. I am just worried about the number of strings and
whether we should put those names anywhere near user visible output.
-Chris
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Re: [Intel-gfx] [PATCH v2] igt/gem_workarounds: Test all types of workarounds

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:40)
> Apart from context based workarounds, we can now also test for global
> MMIO and whitelisting ones.
> 
> Do take into account that this test does not guarantee that all known
> WAs for a given platform are applied. It only checks that the WAs the
> kernel does know about are correctly applied (e.g. they didn't get
> lost on a GPU reset or a suspend/resume).

Can we pass in a wa_regs.txt (manual control) instead of using
i915_wa_regs (regression testing)?

I want to record the wa_regs from the end of the series and confirm that
the registers have the same values at the beginning of the series. We
can't check if regs have disappeared in between, but that way we can do
a quick check they haven't changed value.
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Re: [Intel-gfx] [PATCH 04/11] drm/i915: Move workarounds from init_clock_gating

[Ville Syrjälä]

On Wed, Oct 11, 2017 at 11:15:14AM -0700, Oscar Mateo wrote:
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the name is confusing, it's a display function (even though some GT WAs
> also go here) and it isn't necessarily called on a GPU reset. This patch
> moves these WAs to their rightful place inside i915_workarounds.c.
> 
> TODO: Do we want to keep display WAs separated from GT ones? In that case,
> I would propose another category inside i915_workarounds.c (but I would need
> help deciding what goes where).

The current situation isn't very good. But neither really is moving
display stuff into something called gem_init_hw(). It also gets called
during GPU reset which is at the very least wasted effort when it comes
to display w/as, and could even be actively harmful in case we end up
clobbering something the current display configuration depends on.

> 
> v2:
>   - Also move bdw and chv WAs from init_clock_gating that do not seem to be
> actually related to clock gating.
>   - Rebased.
> 
> Signed-off-by: Oscar Mateo 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_pm.c  | 243 
> +--
>  drivers/gpu/drm/i915/intel_workarounds.c | 195 -
>  2 files changed, 202 insertions(+), 236 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2fcff97..024ee94 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -56,101 +56,6 @@
>  #define INTEL_RC6p_ENABLE(1<<1)
>  #define INTEL_RC6pp_ENABLE   (1<<2)
>  
> -static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> - if (HAS_LLC(dev_priv)) {
> - /*
> -  * WaCompressedResourceDisplayNewHashMode:skl,kbl
> -  * Display WA#0390: skl,kbl
> -  *
> -  * Must match Sampler, Pixel Back End, and Media. See
> -  * WaCompressedResourceSamplerPbeMediaNewHashMode.
> -  */
> - I915_WRITE(CHICKEN_PAR1_1,
> -I915_READ(CHICKEN_PAR1_1) |
> -SKL_DE_COMPRESSED_HASH_MODE);
> - }
> -
> - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> - I915_WRITE(CHICKEN_PAR1_1,
> -I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
> -
> - I915_WRITE(GEN8_CONFIG0,
> -I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
> -
> - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> - I915_WRITE(GEN8_CHICKEN_DCPR_1,
> -I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> -
> - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
> - /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
> - I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> -DISP_FBC_WM_DIS |
> -DISP_FBC_MEMORY_WAKE);
> -
> - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
> - I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> -ILK_DPFC_DISABLE_DUMMY0);
> -
> - if (IS_SKYLAKE(dev_priv)) {
> - /* WaDisableDopClockGating */
> - I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> -& ~GEN7_DOP_CLOCK_GATE_ENABLE);
> - }
> -}
> -
> -static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> - gen9_init_clock_gating(dev_priv);
> -
> - /* WaDisableSDEUnitClockGating:bxt */
> - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> -
> - /*
> -  * FIXME:
> -  * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> -  */
> - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> -
> - /*
> -  * Wa: Backlight PWM may stop in the asserted state, causing backlight
> -  * to stay fully on.
> -  */
> - I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> -PWM1_GATING_DIS | PWM2_GATING_DIS);
> -}
> -
> -static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> - gen9_init_clock_gating(dev_priv);
> -
> - /*
> -  * WaDisablePWMClockGating:glk
> -  * Backlight PWM may stop in the asserted state, causing backlight
> -  * to stay fully on.
> -  */
> - I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> -PWM1_GATING_DIS | PWM2_GATING_DIS);
> -
> - /* WaDDIIOTimeout:glk */
> - if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
> - u32 val = 

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Move workarounds from init_clock_gating

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:14)
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the name is confusing, it's a display function (even though some GT WAs
> also go here) and it isn't necessarily called on a GPU reset. This patch
> moves these WAs to their rightful place inside i915_workarounds.c.
> 
> TODO: Do we want to keep display WAs separated from GT ones? In that case,
> I would propose another category inside i915_workarounds.c (but I would need
> help deciding what goes where).
> 
> v2:
>   - Also move bdw and chv WAs from init_clock_gating that do not seem to be
> actually related to clock gating.
>   - Rebased.

Too much in one patch. Start with copy'n'paste, and then we can see
which w/a you select to move from init_clock_gating.
-Chris
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Re: [Intel-gfx] [PATCH 04/11] drm/i915: Move workarounds from init_clock_gating

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:14)
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the name is confusing, it's a display function (even though some GT WAs
> also go here) and it isn't necessarily called on a GPU reset. This patch
> moves these WAs to their rightful place inside i915_workarounds.c.

How dare you answer my question before I ask it!

s/i915_workarounds/intel_workarounds/
-Chris
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Re: [Intel-gfx] [PATCH 03/11] drm/i915: Split out functions for different kinds of workarounds

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:13)
> There are different kind of workarounds (those that modify registers that
> live in the context image, those that modify global registers, those that
> whitelist registers, etc...) and they have different requirements in terms
> of where they are applied and how. Also, by splitting them apart, it should
> be easier to decide where a new workaround should go.
> 
> v2:
>   - Add multiple MISSING_CASE
>   - Rebased
> 
> Signed-off-by: Oscar Mateo 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_gem.c  |   3 +
>  drivers/gpu/drm/i915/i915_gem_context.c  |   5 +
>  drivers/gpu/drm/i915/intel_lrc.c |  10 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c  |   4 +-
>  drivers/gpu/drm/i915/intel_workarounds.c | 698 
> +++
>  drivers/gpu/drm/i915/intel_workarounds.h |   8 +-
>  6 files changed, 444 insertions(+), 284 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index f76890b..119c456 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -35,6 +35,7 @@
>  #include "intel_drv.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_mocs.h"
> +#include "intel_workarounds.h"
>  #include "i915_gemfs.h"
>  #include 
>  #include 
> @@ -4804,6 +4805,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> }
> }
>  
> +   intel_mmio_workarounds_apply(dev_priv);

Hmm, we still have an overlap with intel_init_clock_gating(). Perusing
those there are several that deserve to be in intel_mmio_wa_apply
instead.

Are we happy with the split between "mmio_workarounds" and "clock_gating"?

So are we looking at intel_display_workarounds, intel_gt_workarounds and
intel_ctx_workarounds?
-Chris
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Re: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions

[Michal Wajdeczko]

On Wed, 11 Oct 2017 20:09:10 +0200, Sagar Arun Kamble  
 wrote:





On 10/11/2017 11:28 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble  
 wrote:





On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble  
 wrote:



i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggtt_disable_guc at the end of reset/suspend/unload is needed
post GGTT suspend operations. Calling it during uc_sanitize covers
all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these
needto be protected by struct_mutex. Hence struct_mutex locking is
added in i915_gem_sanitize while sanitizing uC. struct_mutex is  
already

held during i915_gem_reset_prepare.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 16 +++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index a4bbf6c..77a0746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private  
*dev_priv)

 WARN_ON(dev_priv->gt.awake);
mutex_lock(>struct_mutex);
+/* We need to notify the guc whenever we change the GGTT */
+if (i915_modparams.enable_guc_loading)
+i915_ggtt_enable_guc(dev_priv);
+
 i915_gem_restore_gtt_mappings(dev_priv);
 i915_gem_restore_fences(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 9010ab5..0b799fe 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

 guc_disable_communication(guc);
 gen9_reset_guc_interrupts(dev_priv);
-/* We need to notify the guc whenever we change the GGTT */
-i915_ggtt_enable_guc(dev_priv);
+/*
+ * We need to notify the guc whenever we change the GGTT.
+ * During resume from sleep we would have already updated the
+ * GGTT invalidate function for GuC during i915_gem_resume so
+ * we need to skip here. Will enable here on driver load/reset.
+ */
+if (!guc->suspended)
+i915_ggtt_enable_guc(dev_priv);
if (i915_modparams.enable_guc_submission) {
 /*
@@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private  
*dev_priv)

 guc_free_load_err_log(guc);
i915_guc_submission_cleanup(dev_priv);
-
-if (i915_modparams.enable_guc_loading)
-i915_ggtt_disable_guc(dev_priv);
 }
/**
@@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private  
*dev_priv)

 struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (i915_modparams.enable_guc_loading) {
+if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)


Hmm, isn't that check redundant ?

uc_sanitize can happen without firmware loaded too in which case we


If uc_sanitize can be loaded without firmware loaded, then I assume
i915_modparams.enable_guc_loading will be cleared too, right ?

I'm just wondering if we need to check both modparam and fw status.

actually load time uc_sanitize is happening before uc_sanitize_options


Hmm, so maybe we should call intel_sanitize_options() from or right after
i915_driver_init_early() ? It looks that all 'sanitize-options' are using
only device info flags, there is no MMIO access. Chris/Joonas?



so enable_guc_loading will have
non-zero value for some platforms. So  I think it makes sense to limit  
this to only load_status based.



don't want to ggtt_disable_guc.
if we want to ggtt_disable_guc then we should remove the GEM_BUG_ON in  
it.


Hmm, this is the way how we run CI tests ;)

yes ... from long time :)





+ i915_ggtt_disable_guc(dev_priv);
+
 guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 }


Btw, what should we do with "suspended" flag during sanitize ?

suspended flag is set to true on suspend and false on resume.
sanitize is done post suspend and before resume so we should not touch  
it.
initializing it to false during guc_init_early should take care of  
reload (during unload we are suspending gem but we wont resume)

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Re: [Intel-gfx] [PATCH v2] igt/gem_workarounds: Test all types of workarounds

[Chris Wilson]

Quoting Oscar Mateo (2017-10-11 19:15:40)
> @@ -241,39 +350,34 @@ igt_main
> }, *m;
>  
> igt_fixture {
> +   struct pci_device *pci_dev;
> FILE *file;
> -   char *line = NULL;
> -   size_t line_size;
> -   int i, fd;
> +   int fd;
>  
> device = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(device);
>  
> gen = intel_gen(intel_get_drm_devid(device));
>  
> +   pci_dev = intel_get_pci_device();
> +   igt_require(pci_dev);
> +
> +   intel_register_access_init(pci_dev, 0, device);

intel_register_access_init() takes i915-user-forcewake. Can we limit the
register access to just the mmio tests?
-Chris
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[Intel-gfx] [PATCH v2] igt/gem_workarounds: Test all types of workarounds

[Oscar Mateo]

Apart from context based workarounds, we can now also test for global
MMIO and whitelisting ones.

Do take into account that this test does not guarantee that all known
WAs for a given platform are applied. It only checks that the WAs the
kernel does know about are correctly applied (e.g. they didn't get
lost on a GPU reset or a suspend/resume).

v2:
  - Do not wait for the GPU unnecessarily (Chris)
  - Make a comment that this tests only looks for regressions (Chris)

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 tests/gem_workarounds.c | 185 ++--
 1 file changed, 147 insertions(+), 38 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 7b99961..69174d9 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -28,6 +28,7 @@
 #include "igt.h"
 
 #include 
+#include 
 
 #define PAGE_SIZE 4096
 #define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE)
@@ -62,8 +63,14 @@ static struct write_only_list {
 */
 };
 
-static struct intel_wa_reg *wa_regs;
-static int num_wa_regs;
+static struct intel_wa_reg *ctx_wa_regs;
+static int num_ctx_wa_regs;
+
+static struct intel_wa_reg *mmio_wa_regs;
+static int num_mmio_wa_regs;
+
+static struct intel_wa_reg *whitelist_wa_regs;
+static int num_whitelist_wa_regs;
 
 static bool write_only(const uint32_t addr)
 {
@@ -82,7 +89,7 @@ static bool write_only(const uint32_t addr)
 
 #define MI_STORE_REGISTER_MEM (0x24 << 23)
 
-static int workaround_fail_count(int fd, uint32_t ctx)
+static int ctx_workarounds_fail_count(int fd, uint32_t ctx)
 {
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_relocation_entry *reloc;
@@ -91,13 +98,16 @@ static int workaround_fail_count(int fd, uint32_t ctx)
uint32_t *base, *out;
int fail_count = 0;
 
-   reloc = calloc(num_wa_regs, sizeof(*reloc));
+   if (!num_ctx_wa_regs)
+   return 0;
+
+   reloc = calloc(num_ctx_wa_regs, sizeof(*reloc));
igt_assert(reloc);
 
-   result_sz = 4 * num_wa_regs;
+   result_sz = 4 * num_ctx_wa_regs;
result_sz = PAGE_ALIGN(result_sz);
 
-   batch_sz = 16 * num_wa_regs + 4;
+   batch_sz = 16 * num_ctx_wa_regs + 4;
batch_sz = PAGE_ALIGN(batch_sz);
 
memset(obj, 0, sizeof(obj));
@@ -105,12 +115,12 @@ static int workaround_fail_count(int fd, uint32_t ctx)
gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
obj[1].handle = gem_create(fd, batch_sz);
obj[1].relocs_ptr = to_user_pointer(reloc);
-   obj[1].relocation_count = num_wa_regs;
+   obj[1].relocation_count = num_ctx_wa_regs;
 
out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
-   for (int i = 0; i < num_wa_regs; i++) {
+   for (int i = 0; i < num_ctx_wa_regs; i++) {
*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
-   *out++ = wa_regs[i].addr;
+   *out++ = ctx_wa_regs[i].addr;
reloc[i].target_handle = obj[0].handle;
reloc[i].offset = (out - base) * sizeof(*out);
reloc[i].delta = i * sizeof(uint32_t);
@@ -134,20 +144,20 @@ static int workaround_fail_count(int fd, uint32_t ctx)
igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
 
out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
-   for (int i = 0; i < num_wa_regs; i++) {
+   for (int i = 0; i < num_ctx_wa_regs; i++) {
const bool ok =
-   (wa_regs[i].value & wa_regs[i].mask) ==
-   (out[i] & wa_regs[i].mask);
+   (ctx_wa_regs[i].value & ctx_wa_regs[i].mask) ==
+   (out[i] & ctx_wa_regs[i].mask);
char buf[80];
 
snprintf(buf, sizeof(buf),
 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
-wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
+ctx_wa_regs[i].addr, ctx_wa_regs[i].value, 
ctx_wa_regs[i].mask,
 out[i]);
 
if (ok) {
igt_debug("%s\tOK\n", buf);
-   } else if (write_only(wa_regs[i].addr)) {
+   } else if (write_only(ctx_wa_regs[i].addr)) {
igt_debug("%s\tIGNORED (w/o)\n", buf);
} else {
igt_warn("%s\tFAIL\n", buf);
@@ -163,6 +173,49 @@ static int workaround_fail_count(int fd, uint32_t ctx)
return fail_count;
 }
 
+static int mmio_workarounds_fail_count(struct intel_wa_reg *wa_regs, int 
num_wa_regs)
+{
+   int i, fail_count = 0;
+
+   if (!num_wa_regs)
+   return 0;
+
+   igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
+
+   for (i = 0; i < num_wa_regs; ++i) {
+   const uint32_t val = 

[Intel-gfx] [PATCH 08/11] drm/i915: Print all workaround types correctly in debugfs

[Oscar Mateo]

Let's try to make sure that all WAs are applied correctly and survive
resumes, resets, etc... (with some help from a companion i-g-t patch).

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 48 ++---
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index f108f53..fb49eac 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3399,6 +3399,20 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
return 0;
 }
 
+static void check_wa_register(struct seq_file *m, struct i915_wa_reg *wa_reg)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   u32 read;
+   bool ok;
+
+   read = I915_READ(wa_reg->addr);
+   ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask);
+   seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s\n",
+  i915_mmio_reg_offset(wa_reg->addr),
+  wa_reg->value, wa_reg->mask, read,
+  ok ? "OK" : "FAIL");
+}
+
 static int i915_wa_registers(struct seq_file *m, void *unused)
 {
int i;
@@ -3408,6 +3422,7 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
struct drm_device *dev = _priv->drm;
struct i915_workarounds *workarounds = _priv->workarounds;
enum intel_engine_id id;
+   u32 whitelist_wa_count = 0;
 
ret = mutex_lock_interruptible(>struct_mutex);
if (ret)
@@ -3416,22 +3431,27 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
intel_runtime_pm_get(dev_priv);
 
seq_printf(m, "Context workarounds applied: %d\n", 
workarounds->ctx_wa_count);
-   for_each_engine(engine, dev_priv, id)
-   seq_printf(m, "HW whitelist count for %s: %d\n",
-  engine->name, workarounds->whitelist_wa_count[id]);
for (i = 0; i < workarounds->ctx_wa_count; ++i) {
-   i915_reg_t addr;
-   u32 mask, value, read;
-   bool ok;
-
-   addr = workarounds->ctx_wa_reg[i].addr;
-   mask = workarounds->ctx_wa_reg[i].mask;
-   value = workarounds->ctx_wa_reg[i].value;
-   read = I915_READ(addr);
-   ok = (value & mask) == (read & mask);
-   seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, 
status: %s\n",
-  i915_mmio_reg_offset(addr), value, mask, read, ok ? 
"OK" : "FAIL");
+   struct i915_wa_reg *wa_reg = >ctx_wa_reg[i];
+
+   seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x\n",
+  i915_mmio_reg_offset(wa_reg->addr),
+  wa_reg->value, wa_reg->mask);
}
+   seq_putc(m, '\n');
+
+   seq_printf(m, "MMIO workarounds applied: %d\n", 
workarounds->mmio_wa_count);
+   for (i = 0; i < workarounds->mmio_wa_count; ++i)
+   check_wa_register(m, >mmio_wa_reg[i]);
+   seq_putc(m, '\n');
+
+   for_each_engine(engine, dev_priv, id)
+   whitelist_wa_count += workarounds->whitelist_wa_count[id];
+   seq_printf(m, "Whitelist workarounds applied: %d\n", 
whitelist_wa_count);
+   for_each_engine(engine, dev_priv, id)
+   for (i = 0; i < workarounds->whitelist_wa_count[id]; ++i)
+   check_wa_register(m, 
>whitelist_wa_reg[id][i]);
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
-- 
1.9.1

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[Intel-gfx] [PATCH 05/11] drm/i915: Rename saved workarounds to make it explicit that they are context WAs

[Oscar Mateo]

Some WAs touch registers that get saved/restored together with the logical 
context.
Make this very explicit by renaming a few things in the code.

v2:
  - Improved naming
  - Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  10 +-
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 230 +++
 3 files changed, 123 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0bb6e01..1eb6e58 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3415,18 +3415,18 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
 
intel_runtime_pm_get(dev_priv);
 
-   seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
+   seq_printf(m, "Context workarounds applied: %d\n", 
workarounds->ctx_wa_count);
for_each_engine(engine, dev_priv, id)
seq_printf(m, "HW whitelist count for %s: %d\n",
   engine->name, workarounds->hw_whitelist_count[id]);
-   for (i = 0; i < workarounds->count; ++i) {
+   for (i = 0; i < workarounds->ctx_wa_count; ++i) {
i915_reg_t addr;
u32 mask, value, read;
bool ok;
 
-   addr = workarounds->reg[i].addr;
-   mask = workarounds->reg[i].mask;
-   value = workarounds->reg[i].value;
+   addr = workarounds->ctx_wa_reg[i].addr;
+   mask = workarounds->ctx_wa_reg[i].mask;
+   value = workarounds->ctx_wa_reg[i].value;
read = I915_READ(addr);
ok = (value & mask) == (read & mask);
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, 
status: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5f3999..a528b0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1963,8 +1963,9 @@ struct i915_wa_reg {
 #define I915_MAX_WA_REGS 16
 
 struct i915_workarounds {
-   struct i915_wa_reg reg[I915_MAX_WA_REGS];
-   u32 count;
+   struct i915_wa_reg ctx_wa_reg[I915_MAX_WA_REGS];
+   u32 ctx_wa_count;
+
u32 hw_whitelist_count[I915_NUM_ENGINES];
 };
 
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index bc144c2..c7d2bf9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -25,49 +25,49 @@
 #include "i915_drv.h"
 #include "intel_workarounds.h"
 
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static int ctx_wa_add(struct drm_i915_private *dev_priv,
+ i915_reg_t addr,
+ const u32 mask, const u32 val)
 {
-   const u32 idx = dev_priv->workarounds.count;
+   const u32 idx = dev_priv->workarounds.ctx_wa_count;
 
if (WARN_ON(idx >= I915_MAX_WA_REGS))
return -ENOSPC;
 
-   dev_priv->workarounds.reg[idx].addr = addr;
-   dev_priv->workarounds.reg[idx].value = val;
-   dev_priv->workarounds.reg[idx].mask = mask;
+   dev_priv->workarounds.ctx_wa_reg[idx].addr = addr;
+   dev_priv->workarounds.ctx_wa_reg[idx].value = val;
+   dev_priv->workarounds.ctx_wa_reg[idx].mask = mask;
 
-   dev_priv->workarounds.count++;
+   dev_priv->workarounds.ctx_wa_count++;
 
return 0;
 }
 
-#define WA_REG(addr, mask, val) do { \
-   const int r = wa_add(dev_priv, (addr), (mask), (val)); \
+#define CTX_WA_REG(addr, mask, val) do { \
+   const int r = ctx_wa_add(dev_priv, (addr), (mask), (val)); \
if (r) \
return r; \
} while (0)
 
-#define WA_SET_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+#define CTX_WA_SET_BIT_MASKED(addr, mask) \
+   CTX_WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 
-#define WA_CLR_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+#define CTX_WA_CLR_BIT_MASKED(addr, mask) \
+   CTX_WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
-   WA_REG(addr, mask, _MASKED_FIELD(mask, value))
+#define CTX_WA_SET_FIELD_MASKED(addr, mask, value) \
+   CTX_WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 
 static int gen8_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 {
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+   CTX_WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 
/* WaDisableAsyncFlipPerfMode:bdw,chv */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+   CTX_WA_SET_BIT_MASKED(MI_MODE, 

[Intel-gfx] [PATCH 10/11] drm/i915: Document the i915_workarounds file

[Oscar Mateo]

Does what it says on the tin (plus a few fixes in some old comments).

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 45 +++-
 1 file changed, 38 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 8cdb934..5dcbfea 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -25,6 +25,36 @@
 #include "i915_drv.h"
 #include "intel_workarounds.h"
 
+/**
+ * DOC: Hardware workarounds
+ *
+ * This file is a central place to implement most* of the required workarounds
+ * required for HW to work as originally intended. They fall in four categories
+ * depending on how/when they are applied:
+ *
+ * - Workarounds that touch registers that are saved/restored to/from the HW
+ *   context image. The list is generated once and then emitted (via Load
+ *   Register Immediate commands) everytime a new context is created.
+ * - Workarounds that touch global MMIO registers. The list of these WAs is
+ *   generated once and then applied whenever these registers revert to default
+ *   values (on GPU reset, suspend/resume**, etc..).
+ * - Workarounds that whitelist a privileged register, so that UMDs can manage
+ *   them directly. This is just a special case of a MMMIO workaround (as we
+ *   write the list of these to/be-whitelisted registers to some special HW
+ *   registers).
+ * - Workaround batchbuffers, that get executed automatically by the hardware
+ *   on every HW context restore.
+ *
+ * * Please notice that there are other WAs that, due to their nature, cannot 
be
+ *   applied from a central place. Those are peppered around the rest of the
+ *   code, as needed).
+ *
+ * ** Technically, some registers are powercontext saved & restored, so they
+ *survive a suspend/resume. In practice, writing them again is not too
+ *costly and simplifies things. We can revisit this in the future.
+ *
+ */
+
 static int ctx_wa_add(struct drm_i915_private *dev_priv,
  i915_reg_t addr,
  const u32 mask, const u32 val)
@@ -190,9 +220,9 @@ static int gen9_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
CTX_WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
  GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
-* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be 
set
-* but we do that in per ctx batchbuffer as there is an issue
-* with this register not getting restored on ctx restore
+* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be
+* set but we do that in per ctx batchbuffer as there is an
+* issue with this register not getting restored on ctx restore.
 */
}
 
@@ -1086,10 +1116,11 @@ void intel_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
  * but there is a slight complication as this is applied in WA batch where the
  * values are only initialized once so we cannot take register value at the
  * beginning and reuse it further; hence we save its value to memory, upload a
- * constant value with bit21 set and then we restore it back with the saved 
value.
+ * constant value with bit21 set and then we restore it back with the saved
+ * value.
  * To simplify the WA, a constant value is formed by using the default value
  * of this register. This shouldn't be a problem because we are only modifying
- * it for a short period and this batch in non-premptible. We can ofcourse
+ * it for a short period and this batch in non-premptible. We can of course
  * use additional instructions that read the actual value of the register
  * at that time and set our bit of interest but it makes the WA complicated.
  *
@@ -1125,8 +1156,8 @@ void intel_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
  * Typically we only have one indirect_ctx and per_ctx batch buffer which are
  * initialized at the beginning and shared across all contexts but this field
  * helps us to have multiple batches at different offsets and select them based
- * on a criteria. At the moment this batch always start at the beginning of 
the page
- * and at this point we don't have multiple wa_ctx batch buffers.
+ * on a criteria. At the moment this batch always start at the beginning of the
+ * page and at this point we don't have multiple wa_ctx batch buffers.
  *
  * The number of WA applied are not known at the beginning; we use this field
  * to return the no of DWORDS written.
-- 
1.9.1

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[Intel-gfx] [PATCH 06/11] drm/i915: Save all MMIO WAs and apply them at a later time

[Oscar Mateo]

By doing this, we can dump these workarounds in debugfs for validation (which,
at the moment, we are only able to do for the contexts WAs).

v2:
  - Wrong macro used for MMIO set bit masked
  - Improved naming
  - Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.c  |   5 +
 drivers/gpu/drm/i915/i915_drv.h  |   8 +-
 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 382 +--
 drivers/gpu/drm/i915/intel_workarounds.h |   1 +
 5 files changed, 223 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f1e6517..6e9a0da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "i915_vgpu.h"
+#include "intel_workarounds.h"
 #include "intel_drv.h"
 #include "intel_uc.h"
 
@@ -886,6 +887,10 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);
device_info->gen_mask = BIT(device_info->gen - 1);
 
+   ret = intel_mmio_workarounds_init(dev_priv);
+   if (ret < 0)
+   return ret;
+
spin_lock_init(_priv->irq_lock);
spin_lock_init(_priv->gpu_error.lock);
mutex_init(_priv->backlight_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a528b0b..11e8658 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1960,12 +1960,16 @@ struct i915_wa_reg {
u32 mask;
 };
 
-#define I915_MAX_WA_REGS 16
+#define I915_MAX_CTX_WA_REGS 16
+#define I915_MAX_MMIO_WA_REGS 32
 
 struct i915_workarounds {
-   struct i915_wa_reg ctx_wa_reg[I915_MAX_WA_REGS];
+   struct i915_wa_reg ctx_wa_reg[I915_MAX_CTX_WA_REGS];
u32 ctx_wa_count;
 
+   struct i915_wa_reg mmio_wa_reg[I915_MAX_MMIO_WA_REGS];
+   u32 mmio_wa_count;
+
u32 hw_whitelist_count[I915_NUM_ENGINES];
 };
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d0a83..5858f5f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7041,6 +7041,7 @@ enum {
  */
 #define  L3_GENERAL_PRIO_CREDITS(x)(((x) >> 1) << 19)
 #define  L3_HIGH_PRIO_CREDITS(x)   (((x) >> 1) << 14)
+#define  L3_PRIO_CREDITS_MASK  (0x1f << 19) | (0x1f << 14)
 
 #define GEN7_L3CNTLREG1_MMIO(0xB01C)
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL   0x3C47FF8C
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index c7d2bf9..95a9b75 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -31,7 +31,7 @@ static int ctx_wa_add(struct drm_i915_private *dev_priv,
 {
const u32 idx = dev_priv->workarounds.ctx_wa_count;
 
-   if (WARN_ON(idx >= I915_MAX_WA_REGS))
+   if (WARN_ON(idx >= I915_MAX_CTX_WA_REGS))
return -ENOSPC;
 
dev_priv->workarounds.ctx_wa_reg[idx].addr = addr;
@@ -513,64 +513,97 @@ int intel_ctx_workarounds_emit(struct 
drm_i915_gem_request *req)
return 0;
 }
 
-static void bdw_mmio_workarounds_apply(struct drm_i915_private *dev_priv)
+static int mmio_wa_add(struct drm_i915_private *dev_priv,
+  i915_reg_t addr,
+  const u32 mask, const u32 val)
+{
+   const u32 idx = dev_priv->workarounds.mmio_wa_count;
+
+   if (WARN_ON(idx >= I915_MAX_MMIO_WA_REGS))
+   return -ENOSPC;
+
+   dev_priv->workarounds.mmio_wa_reg[idx].addr = addr;
+   dev_priv->workarounds.mmio_wa_reg[idx].value = val;
+   dev_priv->workarounds.mmio_wa_reg[idx].mask = mask;
+
+   dev_priv->workarounds.mmio_wa_count++;
+
+   return 0;
+}
+
+#define MMIO_WA_REG(addr, mask, val) do { \
+   const int r = mmio_wa_add(dev_priv, (addr), (mask), (val)); \
+   if (r) \
+   return r; \
+   } while (0)
+
+#define MMIO_WA_SET_BIT(addr, mask) \
+   MMIO_WA_REG(addr, (mask), (mask))
+
+#define MMIO_WA_SET_BIT_MASKED(addr, mask) \
+   MMIO_WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+
+#define MMIO_WA_CLR_BIT(addr, mask) \
+   MMIO_WA_REG(addr, (mask), 0)
+
+#define MMIO_WA_SET_FIELD(addr, mask, value) \
+   MMIO_WA_REG(addr, (mask), (value))
+
+static int bdw_mmio_workarounds_init(struct drm_i915_private *dev_priv)
 {
/* The GTT cache must be disabled if the system is using 2M pages. */
-   bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-I915_GTT_PAGE_SIZE_2M);
+   bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, 

[Intel-gfx] [PATCH 07/11] drm/i915: Save all Whitelist WAs and apply them at a later time

[Oscar Mateo]

Same as we have been doing for other types, this allow us to dump
the whole list of workarounds to debugs, for validation purposes.

v2:
  - Improved naming
  - Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |   2 +-
 drivers/gpu/drm/i915/i915_drv.h  |   3 +-
 drivers/gpu/drm/i915/intel_lrc.c |   8 ++-
 drivers/gpu/drm/i915/intel_workarounds.c | 113 ---
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +-
 5 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1eb6e58..f108f53 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3418,7 +3418,7 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
seq_printf(m, "Context workarounds applied: %d\n", 
workarounds->ctx_wa_count);
for_each_engine(engine, dev_priv, id)
seq_printf(m, "HW whitelist count for %s: %d\n",
-  engine->name, workarounds->hw_whitelist_count[id]);
+  engine->name, workarounds->whitelist_wa_count[id]);
for (i = 0; i < workarounds->ctx_wa_count; ++i) {
i915_reg_t addr;
u32 mask, value, read;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11e8658..f1349b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1970,7 +1970,8 @@ struct i915_workarounds {
struct i915_wa_reg mmio_wa_reg[I915_MAX_MMIO_WA_REGS];
u32 mmio_wa_count;
 
-   u32 hw_whitelist_count[I915_NUM_ENGINES];
+   struct i915_wa_reg 
whitelist_wa_reg[I915_NUM_ENGINES][RING_MAX_NONPRIV_SLOTS];
+   u32 whitelist_wa_count[I915_NUM_ENGINES];
 };
 
 struct i915_virtual_gpu {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e632a29..f3d4602 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1499,9 +1499,7 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   ret = intel_whitelist_workarounds_apply(engine);
-   if (ret)
-   return ret;
+   intel_whitelist_workarounds_apply(engine);
 
return 0;
 }
@@ -1988,6 +1986,10 @@ int logical_render_ring_init(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   ret = intel_whitelist_workarounds_init(engine);
+   if (ret)
+   return ret;
+
ret = intel_init_workaround_bb(engine);
if (ret) {
/*
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 95a9b75..8375c29 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -921,64 +921,64 @@ void intel_mmio_workarounds_apply(struct drm_i915_private 
*dev_priv)
}
 }
 
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
+static int whitelist_wa_add(struct intel_engine_cs *engine,
+   i915_reg_t reg)
 {
struct drm_i915_private *dev_priv = engine->i915;
struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
+   const uint32_t index = wa->whitelist_wa_count[engine->id];
 
if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
return -EINVAL;
 
-   I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
-  i915_mmio_reg_offset(reg));
-   wa->hw_whitelist_count[engine->id]++;
+   wa->whitelist_wa_reg[engine->id][index].addr =
+   RING_FORCE_TO_NONPRIV(engine->mmio_base, index);
+   wa->whitelist_wa_reg[engine->id][index].value = 
i915_mmio_reg_offset(reg);
+   wa->whitelist_wa_reg[engine->id][index].mask = 0x;
+
+   wa->whitelist_wa_count[engine->id]++;
 
return 0;
 }
 
-static int gen9_whitelist_workarounds_apply(struct intel_engine_cs *engine)
-{
-   int ret;
+#define WHITELIST_WA_REG(engine, reg) do { \
+   const int r = whitelist_wa_add(engine, reg); \
+   if (r) \
+   return r; \
+} while (0)
 
+static int gen9_whitelist_workarounds_init(struct intel_engine_cs *engine)
+{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
-   ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
-   if (ret)
-   return ret;
+   WHITELIST_WA_REG(engine, GEN9_CTX_PREEMPT_REG);
 
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
-   ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
-   if (ret)
-   return ret;
+   WHITELIST_WA_REG(engine, 

[Intel-gfx] [PATCH 01/11] drm/i915: No need for RING_MAX_NONPRIV_SLOTS space

[Oscar Mateo]

Now that we write RING_FORCE_TO_NONPRIV registers directly to hardware,
[commit 32ced39 ("drm/i915: Transform whitelisting WAs into a simple reg
write")] there is no need to save space for them in the list of context
workarounds.

v2: Refer to previous commit in commit message (Michel)

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Reviewed-by: Michel Thierry 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6bbc4b8..a5f3999 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1960,13 +1960,7 @@ struct i915_wa_reg {
u32 mask;
 };
 
-/*
- * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
- * allowing it for RCS as we don't foresee any requirement of having
- * a whitelist for other engines. When it is really required for
- * other engines then the limit need to be increased.
- */
-#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
+#define I915_MAX_WA_REGS 16
 
 struct i915_workarounds {
struct i915_wa_reg reg[I915_MAX_WA_REGS];
-- 
1.9.1

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[Intel-gfx] [PATCH 04/11] drm/i915: Move workarounds from init_clock_gating

[Oscar Mateo]

I'm not sure why some WAs have historically been applied in init_clock_gating
and some others in the engine setup (GT vs. display? context vs. global
registers?) but it does not look like the best place to apply workarounds:
the name is confusing, it's a display function (even though some GT WAs
also go here) and it isn't necessarily called on a GPU reset. This patch
moves these WAs to their rightful place inside i915_workarounds.c.

TODO: Do we want to keep display WAs separated from GT ones? In that case,
I would propose another category inside i915_workarounds.c (but I would need
help deciding what goes where).

v2:
  - Also move bdw and chv WAs from init_clock_gating that do not seem to be
actually related to clock gating.
  - Rebased.

Signed-off-by: Oscar Mateo 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_pm.c  | 243 +--
 drivers/gpu/drm/i915/intel_workarounds.c | 195 -
 2 files changed, 202 insertions(+), 236 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2fcff97..024ee94 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -56,101 +56,6 @@
 #define INTEL_RC6p_ENABLE  (1<<1)
 #define INTEL_RC6pp_ENABLE (1<<2)
 
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   if (HAS_LLC(dev_priv)) {
-   /*
-* WaCompressedResourceDisplayNewHashMode:skl,kbl
-* Display WA#0390: skl,kbl
-*
-* Must match Sampler, Pixel Back End, and Media. See
-* WaCompressedResourceSamplerPbeMediaNewHashMode.
-*/
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) |
-  SKL_DE_COMPRESSED_HASH_MODE);
-   }
-
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-   I915_WRITE(CHICKEN_PAR1_1,
-  I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
-
-   I915_WRITE(GEN8_CONFIG0,
-  I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
-
-   /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(GEN8_CHICKEN_DCPR_1,
-  I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
-   /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
-   /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
-   I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-  DISP_FBC_WM_DIS |
-  DISP_FBC_MEMORY_WAKE);
-
-   /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
-   I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-  ILK_DPFC_DISABLE_DUMMY0);
-
-   if (IS_SKYLAKE(dev_priv)) {
-   /* WaDisableDopClockGating */
-   I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
-  & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-   }
-}
-
-static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   gen9_init_clock_gating(dev_priv);
-
-   /* WaDisableSDEUnitClockGating:bxt */
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
-   /*
-* FIXME:
-* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
-*/
-   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
-
-   /*
-* Wa: Backlight PWM may stop in the asserted state, causing backlight
-* to stay fully on.
-*/
-   I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
-  PWM1_GATING_DIS | PWM2_GATING_DIS);
-}
-
-static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-   u32 val;
-   gen9_init_clock_gating(dev_priv);
-
-   /*
-* WaDisablePWMClockGating:glk
-* Backlight PWM may stop in the asserted state, causing backlight
-* to stay fully on.
-*/
-   I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
-  PWM1_GATING_DIS | PWM2_GATING_DIS);
-
-   /* WaDDIIOTimeout:glk */
-   if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
-   u32 val = I915_READ(CHICKEN_MISC_2);
-   val &= ~(GLK_CL0_PWR_DOWN |
-GLK_CL1_PWR_DOWN |
-GLK_CL2_PWR_DOWN);
-   I915_WRITE(CHICKEN_MISC_2, val);
-   }
-
-   /* Display WA #1133: WaFbcSkipSegments:glk */
-   val = I915_READ(ILK_DPFC_CHICKEN);
-   val &= ~GLK_SKIP_SEG_COUNT_MASK;
-   val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
-   I915_WRITE(ILK_DPFC_CHICKEN, val);
-}
-
 static void i915_pineview_get_mem_freq(struct drm_i915_private 

[Intel-gfx] [PATCH 09/11] drm/i915: Move WA BB stuff to the workarounds file as well

[Oscar Mateo]

Since we are trying to put all WA stuff together, do not forget about the BB 
WAs.

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 253 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 254 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 3 files changed, 259 insertions(+), 251 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f3d4602..0ba8f1b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1166,255 +1166,6 @@ static int execlists_request_alloc(struct 
drm_i915_gem_request *request)
return 0;
 }
 
-/*
- * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
- * PIPE_CONTROL instruction. This is required for the flush to happen correctly
- * but there is a slight complication as this is applied in WA batch where the
- * values are only initialized once so we cannot take register value at the
- * beginning and reuse it further; hence we save its value to memory, upload a
- * constant value with bit21 set and then we restore it back with the saved 
value.
- * To simplify the WA, a constant value is formed by using the default value
- * of this register. This shouldn't be a problem because we are only modifying
- * it for a short period and this batch in non-premptible. We can ofcourse
- * use additional instructions that read the actual value of the register
- * at that time and set our bit of interest but it makes the WA complicated.
- *
- * This WA is also required for Gen9 so extracting as a function avoids
- * code duplication.
- */
-static u32 *
-gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
-{
-   *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = i915_ggtt_offset(engine->scratch) + 256;
-   *batch++ = 0;
-
-   *batch++ = MI_LOAD_REGISTER_IMM(1);
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = 0x4040 | GEN8_LQSC_FLUSH_COHERENT_LINES;
-
-   batch = gen8_emit_pipe_control(batch,
-  PIPE_CONTROL_CS_STALL |
-  PIPE_CONTROL_DC_FLUSH_ENABLE,
-  0);
-
-   *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
-   *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
-   *batch++ = i915_ggtt_offset(engine->scratch) + 256;
-   *batch++ = 0;
-
-   return batch;
-}
-
-/*
- * Typically we only have one indirect_ctx and per_ctx batch buffer which are
- * initialized at the beginning and shared across all contexts but this field
- * helps us to have multiple batches at different offsets and select them based
- * on a criteria. At the moment this batch always start at the beginning of 
the page
- * and at this point we don't have multiple wa_ctx batch buffers.
- *
- * The number of WA applied are not known at the beginning; we use this field
- * to return the no of DWORDS written.
- *
- * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
- * so it adds NOOPs as padding to make it cacheline aligned.
- * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
- * makes a complete batch buffer.
- */
-static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 
*batch)
-{
-   /* WaDisableCtxRestoreArbitration:bdw,chv */
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-
-   /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
-   if (IS_BROADWELL(engine->i915))
-   batch = gen8_emit_flush_coherentl3_wa(engine, batch);
-
-   /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
-   /* Actual scratch location is at 128 bytes offset */
-   batch = gen8_emit_pipe_control(batch,
-  PIPE_CONTROL_FLUSH_L3 |
-  PIPE_CONTROL_GLOBAL_GTT_IVB |
-  PIPE_CONTROL_CS_STALL |
-  PIPE_CONTROL_QW_WRITE,
-  i915_ggtt_offset(engine->scratch) +
-  2 * CACHELINE_BYTES);
-
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-
-   /* Pad to end of cacheline */
-   while ((unsigned long)batch % CACHELINE_BYTES)
-   *batch++ = MI_NOOP;
-
-   /*
-* MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
-* execution depends on the length specified in terms of cache lines
-* in the register CTX_RCS_INDIRECT_CTX
-*/
-
-   return batch;
-}
-
-static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 
*batch)
-{
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-
-   /* 

[Intel-gfx] [PATCH v2 00/11] Refactor HW workaround code

[Oscar Mateo]

I didn't receive any major opposition to the RFC, so I am sending the patches
again with some review comments from Chris, a typo fix and some aesthetic
improvements.

Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost under certain circumstances
(e.g. a context switch or a GPU reset). This is a proposal to attempt to
eliminate some of this pain, by clarifying the current classification of
workarounds (context saved/restored, global registers, whitelisting, BB),
putting them together on the same file, and improving the existing validation
infrastructure (debugfs/i-g-t).

Oscar Mateo (11):
  drm/i915: No need for RING_MAX_NONPRIV_SLOTS space
  drm/i915: Move a bunch of workaround-related code to its own file
  drm/i915: Split out functions for different kinds of workarounds
  drm/i915: Move workarounds from init_clock_gating
  drm/i915: Rename saved workarounds to make it explicit that they are
context WAs
  drm/i915: Save all MMIO WAs and apply them at a later time
  drm/i915: Save all Whitelist WAs and apply them at a later time
  drm/i915: Print all workaround types correctly in debugfs
  drm/i915: Move WA BB stuff to the workarounds file as well
  drm/i915: Document the i915_workarounds file
  drm/i915: Remove Gen9 WAs with no effect

 drivers/gpu/drm/i915/Makefile|3 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |   52 +-
 drivers/gpu/drm/i915/i915_drv.c  |5 +
 drivers/gpu/drm/i915/i915_drv.h  |   20 +-
 drivers/gpu/drm/i915/i915_gem.c  |3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |5 +
 drivers/gpu/drm/i915/i915_reg.h  |4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   |  679 ---
 drivers/gpu/drm/i915/intel_lrc.c |  266 +-
 drivers/gpu/drm/i915/intel_pm.c  |  243 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |5 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |3 -
 drivers/gpu/drm/i915/intel_workarounds.c | 1364 ++
 drivers/gpu/drm/i915/intel_workarounds.h |   40 +
 14 files changed, 1489 insertions(+), 1203 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h

-- 
1.9.1

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[Intel-gfx] [PATCH 11/11] drm/i915: Remove Gen9 WAs with no effect

[Oscar Mateo]

GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
the BIOS, so there is no way we can enable the three chicken bits
mandated by the WA (the BIOS should be doing it instead).

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 ---
 drivers/gpu/drm/i915/intel_workarounds.c | 2 --
 2 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5858f5f..02c66f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -355,9 +355,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ECOCHK_PPGTT_WT_HSW  (0x2<<3)
 #define   ECOCHK_PPGTT_WB_HSW  (0x3<<3)
 
-#define GEN8_CONFIG0   _MMIO(0xD00)
-#define  GEN9_DEFAULT_FIXES(1 << 3 | 1 << 2 | 1 << 1)
-
 #define GAC_ECO_BITS   _MMIO(0x14090)
 #define   ECOBITS_SNB_BIT  (1<<13)
 #define   ECOBITS_PPGTT_CACHE64B   (3<<8)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5dcbfea..df47fad 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -656,8 +656,6 @@ static int gen9_mmio_workarounds_init(struct 
drm_i915_private *dev_priv)
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
MMIO_WA_SET_BIT(CHICKEN_PAR1_1, SKL_EDP_PSR_FIX_RDWRAP);
 
-   MMIO_WA_SET_BIT(GEN8_CONFIG0, GEN9_DEFAULT_FIXES);
-
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
MMIO_WA_SET_BIT(GEN8_CHICKEN_DCPR_1, MASK_WAKEMEM);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 03/11] drm/i915: Split out functions for different kinds of workarounds

[Oscar Mateo]

There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
be easier to decide where a new workaround should go.

v2:
  - Add multiple MISSING_CASE
  - Rebased

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c  |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c  |   5 +
 drivers/gpu/drm/i915/intel_lrc.c |  10 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   4 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 698 +++
 drivers/gpu/drm/i915/intel_workarounds.h |   8 +-
 6 files changed, 444 insertions(+), 284 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f76890b..119c456 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
 #include "intel_mocs.h"
+#include "intel_workarounds.h"
 #include "i915_gemfs.h"
 #include 
 #include 
@@ -4804,6 +4805,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
 
+   intel_mmio_workarounds_apply(dev_priv);
+
i915_gem_init_swizzling(dev_priv);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..cf104cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_workarounds.h"
 
 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
 
@@ -454,6 +455,10 @@ int i915_gem_contexts_init(struct drm_i915_private 
*dev_priv)
 
GEM_BUG_ON(dev_priv->kernel_context);
 
+   err = intel_ctx_workarounds_init(dev_priv);
+   if (err)
+   goto err;
+
INIT_LIST_HEAD(_priv->contexts.list);
INIT_WORK(_priv->contexts.free_work, contexts_free_worker);
init_llist_head(_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 495ade6..e632a29 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1488,7 +1488,7 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
 
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1499,7 +1499,11 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   return init_workarounds_ring(engine);
+   ret = intel_whitelist_workarounds_apply(engine);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void reset_common_ring(struct intel_engine_cs *engine,
@@ -1827,7 +1831,7 @@ static int gen8_init_rcs_context(struct 
drm_i915_gem_request *req)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(req);
+   ret = intel_ctx_workarounds_emit(req);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7e5d7d3..c3f8961 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -647,7 +647,7 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request 
*req)
 {
int ret;
 
-   ret = intel_ring_workarounds_emit(req);
+   ret = intel_ctx_workarounds_emit(req);
if (ret != 0)
return ret;
 
@@ -706,7 +706,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (INTEL_INFO(dev_priv)->gen >= 6)
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
-   return init_workarounds_ring(engine);
+   return 0;
 }
 
 static void render_ring_cleanup(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a4ea80f..ae66084 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -58,27 +58,8 @@ static int wa_add(struct drm_i915_private *dev_priv,
 #define WA_SET_FIELD_MASKED(addr, mask, value) \
WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
-
-   if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
-   return 

[Intel-gfx] [PATCH 02/11] drm/i915: Move a bunch of workaround-related code to its own file

[Oscar Mateo]

This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.

v2: Use intel_ prefix for code that deals with the hardware (Chris)

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/Makefile|   3 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   | 679 -
 drivers/gpu/drm/i915/intel_lrc.c |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c  |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   3 -
 drivers/gpu/drm/i915/intel_workarounds.c | 705 +++
 drivers/gpu/drm/i915/intel_workarounds.h |  31 ++
 7 files changed, 740 insertions(+), 683 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
 create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 66d23b6..3162a14 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -22,7 +22,8 @@ i915-y := i915_drv.o \
  intel_csr.o \
  intel_device_info.o \
  intel_pm.o \
- intel_runtime_pm.o
+ intel_runtime_pm.o \
+ intel_workarounds.o
 
 i915-$(CONFIG_COMPAT)   += i915_ioc32.o
 i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a59b2a3..0b806f2 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -817,685 +817,6 @@ void intel_engine_get_instdone(struct intel_engine_cs 
*engine,
}
 }
 
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
-{
-   const u32 idx = dev_priv->workarounds.count;
-
-   if (WARN_ON(idx >= I915_MAX_WA_REGS))
-   return -ENOSPC;
-
-   dev_priv->workarounds.reg[idx].addr = addr;
-   dev_priv->workarounds.reg[idx].value = val;
-   dev_priv->workarounds.reg[idx].mask = mask;
-
-   dev_priv->workarounds.count++;
-
-   return 0;
-}
-
-#define WA_REG(addr, mask, val) do { \
-   const int r = wa_add(dev_priv, (addr), (mask), (val)); \
-   if (r) \
-   return r; \
-   } while (0)
-
-#define WA_SET_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
-
-#define WA_CLR_BIT_MASKED(addr, mask) \
-   WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
-
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
-   WA_REG(addr, mask, _MASKED_FIELD(mask, value))
-
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-   struct i915_workarounds *wa = _priv->workarounds;
-   const uint32_t index = wa->hw_whitelist_count[engine->id];
-
-   if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
-   return -EINVAL;
-
-   I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
-  i915_mmio_reg_offset(reg));
-   wa->hw_whitelist_count[engine->id]++;
-
-   return 0;
-}
-
-static int gen8_init_workarounds(struct intel_engine_cs *engine)
-{
-   struct drm_i915_private *dev_priv = engine->i915;
-
-   WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
-   /* WaDisableAsyncFlipPerfMode:bdw,chv */
-   WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
-   /* WaDisablePartialInstShootdown:bdw,chv */
-   WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
-
-   /* Use Force Non-Coherent whenever executing a 3D context. This is a
-* workaround for for a possible hang in the unlikely event a TLB
-* invalidation occurs during a PSD flush.
-*/
-   /* WaForceEnableNonCoherent:bdw,chv */
-   /* WaHdcDisableFetchWhenMasked:bdw,chv */
-   WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_DONOT_FETCH_MEM_WHEN_MASKED |
- HDC_FORCE_NON_COHERENT);
-
-   /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
-* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
-*  polygons in the same 8x4 pixel/sample area to be processed without
-*  stalling waiting for the earlier ones to write to Hierarchical Z
-*  buffer."
-*
-* This optimization is off by default for BDW and CHV; turn it on.
-*/
-   WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
-   /* Wa4x4STCOptimizationDisable:bdw,chv */
-   WA_SET_BIT_MASKED(CACHE_MODE_1, 

Re: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions

[Sagar Arun Kamble]

On 10/11/2017 11:28 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble 
 wrote:





On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble 
 wrote:



i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggtt_disable_guc at the end of reset/suspend/unload is needed
post GGTT suspend operations. Calling it during uc_sanitize covers
all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these
needto be protected by struct_mutex. Hence struct_mutex locking is
added in i915_gem_sanitize while sanitizing uC. struct_mutex is 
already

held during i915_gem_reset_prepare.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 16 +++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index a4bbf6c..77a0746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private 
*dev_priv)

 WARN_ON(dev_priv->gt.awake);
    mutex_lock(>struct_mutex);
+    /* We need to notify the guc whenever we change the GGTT */
+    if (i915_modparams.enable_guc_loading)
+    i915_ggtt_enable_guc(dev_priv);
+
 i915_gem_restore_gtt_mappings(dev_priv);
 i915_gem_restore_fences(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 9010ab5..0b799fe 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)

 guc_disable_communication(guc);
 gen9_reset_guc_interrupts(dev_priv);
-    /* We need to notify the guc whenever we change the GGTT */
-    i915_ggtt_enable_guc(dev_priv);
+    /*
+ * We need to notify the guc whenever we change the GGTT.
+ * During resume from sleep we would have already updated the
+ * GGTT invalidate function for GuC during i915_gem_resume so
+ * we need to skip here. Will enable here on driver load/reset.
+ */
+    if (!guc->suspended)
+    i915_ggtt_enable_guc(dev_priv);
    if (i915_modparams.enable_guc_submission) {
 /*
@@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private 
*dev_priv)

 guc_free_load_err_log(guc);
    i915_guc_submission_cleanup(dev_priv);
-
-    if (i915_modparams.enable_guc_loading)
-    i915_ggtt_disable_guc(dev_priv);
 }
/**
@@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private 
*dev_priv)

 struct intel_uc_fw *huc_fw = _priv->huc.fw;
    if (i915_modparams.enable_guc_loading) {
+    if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)


Hmm, isn't that check redundant ?

uc_sanitize can happen without firmware loaded too in which case we


If uc_sanitize can be loaded without firmware loaded, then I assume
i915_modparams.enable_guc_loading will be cleared too, right ?

I'm just wondering if we need to check both modparam and fw status.
actually load time uc_sanitize is happening before uc_sanitize_options 
so enable_guc_loading will have
non-zero value for some platforms. So  I think it makes sense to limit 
this to only load_status based.



don't want to ggtt_disable_guc.
if we want to ggtt_disable_guc then we should remove the GEM_BUG_ON 
in it.


Hmm, this is the way how we run CI tests ;)

yes ... from long time :)





+ i915_ggtt_disable_guc(dev_priv);
+
 guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 }


Btw, what should we do with "suspended" flag during sanitize ?

suspended flag is set to true on suspend and false on resume.
sanitize is done post suspend and before resume so we should not 
touch it.
initializing it to false during guc_init_early should take care of 
reload (during unload we are suspending gem but we wont resume)


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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Allow PCH platforms fall back to BIOS LVDS mode

[Chris Wilson]

Quoting Ville Syrjala (2017-10-09 17:19:51)
> From: Ville Syrjälä 
> 
> With intel_encoder_current_mode() using the normal state readout code it
> actually works on PCH platforms as well. So let's nuke the PCH check from
> intel_lvds_init(). I suppose there aren't any machines that actually
> need this, but at least we get to eliminate a few lines of code, and one
> FIXME.
> 
> Signed-off-by: Ville Syrjälä 

I have to admit the FIXME comment confused me utterly. Having read the
function, this should now work given the conversion of
intel_encoder_current_mode() to use the common encoder->get_hw_state()
routine.

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PULL] drm-intel-next

[Jani Nikula]

Hi Dave, more v4.15 features.

Our tooling now supports signed tags, this one is probably the
first. Maybe we can make them mandatory in the long run.

drm-intel-next-2017-09-29:
2nd batch of v4.15 features:

- lib/scatterlist updates, use for userptr allocations (Tvrtko)
- Fixed point wrapper cleanup (Mahesh)
- Gen9+ transition watermarks, watermark optimization and fixes (Mahesh)
- Display IPC (Isochronous Priority Control) support (Mahesh)
- GEM workaround fixes (Oscar)
- GVT: PCI config sanitize series (Changbin)
- GVT: Workload submission error handling series (Fred)
- PSR fixes and refactoring (Rodrigo)
- HWSP based optimizations (Chris)
- Private PAT management (Zhi)
- IRQ handling fixes and refactoring (Ville)
- Module parameter refactoring and variable name clash fix (Michal)
- Execlist refactoring, incomplete request unwinding on reset (Chris)
- GuC scheduling improvements (Michal)
- OA updates (Lionel)
- Coffeelake out of alpha support (Rodrigo)
- seqno fixes (Chris)
- Execlist refactoring (Mika)
- DP and DP MST cleanups (Dhinakaran)
- Cannonlake slice/sublice config (Ben)
- Numerous fixes all around (Everyone)

BR,
Jani.

The following changes since commit 754270c7c56292e97d0eff924a5d5d83f92add07:

  Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux 
into drm-next (2017-09-28 08:37:02 +1000)

are available in the git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2017-09-29

for you to fetch changes up to e18063e88bd579c479a2b45820be6c4625f841c3:

  drm/i915: Update DRIVER_DATE to 20170929 (2017-09-29 13:50:38 +0300)


2nd batch of v4.15 features:

- lib/scatterlist updates, use for userptr allocations (Tvrtko)
- Fixed point wrapper cleanup (Mahesh)
- Gen9+ transition watermarks, watermark optimization and fixes (Mahesh)
- Display IPC (Isochronous Priority Control) support (Mahesh)
- GEM workaround fixes (Oscar)
- GVT: PCI config sanitize series (Changbin)
- GVT: Workload submission error handling series (Fred)
- PSR fixes and refactoring (Rodrigo)
- HWSP based optimizations (Chris)
- Private PAT management (Zhi)
- IRQ handling fixes and refactoring (Ville)
- Module parameter refactoring and variable name clash fix (Michal)
- Execlist refactoring, incomplete request unwinding on reset (Chris)
- GuC scheduling improvements (Michal)
- OA updates (Lionel)
- Coffeelake out of alpha support (Rodrigo)
- seqno fixes (Chris)
- Execlist refactoring (Mika)
- DP and DP MST cleanups (Dhinakaran)
- Cannonlake slice/sublice config (Ben)
- Numerous fixes all around (Everyone)


Anuj Phogat (1):
  drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5

Ben Widawsky (1):
  drm/i915/cnl: Add support slice/subslice/eu configs

Changbin Du (4):
  drm/i915/kvmgt: Sanitize PCI bar emulation
  drm/i915/gvt: Add emulation for BAR2 (aperture) with normal file RW 
approach
  drm/i915/gvt: Fix incorrect PCI BARs reporting
  drm/i915/gvt: Add support for PCIe extended configuration space

Chris Wilson (33):
  drm/i915: Disable snooping (userptr, set-cache-level) on gen4
  drm/i915: Disable mmio debugging during user access
  drm/i915: Apply the GTT write flush for all !llc machines
  drm/i915: Only initialize partially filled pagetables
  drm/i915: Cleanup error paths through eb_lookup_vma()
  drm/i915: Move the context descriptor to an inline helper
  drm/i915: Squelch smatch warning for statement with no effect
  drm/i915: Use mul_u32_u32() for 32b x 32b -> 64b result
  drm/i915/selftests: Use mul_u32_u32() for 32b x 32b -> 64b result
  drm/i915: Allow HW status page to be bound high
  drm/i915/execlists: Read the context-status buffer from the HWSP
  drm/i915/execlists: Read the context-status HEAD from the HWSP
  drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos()
  drm/i915: Mark the userptr invalidate workqueue as WQ_MEM_RECLAIM
  drm/i915: Cancel all ready but queued requests when wedging
  drm/i915/execlists: Kick start request processing after a reset
  drm/i915/execlists: Move insert_request()
  drm/i915/execlists: Split insert_request()
  drm/i915/execlists: Unwind incomplete requests on resets
  drm/i915/selftests: Disable iommu for the mock device
  drm/i915/selftests: Only touch archdata.iommu when it exists
  drm/i915/fence: Avoid del_timer_sync() from inside a timer
  drm/i915: Document the split in internal and public execbuf flags
  drm/i915: Only wake the waiter from the interrupt if passed
  drm/i915: Check waiter->seqno carefully in case of preemption
  drm/i915: Confirm request->global_seqno after spin completion
  drm/i915: Make i915_spin_request() static
  drm/i915/lrc: Only enable per-context and per-bb buffers if set
  drm/i915/lrc: Skip no-op per-bb buffer on 

Re: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions

[Michal Wajdeczko]

On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble  
 wrote:





On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble  
 wrote:



i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggtt_disable_guc at the end of reset/suspend/unload is needed
post GGTT suspend operations. Calling it during uc_sanitize covers
all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these
needto be protected by struct_mutex. Hence struct_mutex locking is
added in i915_gem_sanitize while sanitizing uC. struct_mutex is already
held during i915_gem_reset_prepare.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 16 +++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index a4bbf6c..77a0746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private  
*dev_priv)

 WARN_ON(dev_priv->gt.awake);
mutex_lock(>struct_mutex);
+/* We need to notify the guc whenever we change the GGTT */
+if (i915_modparams.enable_guc_loading)
+i915_ggtt_enable_guc(dev_priv);
+
 i915_gem_restore_gtt_mappings(dev_priv);
 i915_gem_restore_fences(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 9010ab5..0b799fe 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

 guc_disable_communication(guc);
 gen9_reset_guc_interrupts(dev_priv);
-/* We need to notify the guc whenever we change the GGTT */
-i915_ggtt_enable_guc(dev_priv);
+/*
+ * We need to notify the guc whenever we change the GGTT.
+ * During resume from sleep we would have already updated the
+ * GGTT invalidate function for GuC during i915_gem_resume so
+ * we need to skip here. Will enable here on driver load/reset.
+ */
+if (!guc->suspended)
+i915_ggtt_enable_guc(dev_priv);
if (i915_modparams.enable_guc_submission) {
 /*
@@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private  
*dev_priv)

 guc_free_load_err_log(guc);
i915_guc_submission_cleanup(dev_priv);
-
-if (i915_modparams.enable_guc_loading)
-i915_ggtt_disable_guc(dev_priv);
 }
/**
@@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private  
*dev_priv)

 struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (i915_modparams.enable_guc_loading) {
+if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)


Hmm, isn't that check redundant ?

uc_sanitize can happen without firmware loaded too in which case we


If uc_sanitize can be loaded without firmware loaded, then I assume
i915_modparams.enable_guc_loading will be cleared too, right ?

I'm just wondering if we need to check both modparam and fw status.


don't want to ggtt_disable_guc.
if we want to ggtt_disable_guc then we should remove the GEM_BUG_ON in  
it.


Hmm, this is the way how we run CI tests ;)




+ i915_ggtt_disable_guc(dev_priv);
+
 guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 }


Btw, what should we do with "suspended" flag during sanitize ?

suspended flag is set to true on suspend and false on resume.
sanitize is done post suspend and before resume so we should not touch  
it.
initializing it to false during guc_init_early should take care of  
reload (during unload we are suspending gem but we wont resume)

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Re: [Intel-gfx] [PATCH v13 18/21] drm/i915/uc: Introduce intel_uc_sanitize to initialize GuC/HuC reset state

[Sagar Arun Kamble]

On 10/11/2017 11:00 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:13 +0200, Sagar Arun Kamble 
 wrote:



In i915_reset/gem_sanitize, GPU will be reset and driver state about
GuC/HuC load status will be invalid. Hence, we mark both GuC/HuC as not
loaded/NONE.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 18 ++
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index f1a785a..a4bbf6c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2954,6 +2954,8 @@ int i915_gem_reset_prepare(struct 
drm_i915_private *dev_priv)

i915_gem_revoke_fences(dev_priv);
+    intel_uc_sanitize(dev_priv);
+
 return err;
 }
@@ -4636,6 +4638,8 @@ void i915_gem_sanitize(struct drm_i915_private 
*i915)

 mutex_unlock(>drm.struct_mutex);
 }
+    intel_uc_sanitize(i915);
+
 /*
  * If we inherit context state from the BIOS or earlier occupants
  * of the GPU, the GPU may be in an inconsistent state when we
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 25acf8f..9010ab5 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -438,3 +438,21 @@ void intel_uc_runtime_resume(struct 
drm_i915_private *dev_priv)

intel_uc_init_hw(dev_priv);
 }
+
+/**
+ * intel_uc_sanitize() - Sanitize uC state.
+ * @dev_priv: i915 device private
+ *
+ * This function marks load_status as FIRMWARE_NONE and sanitizes 
state of

+ * other GuC tasks.
+ */
+void intel_uc_sanitize(struct drm_i915_private *dev_priv)
+{
+    struct intel_uc_fw *guc_fw = _priv->guc.fw;
+    struct intel_uc_fw *huc_fw = _priv->huc.fw;


nitpick:

struct intel_guc *guc = _priv->guc;
struct intel_huc *huc = _priv->huc;

Sure. will update uc_fw through these struct pointers.



+
+    if (i915_modparams.enable_guc_loading) {
+    guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+    huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+    }


Maybe we should move this patch before 13/21 to better handle
"skip_load_on_resume" case ?

yes. in v14 i have moved this patch earlier.



+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h 
b/drivers/gpu/drm/i915/intel_uc.h

index f741ccc..fbae5d8 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -37,5 +37,6 @@
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
 void intel_uc_resume(struct drm_i915_private *dev_priv);
 void intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
#endif


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Re: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions

[Sagar Arun Kamble]

On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble 
 wrote:



i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggtt_disable_guc at the end of reset/suspend/unload is needed
post GGTT suspend operations. Calling it during uc_sanitize covers
all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these
needto be protected by struct_mutex. Hence struct_mutex locking is
added in i915_gem_sanitize while sanitizing uC. struct_mutex is already
held during i915_gem_reset_prepare.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 16 +++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index a4bbf6c..77a0746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private 
*dev_priv)

 WARN_ON(dev_priv->gt.awake);
mutex_lock(>struct_mutex);
+    /* We need to notify the guc whenever we change the GGTT */
+    if (i915_modparams.enable_guc_loading)
+    i915_ggtt_enable_guc(dev_priv);
+
 i915_gem_restore_gtt_mappings(dev_priv);
 i915_gem_restore_fences(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 9010ab5..0b799fe 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)

 guc_disable_communication(guc);
 gen9_reset_guc_interrupts(dev_priv);
-    /* We need to notify the guc whenever we change the GGTT */
-    i915_ggtt_enable_guc(dev_priv);
+    /*
+ * We need to notify the guc whenever we change the GGTT.
+ * During resume from sleep we would have already updated the
+ * GGTT invalidate function for GuC during i915_gem_resume so
+ * we need to skip here. Will enable here on driver load/reset.
+ */
+    if (!guc->suspended)
+    i915_ggtt_enable_guc(dev_priv);
if (i915_modparams.enable_guc_submission) {
 /*
@@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private 
*dev_priv)

 guc_free_load_err_log(guc);
i915_guc_submission_cleanup(dev_priv);
-
-    if (i915_modparams.enable_guc_loading)
-    i915_ggtt_disable_guc(dev_priv);
 }
/**
@@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private 
*dev_priv)

 struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (i915_modparams.enable_guc_loading) {
+    if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)


Hmm, isn't that check redundant ?
uc_sanitize can happen without firmware loaded too in which case we 
don't want to ggtt_disable_guc.

if we want to ggtt_disable_guc then we should remove the GEM_BUG_ON in it.



+ i915_ggtt_disable_guc(dev_priv);
+
 guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 }


Btw, what should we do with "suspended" flag during sanitize ?

suspended flag is set to true on suspend and false on resume.
sanitize is done post suspend and before resume so we should not touch it.
initializing it to false during guc_init_early should take care of 
reload (during unload we are suspending gem but we wont resume)


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Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree

[Rodrigo Vivi]

On Wed, Oct 11, 2017 at 08:51:06AM +, Mark Brown wrote:
> On Tue, Oct 10, 2017 at 08:03:00AM +0100, Mark Brown wrote:
> > Hi all,
> > 
> > After merging the drm-misc-fixes tree, today's linux-next build
> > (x86_allmodconfig) failed like this:
> > 
> >   CC [M]  drivers/gpu/drm/i915/i915_gem_evict.o
> > drivers/gpu/drm/i915/i915_gem_evict.c: In function 
> > ‘i915_gem_evict_for_node’:
> > drivers/gpu/drm/i915/i915_gem_evict.c:318:31: error: implicit declaration 
> > of function ‘i915_vma_has_userfault’; did you mean ‘i915_vma_pin_count’? 
> > [-Werror=implicit-function-declaration]
> >if (flags & PIN_NONFAULT && i915_vma_has_userfault(vma)) {
> >^~
> >i915_vma_pin_count
> > 
> > Caused by commit
> > 
> >   72872c99b6dbc ("drm/i915: Check PIN_NONFAULT overlaps in evict_for_node")
> > 
> > in the drm-intel-fixes tree.  I've used the tree from yesterday.
> 
> This is still present today.

It is fixed now. Sorry for the trouble.

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Re: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble  
 wrote:



i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggtt_disable_guc at the end of reset/suspend/unload is needed
post GGTT suspend operations. Calling it during uc_sanitize covers
all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these
needto be protected by struct_mutex. Hence struct_mutex locking is
added in i915_gem_sanitize while sanitizing uC. struct_mutex is already
held during i915_gem_reset_prepare.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 16 +++-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index a4bbf6c..77a0746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private  
*dev_priv)

WARN_ON(dev_priv->gt.awake);
mutex_lock(>struct_mutex);
+   /* We need to notify the guc whenever we change the GGTT */
+   if (i915_modparams.enable_guc_loading)
+   i915_ggtt_enable_guc(dev_priv);
+
i915_gem_restore_gtt_mappings(dev_priv);
i915_gem_restore_fences(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 9010ab5..0b799fe 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

guc_disable_communication(guc);
gen9_reset_guc_interrupts(dev_priv);
-   /* We need to notify the guc whenever we change the GGTT */
-   i915_ggtt_enable_guc(dev_priv);
+   /*
+* We need to notify the guc whenever we change the GGTT.
+* During resume from sleep we would have already updated the
+* GGTT invalidate function for GuC during i915_gem_resume so
+* we need to skip here. Will enable here on driver load/reset.
+*/
+   if (!guc->suspended)
+   i915_ggtt_enable_guc(dev_priv);
if (i915_modparams.enable_guc_submission) {
/*
@@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private  
*dev_priv)

guc_free_load_err_log(guc);
i915_guc_submission_cleanup(dev_priv);
-
-   if (i915_modparams.enable_guc_loading)
-   i915_ggtt_disable_guc(dev_priv);
 }
/**
@@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private  
*dev_priv)

struct intel_uc_fw *huc_fw = _priv->huc.fw;
if (i915_modparams.enable_guc_loading) {
+   if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)


Hmm, isn't that check redundant ?


+   i915_ggtt_disable_guc(dev_priv);
+
guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
}


Btw, what should we do with "suspended" flag during sanitize ?
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Re: [Intel-gfx] [PATCH v13 18/21] drm/i915/uc: Introduce intel_uc_sanitize to initialize GuC/HuC reset state

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:13 +0200, Sagar Arun Kamble  
 wrote:



In i915_reset/gem_sanitize, GPU will be reset and driver state about
GuC/HuC load status will be invalid. Hence, we mark both GuC/HuC as not
loaded/NONE.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  4 
 drivers/gpu/drm/i915/intel_uc.c | 18 ++
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index f1a785a..a4bbf6c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2954,6 +2954,8 @@ int i915_gem_reset_prepare(struct drm_i915_private  
*dev_priv)

i915_gem_revoke_fences(dev_priv);
+   intel_uc_sanitize(dev_priv);
+
return err;
 }
@@ -4636,6 +4638,8 @@ void i915_gem_sanitize(struct drm_i915_private  
*i915)

mutex_unlock(>drm.struct_mutex);
}
+   intel_uc_sanitize(i915);
+
/*
 * If we inherit context state from the BIOS or earlier occupants
 * of the GPU, the GPU may be in an inconsistent state when we
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 25acf8f..9010ab5 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -438,3 +438,21 @@ void intel_uc_runtime_resume(struct  
drm_i915_private *dev_priv)

intel_uc_init_hw(dev_priv);
 }
+
+/**
+ * intel_uc_sanitize() - Sanitize uC state.
+ * @dev_priv: i915 device private
+ *
+ * This function marks load_status as FIRMWARE_NONE and sanitizes state  
of

+ * other GuC tasks.
+ */
+void intel_uc_sanitize(struct drm_i915_private *dev_priv)
+{
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
+   struct intel_uc_fw *huc_fw = _priv->huc.fw;


nitpick:

struct intel_guc *guc = _priv->guc;
struct intel_huc *huc = _priv->huc;


+
+   if (i915_modparams.enable_guc_loading) {
+   guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+   huc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+   }


Maybe we should move this patch before 13/21 to better handle
"skip_load_on_resume" case ?


+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h  
b/drivers/gpu/drm/i915/intel_uc.h

index f741ccc..fbae5d8 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -37,5 +37,6 @@
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
 void intel_uc_resume(struct drm_i915_private *dev_priv);
 void intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
#endif

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Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Chris Wilson]

Quoting Vinay Belgaumkar (2017-10-11 18:16:23)
> This limitation does not exist for gen8+. It was removed by this patch-
> 
> commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

So where is the mention of gen8 there? And where is the compatibility
test to determine the age of the kernel?

As a hint,

bool has_ctx_exec(int fd, unsigned ring) {
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec;
bool supported;

/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
if (ring & (3 << 13) && !gem_has_bsd2(fd))
return false;
}

memset(, 0, sizeof(exec));
memset(, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer();
execbuf.buffer_count = 1;
execbuf.flags = ring;
execbuf.rsvd1 = gem_context_crate(fd);
supported = __gem_execbuf(fd, ) == -ENOENT;
gem_context_destroy(execbuf.rsvd1);

return supported;
}
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane assert/readout cleanups etc.

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc.
URL   : https://patchwork.freedesktop.org/series/31758/
State : success

== Summary ==

Series 31758v1 drm/i915: Plane assert/readout cleanups etc.
https://patchwork.freedesktop.org/api/1.0/series/31758/revisions/1/mbox/

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:467s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:572s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:527s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:520s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:533s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:515s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:558s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:613s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:273s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:598s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:445s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:458s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:505s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:479s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:495s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:578s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:491s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:666s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:656s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:533s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:510s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:475s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:578s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:437s

8a09bc166a311443214f03b7f5b379fc21783af1 drm-tip: 2017y-10m-11d-16h-00m-59s UTC 
integration manifest
792c22f3223f drm/i915: Add windowing for primary planes on gen2/3 and chv
df8961c3a4f2 drm/i915: Nuke crtc->plane
dbf3070fd778 drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
b3c8f195fe40 drm/i915: Nuke ironlake_get_initial_plane_config()
d5ee901c6b09 drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in 
initial fb readout
23dd92eb8bab drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
22ad8fd53a2c drm/i915: s/enum plane/enum old_plane_id/
c3ed6281fd93 drm/i915: Redo plane sanitation during readout
22ca75ae67fd drm/i915: Add .get_hw_state() method for planes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5997/
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Re: [Intel-gfx] [PATCH v13 14/21] drm/i915/uc: Update GEM runtime resume with need for reload of GuC/HuC

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:09 +0200, Sagar Arun Kamble  
 wrote:



On resume from drm sleep/suspend, we have gem_init_hw path to reload
the GuC/HuC firmware. However, on resume from runtime suspend we needed
to add support to reload the GuC/HuC firmware and resume.
We can leverage intel_uc_init_hw for this based on skip_load_on_resume.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c |  2 +-
 drivers/gpu/drm/i915/intel_uc.c | 28 
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index 7d1b7e1..9e257e2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2113,7 +2113,7 @@ void i915_gem_runtime_resume(struct  
drm_i915_private *dev_priv)

i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
-   intel_uc_resume(dev_priv);
+   intel_uc_runtime_resume(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index f641872..25acf8f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -410,3 +410,31 @@ void intel_uc_resume(struct drm_i915_private  
*dev_priv)

guc->skip_load_on_resume = false;
}
 }
+
+/**
+ * intel_uc_runtime_resume() - Resume uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function invokes intel_uc_suspend that will if GuC is loaded


Please focus on tasks rather than function names.


+ * enable communication with GuC, enable GuC interrupts, invoke GuC OS
+ * resumption and enable GuC submission.
+ * If GuC is not loaded, GuC needs to be loaded and do the entire setup
+ * by leveraging intel_uc_init_hw.
+ *
+ */
+void intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
+{
+   struct intel_guc *guc = _priv->guc;
+
+   if (!guc->suspended)
+   return;
+
+   intel_uc_resume(dev_priv);
+
+   if (guc->skip_load_on_resume)


Hmm, I may be lost, but I feel that some changes from 13/21 done
in intel_uc_resume() looks like good candidate for this function.

What I'm missing is clear distinction what each function will do,
due to lot of conditions and cross calls.


+   return;
+
+   WARN_ON(guc_wopcm_locked(guc));


Why here?


+
+   intel_uc_init_hw(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h  
b/drivers/gpu/drm/i915/intel_uc.h

index 7d9dd9c..f741ccc 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -36,5 +36,6 @@
 void intel_uc_cleanup(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
 void intel_uc_resume(struct drm_i915_private *dev_priv);
+void intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
#endif

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reuse normal state readout for LVDS/DVO fixed mode

[Ville Syrjälä]

On Wed, Oct 11, 2017 at 05:21:56PM +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-10-10 15:33:33)
> > Quoting Ville Syrjala (2017-10-09 17:19:50)
> > > From: Ville Syrjälä 
> > > 
> > > Reuse the normal state readout code to get the fixed mode for LVDS/DVO
> > > encoders. This removes some partially duplicated state readout code
> > > from LVDS/DVO encoders. The duplicated code wasn't actually even
> > > populating the negative h/vsync flags, leading to possible state checker
> > > complaints. The normal readout code populates that stuff fully.
> > > 
> > > Cc: Chris Wilson 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 50 
> > > +---
> > >  drivers/gpu/drm/i915/intel_drv.h |  5 ++--
> > >  drivers/gpu/drm/i915/intel_dvo.c | 33 ++--
> > >  drivers/gpu/drm/i915/intel_lvds.c| 18 -
> > >  4 files changed, 39 insertions(+), 67 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 15844bf92434..f8693374955c 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -10247,48 +10247,44 @@ static void ironlake_pch_clock_get(struct 
> > > intel_crtc *crtc,
> > >  _config->fdi_m_n);
> > >  }
> > >  
> > > -/** Returns the currently programmed mode of the given pipe. */
> > > -struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> > > -struct drm_crtc *crtc)
> > > +/* Returns the currently programmed mode of the given encoder. */
> > > +struct drm_display_mode *
> > > +intel_encoder_current_mode(struct intel_encoder *encoder)
> > >  {
> > > -   struct drm_i915_private *dev_priv = to_i915(dev);
> > > -   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > +   struct intel_crtc_state *crtc_state;
> > > struct drm_display_mode *mode;
> > > -   struct intel_crtc_state *pipe_config;
> > > -   enum pipe pipe = intel_crtc->pipe;
> > > +   struct intel_crtc *crtc;
> > > +   enum pipe pipe;
> > > +
> > > +   if (!encoder->get_hw_state(encoder, ))
> > > +   return NULL;
> > 
> > There's no chance that get_hw_state can return a pipe beyond our
> > knowledge? I'm presuming we are part of the early hw setup here, so may
> > not have sanitized everything?
> > 
> > > +
> > > +   crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > >  
> > > mode = kzalloc(sizeof(*mode), GFP_KERNEL);
> > > if (!mode)
> > > return NULL;
> > >  
> > > -   pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
> > > -   if (!pipe_config) {
> > > +   crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
> > > +   if (!crtc_state) {
> > > kfree(mode);
> > > return NULL;
> > > }
> > >  
> > > -   /*
> > > -* Construct a pipe_config sufficient for getting the clock info
> > > -* back out of crtc_clock_get.
> > > -*
> > > -* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
> > > -* to use a real value here instead.
> > > -*/
> > > -   pipe_config->cpu_transcoder = (enum transcoder) pipe;
> > > -   pipe_config->pixel_multiplier = 1;
> > > -   pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
> > > -   pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
> > > -   pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
> > > -   i9xx_crtc_clock_get(intel_crtc, pipe_config);
> > > +   crtc_state->base.crtc = >base;
> > >  
> > > -   pipe_config->base.adjusted_mode.crtc_clock =
> > > -   pipe_config->port_clock / pipe_config->pixel_multiplier;
> > > +   if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
> > > +   kfree(crtc_state);
> > > +   kfree(mode);
> > > +   return NULL;
> > > +   }
> > >  
> > > -   intel_get_pipe_timings(intel_crtc, pipe_config);
> > > +   encoder->get_config(encoder, crtc_state);
> > >  
> > > -   intel_mode_from_pipe_config(mode, pipe_config);
> > > +   intel_mode_from_pipe_config(mode, crtc_state);
> > >  
> > > -   kfree(pipe_config);
> > > +   kfree(crtc_state);
> > 
> > This all looks consistent to my eyes.
> > >  
> > > return mode;
> > >  }
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 0cab667fff57..b57a691409c4 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1363,8 +1363,9 @@ struct intel_connector *intel_connector_alloc(void);
> > >  bool 

[Intel-gfx] [PATCH i-g-t v2] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Vinay Belgaumkar]

This limitation does not exist for gen8+. It was removed by this patch-

commit f7978a0c581a8a840a28306f8da43e06e7fef3bf

v2: Added commit id that removes the limitation(Chris Wilson)

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
 lib/igt_gt.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..abf789d 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -214,6 +214,7 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
  * @ctx: the contxt specifier
  * @ring: execbuf ring flag
  * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
  *
  * This helper function injects a hanging batch associated with @ctx into 
@ring.
  * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +240,11 @@ igt_hang_t igt_hang_ctx(int fd,
 
igt_require_hang_ring(fd, ring);
 
-   /* One day the kernel ABI will be fixed! */
-   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   if (!(intel_gen(intel_get_drm_devid(fd)) >= 8))
+   {
+   /* One day the kernel ABI will be fixed! */
+   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   }
 
param.context = ctx;
param.size = 0;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v13 13/21] drm/i915/uc: Support resume from sleep w/ and w/o GuC/HuC reload

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:08 +0200, Sagar Arun Kamble  
 wrote:



GuC/HuC resume operation depends on whether firmwares are available
in the WOPCM region. This is known through register WOPCM_SIZE BIT(0).

If it indicates WOPCM is locked (bit is set) we just need to send action
to GuC to resume and enable other related GuC functionality such as
communication, interrupts and submission.

If it indicates WOPCM is not locked then we need to first reload the
GuC/HuC and then do all resume tasks. Currently on resume from sleep,
GuC/HuC are not loaded as GPU is reset at the end of suspend/early  
resume.

So we will have to reload the firmware and send action to resume.
Resume will be done through uc_init_hw from gem_init_hw based on newly
introduced state "guc->suspended". During gem_init_hw firmware load will
be skipped based on resume status during intel_uc_resume.

Also updated the accesses to dev_priv->guc and dev_priv->huc structure by
reusing initial declared pointer.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_guc_reg.h |  1 +
 drivers/gpu/drm/i915/intel_guc.c|  2 +
 drivers/gpu/drm/i915/intel_guc.h|  3 ++
 drivers/gpu/drm/i915/intel_uc.c | 99  
+

 4 files changed, 85 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h  
b/drivers/gpu/drm/i915/i915_guc_reg.h

index 35cf991..532296b 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -75,6 +75,7 @@
/* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE _MMIO(0xc050)
+#define   GUC_WOPCM_LOCKED   BIT(0)
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
 #define   GUC_WOPCM_TOP  (0x80 << 12)/* 512KB */
 #define   BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12)/* 64KB  */
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index 55a0158..73be382 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -65,6 +65,8 @@ void intel_guc_init_early(struct intel_guc *guc)
mutex_init(>send_mutex);
guc->send = intel_guc_send_nop;
guc->notify = gen8_guc_raise_irq;
+   guc->suspended = false;
+   guc->skip_load_on_resume = false;
 }
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index a587210..9f84033 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -38,6 +38,9 @@ struct intel_guc {
struct intel_guc_log log;
struct intel_guc_ct ct;
+   bool suspended;
+   bool skip_load_on_resume;


maybe bool xxx:1 to save space.


+
/* Log snapshot if GuC errors during load */
struct drm_i915_gem_object *load_err_log;
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 1365724..f641872 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -152,14 +152,35 @@ static void guc_disable_communication(struct  
intel_guc *guc)

guc->send = intel_guc_send_nop;
 }
+static inline bool guc_wopcm_locked(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   return I915_READ(GUC_WOPCM_SIZE) & GUC_WOPCM_LOCKED;


what about adding !! trick?


+}
+
 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
+   struct intel_huc *huc = _priv->huc;
int ret, attempts;
if (!i915_modparams.enable_guc_loading)
return 0;
+   /*
+* If on resume from sleep GuC was available we resumed GuC during
+	 * i915_gem_resume. We need to skip load here. Reset  
skip_load_on_resume

+* to allow load during module reload/reset/next resume behavior.
+*/
+   if (guc->skip_load_on_resume) {
+   guc->skip_load_on_resume = false;
+   return 0;
+   }
+
+   WARN_ON_ONCE(guc->fw.load_status == INTEL_UC_FIRMWARE_SUCCESS);
+   WARN_ON_ONCE(huc->fw.load_status == INTEL_UC_FIRMWARE_SUCCESS);
+
guc_disable_communication(guc);
gen9_reset_guc_interrupts(dev_priv);
@@ -197,8 +218,8 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

if (ret)
goto err_submission;
-   intel_huc_init_hw(_priv->huc);
-   ret = intel_guc_init_hw(_priv->guc);
+   intel_huc_init_hw(huc);
+   ret = intel_guc_init_hw(guc);
if (ret == 0 || ret != -EAGAIN)
break;
@@ -214,7 +235,21 @@ int 

[Intel-gfx] ✗ Fi.CI.BAT: warning for softdog: Obey hardlockup_all_cpu_backtrace sysctl (rev2)

[Patchwork]

== Series Details ==

Series: softdog: Obey hardlockup_all_cpu_backtrace sysctl (rev2)
URL   : https://patchwork.freedesktop.org/series/31751/
State : warning

== Summary ==

Series 31751v2 softdog: Obey hardlockup_all_cpu_backtrace sysctl
https://patchwork.freedesktop.org/api/1.0/series/31751/revisions/2/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (fi-bdw-5557u) fdo#102473
Test pm_rpm:
Subgroup basic-rte:
pass   -> SKIP   (fi-hsw-4770r)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473

fi-bdw-5557u total:289  pass:267  dwarn:1   dfail:0   fail:0   skip:21  
time:453s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:391s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:573s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:284s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:517s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:523s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:537s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:517s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:565s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:626s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-gdg-551   total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 
time:274s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:597s
fi-hsw-4770r total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:439s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:506s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:493s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:658s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:653s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:530s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:514s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:472s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:576s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:431s

8a09bc166a311443214f03b7f5b379fc21783af1 drm-tip: 2017y-10m-11d-16h-00m-59s UTC 
integration manifest
bc818a03c9a0 softdog-info

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5996/
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Re: [Intel-gfx] [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjälä]

On Wed, Oct 11, 2017 at 04:21:58PM +, Alex Villacis Lasso wrote:
> El 11/10/17 a las 11:04, Ville Syrjala escribió:
> > From: Ville Syrjälä 
> >
> > This series aims to clean up some of the plane state readout and
> > sanitation, and clean up the enum plane mess a bit by renaming it
> > to enum old_plane_id.
> >
> > The one actual bugfix here is the plane<->crtc sanitation
> > change. Previously we tried to shut down the entire pipe when
> > the plane mapping wasn't what we want, now we just shut down the
> > plane, which is easier.
> >
> > Most of the other stuff is just polish, but I also decided to
> > throw the gen2/3 and chv primary plane windowing support on on top
> > just because it's been bugging me for years, and I was already
> > in the neighbourhood.
> >
> > Series available here:
> > git://github.com/vsyrjala/linux.git plane_sanitation_2
> >
> > Cc: Thierry Reding 
> > Cc: Alex Villacís Lasso 
> >
> > Ville Syrjälä (9):
> >drm/i915: Add .get_hw_state() method for planes
> >drm/i915: Redo plane sanitation during readout
> >drm/i915: s/enum plane/enum old_plane_id/
> >drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
> >drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
> >  fb readout
> >drm/i915: Nuke ironlake_get_initial_plane_config()
> >drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
> >drm/i915: Nuke crtc->plane
> >drm/i915: Add windowing for primary planes on gen2/3 and chv
> >
> >   drivers/gpu/drm/i915/i915_drv.h  |  16 +-
> >   drivers/gpu/drm/i915/intel_display.c | 500 
> > +++
> >   drivers/gpu/drm/i915/intel_drv.h |   8 +-
> >   drivers/gpu/drm/i915/intel_fbc.c |  27 +-
> >   drivers/gpu/drm/i915/intel_pm.c  |  36 +--
> >   drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
> >   6 files changed, 299 insertions(+), 331 deletions(-)
> >
> Sorry if this sounds like a newbie question, but what kernel version should 
> these two patches be applied against? Can they be applied on top of 4.13.5?

Not sure they apply cleanly to something so old. In general we develop
everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
that's where they would at least apply. But in that case it's actually
easier to just grab my plane_sanitation_2 branch directly since it's
sitting on top of the latest drm-tip.

Hmm. Looks like only trivial conflicts when cherry-picking the first
two patches onto 4.13.5. I pushed the result to here:
git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
but note that I only compile tested it so it's still possible it won't
actually work.

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/i915: Parse DSI backlight/cabc ports.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Parse DSI backlight/cabc ports.
URL   : https://patchwork.freedesktop.org/series/31737/
State : warning

== Summary ==

Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
pass   -> FAIL   (shard-hsw) fdo#102655
Test kms_plane:
Subgroup plane-panning-bottom-right-pipe-B-planes:
pass   -> SKIP   (shard-hsw)

fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655

shard-hswtotal:2552 pass:1433 dwarn:6   dfail:0   fail:9   skip:1104 
time:9570s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5989/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Reuse normal state readout for LVDS/DVO fixed mode

[Chris Wilson]

Quoting Chris Wilson (2017-10-10 15:33:33)
> Quoting Ville Syrjala (2017-10-09 17:19:50)
> > From: Ville Syrjälä 
> > 
> > Reuse the normal state readout code to get the fixed mode for LVDS/DVO
> > encoders. This removes some partially duplicated state readout code
> > from LVDS/DVO encoders. The duplicated code wasn't actually even
> > populating the negative h/vsync flags, leading to possible state checker
> > complaints. The normal readout code populates that stuff fully.
> > 
> > Cc: Chris Wilson 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 50 
> > +---
> >  drivers/gpu/drm/i915/intel_drv.h |  5 ++--
> >  drivers/gpu/drm/i915/intel_dvo.c | 33 ++--
> >  drivers/gpu/drm/i915/intel_lvds.c| 18 -
> >  4 files changed, 39 insertions(+), 67 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 15844bf92434..f8693374955c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10247,48 +10247,44 @@ static void ironlake_pch_clock_get(struct 
> > intel_crtc *crtc,
> >  _config->fdi_m_n);
> >  }
> >  
> > -/** Returns the currently programmed mode of the given pipe. */
> > -struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> > -struct drm_crtc *crtc)
> > +/* Returns the currently programmed mode of the given encoder. */
> > +struct drm_display_mode *
> > +intel_encoder_current_mode(struct intel_encoder *encoder)
> >  {
> > -   struct drm_i915_private *dev_priv = to_i915(dev);
> > -   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +   struct intel_crtc_state *crtc_state;
> > struct drm_display_mode *mode;
> > -   struct intel_crtc_state *pipe_config;
> > -   enum pipe pipe = intel_crtc->pipe;
> > +   struct intel_crtc *crtc;
> > +   enum pipe pipe;
> > +
> > +   if (!encoder->get_hw_state(encoder, ))
> > +   return NULL;
> 
> There's no chance that get_hw_state can return a pipe beyond our
> knowledge? I'm presuming we are part of the early hw setup here, so may
> not have sanitized everything?
> 
> > +
> > +   crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> >  
> > mode = kzalloc(sizeof(*mode), GFP_KERNEL);
> > if (!mode)
> > return NULL;
> >  
> > -   pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
> > -   if (!pipe_config) {
> > +   crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
> > +   if (!crtc_state) {
> > kfree(mode);
> > return NULL;
> > }
> >  
> > -   /*
> > -* Construct a pipe_config sufficient for getting the clock info
> > -* back out of crtc_clock_get.
> > -*
> > -* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
> > -* to use a real value here instead.
> > -*/
> > -   pipe_config->cpu_transcoder = (enum transcoder) pipe;
> > -   pipe_config->pixel_multiplier = 1;
> > -   pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
> > -   pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
> > -   pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
> > -   i9xx_crtc_clock_get(intel_crtc, pipe_config);
> > +   crtc_state->base.crtc = >base;
> >  
> > -   pipe_config->base.adjusted_mode.crtc_clock =
> > -   pipe_config->port_clock / pipe_config->pixel_multiplier;
> > +   if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
> > +   kfree(crtc_state);
> > +   kfree(mode);
> > +   return NULL;
> > +   }
> >  
> > -   intel_get_pipe_timings(intel_crtc, pipe_config);
> > +   encoder->get_config(encoder, crtc_state);
> >  
> > -   intel_mode_from_pipe_config(mode, pipe_config);
> > +   intel_mode_from_pipe_config(mode, crtc_state);
> >  
> > -   kfree(pipe_config);
> > +   kfree(crtc_state);
> 
> This all looks consistent to my eyes.
> >  
> > return mode;
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 0cab667fff57..b57a691409c4 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1363,8 +1363,9 @@ struct intel_connector *intel_connector_alloc(void);
> >  bool intel_connector_get_hw_state(struct intel_connector *connector);
> >  void intel_connector_attach_encoder(struct intel_connector *connector,
> > struct intel_encoder *encoder);
> > -struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,

Re: [Intel-gfx] [PATCH v13 10/21] drm/i915/guc: Update uC suspend/resume function separating Host/GuC tasks

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:05 +0200, Sagar Arun Kamble  
 wrote:



Suspending GuC involves bunch of tasks controlled by GuC OS and some
controlled by Host OS.

Host needs to disable submission to GuC and any other GuC functions.  
Then,

GuC's task is initiated by Host sending action to GuC to enter sleep
state. On this action, GuC preempts engines to idle context and then  
saves
internal state to a buffer. It also disables internal interrupts/timers  
to

avoid any wake-ups.
After this, Host should disable GuC interrupts, communication with GuC
(intel_guc_send/notify). GGTT invalidate update will have to be done in
conjunction with GTT related suspend/resume tasks.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed GuC specific helpers as tasks other than send H2G for
sleep/resume are to be done from uc generic functions. (Michal Wajdeczko)

v4: Simplified/Unified the error messaging in uc_runtime_suspend/resume.
(Michal Wajdeczko). Rebase w.r.t i915_modparams change.
Added documentation to intel_uc_runtime_suspend/resume.

v5: Removed enable_guc_loading based check from intel_uc_runtime_suspend
and intel_uc_runtime_resume and pulled FW load_status based checks from
intel_guc_suspend/resume into these functions. (Michal Wajdeczko)

v6: Adjusted intel_uc_runtime_resume with prototype change to not return
value.

v7: Rebase.

v8: Updated commit description and added submission enable/disable in
GuC suspend/resume paths. Removed GGTT invalidate update functions.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
Reviewed-by: Michal Wajdeczko  #6
---
 drivers/gpu/drm/i915/intel_guc.c | 11 ---
 drivers/gpu/drm/i915/intel_uc.c  | 65  
+---

 2 files changed, 61 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index 9a2df69..55a0158 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -177,11 +177,6 @@ int intel_guc_suspend(struct intel_guc *guc)
struct i915_gem_context *ctx;
u32 data[3];
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   gen9_disable_guc_interrupts(i915);
-
ctx = i915->kernel_context;
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
@@ -204,12 +199,6 @@ int intel_guc_resume(struct intel_guc *guc)
struct i915_gem_context *ctx;
u32 data[3];
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   if (i915_modparams.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(i915);
-
ctx = i915->kernel_context;
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index b5c132c..297a321 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -284,18 +284,75 @@ void intel_uc_fini_hw(struct drm_i915_private  
*dev_priv)

i915_ggtt_disable_guc(dev_priv);
 }
+/**
+ * intel_uc_suspend() - Suspend uC operation.
+ * @dev_priv: i915 device private
+ *


Ha! found missing kerneldoc ... maybe it can be partially moved to
previous patch ?


+ * This function disables GuC submission, invokes GuC OS suspension,
+ * disables GuC interrupts and disable communication with GuC.
+ *
+ * Return: non-zero code on error
+ */
 int intel_uc_suspend(struct drm_i915_private *dev_priv)
 {
-   int ret;
+   struct intel_guc *guc = _priv->guc;
+   int ret = 0;
+
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   goto out;


Hmm, is it ok to report DRM_ERROR if Guc was not started/loaded ?
Return 0 seems to be still the best option here.


+
+   i915_guc_submission_disable(dev_priv);
-   ret = intel_guc_suspend(_priv->guc);
+   ret = intel_guc_suspend(guc);
if (ret)
-   DRM_ERROR("Failed to suspend GuC\n");
+   goto out_suspend;
+
+   gen9_disable_guc_interrupts(dev_priv);
+   guc_disable_communication(guc);
+
+   goto out;
+
+out_suspend:
+   i915_guc_submission_enable(dev_priv);
+out:
+   if (ret)
+   DRM_ERROR("uC Suspend failed (%d)\n", ret);


Unless I read wrong, we are re-enabling guc submission on failure,
so maybe error should say something like:

DRM_ERROR("Failed to suspend uC, aborting suspend\n");


return ret;
 }
+/**
+ * intel_uc_resume() - Resume uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function enables communication with GuC, enables GuC interrupts,
+ * invokes GuC OS resumption and enables GuC submission.
+ */
 void intel_uc_resume(struct drm_i915_private *dev_priv)
 {
-   

[Intel-gfx] [PATCH 5/9] drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial fb readout

[Ville Syrjala]

From: Ville Syrjälä 

Use enum pipe, enum plane_id, and enum old_plane_id consistently in the
initial framebuffe readout.

v2: Use old_plane_id in the ilk code

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 58 
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9d37c758f7b5..21160a06ab36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7456,14 +7456,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+   enum old_plane_id plane_id = plane->plane;
+   enum pipe pipe = crtc->pipe;
u32 val, base, offset;
-   int pipe = crtc->pipe, plane = crtc->plane;
int fourcc, pixel_format;
unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
 
-   val = I915_READ(DSPCNTR(plane));
+   val = I915_READ(DSPCNTR(plane_id));
if (!(val & DISPLAY_PLANE_ENABLE))
return;
 
@@ -7490,12 +7492,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
if (INTEL_GEN(dev_priv) >= 4) {
if (plane_config->tiling)
-   offset = I915_READ(DSPTILEOFF(plane));
+   offset = I915_READ(DSPTILEOFF(plane_id));
else
-   offset = I915_READ(DSPLINOFF(plane));
-   base = I915_READ(DSPSURF(plane)) & 0xf000;
+   offset = I915_READ(DSPLINOFF(plane_id));
+   base = I915_READ(DSPSURF(plane_id)) & 0xf000;
} else {
-   base = I915_READ(DSPADDR(plane));
+   base = I915_READ(DSPADDR(plane_id));
}
plane_config->base = base;
 
@@ -7503,15 +7505,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = ((val >> 16) & 0xfff) + 1;
fb->height = ((val >> 0) & 0xfff) + 1;
 
-   val = I915_READ(DSPSTRIDE(pipe));
+   val = I915_READ(DSPSTRIDE(plane_id));
fb->pitches[0] = val & 0xffc0;
 
aligned_height = intel_fb_align_height(fb, 0, fb->height);
 
plane_config->size = fb->pitches[0] * aligned_height;
 
-   DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, 
pitch %d, size 0x%x\n",
- pipe_name(pipe), plane, fb->width, fb->height,
+   DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
+ crtc->base.name, plane->base.name, fb->width, fb->height,
  fb->format->cpp[0] * 8, base, fb->pitches[0],
  plane_config->size);
 
@@ -8482,8 +8484,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+   enum plane_id plane_id = plane->id;
+   enum pipe pipe = crtc->pipe;
u32 val, base, offset, stride_mult, tiling;
-   int pipe = crtc->pipe;
int fourcc, pixel_format;
unsigned int aligned_height;
struct drm_framebuffer *fb;
@@ -8499,7 +8503,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
fb->dev = dev;
 
-   val = I915_READ(PLANE_CTL(pipe, 0));
+   val = I915_READ(PLANE_CTL(pipe, plane_id));
if (!(val & PLANE_CTL_ENABLE))
goto error;
 
@@ -8535,16 +8539,16 @@ skylake_get_initial_plane_config(struct intel_crtc 
*crtc,
goto error;
}
 
-   base = I915_READ(PLANE_SURF(pipe, 0)) & 0xf000;
+   base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xf000;
plane_config->base = base;
 
-   offset = I915_READ(PLANE_OFFSET(pipe, 0));
+   offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
 
-   val = I915_READ(PLANE_SIZE(pipe, 0));
+   val = I915_READ(PLANE_SIZE(pipe, plane_id));
fb->height = ((val >> 16) & 0xfff) + 1;
fb->width = ((val >> 0) & 0x1fff) + 1;
 
-   val = I915_READ(PLANE_STRIDE(pipe, 0));
+   val = I915_READ(PLANE_STRIDE(pipe, plane_id));
stride_mult = intel_fb_stride_alignment(fb, 0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
 
@@ -8552,8 +8556,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
plane_config->size = fb->pitches[0] * aligned_height;
 
-   DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, 
size 0x%x\n",
- pipe_name(pipe), fb->width, fb->height,
+   DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
+ 

[Intel-gfx] [PATCH 8/9] drm/i915: Nuke crtc->plane

[Ville Syrjala]

From: Ville Syrjälä 

Eliminate crtc->plane since it's pretty much a layering violation.
We can always get the plane via crtc->primary if we actually need it.

The only ugly thing left is plane_to_crtc_mapping[], but that's
still needed by the pre-g4x watermark code.

Also revise the comment about emum old_plane_id to make it clear
one should not use it for SKL+ ever.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 +-
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 drivers/gpu/drm/i915/intel_drv.h | 1 -
 drivers/gpu/drm/i915/intel_fbc.c | 4 ++--
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9c4735da2169..0b97860ba39c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,7 +305,7 @@ static inline bool transcoder_is_dsi(enum transcoder 
transcoder)
 
 /*
  * Global legacy plane identifier. Valid only for primary/sprite
- * planes on pre-g4x, and only for primary planes on g4x+.
+ * planes on pre-g4x, and only for primary planes on g4x-bdw.
  */
 enum old_plane_id {
PLANE_A,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ccdfd922fe5b..622b487629d7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13386,14 +13386,13 @@ static int intel_crtc_init(struct drm_i915_private 
*dev_priv, enum pipe pipe)
goto fail;
 
intel_crtc->pipe = pipe;
-   intel_crtc->plane = primary->plane;
 
/* initialize shared scalers */
intel_crtc_init_scalers(intel_crtc, crtc_state);
 
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
-  dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
-   dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
+  dev_priv->plane_to_crtc_mapping[primary->plane] != NULL);
+   dev_priv->plane_to_crtc_mapping[primary->plane] = intel_crtc;
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
 
drm_crtc_helper_add(_crtc->base, _helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0852b33712b1..8396d4de9299 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,7 +793,6 @@ struct intel_crtc_state {
 struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
-   enum old_plane_id plane;
/*
 * Whether the crtc and the connected output pipeline is active. Implies
 * that crtc->enabled is set, i.e. the current mode configuration has
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0b40b89f8e2b..567f10380a0f 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -887,7 +887,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc 
*crtc,
params->vma = cache->vma;
 
params->crtc.pipe = crtc->pipe;
-   params->crtc.plane = crtc->plane;
+   params->crtc.plane = to_intel_plane(crtc->base.primary)->plane;
params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 
params->fb.format = cache->fb.format;
@@ -1083,7 +1083,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
continue;
 
-   if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
+   if (fbc_on_plane_a_only(dev_priv) && plane->plane != PLANE_A)
continue;
 
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-- 
2.13.6

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[Intel-gfx] [PATCH 7/9] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()

[Ville Syrjala]

From: Ville Syrjälä 

Stop using the old for_each_intel_plane_in_state() type iteration
macro and replace it with for_each_new_intel_plane_in_state().
And similarly replace drm_atomic_get_existing_crtc_state() with
intel_atomic_get_new_crtc_state(). Switch over to intel_ types
as well to make the code less cluttered.

Cc: Maarten Lankhorst 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  7 +++
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_fbc.c | 23 ++-
 4 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df120a38ae42..9c4735da2169 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -561,13 +561,13 @@ struct i915_hotplug {
for_each_power_well_rev(__dev_priv, __power_well)   
\
for_each_if ((__power_well)->domains & (__domain_mask))
 
-#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
+#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, 
__i) \
for ((__i) = 0; \
 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 ((plane) = 
to_intel_plane((__state)->base.planes[__i].ptr), \
- (plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].state), 1); \
+ (new_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 (__i)++) \
-   for_each_if (plane_state)
+   for_each_if (plane)
 
 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
for ((__i) = 0; \
@@ -577,7 +577,6 @@ struct i915_hotplug {
 (__i)++) \
for_each_if (crtc)
 
-
 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, 
new_plane_state, __i) \
for ((__i) = 0; \
 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 82be2342d1c6..ccdfd922fe5b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12025,7 +12025,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
return ret;
 
-   intel_fbc_choose_crtc(dev_priv, state);
+   intel_fbc_choose_crtc(dev_priv, intel_state);
return calc_watermark_data(state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 08318260453b..0852b33712b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1645,7 +1645,7 @@ static inline void intel_fbdev_restore_mode(struct 
drm_device *dev)
 
 /* intel_fbc.c */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-  struct drm_atomic_state *state);
+  struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
 void intel_fbc_pre_update(struct intel_crtc *crtc,
  struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 8e3a05505f49..0b40b89f8e2b 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1051,11 +1051,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
  */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-  struct drm_atomic_state *state)
+  struct intel_atomic_state *state)
 {
struct intel_fbc *fbc = _priv->fbc;
-   struct drm_plane *plane;
-   struct drm_plane_state *plane_state;
+   struct intel_plane *plane;
+   struct intel_plane_state *plane_state;
bool crtc_chosen = false;
int i;
 
@@ -1063,7 +1063,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
 
/* Does this atomic commit involve the CRTC currently tied to FBC? */
if (fbc->crtc &&
-   !drm_atomic_get_existing_crtc_state(state, >crtc->base))
+   !intel_atomic_get_new_crtc_state(state, fbc->crtc))
goto out;
 
if (!intel_fbc_can_enable(dev_priv))
@@ -1073,13 +1073,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private 
*dev_priv,
 * plane. We could go for fancier schemes such as checking the plane
 * size, but this would just affect the few platforms that don't tie FBC
 * to pipe or plane A. */
-   for_each_new_plane_in_state(state, plane, plane_state, i) {
-   struct intel_plane_state *intel_plane_state =
-   

[Intel-gfx] [PATCH 9/9] drm/i915: Add windowing for primary planes on gen2/3 and chv

[Ville Syrjala]

From: Ville Syrjälä 

Plane B and C (note that we don't actually expose plane C currently)
on gen2/3 have a window generator, as does the primary plane on CHV
pipe B. So let's allow positioning of these planes freely within the
pipe source area.

Plane A on gen2/3 seems to have some kind of partial window generator
which would allow you to cut the plane off midway through the scanout,
but it would still have to start at the top-left corner of the pipe,
and it would have to be full width. That's doesn't sound all that
useful, so for simplicity let's just keep to the idea that plane A
has to be fullscreen.

Gen4 removed the plane A/B windowing support entirely, and it wasn't
reintroduced until SKL (apart from the CHV pipe B special case).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 43 ++--
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 622b487629d7..595b46255dd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3236,6 +3236,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
i915_reg_t reg = DSPCNTR(plane_id);
int x = plane_state->main.x;
int y = plane_state->main.y;
+   int crtc_x = plane_state->base.dst.x1;
+   int crtc_y = plane_state->base.dst.y1;
+   int crtc_w = drm_rect_width(_state->base.dst);
+   int crtc_h = drm_rect_height(_state->base.dst);
unsigned long irqflags;
 
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
@@ -3251,18 +3255,18 @@ static void i9xx_update_plane(struct intel_plane *plane,
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
if (INTEL_GEN(dev_priv) < 4) {
-   /* pipesrc and dspsize control the size that is scaled from,
-* which should always be the user's requested size.
+   /*
+* PLANE_A doesn't actually have a full window
+* generator but let's assume we still need to
+* program whatever is there.
 */
+   I915_WRITE_FW(DSPPOS(plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(DSPSIZE(plane_id),
- ((crtc_state->pipe_src_h - 1) << 16) |
- (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(DSPPOS(plane_id), 0);
+ ((crtc_h - 1) << 16) | (crtc_w - 1));
} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
+   I915_WRITE_FW(PRIMPOS(plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PRIMSIZE(plane_id),
- ((crtc_state->pipe_src_h - 1) << 16) |
- (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(PRIMPOS(plane_id), 0);
+ ((crtc_h - 1) << 16) | (crtc_w - 1));
I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
}
 
@@ -12737,6 +12741,15 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct 
intel_crtc_state *crtc_state
return max_scale;
 }
 
+static bool intel_primary_plane_has_windowing(struct intel_plane *plane)
+{
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+   return INTEL_GEN(dev_priv) >= 9 ||
+   (IS_CHERRYVIEW(dev_priv) && plane->plane == PLANE_B) ||
+   (INTEL_GEN(dev_priv) < 4 && plane->plane != PLANE_A);
+}
+
 static int
 intel_check_primary_plane(struct intel_plane *plane,
  struct intel_crtc_state *crtc_state,
@@ -12746,16 +12759,14 @@ intel_check_primary_plane(struct intel_plane *plane,
struct drm_crtc *crtc = state->base.crtc;
int min_scale = DRM_PLANE_HELPER_NO_SCALING;
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
-   bool can_position = false;
+   bool can_position = intel_primary_plane_has_windowing(plane);
int ret;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   /* use scaler when colorkey is not required */
-   if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
-   min_scale = 1;
-   max_scale = skl_max_scale(to_intel_crtc(crtc), 
crtc_state);
-   }
-   can_position = true;
+   /* use scaler when colorkey is not required */
+   if (INTEL_GEN(dev_priv) >= 9 &&
+   state->ckey.flags == I915_SET_COLORKEY_NONE) {
+   min_scale = 1;
+   max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
}
 
ret = drm_plane_helper_check_state(>base,
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 6/9] drm/i915: Nuke ironlake_get_initial_plane_config()

[Ville Syrjala]

From: Ville Syrjälä 

The only relevant difference between i9xx_get_initial_plane_config() and
ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
Add that to i9xx_get_initial_plane_config() and nuke
ironlake_get_initial_plane_config().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 79 +++-
 1 file changed, 6 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 21160a06ab36..82be2342d1c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7490,7 +7490,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fourcc = i9xx_format_to_fourcc(pixel_format);
fb->format = drm_format_info(fourcc);
 
-   if (INTEL_GEN(dev_priv) >= 4) {
+   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+   offset = I915_READ(DSPOFFSET(plane_id));
+   base = I915_READ(DSPSURF(plane_id)) & 0xf000;
+   } else if (INTEL_GEN(dev_priv) >= 4) {
if (plane_config->tiling)
offset = I915_READ(DSPTILEOFF(plane_id));
else
@@ -8592,76 +8595,6 @@ static void ironlake_get_pfit_config(struct intel_crtc 
*crtc,
}
 }
 
-static void
-ironlake_get_initial_plane_config(struct intel_crtc *crtc,
- struct intel_initial_plane_config 
*plane_config)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_plane *plane = to_intel_plane(crtc->base.primary);
-   enum old_plane_id plane_id = plane->plane;
-   enum pipe pipe = crtc->pipe;
-   u32 val, base, offset;
-   int fourcc, pixel_format;
-   unsigned int aligned_height;
-   struct drm_framebuffer *fb;
-   struct intel_framebuffer *intel_fb;
-
-   val = I915_READ(DSPCNTR(plane_id));
-   if (!(val & DISPLAY_PLANE_ENABLE))
-   return;
-
-   intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-   if (!intel_fb) {
-   DRM_DEBUG_KMS("failed to alloc fb\n");
-   return;
-   }
-
-   fb = _fb->base;
-
-   fb->dev = dev;
-
-   if (INTEL_GEN(dev_priv) >= 4) {
-   if (val & DISPPLANE_TILED) {
-   plane_config->tiling = I915_TILING_X;
-   fb->modifier = I915_FORMAT_MOD_X_TILED;
-   }
-   }
-
-   pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
-   fourcc = i9xx_format_to_fourcc(pixel_format);
-   fb->format = drm_format_info(fourcc);
-
-   base = I915_READ(DSPSURF(plane_id)) & 0xf000;
-   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   offset = I915_READ(DSPOFFSET(plane_id));
-   } else {
-   if (plane_config->tiling)
-   offset = I915_READ(DSPTILEOFF(plane_id));
-   else
-   offset = I915_READ(DSPLINOFF(plane_id));
-   }
-   plane_config->base = base;
-
-   val = I915_READ(PIPESRC(pipe));
-   fb->width = ((val >> 16) & 0xfff) + 1;
-   fb->height = ((val >> 0) & 0xfff) + 1;
-
-   val = I915_READ(DSPSTRIDE(plane_id));
-   fb->pitches[0] = val & 0xffc0;
-
-   aligned_height = intel_fb_align_height(fb, 0, fb->height);
-
-   plane_config->size = fb->pitches[0] * aligned_height;
-
-   DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 
0x%x\n",
- crtc->base.name, plane->base.name, fb->width, fb->height,
- fb->format->cpp[0] * 8, base, fb->pitches[0],
- plane_config->size);
-
-   plane_config->fb = intel_fb;
-}
-
 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 struct intel_crtc_state *pipe_config)
 {
@@ -14140,7 +14073,7 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
} else if (HAS_DDI(dev_priv)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
-   ironlake_get_initial_plane_config;
+   i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -14148,7 +14081,7 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
-   ironlake_get_initial_plane_config;
+   i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
 

[Intel-gfx] [PATCH 4/9] drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks

[Ville Syrjala]

From: Ville Syrjälä 

Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_pm.c | 36 +++-
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7280f9eb2e95..df120a38ae42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -699,7 +699,8 @@ struct drm_i915_display_funcs {
  struct intel_cdclk_state *cdclk_state);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_state *cdclk_state);
-   int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
+   int (*get_fifo_size)(struct drm_i915_private *dev_priv,
+enum old_plane_id plane_id);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
int (*compute_intermediate_wm)(struct drm_device *dev,
   struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2fcff9788b6f..13f1010eea77 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -521,38 +521,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state 
*crtc_state)
fifo_state->plane[PLANE_CURSOR] = 63;
 }
 
-static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum old_plane_id plane_id)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
 
size = dsparb & 0x7f;
-   if (plane)
+   if (plane_id == PLANE_B)
size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A", size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(plane_id), size);
 
return size;
 }
 
-static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum old_plane_id plane_id)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
 
size = dsparb & 0x1ff;
-   if (plane)
+   if (plane_id == PLANE_B)
size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
size >>= 1; /* Convert to cachelines */
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A", size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(plane_id), size);
 
return size;
 }
 
-static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
+ enum old_plane_id plane_id)
 {
uint32_t dsparb = I915_READ(DSPARB);
int size;
@@ -560,9 +563,8 @@ static int i845_get_fifo_size(struct drm_i915_private 
*dev_priv, int plane)
size = dsparb & 0x7f;
size >>= 2; /* Convert to cachelines */
 
-   DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
- plane ? "B" : "A",
- size);
+   DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+ dsparb, plane_name(plane_id), size);
 
return size;
 }
@@ -2261,8 +2263,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = _a_wm_info;
 
-   fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
-   crtc = intel_get_crtc_for_plane(dev_priv, 0);
+   fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
>config->base.adjusted_mode;
@@ -2288,8 +2290,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (IS_GEN2(dev_priv))
wm_info = _bc_wm_info;
 
-   fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
-   crtc = intel_get_crtc_for_plane(dev_priv, 1);
+   fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
>config->base.adjusted_mode;
@@ -2401,7 +2403,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
adjusted_mode = >config->base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
   

[Intel-gfx] [PATCH 3/9] drm/i915: s/enum plane/enum old_plane_id/

[Ville Syrjala]

From: Ville Syrjälä 

Rename enum plane to enum old_plane_id to make it clear that it only
applies to pre-SKL platforms.

v2: Reorder patches

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 +-
 drivers/gpu/drm/i915/intel_display.c | 84 ++--
 drivers/gpu/drm/i915/intel_drv.h |  6 +--
 3 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6bbc4b83aa0a..7280f9eb2e95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -307,7 +307,7 @@ static inline bool transcoder_is_dsi(enum transcoder 
transcoder)
  * Global legacy plane identifier. Valid only for primary/sprite
  * planes on pre-g4x, and only for primary planes on g4x+.
  */
-enum plane {
+enum old_plane_id {
PLANE_A,
PLANE_B,
PLANE_C,
@@ -1128,7 +1128,7 @@ struct intel_fbc {
 
struct {
enum pipe pipe;
-   enum plane plane;
+   enum old_plane_id plane;
unsigned int fence_y_offset;
} crtc;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a9fd3b8fa922..9d37c758f7b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3223,17 +3223,17 @@ int i9xx_check_plane_surface(struct intel_plane_state 
*plane_state)
return 0;
 }
 
-static void i9xx_update_primary_plane(struct intel_plane *primary,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state 
*plane_state)
+static void i9xx_update_plane(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
 {
-   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_framebuffer *fb = plane_state->base.fb;
-   enum plane plane = primary->plane;
+   enum old_plane_id plane_id = plane->plane;
u32 linear_offset;
u32 dspcntr = plane_state->ctl;
-   i915_reg_t reg = DSPCNTR(plane);
+   i915_reg_t reg = DSPCNTR(plane_id);
int x = plane_state->main.x;
int y = plane_state->main.y;
unsigned long irqflags;
@@ -3254,34 +3254,34 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
/* pipesrc and dspsize control the size that is scaled from,
 * which should always be the user's requested size.
 */
-   I915_WRITE_FW(DSPSIZE(plane),
+   I915_WRITE_FW(DSPSIZE(plane_id),
  ((crtc_state->pipe_src_h - 1) << 16) |
  (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(DSPPOS(plane), 0);
-   } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
-   I915_WRITE_FW(PRIMSIZE(plane),
+   I915_WRITE_FW(DSPPOS(plane_id), 0);
+   } else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
+   I915_WRITE_FW(PRIMSIZE(plane_id),
  ((crtc_state->pipe_src_h - 1) << 16) |
  (crtc_state->pipe_src_w - 1));
-   I915_WRITE_FW(PRIMPOS(plane), 0);
-   I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
+   I915_WRITE_FW(PRIMPOS(plane_id), 0);
+   I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
}
 
I915_WRITE_FW(reg, dspcntr);
 
-   I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
+   I915_WRITE_FW(DSPSTRIDE(plane_id), fb->pitches[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   I915_WRITE_FW(DSPSURF(plane),
+   I915_WRITE_FW(DSPSURF(plane_id),
  intel_plane_ggtt_offset(plane_state) +
  crtc->dspaddr_offset);
-   I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
+   I915_WRITE_FW(DSPOFFSET(plane_id), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
-   I915_WRITE_FW(DSPSURF(plane),
+   I915_WRITE_FW(DSPSURF(plane_id),
  intel_plane_ggtt_offset(plane_state) +
  crtc->dspaddr_offset);
-   I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
-   I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
+   I915_WRITE_FW(DSPTILEOFF(plane_id), (y << 16) | x);
+   I915_WRITE_FW(DSPLINOFF(plane_id), linear_offset);
} else {
-   I915_WRITE_FW(DSPADDR(plane),
+   

[Intel-gfx] [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjala]

From: Ville Syrjälä 

This series aims to clean up some of the plane state readout and
sanitation, and clean up the enum plane mess a bit by renaming it
to enum old_plane_id.

The one actual bugfix here is the plane<->crtc sanitation
change. Previously we tried to shut down the entire pipe when
the plane mapping wasn't what we want, now we just shut down the
plane, which is easier.

Most of the other stuff is just polish, but I also decided to
throw the gen2/3 and chv primary plane windowing support on on top
just because it's been bugging me for years, and I was already
in the neighbourhood.

Series available here:
git://github.com/vsyrjala/linux.git plane_sanitation_2

Cc: Thierry Reding 
Cc: Alex Villacís Lasso 

Ville Syrjälä (9):
  drm/i915: Add .get_hw_state() method for planes
  drm/i915: Redo plane sanitation during readout
  drm/i915: s/enum plane/enum old_plane_id/
  drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
  drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
fb readout
  drm/i915: Nuke ironlake_get_initial_plane_config()
  drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
  drm/i915: Nuke crtc->plane
  drm/i915: Add windowing for primary planes on gen2/3 and chv

 drivers/gpu/drm/i915/i915_drv.h  |  16 +-
 drivers/gpu/drm/i915/intel_display.c | 500 +++
 drivers/gpu/drm/i915/intel_drv.h |   8 +-
 drivers/gpu/drm/i915/intel_fbc.c |  27 +-
 drivers/gpu/drm/i915/intel_pm.c  |  36 +--
 drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
 6 files changed, 299 insertions(+), 331 deletions(-)

-- 
2.13.6

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[Intel-gfx] [PATCH 1/9] drm/i915: Add .get_hw_state() method for planes

[Ville Syrjala]

From: Ville Syrjälä 

Add a .get_hw_state() method for planes, returning true or false
depending on whether the plane is enabled. Use it to rewrite the
plane enabled/disabled asserts in platform agnostic fashion.

We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
supposed sanitize that anyway it doesn't really matter.

v2: Reoder patches to not depend on enum old_plane_id
Just call assert_plane_disabled() from assert_planes_disabled()

Cc: Thierry Reding 
Cc: Alex Villacís Lasso 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 155 +--
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  43 ++
 3 files changed, 101 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b2c5fba102e1..825ab00b6639 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1192,23 +1192,6 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
 pipe_name(pipe));
 }
 
-static void assert_cursor(struct drm_i915_private *dev_priv,
- enum pipe pipe, bool state)
-{
-   bool cur_state;
-
-   if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
-   cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
-   else
-   cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
-
-   I915_STATE_WARN(cur_state != state,
-"cursor on pipe %c assertion failure (expected %s, current %s)\n",
-   pipe_name(pipe), onoff(state), onoff(cur_state));
-}
-#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
-#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
-
 void assert_pipe(struct drm_i915_private *dev_priv,
 enum pipe pipe, bool state)
 {
@@ -1236,77 +1219,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
pipe_name(pipe), onoff(state), onoff(cur_state));
 }
 
-static void assert_plane(struct drm_i915_private *dev_priv,
-enum plane plane, bool state)
+static void assert_plane(struct intel_plane *plane, bool state)
 {
-   u32 val;
-   bool cur_state;
+   bool cur_state = plane->get_hw_state(plane);
 
-   val = I915_READ(DSPCNTR(plane));
-   cur_state = !!(val & DISPLAY_PLANE_ENABLE);
I915_STATE_WARN(cur_state != state,
-"plane %c assertion failure (expected %s, current %s)\n",
-   plane_name(plane), onoff(state), onoff(cur_state));
+   "%s assertion failure (expected %s, current %s)\n",
+   plane->base.name, onoff(state), onoff(cur_state));
 }
 
-#define assert_plane_enabled(d, p) assert_plane(d, p, true)
-#define assert_plane_disabled(d, p) assert_plane(d, p, false)
+#define assert_plane_enabled(p) assert_plane(p, true)
+#define assert_plane_disabled(p) assert_plane(p, false)
 
-static void assert_planes_disabled(struct drm_i915_private *dev_priv,
-  enum pipe pipe)
+static void assert_planes_disabled(struct intel_crtc *crtc)
 {
-   int i;
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   struct intel_plane *plane;
 
-   /* Primary planes are fixed to pipes on gen4+ */
-   if (INTEL_GEN(dev_priv) >= 4) {
-   u32 val = I915_READ(DSPCNTR(pipe));
-   I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
-"plane %c assertion failure, should be disabled but not\n",
-plane_name(pipe));
-   return;
-   }
-
-   /* Need to check both planes against the pipe */
-   for_each_pipe(dev_priv, i) {
-   u32 val = I915_READ(DSPCNTR(i));
-   enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
-   DISPPLANE_SEL_PIPE_SHIFT;
-   I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == 
cur_pipe,
-"plane %c assertion failure, should be off on pipe %c but 
is still active\n",
-plane_name(i), pipe_name(pipe));
-   }
-}
-
-static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
-   enum pipe pipe)
-{
-   int sprite;
-
-   if (INTEL_GEN(dev_priv) >= 9) {
-   for_each_sprite(dev_priv, pipe, sprite) {
-   u32 val = I915_READ(PLANE_CTL(pipe, sprite));
-   I915_STATE_WARN(val & PLANE_CTL_ENABLE,
-"plane %d assertion failure, should be off on pipe 
%c but is still active\n",
-sprite, pipe_name(pipe));
-   }
-   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-   

[Intel-gfx] [PATCH 2/9] drm/i915: Redo plane sanitation during readout

[Ville Syrjala]

From: Ville Syrjälä 

Unify the plane disabling during state readout by pulling the code into
a new helper intel_plane_disable_noatomic(). We'll also read out the
state of all planes, so that we know which planes really need to be
diabled.

Additonally we change the plane<->pipe mapping sanitation to work by
simply disabling the offending planes instead of entire pipes. And
we do it before we otherwise sanitize the crtcs, which means we don't
have to worry about misassigned planes during crtc sanitation anymore.

v2: Reoder patches to not depend on enum old_plane_id

Cc: Thierry Reding 
Cc: Alex Villacís Lasso 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103223
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 116 ---
 1 file changed, 67 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 825ab00b6639..a9fd3b8fa922 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2729,6 +2729,23 @@ intel_set_plane_visible(struct intel_crtc_state 
*crtc_state,
  crtc_state->active_planes);
 }
 
+static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
+struct intel_plane *plane)
+{
+   struct intel_crtc_state *crtc_state =
+   to_intel_crtc_state(crtc->base.state);
+   struct intel_plane_state *plane_state =
+   to_intel_plane_state(plane->base.state);
+
+   intel_set_plane_visible(crtc_state, plane_state, false);
+
+   if (plane->id == PLANE_PRIMARY)
+   intel_pre_disable_primary_noatomic(>base);
+
+   trace_intel_disable_plane(>base, crtc);
+   plane->disable_plane(plane, crtc);
+}
+
 static void
 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 struct intel_initial_plane_config *plane_config)
@@ -2786,12 +2803,7 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
 * simplest solution is to just disable the primary plane now and
 * pretend the BIOS never had it enabled.
 */
-   intel_set_plane_visible(to_intel_crtc_state(crtc_state),
-   to_intel_plane_state(plane_state),
-   false);
-   intel_pre_disable_primary_noatomic(_crtc->base);
-   trace_intel_disable_plane(primary, intel_crtc);
-   intel_plane->disable_plane(intel_plane, intel_crtc);
+   intel_plane_disable_noatomic(intel_crtc, intel_plane);
 
return;
 
@@ -5923,6 +5935,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc 
*crtc,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum intel_display_power_domain domain;
+   struct intel_plane *plane;
u64 domains;
struct drm_atomic_state *state;
struct intel_crtc_state *crtc_state;
@@ -5931,11 +5944,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc 
*crtc,
if (!intel_crtc->active)
return;
 
-   if (crtc->primary->state->visible) {
-   intel_pre_disable_primary_noatomic(crtc);
+   for_each_intel_plane_on_crtc(_priv->drm, intel_crtc, plane) {
+   const struct intel_plane_state *plane_state =
+   to_intel_plane_state(plane->base.state);
 
-   intel_crtc_disable_planes(crtc, 1 << 
drm_plane_index(crtc->primary));
-   crtc->primary->state->visible = false;
+   if (plane_state->base.visible)
+   intel_plane_disable_noatomic(intel_crtc, plane);
}
 
state = drm_atomic_state_alloc(crtc->dev);
@@ -14678,22 +14692,38 @@ void i830_disable_pipe(struct drm_i915_private 
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
 }
 
-static bool
-intel_check_plane_mapping(struct intel_crtc *crtc)
+static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
+  struct intel_plane *primary)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   u32 val;
+   enum plane plane = primary->plane;
+   u32 val = I915_READ(DSPCNTR(plane));
 
-   if (INTEL_INFO(dev_priv)->num_pipes == 1)
-   return true;
+   return (val & DISPLAY_PLANE_ENABLE) == 0 ||
+   (val & DISPPLANE_SEL_PIPE_MASK) == 
DISPPLANE_SEL_PIPE(crtc->pipe);
+}
 
-   val = I915_READ(DSPCNTR(!crtc->plane));
+static void
+intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+{
+   enum pipe pipe;
 
-   if ((val & DISPLAY_PLANE_ENABLE) &&
-   (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
-   return false;
+   if (INTEL_GEN(dev_priv) >= 4)
+   return;
 
-  

Re: [Intel-gfx] [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes

[Jani Nikula]

On Mon, 09 Oct 2017, Thierry Reding  wrote:
> On Mon, Oct 09, 2017 at 12:29:57PM +0300, Jani Nikula wrote:
>> Falling back to the lowest value is likely the only thing we can do, but
>> doing it silently seems like a bad thing to do. Catch it early and make
>> loud noises.
>> 
>> Cc: Alex Deucher 
>> Cc: Thierry Reding 
>> Cc: Rob Clark 
>> Cc: Sean Paul 
>> Cc: Manasi Navare 
>> Cc: dri-de...@lists.freedesktop.org
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/drm_dp_helper.c | 7 +--
>>  1 file changed, 5 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c 
>> b/drivers/gpu/drm/drm_dp_helper.c
>> index 08af8d6b844b..dca21b5a03ec 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>>  u8 drm_dp_link_rate_to_bw_code(int link_rate)
>>  {
>>  switch (link_rate) {
>> -case 162000:
>>  default:
>> +WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
>> + DP_LINK_BW_1_62);
>> +case 162000:
>>  return DP_LINK_BW_1_62;
>>  case 27:
>>  return DP_LINK_BW_2_7;
>> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
>>  int drm_dp_bw_code_to_link_rate(u8 link_bw)
>>  {
>>  switch (link_bw) {
>> -case DP_LINK_BW_1_62:
>>  default:
>> +WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw);
>
> Nit: "DP link BW" because it is an abbreviation. Otherwise looks good:

Thanks for the reviews everyone, pushed patch 1 with BW upcased to
drm-misc-next.

BR,
Jani.

>
> Reviewed-by: Thierry Reding 

-- 
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[Intel-gfx] [PATCH] softdog-info

[Chris Wilson]

Excuse the lack of context here, I have a headache.

References: https://bugs.freedesktop.org/show_bug.cgi?id=103160
---
 drivers/watchdog/softdog.c |  2 ++
 include/linux/watchdog.h   |  9 +
 kernel/watchdog.c  | 39 ---
 3 files changed, 35 insertions(+), 15 deletions(-)

diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c
index 060740625485..61b0bd333114 100644
--- a/drivers/watchdog/softdog.c
+++ b/drivers/watchdog/softdog.c
@@ -58,6 +58,8 @@ static struct hrtimer softdog_preticktock;
 
 static enum hrtimer_restart softdog_fire(struct hrtimer *timer)
 {
+   watchdog_softlockup(NULL, true);
+
module_put(THIS_MODULE);
if (soft_noboot) {
pr_crit("Triggered - Reboot ignored\n");
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index a786e5e8973b..811e15e08718 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -215,4 +215,13 @@ extern void watchdog_unregister_device(struct 
watchdog_device *);
 /* devres register variant */
 int devm_watchdog_register_device(struct device *dev, struct watchdog_device 
*);
 
+#if IS_ENABLED(CONFIG_LOCKUP_DETECTOR)
+extern void watchdog_softlockup(struct pt_regs *regs, bool show_backtrace);
+#else
+static inline void watchdog_softlockup(struct pt_regs *regs,
+  bool show_backtrace)
+{
+}
+#endif
+
 #endif  /* ifndef _LINUX_WATCHDOG_H */
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 6bcb854909c0..a111c4d34798 100644
--- a/kernel/watchdog.c
+++ b/kernel/watchdog.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -415,30 +416,21 @@ static enum hrtimer_restart watchdog_timer_fn(struct 
hrtimer *hrtimer)
}
 
pr_emerg("BUG: soft lockup - CPU#%d stuck for %us! [%s:%d]\n",
-   smp_processor_id(), duration,
-   current->comm, task_pid_nr(current));
-   __this_cpu_write(softlockup_task_ptr_saved, current);
-   print_modules();
-   print_irqtrace_events(current);
-   if (regs)
-   show_regs(regs);
-   else
-   dump_stack();
+smp_processor_id(), duration,
+current->comm, task_pid_nr(current));
+
+   watchdog_softlockup(regs, softlockup_all_cpu_backtrace);
+   if (softlockup_panic)
+   panic("softlockup: hung tasks");
 
if (softlockup_all_cpu_backtrace) {
/* Avoid generating two back traces for current
 * given that one is already made above
 */
-   trigger_allbutself_cpu_backtrace();
-
clear_bit(0, _lockup_nmi_warn);
/* Barrier to sync with other cpus */
smp_mb__after_atomic();
}
-
-   add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
-   if (softlockup_panic)
-   panic("softlockup: hung tasks");
__this_cpu_write(soft_watchdog_warn, true);
} else
__this_cpu_write(soft_watchdog_warn, false);
@@ -787,3 +779,20 @@ void __init lockup_detector_init(void)
nmi_watchdog_available = true;
lockup_detector_setup();
 }
+
+void watchdog_softlockup(struct pt_regs *regs, bool show_backtrace)
+{
+   __this_cpu_write(softlockup_task_ptr_saved, current);
+   print_modules();
+   print_irqtrace_events(current);
+   if (regs)
+   show_regs(regs);
+   else
+   dump_stack();
+
+   if (show_backtrace)
+   trigger_allbutself_cpu_backtrace();
+
+   add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
+}
+EXPORT_SYMBOL(watchdog_softlockup);
-- 
2.15.0.rc0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for softdog: Obey hardlockup_all_cpu_backtrace sysctl

[Patchwork]

== Series Details ==

Series: softdog: Obey hardlockup_all_cpu_backtrace sysctl
URL   : https://patchwork.freedesktop.org/series/31751/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  AR  drivers/watchdog/watchdog.o
  CC  drivers/watchdog/softdog.o
drivers/watchdog/softdog.c: In function ‘softdog_fire’:
drivers/watchdog/softdog.c:66:7: error: ‘sysctl_hardlockup_all_cpu_backtrace’ 
undeclared (first use in this function)
   if (sysctl_hardlockup_all_cpu_backtrace && 1)
   ^~~
drivers/watchdog/softdog.c:66:7: note: each undeclared identifier is reported 
only once for each function it appears in
drivers/watchdog/softdog.c:67:4: error: implicit declaration of function 
‘trigger_allbutself_cpu_backtrace’ [-Werror=implicit-function-declaration]
trigger_allbutself_cpu_backtrace();
^~~~
cc1: some warnings being treated as errors
scripts/Makefile.build:313: recipe for target 'drivers/watchdog/softdog.o' 
failed
make[2]: *** [drivers/watchdog/softdog.o] Error 1
scripts/Makefile.build:572: recipe for target 'drivers/watchdog' failed
make[1]: *** [drivers/watchdog] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [Intel-gfx] [PATCH v13 09/21] drm/i915/uc: Create uC suspend and resume functions

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:04 +0200, Sagar Arun Kamble  
 wrote:



Prepared generic helpers intel_uc_suspend, intel_uc_resume. These are
called from respective GEM functions. Only exception is intel_uc_resume
that needs to be called w/ or w/o GuC loaded in i915_drm_resume path.
Changes to add WOPCM condition check to load GuC during resume will be
added in later patches.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Calling intel_uc_resume from i915_gem_resume post resuming
i915 gem setup. This is symmetrical with i915_gem_suspend.
Removed error messages from i915 suspend/resume routines as
uC suspend/resume routines will have those. (Michal Wajdeczko)
Declare wedged on uc_suspend failure and uc_resume failure.
(Michał Winiarski)
Keeping the uC suspend/resume function definitions close to other
uC functions.

v4: Added implementation to intel_uc_resume as GuC resume is
needed to be triggered post reloading the firmware as well. Added
comments about semantics of GuC resume with the firmware reload.

v5: Updated return from i915_gem_runtime_suspend. Moved the comment
about GuC reload optimization to intel_uc_init_hw. (Michal Wajdeczko)
Updated comments as FIXME.

v6: Kept error handling for failure from i915_gem_runtime_suspend only.
We don't want GEM/GuC resume failure to impact intel_runtime_resume or
i915_drm_resume. GEM suspend failure along i915_drm_suspend can also
be ignored as we reset GPU post that. Updated comments. (Chris, Joonas)

v7: Removed intel_uc_resume from i915_drm_resume as it will be done as
part of intel_uc_init_hw in further patches. Removed TODO comments about
handling GuC load skip on resume. This is to be addressed in further
patches. Added error return from intel_uc_suspend as we plan to add
functionality to resume submission in case of suspend failure in further
patches. Removed runtime uC suspend/resume functions as functionality
will be similar in both paths.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c | 17 +++--
 drivers/gpu/drm/i915/intel_uc.c | 16 
 drivers/gpu/drm/i915/intel_uc.h |  2 ++
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index 38447ae..7d1b7e1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2056,11 +2056,13 @@ static void  
__i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)

 int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
 {
struct drm_i915_gem_object *obj, *on;
-   int i;
+   int i, ret;
mutex_lock(_priv->drm.struct_mutex);
-   intel_guc_suspend(_priv->guc);
+   ret = intel_uc_suspend(dev_priv);
+   if (ret)
+   goto out_unlock;
/*
 * Only called during RPM suspend. All users of the userfault_list
@@ -2098,9 +2100,10 @@ int i915_gem_runtime_suspend(struct  
drm_i915_private *dev_priv)

reg->dirty = true;
}
+out_unlock:
mutex_unlock(_priv->drm.struct_mutex);
-   return 0;
+   return ret;
 }
void i915_gem_runtime_resume(struct drm_i915_private *dev_priv)
@@ -2110,7 +2113,7 @@ void i915_gem_runtime_resume(struct  
drm_i915_private *dev_priv)

i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
-   intel_guc_resume(_priv->guc);
+   intel_uc_resume(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
 }
@@ -4681,7 +4684,9 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
mutex_lock(>struct_mutex);
-   intel_guc_suspend(_priv->guc);
+   ret = intel_uc_suspend(dev_priv);
+   if (ret)
+   goto err_unlock;
mutex_unlock(>struct_mutex);
/*
@@ -4730,7 +4735,7 @@ void i915_gem_resume(struct drm_i915_private  
*dev_priv)

 */
dev_priv->gt.resume(dev_priv);
-   intel_guc_resume(_priv->guc);
+   intel_uc_resume(dev_priv);
mutex_unlock(>struct_mutex);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 7305486..b5c132c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -283,3 +283,19 @@ void intel_uc_fini_hw(struct drm_i915_private  
*dev_priv)

if (i915_modparams.enable_guc_loading)
i915_ggtt_disable_guc(dev_priv);
 }
+
+int intel_uc_suspend(struct drm_i915_private *dev_priv)
+{
+   int ret;
+
+   ret = intel_guc_suspend(_priv->guc);
+   if (ret)
+   DRM_ERROR("Failed to suspend GuC\n");
+
+   return ret;
+}
+
+void intel_uc_resume(struct drm_i915_private *dev_priv)
+{

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use rcu instead of stop_machine in set_wedged (rev2)

[Daniel Vetter]

On Wed, Oct 11, 2017 at 02:56:52PM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Use rcu instead of stop_machine in set_wedged (rev2)
> URL   : https://patchwork.freedesktop.org/series/31664/
> State : success
> 
> == Summary ==
> 
> Test gem_eio:
> Subgroup in-flight-external:
> dmesg-warn -> PASS   (shard-hsw) fdo#102886 +4
> 
> fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
> 
> shard-hswtotal:2552 pass:1440 dwarn:1   dfail:0   fail:8   skip:1103 
> time:9638s
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5987/shards.html

CI approves, I push!
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v13 06/21] drm/i915/guc: Pass intel_guc struct parameter to intel_guc_suspend/resume

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:54:01 +0200, Sagar Arun Kamble  
 wrote:



intel_guc_suspend and intel_guc_resume are GuC specific functions hence
update the parameter from dev_priv to intel_guc struct. While at it do
s/dev_priv/i915 in suspend/resume functions.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c  |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c | 20 ++--
 drivers/gpu/drm/i915/intel_guc.h |  4 ++--
 4 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index 8e25846..a500a81 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1710,7 +1710,7 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
-   intel_guc_resume(dev_priv);
+   intel_guc_resume(_priv->guc);
intel_modeset_init_hw(dev);
@@ -2518,7 +2518,7 @@ static int intel_runtime_suspend(struct device  
*kdev)

 */
i915_gem_runtime_suspend(dev_priv);
-   intel_guc_suspend(dev_priv);
+   intel_guc_suspend(_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2603,7 +2603,7 @@ static int intel_runtime_resume(struct device  
*kdev)

if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
-   intel_guc_resume(dev_priv);
+   intel_guc_resume(_priv->guc);
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index e829e8c..276166d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4645,7 +4645,7 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
-   intel_guc_suspend(dev_priv);
+   intel_guc_suspend(_priv->guc);
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->gt.retire_work);
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index bbe4c32..9a2df69 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -169,20 +169,20 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32  
rsa_offset)

/**
  * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv:  i915 device private
+ * @guc: intel_guc struct
  */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
+int intel_guc_suspend(struct intel_guc *guc)
 {
-   struct intel_guc *guc = _priv->guc;
+   struct drm_i915_private *i915 = guc_to_i915(guc);
struct i915_gem_context *ctx;
u32 data[3];
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
-   gen9_disable_guc_interrupts(dev_priv);
+   gen9_disable_guc_interrupts(i915);
-   ctx = dev_priv->kernel_context;
+   ctx = i915->kernel_context;
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -196,11 +196,11 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

/**
  * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv:  i915 device private
+ * @guc: intel_guc struct
  */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
+int intel_guc_resume(struct intel_guc *guc)
 {
-   struct intel_guc *guc = _priv->guc;
+   struct drm_i915_private *i915 = guc_to_i915(guc);
struct i915_gem_context *ctx;
u32 data[3];
@@ -208,9 +208,9 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

return 0;
if (i915_modparams.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(dev_priv);
+   gen9_enable_guc_interrupts(i915);
-   ctx = dev_priv->kernel_context;
+   ctx = i915->kernel_context;
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index 5046264f..a587210 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -113,8 +113,8 @@ static inline bool  
i915_guc_submission_enabled(struct intel_guc *guc)
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32  
len);

 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
-int intel_guc_suspend(struct drm_i915_private *dev_priv);
-int intel_guc_resume(struct drm_i915_private *dev_priv);
+int intel_guc_suspend(struct intel_guc *guc);
+int intel_guc_resume(struct intel_guc 

Re: [Intel-gfx] [PATCH v13 04/21] drm/i915/guc: Remove enable_guc_submission dependency for invoking GuC log functions

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:53:59 +0200, Sagar Arun Kamble  
 wrote:



With guc_log_level parameter sanitized and GuC interrupts control
functions made self sufficient w.r.t interrupts state, we can remove
the enable_guc_submission checks from flush_guc_logs and
i915_guc_log_register/unregister and intel_uc_fini_hw.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 9 ++---
 drivers/gpu/drm/i915/intel_uc.c  | 3 +--
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c  
b/drivers/gpu/drm/i915/intel_guc_log.c

index 0f201c0..fb5eb2b9 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,7 @@ static void guc_flush_logs(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   if (!i915_guc_submission_enabled(guc) ||
-   i915_modparams.guc_log_level < 0)
+   if (i915_modparams.guc_log_level < 0)
return;
/* First disable the interrupts, will be renabled afterwards */
@@ -646,8 +645,7 @@ int i915_guc_log_control(struct drm_i915_private  
*dev_priv, u64 control_val)

void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-   if (!i915_guc_submission_enabled(_priv->guc) ||
-   i915_modparams.guc_log_level < 0)
+   if (i915_modparams.guc_log_level < 0)


I would expect above two fixes in patch 2/21


return;
mutex_lock(_priv->drm.struct_mutex);
@@ -657,9 +655,6 @@ void i915_guc_log_register(struct drm_i915_private  
*dev_priv)

void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-   if (!i915_guc_submission_enabled(_priv->guc))
-   return;


Hmm, as i915_guc_log_unregister() is called unconditionally by
i915_driver_unregister so maybe here we should have at least

if (i915_modparams.guc_log_level < 0)
return;


-
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
gen9_disable_guc_interrupts(dev_priv);


What about dropping this gen9_disable_guc_interrupts from here
and rely on the intel_uc_fini_hw() that will do the same?

diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 3cf3cbd..974434e 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -280,8 +280,7 @@ void intel_uc_fini_hw(struct drm_i915_private  
*dev_priv)

guc_disable_communication(guc);
-   if (i915_guc_submission_enabled(guc))
-   gen9_disable_guc_interrupts(dev_priv);
+   gen9_disable_guc_interrupts(dev_priv);
i915_guc_submission_fini(dev_priv);
i915_ggtt_disable_guc(dev_priv);


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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove unsafe i915.enable_rc6 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unsafe i915.enable_rc6 (rev2)
URL   : https://patchwork.freedesktop.org/series/21884/
State : success

== Summary ==

shard-hswtotal:2501 pass:1411 dwarn:6   dfail:0   fail:7   skip:1077 
time:9322s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5988/shards.html
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Re: [Intel-gfx] [PATCH v13 03/21] drm/i915/guc: Add status checks to enable/disable_guc_interrupts

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:53:58 +0200, Sagar Arun Kamble  
 wrote:



GuC interrupts are currently enabled by Logging and disabled in different
scenarios. Make disabling check whether interrupts were already disabled
and similar for enable path. This will remove the state tracking for the
callers of these functions based on kernel parameters.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_irq.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c  
b/drivers/gpu/drm/i915/i915_irq.c

index a3de408..6cf417c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -455,18 +455,22 @@ void gen9_reset_guc_interrupts(struct  
drm_i915_private *dev_priv)

void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   if (READ_ONCE(dev_priv->guc.interrupts_enabled))


Hmm, I don't like that functions from irq.c read and modify guc internal
members directly. I would expect that functions here just do their job
and any state is maintained by the helper function(s) in guc.c.

Also note that this change will not help scenario where one client will
try to disable irqs while other client still depends on them.

Michal


+   return;
+
spin_lock_irq(_priv->irq_lock);
-   if (!dev_priv->guc.interrupts_enabled) {
-   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
-  dev_priv->pm_guc_events);
-   dev_priv->guc.interrupts_enabled = true;
-   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-   }
+   WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+  dev_priv->pm_guc_events);
+   dev_priv->guc.interrupts_enabled = true;
+   gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
 }
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   if (!READ_ONCE(dev_priv->guc.interrupts_enabled))
+   return;
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;

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[Intel-gfx] [PATCH] softdog: Obey hardlockup_all_cpu_backtrace sysctl

[Daniel Vetter]

This is used by the nmi watchdog, but also useful by the softdog when
we're trying to figure out where exactly we're stuck.

Cc: Chris Wilson 
Cc: Imre Deak 
References: https://bugs.freedesktop.org/show_bug.cgi?id=103160
Signed-off-by: Daniel Vetter 

---

FIXME: Take the && 1 out once CI is configured to enable this.
-Daniel
---
 drivers/watchdog/softdog.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c
index 060740625485..3a1606011b17 100644
--- a/drivers/watchdog/softdog.c
+++ b/drivers/watchdog/softdog.c
@@ -63,6 +63,8 @@ static enum hrtimer_restart softdog_fire(struct hrtimer 
*timer)
pr_crit("Triggered - Reboot ignored\n");
} else if (soft_panic) {
pr_crit("Initiating panic\n");
+   if (sysctl_hardlockup_all_cpu_backtrace && 1)
+   trigger_allbutself_cpu_backtrace();
panic("Software Watchdog Timer expired");
} else {
pr_crit("Initiating system reboot\n");
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use rcu instead of stop_machine in set_wedged (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Use rcu instead of stop_machine in set_wedged (rev2)
URL   : https://patchwork.freedesktop.org/series/31664/
State : success

== Summary ==

Test gem_eio:
Subgroup in-flight-external:
dmesg-warn -> PASS   (shard-hsw) fdo#102886 +4

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886

shard-hswtotal:2552 pass:1440 dwarn:1   dfail:0   fail:8   skip:1103 
time:9638s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5987/shards.html
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Re: [Intel-gfx] [PATCH v13 02/21] drm/i915/guc: Sanitize module parameter guc_log_level

[Michal Wajdeczko]

On Wed, 11 Oct 2017 10:53:57 +0200, Sagar Arun Kamble  
 wrote:



Parameter guc_log_level needs to be sanitized based on GuC support and
enable_guc_loading parameter since it depends on them like
enable_guc_submission. This will make GuC logging paths independent of
enable_guc_submission parameter in further patches.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index b33d469..3cf3cbd 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -56,6 +56,7 @@ void intel_uc_sanitize_options(struct drm_i915_private  
*dev_priv)


Btw, I think the message "Ignoring GuC options, no hardware\n" is also
applicable when user specified guc_log_level>=0. Please update condition
that controls that message.


i915_modparams.enable_guc_loading = 0;
i915_modparams.enable_guc_submission = 0;
+   i915_modparams.guc_log_level = -1;
return;
}
@@ -72,9 +73,11 @@ void intel_uc_sanitize_options(struct  
drm_i915_private *dev_priv)

i915_modparams.enable_guc_loading = 0;
}
-   /* Can't enable guc submission without guc loaded */
-   if (!i915_modparams.enable_guc_loading)
+   /* Can't enable guc submission and logging without guc loaded */
+   if (!i915_modparams.enable_guc_loading) {
i915_modparams.enable_guc_submission = 0;
+   i915_modparams.guc_log_level = -1;
+   }
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc_submission < 0)


Looks good, but please also update condition in i915_guc_log_register()
as we may now rely only on sanitized guc_log_level:

void i915_guc_log_register(struct drm_i915_private *dev_priv)
{
if (!i915_modparams.enable_guc_submission ||
 
(i915_modparams.guc_log_level < 0))
return;

Also, maybe it is worth to update DOC in intel_guc_log.c and param
description in i915_params.c to indicate (obvious) dependency on guc.

Michal
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