[Intel-gfx] [PATCH] drm/doc: Fix documentation for _vblank_restore().

No code changes, fixes doc build warnings and polish some doc text. Reported-by: Daniel Vetter Cc: Rodrigo Vivi Cc: Daniel Vetter Signed-off-by: Dhinakaran Pandiyan ---

Re: [Intel-gfx] [PATCH] [V4] drm/i915: Enable VBT based BL control for DP

On Wed, 21 Feb 2018, Mustamin B Mustaffa wrote: > Currently, BXT_PP is hardcoded with value '0'. > It practically disabled eDP backlight on MRB (BXT) platform. > > This patch will tell which BXT_PP registers (there are two set of > PP_CONTROL in the spec) to be used

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/3] drm/i915: Share PSR and PSR2 VSC setup

== Series Details == Series: series starting with [1/3] drm/i915: Share PSR and PSR2 VSC setup URL : https://patchwork.freedesktop.org/series/38654/ State : warning == Summary == Test kms_cursor_crc: Subgroup cursor-256x256-suspend: incomplete -> PASS (shard-hsw)

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/guc: Use correct error code for GuC initialization failure

== Series Details == Series: series starting with [v2,1/2] drm/i915/guc: Use correct error code for GuC initialization failure URL : https://patchwork.freedesktop.org/series/38640/ State : failure == Summary == Test kms_vblank: Subgroup pipe-c-wait-idle: dmesg-warn ->

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/huc: Mark firmware as failed on auth failure

== Series Details == Series: drm/i915/huc: Mark firmware as failed on auth failure URL : https://patchwork.freedesktop.org/series/38639/ State : failure == Summary == Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-left-edge: pass -> DMESG-WARN (shard-snb)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev5)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) (rev5) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Series 38559v5 drm/i915: Enable VBT based BL control for DP (v3)

[Intel-gfx] [PATCH] [V4] drm/i915: Enable VBT based BL control for DP

Currently, BXT_PP is hardcoded with value '0'. It practically disabled eDP backlight on MRB (BXT) platform. This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP backlight

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/i915: Clean-up and organize transition WM code.

== Series Details == Series: series starting with [1/2] drm/i915: Clean-up and organize transition WM code. URL : https://patchwork.freedesktop.org/series/38629/ State : warning == Summary == Test kms_cursor_legacy: Subgroup 2x-long-flip-vs-cursor-legacy: fail

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix the frame buffer fence starvation

== Series Details == Series: drm/i915: Fix the frame buffer fence starvation URL : https://patchwork.freedesktop.org/series/38626/ State : success == Summary == Test perf: Subgroup enable-disable: pass -> FAIL (shard-apl) fdo#103715 Test kms_cursor_legacy:

Re: [Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

Thank you. Will include the RB in the next series. Regards Vidya > -Original Message- > From: Kahola, Mika > Sent: Tuesday, February 13, 2018 4:05 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 03/16]

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add and enable DP AUX CH mutex

== Series Details == Series: drm/i915: Add and enable DP AUX CH mutex URL : https://patchwork.freedesktop.org/series/38655/ State : success == Summary == Series 38655v1 drm/i915: Add and enable DP AUX CH mutex https://patchwork.freedesktop.org/api/1.0/series/38655/revisions/1/mbox/ Test

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add and enable DP AUX CH mutex

== Series Details == Series: drm/i915: Add and enable DP AUX CH mutex URL : https://patchwork.freedesktop.org/series/38655/ State : warning == Summary == $ dim checkpatch origin/drm-tip c4130a3bc92e drm/i915: Add and enable DP AUX CH mutex -:13: WARNING: Possible unwrapped commit description

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Share PSR and PSR2 VSC setup

== Series Details == Series: series starting with [1/3] drm/i915: Share PSR and PSR2 VSC setup URL : https://patchwork.freedesktop.org/series/38654/ State : success == Summary == Series 38654v1 series starting with [1/3] drm/i915: Share PSR and PSR2 VSC setup

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Explicit Raw and Adjusted WM latencies.

== Series Details == Series: drm/i915: Explicit Raw and Adjusted WM latencies. URL : https://patchwork.freedesktop.org/series/38652/ State : failure == Summary == Series 38652v1 drm/i915: Explicit Raw and Adjusted WM latencies.

[Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it self, so lets use the mutex register that is available in gen9+ to avoid concurrent access by hardware and driver. Reference: https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf Page 198 -

[Intel-gfx] [PATCH v2 0/1] drm/i915: Add and enable DP AUX CH mutex

v2 of https://lists.freedesktop.org/archives/intel-gfx/2018-February/155502.html and https://lists.freedesktop.org/archives/intel-gfx/2018-February/155498.html Changelog: - removed the PSR dependency, now getting lock all the times when available - renamed functions to avoid nested calls -

[Intel-gfx] [PATCH 1/3] drm/i915: Share PSR and PSR2 VSC setup

Just share the common code in PSR and PSR2. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index

[Intel-gfx] [PATCH 2/3] drm/i915: Replace magic number with macro defined by drm

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 71801a25a2b3..3fc1bdd65b14 100644 ---

[Intel-gfx] [PATCH 3/3] drm/i915: Remove unused variable in hsw_write_infoframe()

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_hdmi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index f5d7bfb43006..fe4bef081dae 100644 ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Explicit Raw and Adjusted WM latencies.

== Series Details == Series: drm/i915: Explicit Raw and Adjusted WM latencies. URL : https://patchwork.freedesktop.org/series/38652/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8568ad0cbdd4 drm/i915: Explicit Raw and Adjusted WM latencies. -:56: CHECK: braces {} should be

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Include fence-hint for timeout warning (rev2)

== Series Details == Series: drm/i915: Include fence-hint for timeout warning (rev2) URL : https://patchwork.freedesktop.org/series/20264/ State : warning == Summary == Test kms_busy: Subgroup extended-modeset-hang-newfb-render-c: pass -> DMESG-WARN (shard-apl)

[Intel-gfx] [PATCH] drm/i915: Explicit Raw and Adjusted WM latencies.

Current code has some limitations: 1. debugfs only shows raw latency we read from PCODE, not the ones we are configuring. 2. When determining if SAGV can be enabled we only apply adjusted wa, but we don't apply the IPC one. So there is the risk of enabling SAGV when we should actually disable

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reduce context HW ID lifetime

On 09/02/18 20:47, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-02-09 18:56:36) On 09/02/18 02:22, Chris Wilson wrote: Future gen reduce the number of bits we will have available to differentiate between contexts, so reduce the lifetime of the ID assignment from that of the

Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

On Wed, Feb 21, 2018 at 12:04:43AM +, Mustaffa, Mustamin B wrote: > Hi Ville, > > Can you point out what makes you says the git diff is broken? Because your diff shows like the change was in vlv_ fucntion, not on bxt_ one... If it wasn't by the TODO comment block I'd reply that your code

Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

Hi Ville, Can you point out what makes you says the git diff is broken? Best regard Mustamin -Original Message- From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] Sent: Tuesday, February 20, 2018 10:26 PM To: Mustaffa, Mustamin B Cc:

Re: [Intel-gfx] [PATCH] drm/i915: fix the issue DP-1 not working in guest

Hi Jani, In GVT (virtualization) environment, it only can use DP. Therefore, we want to enable Port A as DP so that display panel on Port A can be used by GVT. Best regard Mustamin -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Tuesday, February

Re: [Intel-gfx] [PATCH] drm/todo: i915 could use device_link_add

On Tue, Feb 20, 2018 at 04:17:19PM +0200, Imre Deak wrote: > On Tue, Feb 20, 2018 at 02:20:17PM +0100, Daniel Vetter wrote: > > Noticed while reading some unrelated patches. Unfortunately Imre's > > patch to add our early/late hooks predated the device_link > > infrastructure by 2 years. > > > >

[Intel-gfx] [PATCH igt] lib/dummyload: Avoid assertions in lowlevel spin constructor

__igt_spin_batch_new() may be used inside a background helper which is competing against the GPU being reset. As such, we cannot even assert that the spin->handle is busy immediately after submission as it may have already been reset by another client writing to i915_wedged. Signed-off-by: Chris

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: Use correct error code for GuC initialization failure

== Series Details == Series: series starting with [v2,1/2] drm/i915/guc: Use correct error code for GuC initialization failure URL : https://patchwork.freedesktop.org/series/38640/ State : success == Summary == Series 38640v1 series starting with [v2,1/2] drm/i915/guc: Use correct error

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/huc: Mark firmware as failed on auth failure

== Series Details == Series: drm/i915/huc: Mark firmware as failed on auth failure URL : https://patchwork.freedesktop.org/series/38639/ State : success == Summary == Series 38639v1 drm/i915/huc: Mark firmware as failed on auth failure

[Intel-gfx] [PATCH v2 2/2] HAX: Enable GuC for CI

v2: except running with HYPERVISOR Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h

[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC initialization, including special one that indicates request to run driver with disabled GPU submission (-EIO). Unfortunately since commit 121981fafe69

[Intel-gfx] [PATCH] drm/i915/huc: Mark firmware as failed on auth failure

If we fail to authenticate HuC firmware, we should change its load status to FAIL. While around, print HUC_STATUS on firmware verification failure. Signed-off-by: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Anusha Srivatsa

Re: [Intel-gfx] [PATCH igt] igt/gem_eio: Exercise set-wedging against request submission

Quoting Antonio Argenziano (2018-02-20 22:31:58) > On 07/02/18 01:50, Chris Wilson wrote: > > +static void test_set_wedged(int fd) > > +{ > > +#define NCTX 4096 > > + const uint32_t bbe = MI_BATCH_BUFFER_END; > > + const int ring_size = measure_ring_size(fd, 0) - 1; > > + struct

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clean-up and organize transition WM code.

On Tue, Feb 20, 2018 at 09:03:16PM +, Chris Wilson wrote: > Quoting Rodrigo Vivi (2018-02-20 19:09:18) > > Transition WM exist on gen9 but it is not recommended. > > > > Let's make this decision clear and call rename the > > function from "skl_" to "cnl_" so we don't have false > >

Re: [Intel-gfx] [PATCH igt] igt/gem_eio: Exercise set-wedging against request submission

On 07/02/18 01:50, Chris Wilson wrote: Build up a large stockpile of requests, ~500,000, and feed them into the system at 20KHz whilst simultaneously triggering set-wedged in order to try and race i915_gem_set_wedged() against the engine->submit_request() callback. Signed-off-by: Chris Wilson

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs

== Series Details == Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs URL : https://patchwork.freedesktop.org/series/38604/ State : warning == Summary == Test kms_flip: Subgroup 2x-plain-flip-fb-recreate-interruptible: pass -> FAIL

[Intel-gfx] [PATCH igt] igt/perf_pmu: Disable all cpus

Rather than iteratively disable and then immediately reenable a CPU, turn off each in turn, forcing the PMU events onto the next CPU without allowing them to retreat back to CPU0 after the first. If this fails, immediately reboot the system. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clean-up and organize transition WM code.

Quoting Rodrigo Vivi (2018-02-20 19:09:18) > Transition WM exist on gen9 but it is not recommended. > > Let's make this decision clear and call rename the > function from "skl_" to "cnl_" so we don't have false > expectations that transitions should be running on CNL. s/CNL/SKL/ -Chris

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clean-up and organize transition WM code.

Quoting Rodrigo Vivi (2018-02-20 19:09:18) > Transition WM exist on gen9 but it is not recommended. > > Let's make this decision clear and call rename the > function from "skl_" to "cnl_" so we don't have false > expectations that transitions should be running on CNL. > > Also we remove two

Re: [Intel-gfx] [PATCH] drm/i915: Fix the frame buffer fence starvation

Quoting Guang Bai (2018-02-20 11:41:03) > Currently a tiled frame buffer to be scanned out is always installed > with a fence, leading to fence starvation on gen9lp virtualization > use case where graphics stacks of service and guest OSes compete for > fences. > > By design, this fence is always

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/4] drm/i915: Also check view->type for a normal GGTT view

Quoting Patchwork (2018-02-20 20:36:53) > == Series Details == > > Series: series starting with [v2,1/4] drm/i915: Also check view->type for a > normal GGTT view > URL : https://patchwork.freedesktop.org/series/38593/ > State : failure > > == Summary == > > Test kms_flip: > Subgroup

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/4] drm/i915: Also check view->type for a normal GGTT view

== Series Details == Series: series starting with [v2,1/4] drm/i915: Also check view->type for a normal GGTT view URL : https://patchwork.freedesktop.org/series/38593/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

Quoting Zhenyu Wang (2018-02-14 05:28:27) > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for > chinese new year, team would take one week off at least, so like to > send this out before vacation. This has one to fix GTT mmio 8b access > from guest and two simple ones for mmio

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Tue, 2018-02-20 at 10:44 -0800, Rodrigo Vivi wrote: > On Tue, Feb 20, 2018 at 06:25:38PM +0200, Imre Deak wrote: > > On Tue, Feb 20, 2018 at 05:35:20PM +0200, Imre Deak wrote: > > > On Mon, Feb 19, 2018 at 05:49:41PM +0200, Ville Syrjälä wrote: > > > > On Mon, Feb 19, 2018 at 04:47:41PM

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clean-up and organize transition WM code.

== Series Details == Series: series starting with [1/2] drm/i915: Clean-up and organize transition WM code. URL : https://patchwork.freedesktop.org/series/38629/ State : success == Summary == Series 38629v1 series starting with [1/2] drm/i915: Clean-up and organize transition WM code.

Re: [Intel-gfx] [V3] drm/i915: Enable VBT based BL control for DP

On Tue, Feb 20, 2018 at 11:43:57AM +0200, Jani Nikula wrote: > On Tue, 20 Feb 2018, Chris Wilson wrote: > > Quoting Mustaffa, Mustamin B (2018-02-20 08:44:45) > >> Hi Chris, > >> > >> Would you rather for me to use following line instead? > >> > >> + int

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Clean-up and organize transition WM code.

== Series Details == Series: series starting with [1/2] drm/i915: Clean-up and organize transition WM code. URL : https://patchwork.freedesktop.org/series/38629/ State : warning == Summary == $ dim checkpatch origin/drm-tip 28d5d357b8fe drm/i915: Clean-up and organize transition WM code.

Re: [Intel-gfx] [PATCH] drm/i915: Enable VBT based BL control for DP (v3)

On Tue, Feb 20, 2018 at 10:46:45AM +0800, Mustamin B Mustaffa wrote: > Currently, BXT_PP is hardcoded with value '0'. > It practically disabled eDP backlight on MRB (BXT) platform. > > This patch will tell which BXT_PP registers (there are two set of PP_CONTROL > in the spec) > to be used as

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix the frame buffer fence starvation

== Series Details == Series: drm/i915: Fix the frame buffer fence starvation URL : https://patchwork.freedesktop.org/series/38626/ State : success == Summary == Series 38626v1 drm/i915: Fix the frame buffer fence starvation

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Collect aux ch vfunc setup into intel_dp_aux_init()

On Tue, Feb 20, 2018 at 07:05:24PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Collect all the aux ch vfunc assignments into intel_dp_aux_init() > instead of having it spread around. Makes sense and seems cleaner and right. > > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges,

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix the frame buffer fence starvation

== Series Details == Series: drm/i915: Fix the frame buffer fence starvation URL : https://patchwork.freedesktop.org/series/38626/ State : warning == Summary == $ dim checkpatch origin/drm-tip f9fb22a0f4c9 drm/i915: Fix the frame buffer fence starvation -:29: CHECK: Alignment should match

Re: [Intel-gfx] [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

On 17/02/18 06:17, Sagar Arun Kamble wrote: On 2/17/2018 5:48 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-02-17 12:10:32) On 2/17/2018 2:34 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2018-02-17 08:51:44) Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE,

[Intel-gfx] [PATCH 1/2] drm/i915: Clean-up and organize transition WM code.

Transition WM exist on gen9 but it is not recommended. Let's make this decision clear and call rename the function from "skl_" to "cnl_" so we don't have false expectations that transitions should be running on CNL. Also we remove two redundant checks inside this function if (gen <= 9) exit if

[Intel-gfx] [PATCH 2/2] drm/i915: Remove CNL A0 exclusive WA.

We never added any other CNL A0 workaround because we never got any A0 platform. So besides never being executed it is not valid for reference anymore since it is not applicable to ICL. So let's start some clean up here. Cc: Chris Wilson Cc: Mahesh Kumar

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Drop WaDoubleCursorLP3Latency:ivb

On Wed, Jan 31, 2018 at 04:10:10PM +0200, Mika Kahola wrote: > On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > WaDoubleCursorLP3Latency was meant for pre-production hardware. > > Drop it. > > > Reviewed-by: Mika Kahola

[Intel-gfx] [PATCH v2 2/3] drm/i915: Nuke aux regs from intel_dp

From: Ville Syrjälä Just store function pointers that give us the correct register offsets instead of storing the register offsets themselves. Slightly less efficient perhaps but saves a few bytes and better matches how we do things elsewhere. v2: Keep a local

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: GuC test run (rev2)

== Series Details == Series: drm/i915: GuC test run (rev2) URL : https://patchwork.freedesktop.org/series/38615/ State : failure == Summary == Series 38615v2 drm/i915: GuC test run https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/2/mbox/ Test core_auth: Subgroup

Re: [Intel-gfx] [PATCH] drm/i915: Remove unused IRQ chip data of HDMI LPE audio

On Mon, Jan 29, 2018 at 07:09:22PM +0200, Ville Syrjälä wrote: > On Wed, Dec 13, 2017 at 03:06:55PM +0100, Thomas Gleixner wrote: > > On Wed, 13 Dec 2017, Takashi Iwai wrote: > > > On Wed, 13 Dec 2017 12:35:54 +0100, > > > Thomas Gleixner wrote: > > > > > > > > > > On Mon, 11 Dec 2017, Anand,

[Intel-gfx] [PATCH] drm/i915: Fix the frame buffer fence starvation

Currently a tiled frame buffer to be scanned out is always installed with a fence, leading to fence starvation on gen9lp virtualization use case where graphics stacks of service and guest OSes compete for fences. By design, this fence is always needed by i965-(GEN4-) platforms. For GEN4 and

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Tue, Feb 20, 2018 at 06:25:38PM +0200, Imre Deak wrote: > On Tue, Feb 20, 2018 at 05:35:20PM +0200, Imre Deak wrote: > > On Mon, Feb 19, 2018 at 05:49:41PM +0200, Ville Syrjälä wrote: > > > On Mon, Feb 19, 2018 at 04:47:41PM +0200, Imre Deak wrote: > > > > On Fri, Feb 16, 2018 at 04:27:04PM

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Include fence-hint for timeout warning (rev2)

== Series Details == Series: drm/i915: Include fence-hint for timeout warning (rev2) URL : https://patchwork.freedesktop.org/series/20264/ State : success == Summary == Series 20264v2 drm/i915: Include fence-hint for timeout warning

[Intel-gfx] [CI v2] drm/i915: GuC test run

From: Tvrtko Ursulin With disabled aggressive idling from IGT. To see how shard run fares. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 1

[Intel-gfx] [CI] drm/i915: Include fence-hint for timeout warning

If an asynchronous wait on a foriegn fence, we print a warning indicating which fence was not signaled. As i915_sw_fences become more common, include the debug hint (the symbol-name of the target) to help identify the waiter. E.g. [ 31.968144] Asynchronous wait on fence sw_sync:gem_eio:1 timed

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: GuC test run

== Series Details == Series: drm/i915: GuC test run URL : https://patchwork.freedesktop.org/series/38615/ State : failure == Summary == Series 38615v1 drm/i915: GuC test run https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/1/mbox/ Test core_auth: Subgroup basic-auth:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GuC test run

== Series Details == Series: drm/i915: GuC test run URL : https://patchwork.freedesktop.org/series/38615/ State : warning == Summary == $ dim checkpatch origin/drm-tip a6558de0fe3a drm/i915: GuC test run -:20: WARNING: please, no space before tabs #20: FILE:

[Intel-gfx] ✗ Fi.CI.BAT: warning for kernel: Downgrade warning for unsafe parameters

== Series Details == Series: kernel: Downgrade warning for unsafe parameters URL : https://patchwork.freedesktop.org/series/38614/ State : warning == Summary == Series 38614v1 kernel: Downgrade warning for unsafe parameters

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Nuke aux regs from intel_dp

Quoting Ville Syrjälä (2018-02-20 17:49:43) > On Tue, Feb 20, 2018 at 05:30:51PM +, Chris Wilson wrote: > > Quoting Ville Syrjala (2018-02-20 17:05:23) > > > @@ -1089,7 +1089,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > > > struct intel_digital_port *intel_dig_port = > > >

[Intel-gfx] [PATCH libdrm 2/2] intel: allocate buffer with the requested size when reuse is disabled

From: "Xiong, James" Previously a bucket size was used for buffer allocation whether bo_reuse is false or true. This patch returns NULL in function drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the original requested size is used instead. Signed-off-by:

[Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Nuke aux regs from intel_dp

On Tue, Feb 20, 2018 at 05:30:51PM +, Chris Wilson wrote: > Quoting Ville Syrjala (2018-02-20 17:05:23) > > From: Ville Syrjälä > > > > Just store function pointers that give us the correct register offsets > > instead of storing the register offsets

[Intel-gfx] [PATCH libdrm 0/2] improve reuse implementation

From: "Xiong, James" This series 1) align the reuse buffer size to page size instead. The goal is to reduce memory penalty (up to 25% when reuse is enabled ) while maintain similar performance. A potential overhead is: since a bucket now contains cached buffers with

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for kernel: Downgrade warning for unsafe parameters

== Series Details == Series: kernel: Downgrade warning for unsafe parameters URL : https://patchwork.freedesktop.org/series/38614/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4bde7ab1ac4f kernel: Downgrade warning for unsafe parameters -:27: ERROR: Missing Signed-off-by:

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

Quoting Ville Syrjala (2018-02-20 17:05:22) > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges, and we get rid of the

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38612/ State : success == Summary == Series 38612v1 series starting with [1/3] drm/i915: Add enum aux_ch and clean up the aux

[Intel-gfx] [CI] drm/i915: GuC test run

From: Tvrtko Ursulin With disabled aggressive idling from IGT. To see how shard run fares. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 3

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Nuke aux regs from intel_dp

Quoting Ville Syrjala (2018-02-20 17:05:23) > From: Ville Syrjälä > > Just store function pointers that give us the correct register offsets > instead of storing the register offsets themselves. Slightly less > efficient perhaps but saves a few bytes and better

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38612/ State : warning == Summary == $ dim checkpatch origin/drm-tip b454295ca54f drm/i915: Add enum aux_ch and clean up the

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Collect aux ch vfunc setup into intel_dp_aux_init()

Quoting Ville Syrjala (2018-02-20 17:05:24) > From: Ville Syrjälä > > Collect all the aux ch vfunc assignments into intel_dp_aux_init() > instead of having it spread around. > > Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson

Re: [Intel-gfx] [PATCH] [CI] kernel: Downgrade warning for unsafe parameters

Quoting Chris Wilson (2018-02-20 17:18:42) > We make use of unsafe kernel parameters in igt, which generates a > warning and taints the kernel. The warning is unhelpful as we then need > to filter it out again, so kill it at source. > > Cc: Petri Latvala > Cc: Daniel

[Intel-gfx] [PATCH] [CI] kernel: Downgrade warning for unsafe parameters

We make use of unsafe kernel parameters in igt, which generates a warning and taints the kernel. The warning is unhelpful as we then need to filter it out again, so kill it at source. Cc: Petri Latvala Cc: Daniel Vetter --- kernel/params.c | 4

[Intel-gfx] [PATCH 3/3] drm/i915: Collect aux ch vfunc setup into intel_dp_aux_init()

From: Ville Syrjälä Collect all the aux ch vfunc assignments into intel_dp_aux_init() instead of having it spread around. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 53

[Intel-gfx] [PATCH 2/3] drm/i915: Nuke aux regs from intel_dp

From: Ville Syrjälä Just store function pointers that give us the correct register offsets instead of storing the register offsets themselves. Slightly less efficient perhaps but saves a few bytes and better matches how we do things elsewhere. Signed-off-by: Ville

[Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

From: Ville Syrjälä Since we no longer have a 1:1 correspondence between ports and AUX channels, let's give AUX channels their own enum. Makes it easier to tell the apples from the oranges, and we get rid of the port E AUX power domain FIXME since we now derive the

[Intel-gfx] [igt CI 3/3] igt/gem_exec_schedule: Replace constant 16 with its magic macro

s/16/MAX_ELSP_QLEN/ as appropriate v2: Use ARRAY_SIZE for loop bounds over fixed size arrays Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- tests/gem_exec_schedule.c | 19 +++ 1 file changed, 11

[Intel-gfx] [igt CI 1/3] igt/gem_exec_schedule: Trim max number of contexts used

icl offers a much reduced context space, and in its simplest setup we cannot allocate one context per priority level, so trim the number and reuse the same context for multiple priority requests. v2: Bump the MAX to 1024 (still lower than the ~4096 previously in use) v3: Also limit NCTX to

[Intel-gfx] [igt CI 2/3] igt/gem_exec_schedule: Dump the engine info prior to sync on preempt_other

It is useful to dump the request layout between engines help debug ordering issues and stuck preemption, so add it to preempt_other(). Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- tests/gem_exec_schedule.c | 1 + 1

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/mm: Fix caching of leftmost node in the interval tree (rev2)

Quoting Patchwork (2018-02-20 14:03:13) > == Series Details == > > Series: drm/mm: Fix caching of leftmost node in the interval tree (rev2) > URL : https://patchwork.freedesktop.org/series/38351/ > State : success > > == Summary == > > Test kms_cursor_crc: > Subgroup

Re: [Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Wait for PSR to be disabled

Quoting Daniel Vetter (2018-02-20 15:44:38) > On Tue, Feb 20, 2018 at 02:33:08PM +, Chris Wilson wrote: > > PSR may not exit instantaneously, so while asserting that PSR is > > disabled after an action, we may have to wait a short while. Currently > > that wait is waiting for PSR to enabled

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Tue, Feb 20, 2018 at 05:35:20PM +0200, Imre Deak wrote: > On Mon, Feb 19, 2018 at 05:49:41PM +0200, Ville Syrjälä wrote: > > On Mon, Feb 19, 2018 at 04:47:41PM +0200, Imre Deak wrote: > > > On Fri, Feb 16, 2018 at 04:27:04PM -0800, Rodrigo Vivi wrote: > > > > On Fri, Feb 16, 2018 at 03:25:55PM

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs

== Series Details == Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs URL : https://patchwork.freedesktop.org/series/38604/ State : success == Summary == Series 38604v1 series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs

== Series Details == Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs URL : https://patchwork.freedesktop.org/series/38604/ State : warning == Summary == $ dim checkpatch origin/drm-tip 976122bb3624 drm/i915/icl: Add the ICL PCI IDs -:47: ERROR: Macros with complex values

Re: [Intel-gfx] [PATCH v2 3/8] drm/atomic: Include color encoding/range in plane state dump

On 2018-02-19 03:28 PM, Ville Syrjala wrote: > From: Ville Syrjälä > > Include color_enconding and color_range in the plane state dump. > > v2: Add kerneldoc (danvet) > > Cc: Harry Wentland > Cc: Daniel Vetter > Cc:

Re: [Intel-gfx] [PATCH igt] igt/kms_frontbuffer_tracking: Wait for PSR to be disabled

On Tue, Feb 20, 2018 at 02:33:08PM +, Chris Wilson wrote: > PSR may not exit instantaneously, so while asserting that PSR is > disabled after an action, we may have to wait a short while. Currently > that wait is waiting for PSR to enabled and expecting to timeout; this > fails when we start

[Intel-gfx] [PATCH 3/4] drm/i915/icl: Prepare for more rings

From: Tvrtko Ursulin Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be

[Intel-gfx] [PATCH 4/4] drm/i915/icl: Interrupt handling

v2: Rebase. v3: * Remove DPF, it has been removed from SKL+. * Fix -internal rebase wrt. execlists interrupt handling. v4: Rebase. v5: * Updated for POR changes. (Daniele Ceraolo Spurio) * Merged with irq handling fixes by Daniele Ceraolo Spurio: * Simplify the code by using

[Intel-gfx] [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs

From: Paulo Zanoni This is the current PCI ID list in our documentation. Let's leave the _gt#_ part out for now since our current documentation is not 100% clear and we don't need this info now anyway. v2: Use the new ICL_11 naming (Kelvin Gardiner). v3: Latest IDs as

[Intel-gfx] [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs

From: Tvrtko Ursulin Show GEN11 specific interrupt registers in debugfs v2: Update for POR changes. (Daniele Ceraolo Spurio) v3: get runtime pm ref. unify common parts with gen8 (Daniele) Cc: Ceraolo Spurio, Daniele Signed-off-by:

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Mon, Feb 19, 2018 at 05:49:41PM +0200, Ville Syrjälä wrote: > On Mon, Feb 19, 2018 at 04:47:41PM +0200, Imre Deak wrote: > > On Fri, Feb 16, 2018 at 04:27:04PM -0800, Rodrigo Vivi wrote: > > > On Fri, Feb 16, 2018 at 03:25:55PM -0800, Dhinakaran Pandiyan wrote: > > > > PSR requires AUX IO well

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