Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Do not do fb src adjustments for NV12

> -Original Message- > From: Saarinen, Jani > Sent: Wednesday, April 18, 2018 11:07 AM > To: Srinivas, Vidya ; Maarten Lankhorst > ; intel-gfx@lists.freedesktop.org > Cc: Kamath, Sunil > Subject: RE:

Re: [Intel-gfx] [PATCH] gpu: drm: i915: Change return type to vm_fault_t

On Tue, 17 Apr 2018, Souptick Joarder wrote: > On 17-Apr-2018 9:45 PM, "Matthew Wilcox" wrote: >> >> On Tue, Apr 17, 2018 at 09:14:32PM +0530, Souptick Joarder wrote: >> > Not exactly. The plan for these patches is to introduce new vm_fault_t > type >>

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Do not do fb src adjustments for NV12

Hi, > -Original Message- > From: Srinivas, Vidya > Sent: keskiviikko 18. huhtikuuta 2018 6.56 > To: Saarinen, Jani ; Maarten Lankhorst > ; intel-gfx@lists.freedesktop.org > Cc: Kamath, Sunil > Subject:

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable NV12 support (rev2)

== Series Details == Series: Enable NV12 support (rev2) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4060_full -> Patchwork_8717_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8717_full

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

On Tuesday 17 April 2018 11:39 PM, Ville Syrjälä wrote: On Tue, Apr 17, 2018 at 02:25:32PM +0530, Ramalingam C wrote: >From Gen9 onwards Bspec says HW supports Max Bytes per single RD/WR op is 511Bytes instead of previous 256Bytes used in SW. This change allows the max bytes per op upto

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable NV12 support (rev2)

== Series Details == Series: Enable NV12 support (rev2) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4060 -> Patchwork_8717 = == Summary - WARNING == Minor unknown changes coming with Patchwork_8717 need to be

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Do not do fb src adjustments for NV12

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Tuesday, April 17, 2018 3:32 PM > To: Srinivas, Vidya ; Saarinen, Jani > ; intel-gfx@lists.freedesktop.org > Cc: Kamath, Sunil

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable NV12 support (rev2)

== Series Details == Series: Enable NV12 support (rev2) URL : https://patchwork.freedesktop.org/series/41674/ State : warning == Summary == $ dim checkpatch origin/drm-tip e7aa87c8fdf6 drm/i915: Enable display workaround 827 for all planes, v2. -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment

[Intel-gfx] [PATCH v4 0/6] Enable NV12 support

Enabling NV12 support: - Framebuffer creation - Primary and Sprite plane support Patch series depend on Enable display workaround 827 patch mentioned below submitted by Maarten Changes from prev version: Included RB from Maarten for patches Included RB from Kristian Chandra Konduru (3):

[Intel-gfx] [PATCH v4 4/6] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH v4 5/6] drm/i915: Enable Display WA 0528

Possible hang with NV12 plane surface formats. WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_* register bit 22 must be set to 1 and the render decompression must not be enabled on any of the planes in that pipe. v2: removed unnecessary POSTING_READ v3: Added RB from Maarten

[Intel-gfx] [PATCH v4 3/6] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

From: Maarten Lankhorst We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. v2: For NV12, making the src coordinates multiplier of 4 v3: Moving all the src coords handling code

[Intel-gfx] [PATCH v4 2/6] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH v4 1/6] drm/i915: Enable display workaround 827 for all planes, v2.

From: Maarten Lankhorst The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Do not do fb src adjustments for NV12

> -Original Message- > From: Saarinen, Jani > Sent: Tuesday, April 17, 2018 4:23 PM > To: Srinivas, Vidya ; Maarten Lankhorst > ; intel-gfx@lists.freedesktop.org > Cc: Kamath, Sunil > Subject: RE:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbdev: Enable late fbdev initial configuration

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration URL : https://patchwork.freedesktop.org/series/41851/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4060_full -> Patchwork_8714_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

On Wed, 2018-04-18 at 00:44 +0100, Chris Wilson wrote: > Quoting José Roberto de Souza (2018-04-17 23:34:18) > > If the initial fbdev configuration(intel_fbdev_initial_config()) > > runs and > > there still no sink connected it will cause > > drm_fb_helper_initial_config() to return 0 as no error

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/fbdev: Enable late fbdev initial configuration (rev2)

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration (rev2) URL : https://patchwork.freedesktop.org/series/41851/ State : failure == Summary == Applying: drm/i915/fbdev: Enable late fbdev initial configuration error: patch failed:

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13)

== Series Details == Series: series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13) URL : https://patchwork.freedesktop.org/series/40503/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4060 -> Patchwork_8715 = == Summary -

Re: [Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

Quoting José Roberto de Souza (2018-04-17 23:34:18) > If the initial fbdev configuration(intel_fbdev_initial_config()) runs and > there still no sink connected it will cause > drm_fb_helper_initial_config() to return 0 as no error happened(but > internally the return is -EAGAIN). > Because no

[Intel-gfx] [PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a MMIO read into L3Bank range will return 0

[Intel-gfx] [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will be returned. However, that means each

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbdev: Enable late fbdev initial configuration

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration URL : https://patchwork.freedesktop.org/series/41851/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4060 -> Patchwork_8714 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] [PATCH 01/10] include: Move ascii85 functions from i915 to linux/ascii85.h

The i915 DRM driver very cleverly used ascii85 encoding for their GPU state file. Move the encode functions to a general header file to support other drivers that might be interested in the same functionality. v3: Fix error_puts -> err_puts pointed out by the 01.org bot v2: Update API to be

[Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

If the initial fbdev configuration(intel_fbdev_initial_config()) runs and there still no sink connected it will cause drm_fb_helper_initial_config() to return 0 as no error happened(but internally the return is -EAGAIN). Because no framebuffer was allocated, when a sink is connected

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)

== Series Details == Series: series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11) URL : https://patchwork.freedesktop.org/series/40503/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8713_full = ==

Re: [Intel-gfx] [PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/17/2018 2:34 PM, Oscar Mateo wrote: On 4/17/2018 2:05 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)

== Series Details == Series: series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11) URL : https://patchwork.freedesktop.org/series/40503/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8713 = == Summary -

Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 4/17/2018 2:05 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

Re: [Intel-gfx] [PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/17/2018 2:05 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

[Intel-gfx] [PATCH v8 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a MMIO read into L3Bank range will return 0

[Intel-gfx] [PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will be returned. However, that means each

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: set minimum CD clock to twice the BCLK. (rev4)

== Series Details == Series: drm/i915: set minimum CD clock to twice the BCLK. (rev4) URL : https://patchwork.freedesktop.org/series/32657/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8712_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

Hey Chris, Chris Wilson writes: > I have to ask, if this is all just to work around iowait triggering high > frequencies for GPU bound applications, does it all just boil down to > i915 incorrectly using iowait. Does this patch set perform better than > > diff --git

Re: [Intel-gfx] [PATCH v4] drm/i915: Enable edp psr error interrupts on hsw

On Tue, 2018-04-17 at 20:41 +0300, Ville Syrjälä wrote: > On Mon, Apr 16, 2018 at 05:43:54PM -0700, Paulo Zanoni wrote: > > Em Qui, 2018-04-05 às 15:00 -0700, Dhinakaran Pandiyan escreveu: > > > From: Daniel Vetter > > > > > > The definitions for the error register

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: set minimum CD clock to twice the BCLK. (rev4)

== Series Details == Series: drm/i915: set minimum CD clock to twice the BCLK. (rev4) URL : https://patchwork.freedesktop.org/series/32657/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8712 = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

On 4/17/2018 12:17 PM, Kumar, Abhay wrote: On 4/17/2018 12:06 PM, Abhay Kumar wrote: In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz. This change will ensure CD clock to be twice of  BCLK. v2: - Address

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: set minimum CD clock to twice the BCLK. (rev4)

== Series Details == Series: drm/i915: set minimum CD clock to twice the BCLK. (rev4) URL : https://patchwork.freedesktop.org/series/32657/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: set minimum CD clock to twice the BCLK.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: set minimum CD clock to twice the BCLK. (rev4)

== Series Details == Series: drm/i915: set minimum CD clock to twice the BCLK. (rev4) URL : https://patchwork.freedesktop.org/series/32657/ State : warning == Summary == $ dim checkpatch origin/drm-tip e052a1b9f10b drm/i915: set minimum CD clock to twice the BCLK. -:6:

Re: [Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

On 4/17/2018 12:06 PM, Abhay Kumar wrote: In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz. This change will ensure CD clock to be twice of BCLK. v2: - Address comment (Jani) - New design approach v3: -

Re: [Intel-gfx] Incorrect plane programming sequence results into a corrupted display/hard hung system

On Thu, Apr 12, 2018 at 07:28:48PM +, Runyan, Arthur J wrote: > This seems like a typical atomic modeset requirement. > > IPC should not impact register programming. > Vblank evasion only works if you have a guarantee on worst case > interrupts/delays. I think locks is part of the

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: Fix audio detection issue on GLK (rev3)

== Series Details == Series: drm/i915/audio: Fix audio detection issue on GLK (rev3) URL : https://patchwork.freedesktop.org/series/41334/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8711_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup. This result in no audio forever as cdclk is < 96Mhz. This change will ensure CD clock to be twice of BCLK. v2: - Address comment (Jani) - New design approach v3: - Typo fix on top of v1 Bugzilla:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: Fix audio detection issue on GLK (rev3)

== Series Details == Series: drm/i915/audio: Fix audio detection issue on GLK (rev3) URL : https://patchwork.freedesktop.org/series/41334/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8711 = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/gmbus: Enable burst read

On Tue, Apr 17, 2018 at 02:25:33PM +0530, Ramalingam C wrote: > Support for Burst read in HW is added for HDCP2.2 compliance > requirement. > > This patch enables the burst read for all the gmbus read of more than > 511Bytes, on capable platforms. > > v2: > Extra line is removed. > v3: >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/audio: Fix audio detection issue on GLK (rev3)

== Series Details == Series: drm/i915/audio: Fix audio detection issue on GLK (rev3) URL : https://patchwork.freedesktop.org/series/41334/ State : warning == Summary == $ dim checkpatch origin/drm-tip 31e1d7550f3b drm/i915/audio: Fix audio detection issue on GLK -:16:

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On 4/17/2018 11:22 AM, Gaurav K Singh wrote: On Geminilake, sometimes audio card is not getting detected after reboot. This is a spurious issue happening on Geminilake. HW codec and HD audio controller link was going out of sync for which there was a fix in i915 driver but was not getting

[Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On Geminilake, sometimes audio card is not getting detected after reboot. This is a spurious issue happening on Geminilake. HW codec and HD audio controller link was going out of sync for which there was a fix in i915 driver but was not getting invoked for GLK. Extending this fix to GLK as well.

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

On Tue, Apr 17, 2018 at 02:25:32PM +0530, Ramalingam C wrote: > >From Gen9 onwards Bspec says HW supports Max Bytes per single RD/WR op is > 511Bytes instead of previous 256Bytes used in SW. > > This change allows the max bytes per op upto 511Bytes from Gen9 onwards. > > v2: > No Change. > v3:

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

On 4/17/2018 12:18 AM, Gaurav K Singh wrote: On Geminilake, sometimes audio card is not getting detected after reboot. This is a spurious issue happening on Geminilake. HW codec and HD audio controller link was going out of sync for which there was a fix in i915 driver but was not getting

Re: [Intel-gfx] [PATCH] drm/i915: Fix LSPCON TMDS output buffer enabling from low-power state

On Mon, Apr 16, 2018 at 06:53:09PM +0300, Imre Deak wrote: > LSPCON adapters in low-power state may ignore the first I2C write during > TMDS output buffer enabling, resulting in a blank screen even with an > otherwise enabled pipe. Fix this by reading back and validating the > written value a few

Re: [Intel-gfx] [PATCH v10 10/11] drm: Add aspect ratio parsing in DRM layer

On Tue, Apr 17, 2018 at 10:45:07AM +0530, Nautiyal, Ankit K wrote: > > On 4/6/2018 11:14 PM, Ville Syrjälä wrote: > > On Fri, Apr 06, 2018 at 10:55:14PM +0530, Nautiyal, Ankit K wrote: > >> This patch is causing failure of IGT test kms_3d. The kms_3d test > >> expects the no. of 3d modes to be

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Fix error checking for wait_var_timeout

== Series Details == Series: drm/i915/selftests: Fix error checking for wait_var_timeout URL : https://patchwork.freedesktop.org/series/41835/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8710_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH v4] drm/i915: Enable edp psr error interrupts on hsw

On Mon, Apr 16, 2018 at 05:43:54PM -0700, Paulo Zanoni wrote: > Em Qui, 2018-04-05 às 15:00 -0700, Dhinakaran Pandiyan escreveu: > > From: Daniel Vetter > > > > The definitions for the error register should be valid on bdw/skl > > too, > > but there we haven't even

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix error checking for wait_var_timeout

== Series Details == Series: drm/i915/selftests: Fix error checking for wait_var_timeout URL : https://patchwork.freedesktop.org/series/41835/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8710 = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Don't use -ETIMEDOUT from inside a test

== Series Details == Series: drm/i915/selftests: Don't use -ETIMEDOUT from inside a test URL : https://patchwork.freedesktop.org/series/41828/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8709_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41827/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8708_full = == Summary - WARNING ==

[Intel-gfx] [PATCH] drm/i915/selftests: Fix error checking for wait_var_timeout

The old wait_on_atomic_t used a custom callback to perform the schedule(), which used my return semantics of reporting an error code on timeout. wait_var_event_timeout() uses the schedule() return semantics of reporting the remaining jiffies (1 if it timed out with 0 jiffies remaining!) and 0 on

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/crc: make locking and source check more robust

== Series Details == Series: drm/i915/crc: make locking and source check more robust URL : https://patchwork.freedesktop.org/series/41821/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8707_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH] gpu: drm: i915: Change return type to vm_fault_t

On Tue, Apr 17, 2018 at 5:29 PM, Jani Nikula wrote: > On Tue, 17 Apr 2018, Souptick Joarder wrote: >> Use new return type vm_fault_t for fault handler. For >> now, this is just documenting that the function returns >> a VM_FAULT value rather

Re: [Intel-gfx] [PATCH] gpu: drm: i915: Change return type to vm_fault_t

On Tue, Apr 17, 2018 at 09:14:32PM +0530, Souptick Joarder wrote: > Not exactly. The plan for these patches is to introduce new vm_fault_t type > in vm_operations_struct fault handlers. It's now available in 4.17-rc1. We > will > push all the required drivers/filesystem changes through different

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Don't use -ETIMEDOUT from inside a test

== Series Details == Series: drm/i915/selftests: Don't use -ETIMEDOUT from inside a test URL : https://patchwork.freedesktop.org/series/41828/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8709 = == Summary - WARNING == Minor unknown changes coming

Re: [Intel-gfx] [PATCH v7 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/16/2018 3:09 PM, Oscar Mateo wrote: On 04/16/2018 02:22 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41827/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8708 = == Summary - WARNING == Minor

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41827/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Move the priotree struct to its own headers Okay!

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41827/ State : warning == Summary == $ dim checkpatch origin/drm-tip 22ae52c5d491 drm/i915: Move the priotree struct to its own

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/crc: make locking and source check more robust

== Series Details == Series: drm/i915/crc: make locking and source check more robust URL : https://patchwork.freedesktop.org/series/41821/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8707 = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

On Tue, 2018-04-17 at 15:03 +0100, Chris Wilson wrote: > I have to ask, if this is all just to work around iowait triggering > high > frequencies for GPU bound applications, does it all just boil down to > i915 incorrectly using iowait. Does this patch set perform better > than > > diff --git

Re: [Intel-gfx] [PATCH] gpu: drm: i915: Change return type to vm_fault_t

On Tue, 17 Apr 2018, Souptick Joarder wrote: > Use new return type vm_fault_t for fault handler. For > now, this is just documenting that the function returns > a VM_FAULT value rather than an errno. Once all instances > are converted, vm_fault_t will become a distinct type.

Re: [Intel-gfx] [Freedreno] [PATCH 01/10] include: Move ascii85 functions from i915 to linux/ascii85.h

On Mon, Apr 16, 2018 at 10:52:59AM -0700, Eric Anholt wrote: > Chris Wilson writes: > > > Quoting Jordan Crouse (2018-04-05 23:06:53) > >> On Thu, Apr 05, 2018 at 04:00:47PM -0600, Jordan Crouse wrote: > >> > The i915 DRM driver very cleverly used ascii85 encoding for

[Intel-gfx] [PATCH] drm/i915/selftests: Don't use -ETIMEDOUT from inside a test

-ETIMEDOUT is reserved in the selftests for use by igt_timeout, and the errno is magically handled by the test runner to break from inside the test loop without propagating back to userspace as a failure. So convert the -ETIMEDOUT from wait_var_event_timeout() into another errno. Signed-off-by:

[Intel-gfx] [PATCH v2 3/3] drm/i915: Pack params to engine->schedule() into a struct

Today we only want to pass along the priority to engine->schedule(), but in the future we want to have much more control over the various aspects of the GPU during a context's execution, for example controlling the frequency allowed. As we need an ever growing number of parameters for scheduling,

[Intel-gfx] [PATCH v2 2/3] drm/i915: Rename priotree to sched

Having moved the priotree struct into i915_scheduler.h, identify it as the scheduling element and rebrand into i915_sched. This becomes more useful as we start attaching more information we require to propagate through the scheduler. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH v2 1/3] drm/i915: Move the priotree struct to its own headers

Over time the priotree has grown from a sorted list to a more complicated structure for propagating constraints along the dependency chain to try and resolve priority inversion. Start to segregate this information from the rest of the request/fence tracking. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake

Quoting Jani Nikula (2018-04-17 12:02:52) > On Mon, 16 Apr 2018, "Srivatsa, Anusha" wrote: > >>-Original Message- > >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com] > >>Sent: Wednesday, April 11, 2018 5:27 AM > >>To: Ian W MORRISON

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add documentation to gen9_set_dc_state()

== Series Details == Series: drm/i915: Add documentation to gen9_set_dc_state() URL : https://patchwork.freedesktop.org/series/41811/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8705_full = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

I have to ask, if this is all just to work around iowait triggering high frequencies for GPU bound applications, does it all just boil down to i915 incorrectly using iowait. Does this patch set perform better than diff --git a/drivers/gpu/drm/i915/i915_request.c

Re: [Intel-gfx] [PATCH] drm/i915: Call i915_perf_fini() on init_hw error unwind

Quoting Michal Wajdeczko (2018-04-14 16:59:13) > On Sat, 14 Apr 2018 11:12:33 +0200, Chris Wilson > wrote: > > > We have to cleanup after i915_perf_init(), even on the error path, as it > > passes a pointer into the module to the sysfs core. If we fail to > >

[Intel-gfx] [RFC/CI PATCH] drm/i915/crc: make locking and source check more robust

It seems to me intel_pipe_crc source and skipped should be checked and modified atomically. Skipped could concievably be changed when source has already been disabled. Alas I can't think of a real world scenario where this could impact CRCs in IGT. Signed-off-by: Jani Nikula

Re: [Intel-gfx] [RFC 6/7] drm/i915: Add sysfs toggle to enable per-client engine stats

Quoting Tvrtko Ursulin (2018-04-17 13:27:35) > From: Tvrtko Ursulin > > By default we are not collecting any per-engine and per-context > statistcs. > > Add a new sysfs toggle to enable this facility: > > $ echo 1 >/sys/class/drm/card0/clients/enable_stats I have to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove skl dc6 enable/disable functions

== Series Details == Series: drm/i915: Remove skl dc6 enable/disable functions URL : https://patchwork.freedesktop.org/series/41803/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8704_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✗ Fi.CI.BAT: failure for Per-context and per-client engine busyness (rev5)

== Series Details == Series: Per-context and per-client engine busyness (rev5) URL : https://patchwork.freedesktop.org/series/32645/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8706 = == Summary - FAILURE == Serious unknown changes coming with

[Intel-gfx] ✓ Fi.CI.IGT: success for GMBUS changes (rev3)

== Series Details == Series: GMBUS changes (rev3) URL : https://patchwork.freedesktop.org/series/41632/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8703_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8703_full need to

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per-context and per-client engine busyness (rev5)

== Series Details == Series: Per-context and per-client engine busyness (rev5) URL : https://patchwork.freedesktop.org/series/32645/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Use seqlock in engine stats Okay! Commit: drm/i915: Track per-context engine

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per-context and per-client engine busyness (rev5)

== Series Details == Series: Per-context and per-client engine busyness (rev5) URL : https://patchwork.freedesktop.org/series/32645/ State : warning == Summary == $ dim checkpatch origin/drm-tip a367a6c9fd96 drm/i915: Use seqlock in engine stats 557e1f39ef83 drm/i915: Track per-context engine

Re: [Intel-gfx] [igt-dev] [RFC 2/7] drm/i915: Track per-context engine busyness

Quoting Tvrtko Ursulin (2018-04-17 13:27:31) > From: Tvrtko Ursulin > > Some customers want to know how much of the GPU time are their clients > using in order to make dynamic load balancing decisions. > > With the hooks already in place which track the overall engine

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Use seqlock in engine stats

Quoting Tvrtko Ursulin (2018-04-17 13:27:30) > From: Tvrtko Ursulin > > We can convert engine stats from a spinlock to seqlock to ensure interrupt > processing is never even a tiny bit delayed by parallel readers. > > There is a smidgen bit more cost on the write lock

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GMBUS changes (rev3)

On Tue, 17 Apr 2018, Patchwork wrote: > == Series Details == > > Series: GMBUS changes (rev3) > URL : https://patchwork.freedesktop.org/series/41632/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 16f60217eb21 drm/i915/gmbus: Increase

Re: [Intel-gfx] [RFC v4 0/7] Per-context and per-client engine busyness

Quoting Tvrtko Ursulin (2018-04-17 13:27:29) > From: Tvrtko Ursulin > > Another re-post of my earlier, now slightly updated work, to expose a DRM > client > hierarchy in sysfs in order to enable a top like tool: > > intel-gpu-top - load avg 40.80, 27.11, 1.50; 882/

[Intel-gfx] [RFC v4 0/7] Per-context and per-client engine busyness

From: Tvrtko Ursulin Another re-post of my earlier, now slightly updated work, to expose a DRM client hierarchy in sysfs in order to enable a top like tool: intel-gpu-top - load avg 40.80, 27.11, 1.50; 882/ 950 MHz;0% RC6; 13.26 Watts; 261903 irqs/s

[Intel-gfx] [RFC 2/7] drm/i915: Track per-context engine busyness

From: Tvrtko Ursulin Some customers want to know how much of the GPU time are their clients using in order to make dynamic load balancing decisions. With the hooks already in place which track the overall engine busyness, we can extend that slightly to split that time

[Intel-gfx] [PATCH 1/7] drm/i915: Use seqlock in engine stats

From: Tvrtko Ursulin We can convert engine stats from a spinlock to seqlock to ensure interrupt processing is never even a tiny bit delayed by parallel readers. There is a smidgen bit more cost on the write lock side, and an extremely unlikely chance that readers will

[Intel-gfx] [RFC 5/7] drm/i915: Expose per-engine client busyness

From: Tvrtko Ursulin Expose per-client and per-engine busyness under the previously added sysfs client root. The new files are one per-engine instance and located under the 'busy' directory. Each contains a monotonically increasing nano-second resolution times each

[Intel-gfx] [RFC 3/7] drm/i915: Expose list of clients in sysfs

From: Tvrtko Ursulin Expose a list of clients with open file handles in sysfs. This will be a basis for a top-like utility showing per-client and per- engine GPU load. Currently we only expose each client's pid and name under opaque numbered directories in

[Intel-gfx] [RFC 6/7] drm/i915: Add sysfs toggle to enable per-client engine stats

From: Tvrtko Ursulin By default we are not collecting any per-engine and per-context statistcs. Add a new sysfs toggle to enable this facility: $ echo 1 >/sys/class/drm/card0/clients/enable_stats v2: Rebase. Signed-off-by: Tvrtko Ursulin

[Intel-gfx] [RFC 4/7] drm/i915: Update client name on context create

From: Tvrtko Ursulin Some clients have the DRM fd passed to them over a socket by the X server. Grab the real client and pid when they create their first context and update the exposed data for more useful enumeration. Signed-off-by: Tvrtko Ursulin

[Intel-gfx] [RFC 7/7] drm/i915: Allow clients to query own per-engine busyness

From: Tvrtko Ursulin Some customers want to know how much of the GPU time are their clients using in order to make dynamic load balancing decisions. With the accounting infrastructure in place in the previous patch, we add a new context param

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add documentation to gen9_set_dc_state()

== Series Details == Series: drm/i915: Add documentation to gen9_set_dc_state() URL : https://patchwork.freedesktop.org/series/41811/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8705 = == Summary - SUCCESS == No regressions found. External URL:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove skl dc6 enable/disable functions

== Series Details == Series: drm/i915: Remove skl dc6 enable/disable functions URL : https://patchwork.freedesktop.org/series/41803/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8704 = == Summary - SUCCESS == No regressions found. External URL:

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