[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)

== Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) URL : https://patchwork.freedesktop.org/series/42459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8969_full = == Summary - WARNING ==

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)

== Series Details == Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) URL : https://patchwork.freedesktop.org/series/42971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8968_full = == Summary - WARNING == Minor

[Intel-gfx] ✓ Fi.CI.IGT: success for DRM helpers for Display Stream Compression PPS infoframes (rev2)

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes (rev2) URL : https://patchwork.freedesktop.org/series/42968/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8967_full = == Summary - WARNING == Minor unknown

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

== Series Details == Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. URL : https://patchwork.freedesktop.org/series/42971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8966_full = == Summary - WARNING == Minor unknown

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)

== Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) URL : https://patchwork.freedesktop.org/series/42459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8969 = == Summary - SUCCESS == No regressions

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)

== Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) URL : https://patchwork.freedesktop.org/series/42459/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)

== Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) URL : https://patchwork.freedesktop.org/series/42459/ State : warning == Summary == $ dim checkpatch origin/drm-tip 420c5e74238d drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio

Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

On Fri, 2018-04-27 at 11:54 +0530, vathsala nagaraju wrote: > From: Vathsala Nagaraju > > Prints live state of psr1.Extending the existing > PSR2 live state function to cover psr1. > > Tested on KBL with psr2 and psr1 panel. Thanks for the patch, please see

[Intel-gfx] [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

From: Ville Syrjälä CDCLK has to be at least twice the BLCK regardless of audio. Audio driver has to probe using this hook and increase the clock even in absence of any display. v2: Use atomic refcount for get_power, put_power so that we can call each

[Intel-gfx] ✓ Fi.CI.IGT: success for DRM helpers for Display Stream Compression PPS infoframes

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes URL : https://patchwork.freedesktop.org/series/42968/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8965_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)

== Series Details == Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) URL : https://patchwork.freedesktop.org/series/42971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8968 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] [PATCH v2] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

By moving the check from psr_compute_config() to psr_init_dpcd(), we get to set the dev_priv->psr.sink_support flag only when the panel is capable of changing power state. An additional benefit is that the check will be performed only at init time instead of every atomic_check. This should change

[Intel-gfx] ✓ Fi.CI.BAT: success for DRM helpers for Display Stream Compression PPS infoframes (rev2)

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes (rev2) URL : https://patchwork.freedesktop.org/series/42968/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8967 = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

On Wed, 2018-05-09 at 14:54 -0700, Dhinakaran Pandiyan wrote: > By moving the check from psr_compute_config() to psr_init_dpcd(), we > get > to set the dev_priv->psr.sink_support flag only when the panel is > capable of changing power state. An additional benefit is that the > check > will be

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DRM helpers for Display Stream Compression PPS infoframes (rev2)

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes (rev2) URL : https://patchwork.freedesktop.org/series/42968/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DRM helpers for Display Stream Compression PPS infoframes (rev2)

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes (rev2) URL : https://patchwork.freedesktop.org/series/42968/ State : warning == Summary == $ dim checkpatch origin/drm-tip bf8fa6314dd0 drm/dp: Define payload size for DP SDP PPS packet feef4201c5b3

[Intel-gfx] [PATCH v2 4/4] drm/dsc: Add helpers for DSC picture parameter set infoframes

According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP

Re: [Intel-gfx] [PATCH v4 6/8] drm/i915: reprogram NOA muxes on context switch when using perf

On 09/05/18 18:48, Lionel Landwerlin wrote: @@ -1953,10 +1992,26 @@ static int gen8_emit_bb_start(struct i915_request *rq, rq->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); } - cs = intel_ring_begin(rq, 6); + cs = intel_ring_begin(rq,

Re: [Intel-gfx] [PATCH] dim: replace pipe commands with single sed

Now CC the right mailing list. The way dim sets up the repository you can't have individual git configs, e.g. to set a different sendemail.to for dim-tools :( Lucas De Marchi On Wed, May 9, 2018 at 2:28 PM, Lucas De Marchi wrote: > A single sed can do the job of

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

== Series Details == Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. URL : https://patchwork.freedesktop.org/series/42971/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8966 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] ✓ Fi.CI.BAT: success for DRM helpers for Display Stream Compression PPS infoframes

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes URL : https://patchwork.freedesktop.org/series/42968/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8965 = == Summary - SUCCESS == No regressions found. External

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DRM helpers for Display Stream Compression PPS infoframes

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes URL : https://patchwork.freedesktop.org/series/42968/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc: Define

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DRM helpers for Display Stream Compression PPS infoframes

== Series Details == Series: DRM helpers for Display Stream Compression PPS infoframes URL : https://patchwork.freedesktop.org/series/42968/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3e29c3165299 drm/dp: Define payload size for DP SDP PPS packet 6fa61cb1f2d1 drm/dsc:

[Intel-gfx] [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

By moving the check from psr_compute_config() to psr_init_dpcd(), we get to set the dev_priv->psr.sink_support flag only when the panel is capable of changing power state. An additional benefit is that the check will be performed only at init time instead of every atomic_check. This should change

[Intel-gfx] [PATCH 0/4] DRM helpers for Display Stream Compression PPS infoframes

VESA Display Stream Compression is a specification for visually losless video compression over display links. The DSC standard also defines a picture parameter set (PPS) which encoder must communicate to decoders. This is done by encapsulating PPS header and payload bytes in an infoframe that can

[Intel-gfx] [PATCH 1/4] drm/dp: Define payload size for DP SDP PPS packet

DP 1.4 spec defines DP secondary data packet for DSC picture parameter set. This patch defines its payload size according to the DP 1.4 specification. Signed-off-by: Manasi Navare Cc: Jani Nikula Cc: Ville Syrjala

[Intel-gfx] [PATCH 3/4] drm/dsc: Define VESA Display Stream Compression Capabilities

From: Gaurav K Singh This defines all the DSC parameters as per the VESA DSC spec that will be required for DSC encoder/decoder v2: Define this struct in DRM (From Manasi) * Changed the data types to u8/u16 instead of unsigned longs (Manasi) * Remove driver specific

[Intel-gfx] [PATCH 4/4] drm/dsc: Add helpers for DSC picture parameter set infoframes

According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP

[Intel-gfx] [PATCH 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

This patch defines a new header file for all the DSC 1.2 structures and creates a structure for PPS infoframe which will be used to send picture parameter set secondary data packet for display stream compression. All the PPS infoframe syntax elements are taken from DSC 1.2 specification from VESA.

[Intel-gfx] [PATCH] dim: replace pipe commands with single sed

A single sed can do the job of taking the second line after a match and it looks simpler. Signed-off-by: Lucas De Marchi --- I noticed this while reviewing "[PATCH 2/4] dim: shut up sed broken pipe noise in apply-pull". dim | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, This weeks fixes is a little busier than normal, due to the omap changes. However since these aren't regressions, it shouldn't be something to be concerned about. drm-misc-fixes-2018-05-09: atomic: Clear state pointers on clear (Ville) vc4: Fix oops in dpi disable (Eric) omap: Various

Re: [Intel-gfx] [PATCH v14 10/10] drm: Add and handle new aspect ratios in DRM layer

On Tue, May 08, 2018 at 04:39:45PM +0530, Nautiyal, Ankit K wrote: > From: "Sharma, Shashank" > > HDMI 2.0/CEA-861-F introduces two new aspect ratios: > - 64:27 > - 256:135 > > This patch: > - Adds new DRM flags for to represent these new aspect ratios. > - Adds new

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: per context slice/subslice powergating (rev3)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev3) URL : https://patchwork.freedesktop.org/series/42285/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

Re: [Intel-gfx] [RFC] drm/i915/dp: optimize eDP 1.4+ link config fast and narrow

On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote: > We've opted to use the maximum link rate and lane count for eDP panels, > because typically the maximum supported configuration reported by the > panel has matched the native resolution requirements of the panel, and > optimizing the

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Remove tasklet flush before disable

== Series Details == Series: series starting with [1/5] drm/i915: Remove tasklet flush before disable URL : https://patchwork.freedesktop.org/series/42950/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8963_full = == Summary - WARNING == Minor

[Intel-gfx] [PATCH v4 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not accessible via LRI). If the

[Intel-gfx] [PATCH v4 1/8] drm/i915: Program RPCS for Broadwell

From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the

[Intel-gfx] [PATCH v4 0/8] drm/i915: per context slice/subslice powergating

Hi all, Another update following Chris' review (Thanks!). A few more IGT tests to come to verify that interaction with perf. Cheers, Chris Wilson (3): drm/i915: Program RPCS for Broadwell drm/i915: Record the sseu configuration per-context & engine drm/i915: Expose RPCS (SSEU)

[Intel-gfx] [PATCH v4 5/8] drm/i915: give engine to execlists cancel helper

We would like to set a value on the associated engine in this helper in a following commit. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c| 10 +-

[Intel-gfx] [PATCH v4 7/8] drm/i915: count powergating transitions per engine

This can be used to monitor the number of powergating transition changes for a particular workload. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ drivers/gpu/drm/i915/intel_lrc.c| 1 +

[Intel-gfx] [PATCH v4 3/8] drm/i915/perf: simplify configure all context function

We don't need any special treatment on error so just return as soon as possible. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] [PATCH v4 2/8] drm/i915: Record the sseu configuration per-context & engine

From: Chris Wilson We want to expose the ability to reconfigure the slices, subslice and eu per context and per engine. To facilitate that, store the current configuration on the context for each engine, which is initially set to the device default upon creation. v2:

[Intel-gfx] [PATCH v4 6/8] drm/i915: reprogram NOA muxes on context switch when using perf

If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. We need to reprogram them when we detect a powergating configuration change. In this change i915/perf is responsible for

[Intel-gfx] [PATCH v4 4/8] drm/i915: add new pipe control helper for mmio writes

We'll use those helpers in the following commits. It's a good thing to have them around as they need to apply a particular workaround on Skylake. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c| 34 +

[Intel-gfx] ✓ Fi.CI.IGT: success for GMBUS changes (rev4)

== Series Details == Series: GMBUS changes (rev4) URL : https://patchwork.freedesktop.org/series/41632/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8962_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8962_full need to

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 08/05/18 21:56, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-03 18:18:43) On 25/04/2018 12:45, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a

[Intel-gfx] [PATCH i-g-t v4 7/7] trace.pl: Fix request split mode

From: Tvrtko Ursulin Request split mode had several bugs, both in the original version and also after the recent refactorings. One big one was that it wasn't considering different submit ports as a reason to split execution, and also that it was too time based instead

Re: [Intel-gfx] [PATCH v3 4/6] drm/i915: reprogram NOA muxes on context switch when using perf

On 09/05/18 09:59, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-05-08 19:03:45) If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. We need to reprogram them when we

Re: [Intel-gfx] [RFC] drm/i915/dp: optimize eDP 1.4+ link config fast and narrow

On Wed, 2018-05-09 at 08:09 -0700, Matt Atwood wrote: > On Wed, 2018-05-09 at 05:21 -0700, Rodrigo Vivi wrote: > > On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote: > > > We've opted to use the maximum link rate and lane count for eDP > > > panels, > > > because typically the maximum

Re: [Intel-gfx] [PATCH v3 23/40] drm/i915: Implement HDCP2.2 receiver authentication

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Remove tasklet flush before disable

== Series Details == Series: series starting with [1/5] drm/i915: Remove tasklet flush before disable URL : https://patchwork.freedesktop.org/series/42950/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8963 = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH v3 22/40] drm/i915: Wrappers for mei HDCP2.2 services

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [RFC] drm/i915/dp: optimize eDP 1.4+ link config fast and narrow

On Wed, 2018-05-09 at 05:21 -0700, Rodrigo Vivi wrote: > On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote: > > We've opted to use the maximum link rate and lane count for eDP > > panels, > > because typically the maximum supported configuration reported by > > the > > panel has matched

Re: [Intel-gfx] [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Remove tasklet flush before disable

== Series Details == Series: series starting with [1/5] drm/i915: Remove tasklet flush before disable URL : https://patchwork.freedesktop.org/series/42950/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Remove tasklet flush before disable Okay! Commit: drm/i915:

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Wrap tasklet_struct for abuse

Quoting Chris Wilson (2018-05-09 15:27:58) > In the next few patches, we want to abuse tasklet to avoid ksoftirqd > latency along critical paths. To make that abuse easily to swallow, > first coat the tasklet in a little syntactic sugar. > > Signed-off-by: Chris Wilson

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Remove tasklet flush before disable

== Series Details == Series: series starting with [1/5] drm/i915: Remove tasklet flush before disable URL : https://patchwork.freedesktop.org/series/42950/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8083271a8a5b drm/i915: Remove tasklet flush before disable 23f6b88c5a19

[Intel-gfx] ✓ Fi.CI.BAT: success for GMBUS changes (rev4)

== Series Details == Series: GMBUS changes (rev4) URL : https://patchwork.freedesktop.org/series/41632/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8962 = == Summary - WARNING == Minor unknown changes coming with Patchwork_8962 need to be verified

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GMBUS changes (rev4)

== Series Details == Series: GMBUS changes (rev4) URL : https://patchwork.freedesktop.org/series/41632/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op -O:drivers/gpu/drm/i915/intel_i2c.c:403:23: warning: expression using

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GMBUS changes (rev4)

== Series Details == Series: GMBUS changes (rev4) URL : https://patchwork.freedesktop.org/series/41632/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7ef555142951 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op 3e623cbfe855 drm/i915/gmbus: Enable burst read -:34:

[Intel-gfx] [PATCH 5/5] drm/i915: Speed up idle detection by kicking the tasklets

We rely on ksoftirqd to run in a timely fashion in order to drain the execlists queue. Quite frequently, it does not. In some cases we may see latencies of over 200ms triggering our idle timeouts and forcing us to declare the driver wedged! Thus we can speed up idle detection by bypassing

[Intel-gfx] [PATCH 3/5] drm/i915/execlists: Direct submit onto idle engines

Bypass using the tasklet to submit the first request to HW, as the tasklet may be deferred unto ksoftirqd and at a minimum will add in excess of 10us (and maybe tens of milliseconds) to our execution latency. This latency reduction is most notable when execution flows between engines. v2: Beware

[Intel-gfx] [PATCH 1/5] drm/i915: Remove tasklet flush before disable

The idea was to try and let the existing tasklet run to completion before we began the reset, but it involves a racy check against anything else that tries to run the tasklet. Rather than acknowledge and ignore the race, let it be and don't try and be too clever. The tasklet will resume execution

[Intel-gfx] [PATCH 2/5] drm/i915: Wrap tasklet_struct for abuse

In the next few patches, we want to abuse tasklet to avoid ksoftirqd latency along critical paths. To make that abuse easily to swallow, first coat the tasklet in a little syntactic sugar. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin ---

[Intel-gfx] [PATCH 4/5] drm/i915/execlists: Direct submission from irq handler

Continuing the theme of bypassing ksoftirqd latency, also first try to directly submit from the CS interrupt handler to clear the ELSP and queue the next. In the past, we have been hesitant to do this as the context switch processing has been quite heavy, requiring forcewaked mmio. However, as we

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse

== Series Details == Series: series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse URL : https://patchwork.freedesktop.org/series/42942/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4162_full -> Patchwork_8961_full = == Summary - WARNING == Minor

Re: [Intel-gfx] [PATCH v3 20/40] drm/i915: Define HDCP2.2 related variables

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 19/40] drm/i915: wrapping all hdcp var into intel_hdcp

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Combine tasklet_kill and tasklet_disable

Quoting Chris Wilson (2018-05-09 15:02:12) > Quoting Mika Kuoppala (2018-05-09 14:54:04) > > Chris Wilson writes: > > > > > Ideally, we want to atomically flush and disable the tasklet before > > > resetting the GPU. At present, we rely on being the only part to touch >

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Combine tasklet_kill and tasklet_disable

Quoting Mika Kuoppala (2018-05-09 14:54:04) > Chris Wilson writes: > > > Ideally, we want to atomically flush and disable the tasklet before > > resetting the GPU. At present, we rely on being the only part to touch > > our tasklet and serialisation of the reset process

Re: [Intel-gfx] [PATCH v3 18/40] misc/mei/hdcp: Closing wired HDCP2.2 Tx Session

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH] drm/i915/psr: Check if VBT says PSR can be enabled.

On Wed, May 09, 2018 at 05:29:14AM -0700, Rodrigo Vivi wrote: > On Tue, May 08, 2018 at 05:35:24PM -0700, Dhinakaran Pandiyan wrote: > > Driver features data block has a boolean flag for PSR, use this to decide > > whether PSR should be enabled on a platform. The module parameter can > > still be

Re: [Intel-gfx] [PATCH v3 17/40] misc/mei/hdcp: Enabling the HDCP authentication

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:28 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915: Combine tasklet_kill and tasklet_disable

Chris Wilson writes: > Ideally, we want to atomically flush and disable the tasklet before > resetting the GPU. At present, we rely on being the only part to touch > our tasklet and serialisation of the reset process to ensure that we can > suspend the tasklet from the

[Intel-gfx] [PATCH v4 2/2] drm/i915/gmbus: Enable burst read

Support for Burst read in HW is added for HDCP2.2 compliance requirement. This patch enables the burst read for all the gmbus read of more than 511Bytes, on capable platforms. v2: Extra line is removed. v3: Macro is added for detecting the BURST_READ Support [Jani] Runtime detection of the

[Intel-gfx] [PATCH v4 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of enabling the 511Bytes per RD/WR cycle on legacy platforms for no absolute ROIs, this change allows the max bytes per op upto 511Bytes from Gen9 onwards. v2: No Change. v3: Inline function for max_xfer_size and renaming of

[Intel-gfx] [PATCH v4 0/2] GMBUS changes

I am not aware if there is a reason for restricting the Bytes per GMBUS WR/RD to 256 at present. But HW has 9Bits for Total Byte count for a single read or Write cycle. Means we can extend a cycle of RD/WR to 511Bytes. At present nothing much as ROI, as most of the usecases are for less than

Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Wrap tasklet_struct for abuse

Quoting Mika Kuoppala (2018-05-09 14:44:30) > Chris Wilson writes: > > > In the next few patches, we want to abuse tasklet to avoid ksoftirqd > > latency along critical paths. To make that abuse easily to swallow, > > first coat the tasklet in a little syntactic sugar.

Re: [Intel-gfx] [PATCH v3 16/40] misc/mei/hdcp: Verify M_prime

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Wrap tasklet_struct for abuse

Chris Wilson writes: > In the next few patches, we want to abuse tasklet to avoid ksoftirqd > latency along critical paths. To make that abuse easily to swallow, > first coat the tasklet in a little syntactic sugar. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915/psr: Check if VBT says PSR can be enabled.

On Tue, May 08, 2018 at 05:35:24PM -0700, Dhinakaran Pandiyan wrote: > Driver features data block has a boolean flag for PSR, use this to decide > whether PSR should be enabled on a platform. The module parameter can > still be used to override this. > > Note: The feature currently remains

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse

== Series Details == Series: series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse URL : https://patchwork.freedesktop.org/series/42942/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4162 -> Patchwork_8961 = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [RFC] drm/i915/dp: optimize eDP 1.4+ link config fast and narrow

On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote: > We've opted to use the maximum link rate and lane count for eDP panels, > because typically the maximum supported configuration reported by the > panel has matched the native resolution requirements of the panel, and > optimizing the

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse

== Series Details == Series: series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse URL : https://patchwork.freedesktop.org/series/42942/ State : warning == Summary == $ dim checkpatch origin/drm-tip 949ea8da2485 drm/i915: Wrap tasklet_struct for abuse -:53:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse

== Series Details == Series: series starting with [v3,1/5] drm/i915: Wrap tasklet_struct for abuse URL : https://patchwork.freedesktop.org/series/42942/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Wrap tasklet_struct for abuse Okay! Commit: drm/i915: Combine

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer"

== Series Details == Series: drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer" URL : https://patchwork.freedesktop.org/series/42937/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4162_full -> Patchwork_8960_full = == Summary - WARNING == Minor unknown

[Intel-gfx] [PATCH v3 4/5] drm/i915/execlists: Direct submission from irq handler

Continuing the theme of bypassing ksoftirqd latency, also first try to directly submit from the CS interrupt handler to clear the ELSP and queue the next. In the past, we have been hesitant to do this as the context switch processing has been quite heavy, requiring forcewaked mmio. However, as we

[Intel-gfx] [PATCH v3 1/5] drm/i915: Wrap tasklet_struct for abuse

In the next few patches, we want to abuse tasklet to avoid ksoftirqd latency along critical paths. To make that abuse easily to swallow, first coat the tasklet in a little syntactic sugar. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin ---

[Intel-gfx] [PATCH v3 3/5] drm/i915/execlists: Direct submit onto idle engines

Bypass using the tasklet to submit the first request to HW, as the tasklet may be deferred unto ksoftirqd and at a minimum will add in excess of 10us (and maybe tens of milliseconds) to our execution latency. This latency reduction is most notable when execution flows between engines. v2: Beware

[Intel-gfx] [PATCH v3 2/5] drm/i915: Combine tasklet_kill and tasklet_disable

Ideally, we want to atomically flush and disable the tasklet before resetting the GPU. At present, we rely on being the only part to touch our tasklet and serialisation of the reset process to ensure that we can suspend the tasklet from the mix of reset/wedge pathways. In this patch, we move the

[Intel-gfx] [PATCH v3 5/5] drm/i915: Speed up idle detection by kicking the tasklets

We rely on ksoftirqd to run in a timely fashion in order to drain the execlists queue. Quite frequently, it does not. In some cases we may see latencies of over 200ms triggering our idle timeouts and forcing us to declare the driver wedged! Thus we can speed up idle detection by bypassing

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: fix spelling mistake: "seqeuncer" -> "sequencer"

== Series Details == Series: drm/i915/dp: fix spelling mistake: "seqeuncer" -> "sequencer" URL : https://patchwork.freedesktop.org/series/42935/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4162_full -> Patchwork_8959_full = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

Oscar Mateo writes: > Avoids a hang during soft reset. > > v2: Rebased on top of the WA refactoring > v3: Added References (Mika) > v4: > - Rebased > - C, not lisp (Chris) > - Which steppings affected by this are not clear. > For the moment, apply unconditionally

Re: [Intel-gfx] [PATCH v3 15/40] misc/mei/hdcp: Repeater topology verifcation and ack

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 14/40] misc/mei/hdcp: Prepare Session Key

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer"

== Series Details == Series: drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer" URL : https://patchwork.freedesktop.org/series/42937/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4162 -> Patchwork_8960 = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH][V2] drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer"

On Wed, 09 May 2018, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistakes in WARN warning message text and > in comments: > > "seqeuncer", "seqeuencer" -> "sequencer" > > Signed-off-by: Colin Ian King

Re: [Intel-gfx] [PATCH v3 13/40] misc/mei/hdcp: Verify L_prime

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 12/40] misc/mei/hdcp: Initiate Locality check

>-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

Re: [Intel-gfx] [PATCH v3 11/40] misc/mei/hdcp: Store the HDCP Pairing info

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Tuesday, April 3, 2018 7:27 PM >To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; >seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;

  1   2   >