[Intel-gfx] ✓ Fi.CI.IGT: success for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201_full -> Patchwork_9040_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9040_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9040_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9040_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9040_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822) +1

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167) +1

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  FAIL (fdo#105454, fdo#106509) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9040

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9040: 28641b50ce4db9b033993f54fc0fbc6b96866619 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9040/shards.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV 
and CHV
URL   : https://patchwork.freedesktop.org/series/43368/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4201_full -> Patchwork_9039_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9039_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9039_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43368/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9039_full:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  PASS -> DMESG-FAIL


 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS

igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
  shard-apl:  PASS -> SKIP +24


== Known issues ==

  Here are the changes found in Patchwork_9039_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_eio@in-flight-suspend:
  shard-kbl:  PASS -> FAIL (fdo#105957)

igt@kms_atomic_transition@2x-modeset-transitions-nonblocking-fencing:
  shard-hsw:  PASS -> DMESG-WARN (fdo#102614)

igt@kms_cursor_crc@cursor-128x128-suspend:
  shard-apl:  PASS -> DMESG-WARN (fdo#103558)

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip@flip-vs-blocking-wf-vblank:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724)

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9039

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9039: b3fc769740221068d91eb1879d9daa75ef108dd3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9039/shards.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Store a pointer to intel_context in i915_request

[Zhenyu Wang]

On 2018.05.17 22:26:32 +0100, Chris Wilson wrote:
> To ease the frequent and ugly pointer dance of
> >gem_context->engine[request->engine->id] during request
> submission, store that pointer as request->hw_context. One major
> advantage that we will exploit later is that this decouples the logical
> context state from the engine itself.
> 
> v2: Set mock_context->ops so we don't crash and burn in selftests.
> Cleanups from Tvrtko.
> 
> Signed-off-by: Chris Wilson 
> Cc: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/gvt/mmio_context.c   |   6 +-
>  drivers/gpu/drm/i915/gvt/mmio_context.h   |   2 +-
>  drivers/gpu/drm/i915/gvt/scheduler.c  | 141 +++---
>  drivers/gpu/drm/i915/gvt/scheduler.h  |   1 -

gvt change looks fine to me.

Acked-by: Zhenyu Wang 

>  drivers/gpu/drm/i915/i915_drv.h   |   1 +
>  drivers/gpu/drm/i915/i915_gem.c   |  12 +-
>  drivers/gpu/drm/i915/i915_gem_context.c   |  17 ++-
>  drivers/gpu/drm/i915/i915_gem_context.h   |  21 ++-
>  drivers/gpu/drm/i915/i915_gpu_error.c |   3 +-
>  drivers/gpu/drm/i915/i915_perf.c  |  25 ++--
>  drivers/gpu/drm/i915/i915_request.c   |  34 ++---
>  drivers/gpu/drm/i915/i915_request.h   |   1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c|  54 ---
>  drivers/gpu/drm/i915/intel_guc_submission.c   |  10 +-
>  drivers/gpu/drm/i915/intel_lrc.c  | 125 +---
>  drivers/gpu/drm/i915/intel_lrc.h  |   7 -
>  drivers/gpu/drm/i915/intel_ringbuffer.c   | 100 -
>  drivers/gpu/drm/i915/intel_ringbuffer.h   |   9 +-
>  drivers/gpu/drm/i915/selftests/mock_context.c |   7 +
>  drivers/gpu/drm/i915/selftests/mock_engine.c  |  41 +++--
>  20 files changed, 321 insertions(+), 296 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c 
> b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 0f949554d118..708170e61625 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -446,9 +446,9 @@ static void switch_mocs(struct intel_vgpu *pre, struct 
> intel_vgpu *next,
>  
>  #define CTX_CONTEXT_CONTROL_VAL  0x03
>  
> -bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id)
> +bool is_inhibit_context(struct intel_context *ce)
>  {
> - u32 *reg_state = ctx->__engine[ring_id].lrc_reg_state;
> + const u32 *reg_state = ce->lrc_reg_state;
>   u32 inhibit_mask =
>   _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>  
> @@ -501,7 +501,7 @@ static void switch_mmio(struct intel_vgpu *pre,
>* itself.
>*/
>   if (mmio->in_context &&
> - !is_inhibit_context(s->shadow_ctx, ring_id))
> + 
> !is_inhibit_context(>shadow_ctx->__engine[ring_id]))
>   continue;
>  
>   if (mmio->mask)
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h 
> b/drivers/gpu/drm/i915/gvt/mmio_context.h
> index 0439eb8057a8..5c3b9ff9f96a 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.h
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
> @@ -49,7 +49,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
>  
>  void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
>  
> -bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id);
> +bool is_inhibit_context(struct intel_context *ce);
>  
>  int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
>  struct i915_request *req);
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
> b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 17f9f8d7e148..e1760030dda1 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -54,11 +54,8 @@ static void set_context_pdp_root_pointer(
>  
>  static void update_shadow_pdps(struct intel_vgpu_workload *workload)
>  {
> - struct intel_vgpu *vgpu = workload->vgpu;
> - int ring_id = workload->ring_id;
> - struct i915_gem_context *shadow_ctx = vgpu->submission.shadow_ctx;
>   struct drm_i915_gem_object *ctx_obj =
> - shadow_ctx->__engine[ring_id].state->obj;
> + workload->req->hw_context->state->obj;
>   struct execlist_ring_context *shadow_ring_context;
>   struct page *page;
>  
> @@ -128,9 +125,8 @@ static int populate_shadow_context(struct 
> intel_vgpu_workload *workload)
>   struct intel_vgpu *vgpu = workload->vgpu;
>   struct intel_gvt *gvt = vgpu->gvt;
>   int ring_id = workload->ring_id;
> - struct i915_gem_context *shadow_ctx = vgpu->submission.shadow_ctx;
>   struct drm_i915_gem_object *ctx_obj =
> - shadow_ctx->__engine[ring_id].state->obj;
> + workload->req->hw_context->state->obj;
>   struct execlist_ring_context 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Move request->ctx aside

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Move request->ctx aside
URL   : https://patchwork.freedesktop.org/series/43363/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201_full -> Patchwork_9038_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9038_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9038_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43363/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9038_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  PASS -> SKIP

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9038_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_cpu_reloc@full:
  shard-apl:  PASS -> INCOMPLETE (fdo#103927)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@flip-vs-wf_vblank-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724) +1

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9038

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9038: 2c493945260f30f5c84326521ac8368db05309fa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9038/shards.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200_full -> Patchwork_9037_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9037_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9037_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43344/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9037_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
  shard-kbl:  PASS -> SKIP

igt@kms_plane_lowres@pipe-c-tiling-x:
  shard-apl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9037_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#105454, fdo#106509)

igt@kms_cursor_legacy@flip-vs-cursor-legacy:
  shard-hsw:  PASS -> FAIL (fdo#102670)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724) +1

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#106247)
  shard-apl:  PASS -> DMESG-FAIL (fdo#105602, fdo#103558)

igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
  shard-apl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558) +10

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  DMESG-FAIL -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105707) -> PASS

igt@kms_flip@basic-flip-vs-dpms:
  shard-hsw:  DMESG-WARN (fdo#102614) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  FAIL (fdo#102887) -> PASS
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9037

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9037: afd1ce5db4288f5db1492a593829c91d635a5486 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9037/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR

[Tarun Vyas]

On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote:
> Ville noticed that we are unncessarily reading DPCD's after knowing
> panel did not support PSR. Looks like this check that was present
> earlier got removed unintentionally, let's put it back.
> 
> While we do this, add the PSR version number in the debug print.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 14 --
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..8fe6d2f9ab2b 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -250,10 +250,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>   drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>sizeof(intel_dp->psr_dpcd));
>  
> - if (intel_dp->psr_dpcd[0]) {
> - dev_priv->psr.sink_support = true;
> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> - }
> + if (!intel_dp->psr_dpcd[0])
> + return;
> +
> + DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
> +   intel_dp->psr_dpcd[0]);
> + dev_priv->psr.sink_support = true;
>  
>   if (INTEL_GEN(dev_priv) >= 9 &&
>   (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> @@ -270,8 +272,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>*/
>   dev_priv->psr.sink_psr2_support =
>   intel_dp_get_y_coord_required(intel_dp);
> - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
> -   ? "supported" : "not supported");
> + DRM_DEBUG_KMS("PSR2 %ssupported\n",
> +   dev_priv->psr.sink_psr2_support ? "" : "not ");
Would it make sense to make it clearer that PSR2 is not supported b/c of lack 
of y-coordinate support on the sink ?

Reviewed-by: Tarun Vyas 
>  
>   if (dev_priv->psr.sink_psr2_support) {
>   dev_priv->psr.colorimetry_support =
> -- 
> 2.14.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2] drm/i915/guc: Keep guc submission permanently engaged (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v2] drm/i915/guc: Keep guc submission permanently 
engaged (rev2)
URL   : https://patchwork.freedesktop.org/series/43352/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4200_full -> Patchwork_9036_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9036_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9036_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43352/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9036_full:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@live_guc:
  shard-kbl:  PASS -> DMESG-FAIL

igt@drv_selftest@live_hangcheck:
  shard-apl:  PASS -> DMESG-FAIL +1

igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
  shard-glk:  PASS -> DMESG-WARN

igt@perf@gen8-unprivileged-single-ctx-counters:
  shard-kbl:  PASS -> FAIL
  shard-apl:  PASS -> FAIL

igt@pm_rpm@debugfs-read:
  shard-kbl:  PASS -> DMESG-WARN


 Warnings 

igt@drv_missed_irq:
  shard-apl:  PASS -> SKIP

igt@perf@polling:
  shard-kbl:  PASS -> SKIP +37


== Known issues ==

  Here are the changes found in Patchwork_9036_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#105454, fdo#106509)

igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
  shard-hsw:  PASS -> DMESG-WARN (fdo#102614)

igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
  shard-glk:  PASS -> FAIL (fdo#103928)

igt@kms_flip@plain-flip-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip_tiling@flip-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167)

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)

igt@perf_pmu@busy-accuracy-50-rcs0:
  shard-kbl:  PASS -> FAIL (fdo#105157)


 Possible fixes 

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105707) -> PASS

igt@kms_flip@basic-flip-vs-dpms:
  shard-hsw:  DMESG-WARN (fdo#102614) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  FAIL (fdo#102887) -> PASS
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105157 https://bugs.freedesktop.org/show_bug.cgi?id=105157
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9036

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9036: e6d22baddf5d3d69c62443be579acdb7acc66908 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9036/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201 -> Patchwork_9040 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/6/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9040 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-cnl-y3:  FAIL (fdo#103167, fdo#104724) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS


 Warnings 

igt@gem_ringfill@basic-default-hang:
  fi-pnv-d510:DMESG-WARN (fdo#101600) -> INCOMPLETE (fdo#105000)


  fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105000 https://bugs.freedesktop.org/show_bug.cgi?id=105000
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9040

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9040: 28641b50ce4db9b033993f54fc0fbc6b96866619 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

28641b50ce4d drm/dsc: Add helpers for DSC picture parameter set infoframes
c3afd0709328 drm/dsc: Define VESA Display Stream Compression Capabilities
dea28cb7e27a drm/dsc: Define Display Stream Compression PPS infoframe
f915268ebce9 drm/dp: Define payload size for DP SDP PPS packet

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9040/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/dp: Define payload size for DP SDP PPS packet
Okay!

Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!

Commit: drm/dsc: Define VESA Display Stream Compression Capabilities
Okay!

Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes
-
+drivers/gpu/drm/drm_dsc.c:106:43: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:110:42: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:114:45: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:118:44: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:122:43: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:133:50: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:142:57: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:156:47: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:160:49: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:164:47: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:168:45: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:178:46: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:210:63: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:222:47: warning: restricted __be16 degrades to 
integer
+drivers/gpu/drm/drm_dsc.c:226:55: warning: restricted __be16 degrades to 
integer

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f915268ebce9 drm/dp: Define payload size for DP SDP PPS packet
dea28cb7e27a drm/dsc: Define Display Stream Compression PPS infoframe
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#25: 
new file mode 100644

-:30: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#30: FILE: include/drm/drm_dsc.h:1:
+/*

total: 0 errors, 2 warnings, 0 checks, 442 lines checked
c3afd0709328 drm/dsc: Define VESA Display Stream Compression Capabilities
28641b50ce4d drm/dsc: Add helpers for DSC picture parameter set infoframes
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#14: 
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst

-:64: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#64: 
new file mode 100644

-:69: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#69: FILE: drivers/gpu/drm/drm_dsc.c:1:
+/*

-:210: WARNING:LONG_LINE: line over 100 characters
#210: FILE: drivers/gpu/drm/drm_dsc.c:142:
+   pps_sdp->pps_payload.scale_increment_interval = 
DSC_PPS_SWAP_BYTES(dsc_cfg->scale_increment_interval,

-:214: WARNING:LONG_LINE: line over 100 characters
#214: FILE: drivers/gpu/drm/drm_dsc.c:146:
+   pps_sdp->pps_payload.scale_decrement_interval_high = 
(u8)((dsc_cfg->scale_decrement_interval &

-:215: WARNING:LONG_LINE: line over 100 characters
#215: FILE: drivers/gpu/drm/drm_dsc.c:147:
+  
DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>

-:278: WARNING:LONG_LINE: line over 100 characters
#278: FILE: drivers/gpu/drm/drm_dsc.c:210:
+   pps_sdp->pps_payload.rc_range_parameters[i] = 
DSC_PPS_SWAP_BYTES(pps_sdp->pps_payload.rc_range_parameters[i],

-:294: WARNING:LONG_LINE: line over 100 characters
#294: FILE: drivers/gpu/drm/drm_dsc.c:226:
+   pps_sdp->pps_payload.second_line_offset_adj = 
DSC_PPS_SWAP_BYTES(dsc_cfg->second_line_offset_adj,

-:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val' - possible 
side-effects?
#322: FILE: include/drm/drm_dsc.h:43:
+#define DSC_PPS_SWAP_BYTES(val, swap)  ((swap) ? val : 
cpu_to_be16(val))

total: 0 errors, 8 warnings, 1 checks, 288 lines checked

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[Intel-gfx] [PATCH v3 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

[Manasi Navare]

This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.

v3:
* Add a comment for bits_per_component as per DSC spec (Harry Wentland)
v2:
* Fix the comments for kernel-doc

Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Harry Wentland 
---
 include/drm/drm_dsc.h | 442 ++
 1 file changed, 442 insertions(+)
 create mode 100644 include/drm/drm_dsc.h

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 000..73bd0f1
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,442 @@
+/*
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Manasi Navare 
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include 
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big 
Endian
+ * format.
+ */
+struct picture_parameter_set {
+   /**
+* @dsc_version_minor:
+* PPS0[3:0] - Contains Minor version of DSC
+*/
+   u8 dsc_version_minor:4;
+   /**
+* @dsc_version_major:
+* PPS0[7:4] - Contains major version of DSC
+*/
+   u8 dsc_version_major:4;
+   /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+   u8 pps_identifier;
+   /**
+* @pps2_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+   u8 pps2_reserved;
+   /**
+* @linebuf_depth:
+* PPS3[3:0] - Contains linebuffer bit depth used to generate
+* the bitstream. (0x0 - 16 bits for DSc 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+*/
+   u8 linebuf_depth:4;
+   /**
+* @bits_per_component:
+* PPS3[7:4] - Bits per component for the original pixels
+* of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+   u8 bits_per_component:4;
+   /**
+* @bpp_high:
+* PPS4[1:0] - These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+*/
+   u8 bpp_high:2;
+   /**
+* @vbr_enable:
+* PPS4[2] - 0 = VBR disabled, 1 = VBR enabled
+*/
+   u8 vbr_enable:1;
+   /**
+* @simple_422:
+* PPS4[3] - Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+*/
+   u8 simple_422:1;
+   /**
+* @convert_rgb:
+* PPS4[4] - Indicates if DSC color space conversion is active
+*/
+   u8 convert_rgb:1;
+   /**
+* @block_pred_enable:
+* PPS4[5] - Indicates if BP is used to code any groups in picture
+  

[Intel-gfx] [PATCH v3 4/4] drm/dsc: Add helpers for DSC picture parameter set infoframes

[Manasi Navare]

According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.

v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)

v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)

Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Acked-by: Harry Wentland 
---
 Documentation/gpu/drm-kms-helpers.rst |  12 ++
 drivers/gpu/drm/Makefile  |   2 +-
 drivers/gpu/drm/drm_dsc.c | 231 ++
 include/drm/drm_dsc.h |  16 +++
 4 files changed, 260 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c

diff --git a/Documentation/gpu/drm-kms-helpers.rst 
b/Documentation/gpu/drm-kms-helpers.rst
index e37557b..13837f7 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -205,6 +205,18 @@ MIPI DSI Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
 
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :export:
+
 Output Probing Helper Functions Reference
 =
 
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 8873d47..df70373 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
 drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o 
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 000..30e567f
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,231 @@
+/*
+ *Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+   memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+   pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+   pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big 

[Intel-gfx] [PATCH v3 1/4] drm/dp: Define payload size for DP SDP PPS packet

[Manasi Navare]

DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.

Signed-off-by: Manasi Navare 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Harry Wentland 
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c015649..d13e512 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -992,6 +992,7 @@ struct dp_sdp_header {
 
 #define EDP_SDP_HEADER_REVISION_MASK   0x1F
 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
 
 struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
-- 
2.7.4

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[Intel-gfx] [PATCH v3 3/4] drm/dsc: Define VESA Display Stream Compression Capabilities

[Manasi Navare]

From: Gaurav K Singh 

This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder

v3:
Remove the duplicate define (Harry) (From Manasi)

v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)

Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Signed-off-by: Gaurav K Singh 
Reviewed-by: Harry Wentland 
---
 include/drm/drm_dsc.h | 108 ++
 1 file changed, 108 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 73bd0f1..7f6209e 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -31,6 +31,114 @@
 /* VESA Display Stream Compression DSC 1.2 constants */
 #define DSC_NUM_BUF_RANGES 15
 
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+   /* Min Quantization Parameters allowed for this range */
+   u8 range_min_qp;
+   /* Max Quantization Parameters allowed for this range */
+   u8 range_max_qp;
+   /* Bits/group offset to apply to target for this group */
+   u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+   /* Bits / component for previous reconstructed line buffer */
+   u8 line_buf_depth;
+   /* Bits per component to code (must be 8, 10, or 12) */
+   u8 bits_per_component;
+   /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+   bool convert_rgb;
+   u8 slice_count;
+   /* Slice Width */
+   u16 slice_width;
+   /* Slice Height */
+   u16 slice_height;
+   /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+   bool enable422;
+   /* Picture Width */
+   u16 pic_width;
+   /* Picture Height */
+   u16 pic_height;
+   /* Offset to bits/group used by RC to determine QP adjustment */
+   u8 rc_tgt_offset_high;
+   /* Offset to bits/group used by RC to determine QP adjustment */
+   u8 rc_tgt_offset_low;
+   /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+   u16 bits_per_pixel;
+   /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+   u8 rc_edge_factor;
+   /* Slow down incrementing once the range reaches this value */
+   u8 rc_quant_incr_limit1;
+   /* Slow down incrementing once the range reaches this value */
+   u8 rc_quant_incr_limit0;
+   /* Number of pixels to delay the initial transmission */
+   u16 initial_xmit_delay;
+   /* Number of pixels to delay the VLD on the decoder,not including SSM */
+   u16  initial_dec_delay;
+   /* Block prediction enable */
+   bool block_pred_enable;
+   /* Bits/group offset to use for first line of the slice */
+   u8 first_line_bpg_offset;
+   /* Value to use for RC model offset at slice start */
+   u16 initial_offset;
+   /* Thresholds defining each of the buffer ranges */
+   u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+   /* Parameters for each of the RC ranges */
+   struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+   /* Total size of RC model */
+   u16 rc_model_size;
+   /* Minimum QP where flatness information is sent */
+   u8 flatness_min_qp;
+   /* Maximum QP where flatness information is sent */
+   u8 flatness_max_qp;
+   /* Initial value for scale factor */
+   u8 initial_scale_value;
+   /* Decrement scale factor every scale_decrement_interval groups */
+   u16 scale_decrement_interval;
+   /* Increment scale factor every scale_increment_interval groups */
+   u16 scale_increment_interval;
+   /* Non-first line BPG offset to use */
+   u16 nfl_bpg_offset;
+   /* BPG offset used to enforce slice bit */
+   u16 slice_bpg_offset;
+   /* Final RC linear transformation offset value */
+   u16 final_offset;
+   /* Enable on-off VBR (ie., disable stuffing bits) */
+   bool vbr_enable;
+   /* Mux word size (in bits) for SSM mode */
+   u8 mux_word_size;
+   /*
+* The (max) size in bytes of the "chunks" that are
+* used in slice multiplexing
+*/
+   u16 slice_chunk_size;
+   /* Rate Control buffer siz in bits */
+   u16 rc_bits;
+   /* DSC Minor Version */
+   u8 dsc_version_minor;
+   /* DSC Major version */
+ 

Re: [Intel-gfx] [PATCH i-g-t] igt/kms_frontbuffer_tracking: Skip over IGT_DRAW_BLT when there's no BLT

[Antonio Argenziano]

On 17/05/18 02:56, Chris Wilson wrote:

If the blitter is not available, we cannot use it as a source for dirty
rectangles. We shall have to rely on the other engines to create GPU
dirty instead.

v2: Try using lots of subgroup+fixtures

Signed-off-by: Chris Wilson 



TEST_MODE_ITER_BEGIN(t)
+   igt_fixture {
+   if (t.method == IGT_DRAW_BLT)
+   gem_require_blitter(drm.fd); > + }


Put the require inside the subtest so to leave a constant sub-tests 
list. Unless I got lost in the nested macros ;).


Thanks,
Antonio


igt_subtest_f("%s-%s-%s-%s-%s-draw-%s",
  feature_str(t.feature),
  pipes_str(t.pipes),


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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for 
HSW/BDW too
URL   : https://patchwork.freedesktop.org/series/43353/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200_full -> Patchwork_9035_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9035_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9035_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43353/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9035_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  PASS -> SKIP +3


== Known issues ==

  Here are the changes found in Patchwork_9035_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@modeset-vs-vblank-race:
  shard-glk:  PASS -> FAIL (fdo#103060)

igt@kms_flip@plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167) +1

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  DMESG-FAIL -> PASS

igt@kms_flip@basic-flip-vs-dpms:
  shard-hsw:  DMESG-WARN (fdo#102614) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  FAIL (fdo#102887) -> PASS
  shard-glk:  FAIL (fdo#105363) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9035

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9035: 2749433724c67bb7a20f7bbecb4f237b4d054e35 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9035/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

[Paulo Zanoni]

Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu:
> 
> On 5/17/2018 9:55 AM, Michel Thierry wrote:
> > On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
> > > Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
> > > > Stop reading some now deprecated interrupt registers in both
> > > > debugfs and error state. Instead, read the new equivalents in
> > > > the
> > > > Gen11 interrupt repartitioning scheme.
> > > > 
> > > > Note that the equivalent to the PM ISR & IIR cannot be read
> > > > without
> > > > affecting the current state of the system, so I've opted for
> > > > leaving
> > > > them out. See gen11_service_one_iir() for more info.
> > > 
> > > I can't find this function. Did you mean something else?
> > > 
> > 
> > s/gen11_service_one_iir/gen11_reset_one_iir/
> > 
> 
> Yup, that's right. Thanks Michel, I didn't realize this had been
> renamed 
> in upstream.

I fixed this in the commit message, did a small bikeshed on the single-
if-with-braces and merged the patch.

I downloaded your patch through patchwork and it changed your name
(patch author) from "Oscar Mateo" to "Oscar Mateo Lozano" (then dim
push-queued complained the patch was missing author Signed-off-by due
to the name difference, which made me notice it). You may want to
either fix your name in patchwork so it appears as "Oscar Mateo" or
change your git configuration to add the missing name.

Thanks for the patch and reviews.

Thanks,
Paulo

> 
> > > 
> > > 
> > > > 
> > > > v2: else if !!! (Paulo)
> > > > v3: another else if (Vinay)
> > > > v4:
> > > >- Rebased
> > > >- Renamed patch
> > > >- Improved the ordering of GENs
> > > >- Improved the printing of per-GEN info
> > > > v5: Avoid maybe-unitialized & add comment explaining the lack
> > > >  of PM ISR & IIR
> > > > 
> > > > Suggested-by: Paulo Zanoni 
> > > > Signed-off-by: Oscar Mateo 
> > > > Cc: Tvrtko Ursulin 
> > > > Cc: Daniele Ceraolo Spurio 
> > > > Cc: Sagar Arun Kamble 
> > > > Cc: Vinay Belgaumkar 
> > > > ---
> > > >   drivers/gpu/drm/i915/i915_debugfs.c   | 34
> > > > -
> > > > -
> > > >   drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
> > > >   drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
> > > >   3 files changed, 35 insertions(+), 12 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index d663a9e0..d992dd2 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct
> > > > seq_file *m, void *unused)
> > > > intel_uncore_forcewake_put(dev_priv,
> > > > FORCEWAKE_ALL);
> > > >   -if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> > > > -pm_ier = I915_READ(GEN6_PMIER);
> > > > -pm_imr = I915_READ(GEN6_PMIMR);
> > > > -pm_isr = I915_READ(GEN6_PMISR);
> > > > -pm_iir = I915_READ(GEN6_PMIIR);
> > > > -pm_mask = I915_READ(GEN6_PMINTRMSK);
> > > > -} else {
> > > > +if (INTEL_GEN(dev_priv) >= 11) {
> > > > +pm_ier =
> > > > I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> > > > +pm_imr =
> > > > I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
> > > > +/*
> > > > + * The equivalent to the PM ISR & IIR cannot
> > > > be read
> > > > + * without affecting the current state of
> > > > the system
> > > > + */
> > > > +pm_isr = 0;
> > > > +pm_iir = 0;
> > > > +} else if (INTEL_GEN(dev_priv) >= 8) {
> > > >   pm_ier = I915_READ(GEN8_GT_IER(2));
> > > >   pm_imr = I915_READ(GEN8_GT_IMR(2));
> > > >   pm_isr = I915_READ(GEN8_GT_ISR(2));
> > > >   pm_iir = I915_READ(GEN8_GT_IIR(2));
> > > > -pm_mask = I915_READ(GEN6_PMINTRMSK);
> > > > +} else {
> > > > +pm_ier = I915_READ(GEN6_PMIER);
> > > > +pm_imr = I915_READ(GEN6_PMIMR);
> > > > +pm_isr = I915_READ(GEN6_PMISR);
> > > > +pm_iir = I915_READ(GEN6_PMIIR);
> > > >   }
> > > > +pm_mask = I915_READ(GEN6_PMINTRMSK);
> > > > +
> > > >   seq_printf(m, "Video Turbo Mode: %s\n",
> > > >  yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
> > > >   seq_printf(m, "HW control enabled: %s\n",
> > > > @@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct
> > > > seq_file
> > > > *m, void *unused)
> > > >   seq_printf(m, "SW control enabled: %s\n",
> > > >  yesno((rpmodectl &
> > > > GEN6_RP_MEDIA_MODE_MASK) ==
> > > > GEN6_RP_MEDIA_SW_MODE));
> > > > -seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
> > > > IIR=0x%08x, 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV 
and CHV
URL   : https://patchwork.freedesktop.org/series/43368/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201 -> Patchwork_9039 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43368/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9039 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-4200u:   PASS -> DMESG-FAIL (fdo#102614, fdo#106103)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-cnl-y3:  FAIL (fdo#104724, fdo#103167) -> PASS


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9039

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9039: b3fc769740221068d91eb1879d9daa75ef108dd3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

b3fc76974022 drm/i915/psr: Avoid PSR exit max time timeout
1e477b3f6103 drm/i915/psr/bdw+: Enable CRC check in the static frame on the 
sink side
3a64512fbe43 drm/i915/psr: Handle PSR RFB storage error
704b28a727be drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
03733f0d0e8c drm/i915/psr: Remove intel_crtc_state parameter from disable()
76eeb06056e8 drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux 
xfer
6e561e557b3d drm/i915/psr: Nuke PSR support for VLV and CHV

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9039/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV 
and CHV
URL   : https://patchwork.freedesktop.org/series/43368/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Nuke PSR support for VLV and CHV
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3663:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3662:16: warning: expression 
using sizeof(void)

Commit: drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux xfer
Okay!

Commit: drm/i915/psr: Remove intel_crtc_state parameter from disable()
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3662:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3661:16: warning: expression 
using sizeof(void)

Commit: drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
Okay!

Commit: drm/i915/psr: Handle PSR RFB storage error
Okay!

Commit: drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side
Okay!

Commit: drm/i915/psr: Avoid PSR exit max time timeout
-O:drivers/gpu/drm/i915/intel_psr.c:387:32: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:386:32: warning: expression using sizeof(void)

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/7] drm/i915/psr: Nuke PSR support for VLV 
and CHV
URL   : https://patchwork.freedesktop.org/series/43368/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6e561e557b3d drm/i915/psr: Nuke PSR support for VLV and CHV
76eeb06056e8 drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux 
xfer
03733f0d0e8c drm/i915/psr: Remove intel_crtc_state parameter from disable()
704b28a727be drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
3a64512fbe43 drm/i915/psr: Handle PSR RFB storage error
1e477b3f6103 drm/i915/psr/bdw+: Enable CRC check in the static frame on the 
sink side
-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:4023:
+#define   EDP_PSR_CRC_ENABLE   (1<<10) /* BDW+ */
  ^

total: 0 errors, 0 warnings, 1 checks, 66 lines checked
b3fc76974022 drm/i915/psr: Avoid PSR exit max time timeout
-:48: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#48: FILE: drivers/gpu/drm/i915/intel_psr.c:642:
+   I915_WRITE(EDP_PSR_DEBUG,
+ EDP_PSR_DEBUG_MASK_MEMUP |

total: 0 errors, 0 warnings, 1 checks, 32 lines checked

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Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Keep guc submission permanently engaged

[Chris Wilson]

Quoting Chris Wilson (2018-05-17 21:06:10)
> We make a decision at module load whether to use the GuC backend or not,
> but lose that setup across set-wedge. Currently, the guc doesn't
> override the engine->set_default_submission hook letting execlists sneak
> back in temporarily on unwedging leading to an unbalanced park/unpark.
> 
> v2: Remove comment about switching back temporarily to execlists on
> guc_submission_disable(). We currently only call disable on shutdown,
> and plan to also call disable before suspend and reset, in which case we
> will either restore guc submission or mark the driver as wedged, making
> the reset back to execlists pointless.
> 
> Testcase: igt/gem_eio
> Signed-off-by: Chris Wilson 
> Cc: Michał Winiarski 
> Cc: Michal Wajdeczko 

I think this makes sense given the current limitations; and fixes the
crash we have in gem_eio on guc. Worth pulling into your series Michal
and giving it another spin?
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/guc: Keep guc submission permanently engaged

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Keep guc submission 
permanently engaged
URL   : https://patchwork.freedesktop.org/series/43352/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4200_full -> Patchwork_9034_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9034_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9034_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43352/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9034_full:

  === IGT changes ===

 Possible regressions 

igt@debugfs_test@read_all_entries_display_off:
  shard-kbl:  PASS -> DMESG-WARN

igt@drv_selftest@live_guc:
  shard-kbl:  PASS -> DMESG-FAIL

igt@drv_selftest@live_hangcheck:
  shard-apl:  PASS -> DMESG-FAIL +1

igt@perf@gen8-unprivileged-single-ctx-counters:
  shard-kbl:  PASS -> FAIL
  shard-apl:  PASS -> FAIL

igt@pm_rpm@debugfs-read:
  shard-apl:  PASS -> DMESG-WARN


 Warnings 

igt@drv_missed_irq:
  shard-apl:  PASS -> SKIP

igt@perf@polling:
  shard-kbl:  PASS -> SKIP +37


== Known issues ==

  Here are the changes found in Patchwork_9034_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
  shard-glk:  PASS -> FAIL (fdo#106509, fdo#105454)

igt@kms_cursor_legacy@flip-vs-cursor-atomic:
  shard-hsw:  PASS -> FAIL (fdo#102670)

igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060) +1

igt@kms_flip@flip-vs-blocking-wf-vblank:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#102887, fdo#105363)

igt@kms_flip@plain-flip-ts-check:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167)

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)

igt@perf_pmu@busy-accuracy-50-rcs0:
  shard-kbl:  PASS -> FAIL (fdo#105157)


 Possible fixes 

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105707) -> PASS

igt@kms_flip@basic-flip-vs-dpms:
  shard-hsw:  DMESG-WARN (fdo#102614) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-hsw:  FAIL (fdo#102887) -> PASS
  shard-glk:  FAIL (fdo#105363) -> PASS

igt@kms_setmode@basic:
  shard-hsw:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105157 https://bugs.freedesktop.org/show_bug.cgi?id=105157
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9034

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9034: 94d5d62f10afa7758aa93e7568b5d85e6489861d @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9034/shards.html
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[Intel-gfx] [PATCH v3 7/7] drm/i915/psr: Avoid PSR exit max time timeout

[José Roberto de Souza]

Also masking max time as a trigger to exit PSR for the remaning
platforms that do not support sink CRC check(gen <= 8).
This will make PSR exits more deterministic and only when really
needed. If this was used to fix a issue in some pannel than can
only self-refresh for a few seconds, that panel will interrupt
and assert one of the PSR errors handled in:
'drm/i915/psr: Handle PSR RFB storage error' and
'drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink'

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_psr.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2f29dcd6f69e..8e2e90d139b5 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -376,7 +376,6 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
 
-   uint32_t max_sleep_time = 0x1f;
/*
 * Let's respect VBT in case VBT asks a higher idle_frame value.
 * Let's use 6 as the minimum to cover all known cases including
@@ -387,7 +386,6 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = EDP_PSR_ENABLE;
 
-   val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
if (IS_HASWELL(dev_priv))
@@ -640,14 +638,12 @@ static void hsw_psr_enable_source(struct intel_dp 
*intel_dp,
 * preventing  other hw tracking issues now we can rely
 * on frontbuffer tracking.
 */
-   u32 val = EDP_PSR_DEBUG_MASK_MEMUP |
+   I915_WRITE(EDP_PSR_DEBUG,
+ EDP_PSR_DEBUG_MASK_MEMUP |
  EDP_PSR_DEBUG_MASK_HPD |
  EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
-
-   if (INTEL_GEN(dev_priv) >= 8)
-   val |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
-   I915_WRITE(EDP_PSR_DEBUG, val);
+ EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
+ EDP_PSR_DEBUG_MASK_MAX_SLEEP);
}
 }
 
-- 
2.17.0

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[Intel-gfx] [PATCH v3 2/7] drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux xfer

[José Roberto de Souza]

This reduces the spaghetti that intel_dp_aux_xfer() and reuses code.
The only difference is that now it will wait up to 10ms instead of
3ms.

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_dp.c | 20 +++-
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2cc58596ff5a..b86da48fd38e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1102,23 +1102,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
intel_dp_check_edp(intel_dp);
 
/* Try to wait for any previous AUX channel activity */
-   for (try = 0; try < 3; try++) {
-   status = I915_READ_NOTRACE(ch_ctl);
-   if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
-   break;
-   msleep(1);
-   }
-
-   if (try == 3) {
-   static u32 last_status = -1;
-   const u32 status = I915_READ(ch_ctl);
-
-   if (status != last_status) {
-   WARN(1, "dp_aux_ch not started status 0x%08x\n",
-status);
-   last_status = status;
-   }
-
+   status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
+   if (status & DP_AUX_CH_CTL_SEND_BUSY) {
+   DRM_WARN("dp_aux_ch not started status 0x%08x\n", status);
ret = -EBUSY;
goto out;
}
-- 
2.17.0

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[Intel-gfx] [PATCH v3 1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

[José Roberto de Souza]

From: Dhinakaran Pandiyan 

PSR hardware and hence the driver code for VLV and CHV deviates a lot from
their DDI counterparts. While the feature has been disabled for a long time
now, retaining support for these platforms is a maintenance burden. There
have been multiple refactoring commits to just keep the existing code for
these platforms in line with the rest. There are known issues that need to
be fixed to enable PSR on these platforms, and there is no PSR capable
platform in CI to ensure the code does not break again if we get around to
fixing the existing issues. On account of all these reasons, let's nuke
this code for now and bring it back if a need arises in the future.

Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Cc: Ville Syrjälä 
Signed-off-by: Dhinakaran Pandiyan 
Acked-by: Jani Nikula 
Acked-by: Rodrigo Vivi  
---

Please review this one here: https://patchwork.freedesktop.org/patch/30/

 drivers/gpu/drm/i915/i915_debugfs.c  |  42 +---
 drivers/gpu/drm/i915/i915_drv.h  |   1 -
 drivers/gpu/drm/i915/i915_pci.c  |   2 -
 drivers/gpu/drm/i915/intel_drv.h |   2 -
 drivers/gpu/drm/i915/intel_frontbuffer.c |   2 -
 drivers/gpu/drm/i915/intel_psr.c | 248 ++-
 6 files changed, 27 insertions(+), 270 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13e7b9e4a6e6..0096e209fe04 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2630,8 +2630,6 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
u32 psrperf = 0;
-   u32 stat[3];
-   enum pipe pipe;
bool enabled = false;
bool sink_support;
 
@@ -2652,47 +2650,17 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
seq_printf(m, "Re-enable work scheduled: %s\n",
   yesno(work_busy(_priv->psr.work.work)));
 
-   if (HAS_DDI(dev_priv)) {
-   if (dev_priv->psr.psr2_enabled)
-   enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
-   else
-   enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
-   } else {
-   for_each_pipe(dev_priv, pipe) {
-   enum transcoder cpu_transcoder =
-   intel_pipe_to_cpu_transcoder(dev_priv, pipe);
-   enum intel_display_power_domain power_domain;
-
-   power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
-   if (!intel_display_power_get_if_enabled(dev_priv,
-   power_domain))
-   continue;
-
-   stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
-   VLV_EDP_PSR_CURR_STATE_MASK;
-   if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
-   (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
-   enabled = true;
-
-   intel_display_power_put(dev_priv, power_domain);
-   }
-   }
+   if (dev_priv->psr.psr2_enabled)
+   enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
+   else
+   enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
 
seq_printf(m, "Main link in standby mode: %s\n",
   yesno(dev_priv->psr.link_standby));
 
-   seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
-
-   if (!HAS_DDI(dev_priv))
-   for_each_pipe(dev_priv, pipe) {
-   if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
-   (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
-   seq_printf(m, " pipe %c", pipe_name(pipe));
-   }
-   seq_puts(m, "\n");
+   seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
 
/*
-* VLV/CHV PSR has no kind of performance counter
 * SKL+ Perf counter is reset to 0 everytime DC state is entered
 */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34c125e2d90c..c58c5dae4424 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -607,7 +607,6 @@ struct i915_psr {
bool link_standby;
bool colorimetry_support;
bool alpm;
-   bool has_hw_tracking;
bool psr2_enabled;
u8 sink_sync_latency;
bool debug;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4364922e935d..97a91e6af7e3 100644
--- 

[Intel-gfx] [PATCH v3 5/7] drm/i915/psr: Handle PSR RFB storage error

[José Roberto de Souza]

Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.

v3:
disabling PSR instead of exiting on error

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_psr.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 60797c8f9f0e..f72e3f91809f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1046,6 +1046,20 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
psr_disable(intel_dp);
}
 
+   if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_ERROR_STATUS, ) != 1) {
+   DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
+   goto exit;
+   }
+
+   if (val & DP_PSR_RFB_STORAGE_ERROR) {
+   DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
+   psr_disable(intel_dp);
+   }
+   if (val & (DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR))
+   DRM_ERROR("PSR_ERROR_STATUS not handled %x\n", val);
+   /* clear status register */
+   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val);
+
/* TODO: handle other PSR/PSR2 errors */
 exit:
mutex_unlock(>lock);
-- 
2.17.0

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[Intel-gfx] [PATCH v3 3/7] drm/i915/psr: Remove intel_crtc_state parameter from disable()

[José Roberto de Souza]

It was only used in VLV/CHV so after the removal of the PSR support
for those platforms it is not necessary any more.

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 +--
 drivers/gpu/drm/i915/intel_psr.c | 5 ++---
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c58c5dae4424..34e3449ea182 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -615,8 +615,7 @@ struct i915_psr {
 
void (*enable_source)(struct intel_dp *,
  const struct intel_crtc_state *);
-   void (*disable_source)(struct intel_dp *,
-  const struct intel_crtc_state *);
+   void (*disable_source)(struct intel_dp *intel_dp);
void (*enable_sink)(struct intel_dp *);
void (*activate)(struct intel_dp *);
void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 29443d2c35bb..d88799482875 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -698,8 +698,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
mutex_unlock(_priv->psr.lock);
 }
 
-static void hsw_psr_disable(struct intel_dp *intel_dp,
-   const struct intel_crtc_state *old_crtc_state)
+static void hsw_psr_disable(struct intel_dp *intel_dp)
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -768,7 +767,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
return;
}
 
-   dev_priv->psr.disable_source(intel_dp, old_crtc_state);
+   dev_priv->psr.disable_source(intel_dp);
 
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
-- 
2.17.0

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[Intel-gfx] [PATCH v3 6/7] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

[José Roberto de Souza]

Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.

Also spec recommends to disable MAX_SLEEP as a trigger to exit PSR when
CRC check is enabled to improve power savings.

Spec: 7723

v3:
disabling PSR instead of exiting on error

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 29 -
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb79272..1add22e664ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4020,6 +4020,7 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL  (1<<11)
+#define   EDP_PSR_CRC_ENABLE   (1<<10) /* BDW+ */
 #define   EDP_PSR_TP2_TP3_TIME_500us   (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us   (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us  (2<<8)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f72e3f91809f..2f29dcd6f69e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -363,6 +363,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
dpcd_val |= DP_PSR_ENABLE_PSR2;
if (dev_priv->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+   if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
+   dpcd_val |= DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -418,6 +420,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
 
+   if (INTEL_GEN(dev_priv) >= 8)
+   val |= EDP_PSR_CRC_ENABLE;
+
val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
I915_WRITE(EDP_PSR_CTL, val);
 }
@@ -635,11 +640,14 @@ static void hsw_psr_enable_source(struct intel_dp 
*intel_dp,
 * preventing  other hw tracking issues now we can rely
 * on frontbuffer tracking.
 */
-   I915_WRITE(EDP_PSR_DEBUG,
-  EDP_PSR_DEBUG_MASK_MEMUP |
-  EDP_PSR_DEBUG_MASK_HPD |
-  EDP_PSR_DEBUG_MASK_LPSP |
-  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
+   u32 val = EDP_PSR_DEBUG_MASK_MEMUP |
+ EDP_PSR_DEBUG_MASK_HPD |
+ EDP_PSR_DEBUG_MASK_LPSP |
+ EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+   if (INTEL_GEN(dev_priv) >= 8)
+   val |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+   I915_WRITE(EDP_PSR_DEBUG, val);
}
 }
 
@@ -1051,16 +1059,19 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
goto exit;
}
 
-   if (val & DP_PSR_RFB_STORAGE_ERROR) {
-   DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
+   if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR)) {
+   if (val & DP_PSR_RFB_STORAGE_ERROR)
+   DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
+   if (val & DP_PSR_LINK_CRC_ERROR)
+   DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
psr_disable(intel_dp);
}
-   if (val & (DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR))
+   if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
DRM_ERROR("PSR_ERROR_STATUS not handled %x\n", val);
/* clear status register */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val);
 
-   /* TODO: handle other PSR/PSR2 errors */
+   /* TODO: handle PSR2 errors */
 exit:
mutex_unlock(>lock);
 }
-- 
2.17.0

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[Intel-gfx] [PATCH v3 4/7] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

[José Roberto de Souza]

eDP spec states that sink device will do a short pulse in HPD
line when there is a PSR/PSR2 error that needs to be handled by
source, this is handling the first and most simples error:
DP_PSR_SINK_INTERNAL_ERROR.

Here taking the safest approach and disabling PSR(at least until
the next modeset), to avoid multiple rendering issues due to
bad pannels.

v3:
disabling PSR instead of exiting on error

Cc: Dhinakaran Pandiyan 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_dp.c  |  2 ++
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 62 +---
 3 files changed, 52 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b86da48fd38e..fa2851d4fb36 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4479,6 +4479,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
if (intel_dp_needs_link_retrain(intel_dp))
return false;
 
+   intel_psr_short_pulse(intel_dp);
+
if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
/* Send a Hotplug Uevent to userspace to start modeset */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4508be628450..892da65358e9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1921,6 +1921,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
  struct intel_crtc_state *crtc_state);
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
+void intel_psr_short_pulse(struct intel_dp *intel_dp);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d88799482875..60797c8f9f0e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -741,6 +741,23 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
psr_aux_io_power_put(intel_dp);
 }
 
+static void psr_disable(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   if (!dev_priv->psr.enabled)
+   return;
+
+   dev_priv->psr.disable_source(intel_dp);
+
+   /* Disable PSR on Sink */
+   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
+   dev_priv->psr.enabled = NULL;
+   cancel_delayed_work_sync(_priv->psr.work);
+}
+
 /**
  * intel_psr_disable - Disable PSR
  * @intel_dp: Intel DP
@@ -762,20 +779,8 @@ void intel_psr_disable(struct intel_dp *intel_dp,
return;
 
mutex_lock(_priv->psr.lock);
-   if (!dev_priv->psr.enabled) {
-   mutex_unlock(_priv->psr.lock);
-   return;
-   }
-
-   dev_priv->psr.disable_source(intel_dp);
-
-   /* Disable PSR on Sink */
-   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
-
-   dev_priv->psr.enabled = NULL;
+   psr_disable(intel_dp);
mutex_unlock(_priv->psr.lock);
-
-   cancel_delayed_work_sync(_priv->psr.work);
 }
 
 static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
@@ -1014,3 +1019,34 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
 
 }
+
+void intel_psr_short_pulse(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct i915_psr *psr = _priv->psr;
+   uint8_t val;
+
+   if (!HAS_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
+   return;
+
+   mutex_lock(>lock);
+
+   if (psr->enabled != intel_dp)
+   goto exit;
+
+   if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, ) != 1) {
+   DRM_ERROR("PSR_STATUS dpcd read failed\n");
+   goto exit;
+   }
+
+   if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
+   DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
+   psr_disable(intel_dp);
+   }
+
+   /* TODO: handle other PSR/PSR2 errors */
+exit:
+   mutex_unlock(>lock);
+}
-- 
2.17.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Move request->ctx aside

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Move request->ctx aside
URL   : https://patchwork.freedesktop.org/series/43363/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201 -> Patchwork_9038 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9038 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9038, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43363/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9038:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9038 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-4200u:   PASS -> DMESG-FAIL (fdo#102614, fdo#106103)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
  fi-skl-6770hq:  PASS -> FAIL (fdo#103481)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128) -> PASS

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: FAIL (fdo#102575) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-cnl-y3:  FAIL (fdo#104724, fdo#103167) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4201 -> Patchwork_9038

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9038: 2c493945260f30f5c84326521ac8368db05309fa @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

2c493945260f drm/i915: Pull the context->pin_count dec into the common 
intel_context_unpin
d07c5249461e drm/i915: Store a pointer to intel_context in i915_request
bad6e2451dd0 drm/i915: Move fiddling with engine->last_retired_context
8fcf7c152cf1 drm/i915: Move request->ctx aside

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9038/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Move request->ctx aside

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Move request->ctx aside
URL   : https://patchwork.freedesktop.org/series/43363/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Move request->ctx aside
Okay!

Commit: drm/i915: Move fiddling with engine->last_retired_context
Okay!

Commit: drm/i915: Store a pointer to intel_context in i915_request
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3663:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Pull the context->pin_count dec into the common 
intel_context_unpin
Okay!

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[Intel-gfx] [PATCH 3/4] drm/i915: Store a pointer to intel_context in i915_request

[Chris Wilson]

To ease the frequent and ugly pointer dance of
>gem_context->engine[request->engine->id] during request
submission, store that pointer as request->hw_context. One major
advantage that we will exploit later is that this decouples the logical
context state from the engine itself.

v2: Set mock_context->ops so we don't crash and burn in selftests.
Cleanups from Tvrtko.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gvt/mmio_context.c   |   6 +-
 drivers/gpu/drm/i915/gvt/mmio_context.h   |   2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c  | 141 +++---
 drivers/gpu/drm/i915/gvt/scheduler.h  |   1 -
 drivers/gpu/drm/i915/i915_drv.h   |   1 +
 drivers/gpu/drm/i915/i915_gem.c   |  12 +-
 drivers/gpu/drm/i915/i915_gem_context.c   |  17 ++-
 drivers/gpu/drm/i915/i915_gem_context.h   |  21 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c |   3 +-
 drivers/gpu/drm/i915/i915_perf.c  |  25 ++--
 drivers/gpu/drm/i915/i915_request.c   |  34 ++---
 drivers/gpu/drm/i915/i915_request.h   |   1 +
 drivers/gpu/drm/i915/intel_engine_cs.c|  54 ---
 drivers/gpu/drm/i915/intel_guc_submission.c   |  10 +-
 drivers/gpu/drm/i915/intel_lrc.c  | 125 +---
 drivers/gpu/drm/i915/intel_lrc.h  |   7 -
 drivers/gpu/drm/i915/intel_ringbuffer.c   | 100 -
 drivers/gpu/drm/i915/intel_ringbuffer.h   |   9 +-
 drivers/gpu/drm/i915/selftests/mock_context.c |   7 +
 drivers/gpu/drm/i915/selftests/mock_engine.c  |  41 +++--
 20 files changed, 321 insertions(+), 296 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c 
b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 0f949554d118..708170e61625 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -446,9 +446,9 @@ static void switch_mocs(struct intel_vgpu *pre, struct 
intel_vgpu *next,
 
 #define CTX_CONTEXT_CONTROL_VAL0x03
 
-bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id)
+bool is_inhibit_context(struct intel_context *ce)
 {
-   u32 *reg_state = ctx->__engine[ring_id].lrc_reg_state;
+   const u32 *reg_state = ce->lrc_reg_state;
u32 inhibit_mask =
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
 
@@ -501,7 +501,7 @@ static void switch_mmio(struct intel_vgpu *pre,
 * itself.
 */
if (mmio->in_context &&
-   !is_inhibit_context(s->shadow_ctx, ring_id))
+   
!is_inhibit_context(>shadow_ctx->__engine[ring_id]))
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h 
b/drivers/gpu/drm/i915/gvt/mmio_context.h
index 0439eb8057a8..5c3b9ff9f96a 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
@@ -49,7 +49,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
 
 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
 
-bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id);
+bool is_inhibit_context(struct intel_context *ce);
 
 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
   struct i915_request *req);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 17f9f8d7e148..e1760030dda1 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -54,11 +54,8 @@ static void set_context_pdp_root_pointer(
 
 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
 {
-   struct intel_vgpu *vgpu = workload->vgpu;
-   int ring_id = workload->ring_id;
-   struct i915_gem_context *shadow_ctx = vgpu->submission.shadow_ctx;
struct drm_i915_gem_object *ctx_obj =
-   shadow_ctx->__engine[ring_id].state->obj;
+   workload->req->hw_context->state->obj;
struct execlist_ring_context *shadow_ring_context;
struct page *page;
 
@@ -128,9 +125,8 @@ static int populate_shadow_context(struct 
intel_vgpu_workload *workload)
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
int ring_id = workload->ring_id;
-   struct i915_gem_context *shadow_ctx = vgpu->submission.shadow_ctx;
struct drm_i915_gem_object *ctx_obj =
-   shadow_ctx->__engine[ring_id].state->obj;
+   workload->req->hw_context->state->obj;
struct execlist_ring_context *shadow_ring_context;
struct page *page;
void *dst;
@@ -280,10 +276,8 @@ static int shadow_context_status_change(struct 
notifier_block *nb,
return NOTIFY_OK;
 }
 
-static void shadow_context_descriptor_update(struct i915_gem_context *ctx,
-   

[Intel-gfx] [PATCH 4/4] drm/i915: Pull the context->pin_count dec into the common intel_context_unpin

[Chris Wilson]

As all backends implement the same pin_count mechanism and do a
dec-and-test as their first step, pull that into the common
intel_context_unpin(). This also pulls into the caller, eliminating the
indirect call in the usual steady state case. The intel_context_pin()
side is a little more complicated as it combines the lookup/alloc as
well as pinning the state, and so is left for a later date.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_context.h  |  4 
 drivers/gpu/drm/i915/intel_lrc.c | 13 +
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  6 --
 drivers/gpu/drm/i915/selftests/mock_engine.c |  3 ---
 4 files changed, 5 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 749a4ff566f5..c3262b4dd2ee 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -285,6 +285,10 @@ static inline void __intel_context_pin(struct 
intel_context *ce)
 
 static inline void intel_context_unpin(struct intel_context *ce)
 {
+   GEM_BUG_ON(!ce->pin_count);
+   if (--ce->pin_count)
+   return;
+
GEM_BUG_ON(!ce->ops);
ce->ops->unpin(ce);
 }
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 89a3a31721da..3744f5750624 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1342,7 +1342,7 @@ static void execlists_context_destroy(struct 
intel_context *ce)
__i915_gem_object_release_unless_active(ce->state->obj);
 }
 
-static void __execlists_context_unpin(struct intel_context *ce)
+static void execlists_context_unpin(struct intel_context *ce)
 {
intel_ring_unpin(ce->ring);
 
@@ -1353,17 +1353,6 @@ static void __execlists_context_unpin(struct 
intel_context *ce)
i915_gem_context_put(ce->gem_context);
 }
 
-static void execlists_context_unpin(struct intel_context *ce)
-{
-   lockdep_assert_held(>gem_context->i915->drm.struct_mutex);
-   GEM_BUG_ON(ce->pin_count == 0);
-
-   if (--ce->pin_count)
-   return;
-
-   __execlists_context_unpin(ce);
-}
-
 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
 {
unsigned int flags;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0c0c9f531e4e..001cf6bcb349 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1195,12 +1195,6 @@ static void intel_ring_context_destroy(struct 
intel_context *ce)
 
 static void intel_ring_context_unpin(struct intel_context *ce)
 {
-   lockdep_assert_held(>gem_context->i915->drm.struct_mutex);
-   GEM_BUG_ON(ce->pin_count == 0);
-
-   if (--ce->pin_count)
-   return;
-
if (ce->state) {
ce->state->obj->pin_global--;
i915_vma_unpin(ce->state);
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c 
b/drivers/gpu/drm/i915/selftests/mock_engine.c
index 33eddfc1f8ce..f1ac7453053e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -74,9 +74,6 @@ static void hw_delay_complete(struct timer_list *t)
 
 static void mock_context_unpin(struct intel_context *ce)
 {
-   if (--ce->pin_count)
-   return;
-
i915_gem_context_put(ce->gem_context);
 }
 
-- 
2.17.0

___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/huc: Load HuC v03.00.2555 for Geminilake.

[John Spotswood]

On Fri, 2018-04-27 at 16:33 -0700, Anusha Srivatsa wrote:
> load the v03.00.2555 huC on geminilake.
> 
> Cc: Tomi Sarvela 
> Cc: Jani Saarinen 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/intel_huc_fw.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
> b/drivers/gpu/drm/i915/intel_huc_fw.c
> index f93d238..5e96690 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -34,6 +34,10 @@
>  #define KBL_HUC_FW_MINOR 00
>  #define KBL_BLD_NUM 1810
>  
> +#define GLK_HUC_FW_MAJOR 02
> +#define GLK_HUC_FW_MINOR 00
> +#define GLK_BLD_NUM 1810

Is this version number a cut-n-paste error?  It seems to be the
version number as KBL directly above it.

> +
>  #define HUC_FW_PATH(platform, major, minor, bld_num) \
>   "i915/" __stringify(platform) "_huc_ver" __stringify(major)
> "_" \
>   __stringify(minor) "_" __stringify(bld_num) ".bin"
> @@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
>   KBL_HUC_FW_MINOR, KBL_BLD_NUM)
>  MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
>  
> +#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
> + GLK_HUC_FW_MINOR, GLK_BLD_NUM)
> +MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
> +
>  static void huc_fw_select(struct intel_uc_fw *huc_fw)
>  {
>   struct intel_huc *huc = container_of(huc_fw, struct
> intel_huc, fw);
> @@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw
> *huc_fw)
>   huc_fw->path = I915_KBL_HUC_UCODE;
>   huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
>   huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
> + } else if (IS_GEMINILAKE(dev_priv)) {
> + huc_fw->path = I915_GLK_HUC_UCODE;
> + huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
> + huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
>   } else {
>   DRM_WARN("%s: No firmware known for this
> platform!\n",
>    intel_uc_fw_type_repr(huc_fw->type));
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[Intel-gfx] [PATCH 2/4] drm/i915: Move fiddling with engine->last_retired_context

[Chris Wilson]

Move the knowledge about resetting the current context tracking on the
engine from inside i915_gem_context.c into intel_engine_cs.c

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 12 ++--
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 4bf18b5c6f1d..9e70f4dfa703 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -514,16 +514,8 @@ void i915_gem_contexts_lost(struct drm_i915_private 
*dev_priv)
 
lockdep_assert_held(_priv->drm.struct_mutex);
 
-   for_each_engine(engine, dev_priv, id) {
-   engine->legacy_active_context = NULL;
-   engine->legacy_active_ppgtt = NULL;
-
-   if (!engine->last_retired_context)
-   continue;
-
-   intel_context_unpin(engine->last_retired_context, engine);
-   engine->last_retired_context = NULL;
-   }
+   for_each_engine(engine, dev_priv, id)
+   intel_engine_lost_context(engine);
 }
 
 void i915_gem_contexts_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7983b8a1ad44..9e618aab6568 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1096,6 +1096,29 @@ void intel_engines_unpark(struct drm_i915_private *i915)
}
 }
 
+/**
+ * intel_engine_lost_context: called when the GPU is reset into unknown state
+ * @engine: the engine
+ *
+ * We have either reset the GPU or otherwise about to lose state tracking of
+ * the current GPU logical state (e.g. suspend). On next use, it is therefore
+ * imperative that we make no presumptions about the current state and load
+ * from scratch.
+ */
+void intel_engine_lost_context(struct intel_engine_cs *engine)
+{
+   struct i915_gem_context *ctx;
+
+   lockdep_assert_held(>i915->drm.struct_mutex);
+
+   engine->legacy_active_context = NULL;
+   engine->legacy_active_ppgtt = NULL;
+
+   ctx = fetch_and_zero(>last_retired_context);
+   if (ctx)
+   intel_context_unpin(ctx, engine);
+}
+
 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
 {
switch (INTEL_GEN(engine->i915)) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 61f385a92484..2b16185e36c4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -1053,6 +1053,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine);
 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
 
 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine);
+void intel_engine_lost_context(struct intel_engine_cs *engine);
 
 void intel_engines_park(struct drm_i915_private *i915);
 void intel_engines_unpark(struct drm_i915_private *i915);
-- 
2.17.0

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[Intel-gfx] [PATCH 1/4] drm/i915: Move request->ctx aside

[Chris Wilson]

In the next patch, we want to store the intel_context pointer inside
i915_request, as it is frequently access via a convoluted dance when
submitting the request to hw. Having two context pointers inside
i915_request leads to confusion so first rename the existing
i915_gem_context pointer to i915_request.gem_context.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gvt/scheduler.c  |  4 +--
 drivers/gpu/drm/i915/i915_debugfs.c   |  4 +--
 drivers/gpu/drm/i915/i915_gem.c   | 10 +++---
 drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++-
 drivers/gpu/drm/i915/i915_request.c   | 12 +++
 drivers/gpu/drm/i915/i915_request.h   |  2 +-
 drivers/gpu/drm/i915/i915_trace.h | 10 +++---
 drivers/gpu/drm/i915/intel_engine_cs.c|  2 +-
 drivers/gpu/drm/i915/intel_guc_submission.c   |  7 +++--
 drivers/gpu/drm/i915/intel_lrc.c  | 31 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c   | 12 +++
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  5 ++-
 drivers/gpu/drm/i915/selftests/intel_lrc.c|  2 +-
 13 files changed, 64 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index c2d183b91500..17f9f8d7e148 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -205,7 +205,7 @@ static int populate_shadow_context(struct 
intel_vgpu_workload *workload)
 
 static inline bool is_gvt_request(struct i915_request *req)
 {
-   return i915_gem_context_force_single_submission(req->ctx);
+   return i915_gem_context_force_single_submission(req->gem_context);
 }
 
 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
@@ -305,7 +305,7 @@ static int copy_workload_to_ring_buffer(struct 
intel_vgpu_workload *workload)
struct i915_request *req = workload->req;
 
if (IS_KABYLAKE(req->i915) &&
-   is_inhibit_context(req->ctx, req->engine->id))
+   is_inhibit_context(req->gem_context, req->engine->id))
intel_vgpu_restore_inhibit_context(vgpu, req);
 
/* allocate shadow ring buffer */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 13e7b9e4a6e6..ee8e2ff2c426 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -542,8 +542,8 @@ static int i915_gem_object_info(struct seq_file *m, void 
*data)
   struct i915_request,
   client_link);
rcu_read_lock();
-   task = pid_task(request && request->ctx->pid ?
-   request->ctx->pid : file->pid,
+   task = pid_task(request && request->gem_context->pid ?
+   request->gem_context->pid : file->pid,
PIDTYPE_PID);
print_file_stats(m, task ? task->comm : "", stats);
rcu_read_unlock();
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b0fe452ce17c..a20f8db5729d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3067,7 +3067,7 @@ static void skip_request(struct i915_request *request)
 static void engine_skip_context(struct i915_request *request)
 {
struct intel_engine_cs *engine = request->engine;
-   struct i915_gem_context *hung_ctx = request->ctx;
+   struct i915_gem_context *hung_ctx = request->gem_context;
struct i915_timeline *timeline = request->timeline;
unsigned long flags;
 
@@ -3077,7 +3077,7 @@ static void engine_skip_context(struct i915_request 
*request)
spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
 
list_for_each_entry_continue(request, >timeline.requests, link)
-   if (request->ctx == hung_ctx)
+   if (request->gem_context == hung_ctx)
skip_request(request);
 
list_for_each_entry(request, >requests, link)
@@ -3123,11 +3123,11 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
}
 
if (stalled) {
-   i915_gem_context_mark_guilty(request->ctx);
+   i915_gem_context_mark_guilty(request->gem_context);
skip_request(request);
 
/* If this context is now banned, skip all pending requests. */
-   if (i915_gem_context_is_banned(request->ctx))
+   if (i915_gem_context_is_banned(request->gem_context))
engine_skip_context(request);
} else {
/*
@@ -3137,7 +3137,7 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
 */
request = 

Re: [Intel-gfx] [PATCH] drm/i915: Nul-terminate legacy debug string

[Chris Wilson]

Quoting Ville Syrjälä (2018-05-17 20:06:28)
> On Thu, May 17, 2018 at 04:28:24PM +0100, Chris Wilson wrote:
> > Make sure that when we don't have any scheduler attributes for the
> > request the string is terminated.
> > 
> > Fixes: 247870ac8ea7 ("drm/i915: Build request info on stack before printk")
> > Signed-off-by: Chris Wilson 
> > Cc: Joonas Lahtinen 
> 
> Reviewed-by: Ville Syrjälä 

Thanks for the review, pushed before I have to read any more garbage in
the CI logs.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200 -> Patchwork_9037 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43344/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9037 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cfl-8700k:   PASS -> FAIL (fdo#103928)


 Possible fixes 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   DMESG-WARN -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-kbl-7567u:   FAIL (fdo#103191, fdo#104724) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9037

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9037: afd1ce5db4288f5db1492a593829c91d635a5486 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

afd1ce5db428 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
5bad7132a89f drm/i915/selftests: Wait longer for the old active request

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9037/issues.html
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Re: [Intel-gfx] [drm-tip:drm-tip 711/734] drivers/gpu/drm/rcar-du/rcar_du_vsp.c:317:6: error: 'struct rcar_du_vsp_plane_state' has no member named 'alpha'

[Laurent Pinchart]

Hi Dave,

On Thursday, 17 May 2018 08:05:03 EEST Dave Airlie wrote:
> On 17 May 2018 at 14:42, Dave Airlie  wrote:
> > On 16 May 2018 at 01:37, Laurent Pinchart wrote:
> >> On Tuesday, 15 May 2018 17:24:52 EEST kbuild test robot wrote:
> >>> tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
> >>> head:   c03987223c762e4a61142f0a9be6027bb181cdfa
> >>> commit: 9037d4b98b255979c6636045794775f5a89cc623 [711/734] Merge branch
> >>> 'drm/du/next' of git://linuxtv.org/pinchartl/media into drm-next config:
> >>> arm64-defconfig (attached as .config)
> >>> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> >>> 
> >>> reproduce:
> >>> wget
> >>> 
> >>> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> >>> -O
> >>> ~/bin/make.cross chmod +x ~/bin/make.cross
> >>> 
> >>> git checkout 9037d4b98b255979c6636045794775f5a89cc623
> >>> # save the attached .config to linux build tree
> >>> make.cross ARCH=arm64
> >>> 
> >>> All errors (new ones prefixed by >>):
> >>>drivers/gpu/drm/rcar-du/rcar_du_vsp.c: In function
> >> 
> >> 'rcar_du_vsp_plane_atomic_duplicate_state':
> >>> >> drivers/gpu/drm/rcar-du/rcar_du_vsp.c:317:6: error: 'struct
> >>> >> rcar_du_vsp_plane_state' has no member named 'alpha'
> >>> >> 
> >>>  copy->alpha = to_rcar_vsp_plane_state(plane->state)->alpha;
> >>>  ^~
> >>>drivers/gpu/drm/rcar-du/rcar_du_vsp.c:317:53: error: 'struct
> >>> rcar_du_vsp_plane_state' has no member named 'alpha' copy->alpha =
> >>> to_rcar_vsp_plane_state(plane->state)->alpha;
> >> 
> >> This error is caused by a conflict between commit 75a07f399cd4 (drm:
> >> rcar-du: Zero-out sg_tables when duplicating plane state) present in my
> >> R-Car DU pull request sent for the DRM tree and commit 301a9b8d5456
> >> ("drm/rcar-du: Convert to the new generic alpha property") present in
> >> drm-misc-next but not merged in the drm tree yet.
> >> 
> >> Dave, how would you like to handle this ? I can rebase my drm/du/next
> >> branch on top of your tree once you merge drm-misc-next and send a new
> >> pull request, but I'd like to avoid missing the v4.18 merge window.
> >> Another option would be to handle the error in the drm-misc-next merge.
> >> If there's an easier option, please let me know how I can help.
> > 
> > Is this broken in my tree now? since I seem to have both of these patches
> > and my local arm build succeeds.
> > 
> > Is there a merge from somewhere else confusing things?
> 
> Turns out my arm64 builds weren't setup properly, I've fixed them up and can
> now see builds failures.
> 
> I've applied both rcar-du fixes to drm-next.

Thank you. I've verified your for-next branch and everything seems fine now.

-- 
Regards,

Laurent Pinchart



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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5bad7132a89f drm/i915/selftests: Wait longer for the old active request
afd1ce5db428 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#11: 
<7>[  239.094843] i915_gem_set_wedged   current seqno 19a98, last 19a9a, 
hangcheck 0 [5158 ms]

total: 0 errors, 1 warnings, 0 checks, 9 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/guc: Keep guc submission permanently engaged (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v2] drm/i915/guc: Keep guc submission permanently 
engaged (rev2)
URL   : https://patchwork.freedesktop.org/series/43352/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200 -> Patchwork_9036 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43352/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9036 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cnl-psr: PASS -> FAIL (fdo#100368)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)


 Possible fixes 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   DMESG-WARN -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-kbl-7567u:   FAIL (fdo#104724, fdo#103191) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9036

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9036: e6d22baddf5d3d69c62443be579acdb7acc66908 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

e6d22baddf5d HAX guc please
c2389916289a drm/i915/guc: Keep guc submission permanently engaged

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9036/issues.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Modify psr_wait_for_idle to be reused.

[Tarun Vyas]

On Mon, May 14, 2018 at 03:00:15PM -0700, Tarun Vyas wrote:
> On Mon, May 14, 2018 at 10:15:19PM +0100, Chris Wilson wrote:
> > Quoting Tarun Vyas (2018-05-14 21:49:20)
> > > intel_pipe_update_start also needs to wait for PSR to idle
> > > out. Need some minor modifications in psr_wait_for_idle in
> > > order to reuse it.
> > > 
> > > Cc: Chris Wilson 
> > > Signed-off-by: Tarun Vyas 
> > > ---
> > >  drivers/gpu/drm/i915/intel_psr.c | 29 ++---
> > >  1 file changed, 18 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index db27f2faa1de..40aafc0f4513 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -889,11 +889,15 @@ static bool psr_wait_for_idle(struct 
> > > drm_i915_private *dev_priv)
> > > i915_reg_t reg;
> > > u32 mask;
> > > int err;
> > > +   bool wait = false;
> > > +
> > > +   mutex_lock(_priv->psr.lock);
> > >  
> > > intel_dp = dev_priv->psr.enabled;
> > > if (!intel_dp)
> > > -   return false;
> > > +   goto unlock;
> > >  
> > > +   wait = true;
> > > if (HAS_DDI(dev_priv)) {
> > > if (dev_priv->psr.psr2_enabled) {
> > > reg = EDP_PSR2_STATUS;
> > > @@ -911,15 +915,18 @@ static bool psr_wait_for_idle(struct 
> > > drm_i915_private *dev_priv)
> > > mask = VLV_EDP_PSR_IN_TRANS;
> > > }
> > >  
> > > +unlock:
> > > mutex_unlock(_priv->psr.lock);
> > >  
> > > -   err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> > > -   if (err)
> > > -   DRM_ERROR("Timed out waiting for PSR Idle for 
> > > re-enable\n");
> > > +   if(wait) {
> > > +   err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> > > +   if (err) {
> > > +   DRM_ERROR("Timed out waiting for PSR Idle for 
> > > re-enable\n");
> > > +   wait = false;
> > > +   }
> > > +   }
> > >  
> > > -   /* After the unlocked wait, verify that PSR is still wanted! */
> > > -   mutex_lock(_priv->psr.lock);
> > > -   return err == 0 && dev_priv->psr.enabled;
> > > +   return wait;
> I wanted to avoid taking this additional lock b/c all we need inside 
> intel_pipe_update_start is for PSR to go idle. So can we retain moving it to 
> intel_psr_work ?
> > >  }
> > >  
> > >  static void intel_psr_work(struct work_struct *work)
> > > @@ -927,7 +934,6 @@ static void intel_psr_work(struct work_struct *work)
> > > struct drm_i915_private *dev_priv =
> > > container_of(work, typeof(*dev_priv), psr.work.work);
> > >  
> > > -   mutex_lock(_priv->psr.lock);
> > >  
> > > /*
> > >  * We have to make sure PSR is ready for re-enable
> > > @@ -936,14 +942,15 @@ static void intel_psr_work(struct work_struct *work)
> > >  * and be ready for re-enable.
> > >  */
> > > if (!psr_wait_for_idle(dev_priv))
> > > -   goto unlock;
> > > +   return;
> > >  
> > > -   /*
> > > +   /* After the unlocked wait, verify that PSR is still wanted!
> > >  * The delayed work can race with an invalidate hence we need to
> > >  * recheck. Since psr_flush first clears this and then 
> > > reschedules we
> > >  * won't ever miss a flush when bailing out here.
> > >  */
> > > -   if (dev_priv->psr.busy_frontbuffer_bits)
> > > +   mutex_lock(_priv->psr.lock);
> > > +   if (dev_priv->psr.enabled && dev_priv->psr.busy_frontbuffer_bits)
> > > goto unlock;
> > 
> > I'm not sold on the locking dropping here, doing so inside the wait is
> > bad enough. (And do we need to there anyway?)
> > 
Per the commit message in "daeb725e drm/i915/psr: Chase psr.enabled only under 
the psr.lock",
the wait_for_register is done after dropping the locks so that we don't block 
the modeset path.
> > Since you need to introduce intel_psr_wait_for_idle() anyway, how about
> > 
> > void intel_psr_wait_for_idle(...)
> > {
> > mutex_lock(>psr.lock);
> > psr_wait_for_idle();
> > mutex_unlock(>psr.lock);
On a second thought, I need to wait for PSR idle inside 
intel_pipe_update_start. Now, intel_psr_disable/intel_psr_enable will
*not race* inside intel_pipe_update_start(), so we do not need any psr.locks, 
at all.
The locking dropping inside psr_wait_for_idle makes it difficult to move the 
common wait code, so I was thinking if I can do
something like:
void intel_psr_wait_for_idle(...)
{
if (dev_priv->psr.psr2_enabled) {
reg = EDP_PSR2_STATUS;
mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
reg = EDP_PSR_STATUS;
mask = EDP_PSR_STATUS_STATE_MASK;
}

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2] drm/i915/guc: Keep guc submission permanently engaged (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v2] drm/i915/guc: Keep guc submission permanently 
engaged (rev2)
URL   : https://patchwork.freedesktop.org/series/43352/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c2389916289a drm/i915/guc: Keep guc submission permanently engaged
e6d22baddf5d HAX guc please
-:19: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 8 lines checked

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4198_full -> Patchwork_9033_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9033_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9033_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43344/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9033_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS +1


== Known issues ==

  Here are the changes found in Patchwork_9033_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_create@basic:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602)

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_cursor_crc@cursor-128x128-suspend:
  shard-kbl:  PASS -> FAIL (fdo#103232, fdo#103191, fdo#104724)

igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
  shard-hsw:  PASS -> FAIL (fdo#104873)

igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
  shard-hsw:  PASS -> FAIL (fdo#102670)

igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
  shard-hsw:  PASS -> FAIL (fdo#103928)

igt@kms_flip@dpms-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060)

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363, fdo#102887)

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +1

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822)

igt@kms_flip_tiling@flip-to-y-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724) +1

igt@kms_rotation_crc@sprite-rotation-90:
  shard-apl:  PASS -> FAIL (fdo#104724, fdo#103925)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-apl:  DMESG-FAIL -> PASS

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
  shard-glk:  FAIL (fdo#105703) -> PASS

igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
  shard-hsw:  FAIL (fdo#103060) -> PASS

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  FAIL (fdo#103167, fdo#104724) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4198 -> Patchwork_9033

  CI_DRM_4198: 9f0af9e6938d975b744e3533410bf6398f3ce2d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9033: 272940a885c0c7bfe68e7be018bc5a3a18d806d6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 

[Intel-gfx] [PATCH v2] drm/i915/guc: Keep guc submission permanently engaged

[Chris Wilson]

We make a decision at module load whether to use the GuC backend or not,
but lose that setup across set-wedge. Currently, the guc doesn't
override the engine->set_default_submission hook letting execlists sneak
back in temporarily on unwedging leading to an unbalanced park/unpark.

v2: Remove comment about switching back temporarily to execlists on
guc_submission_disable(). We currently only call disable on shutdown,
and plan to also call disable before suspend and reset, in which case we
will either restore guc submission or mark the driver as wedged, making
the reset back to execlists pointless.

Testcase: igt/gem_eio
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 37 ++---
 drivers/gpu/drm/i915/intel_lrc.c|  2 +-
 drivers/gpu/drm/i915/intel_lrc.h|  2 ++
 3 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 637e852888ec..fdd4cfcc0e8e 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1264,6 +1264,29 @@ static void guc_submission_unpark(struct intel_engine_cs 
*engine)
intel_engine_pin_breadcrumbs_irq(engine);
 }
 
+static void guc_set_default_submission(struct intel_engine_cs *engine)
+{
+   /*
+* We inherit a bunch of functions from execlists that we'd like
+* to keep using:
+*
+*engine->submit_request = execlists_submit_request;
+*engine->cancel_requests = execlists_cancel_requests;
+*engine->schedule = execlists_schedule;
+*
+* But we need to override the actual submission backend in order
+* to talk to the GuC.
+*/
+   execlists_set_default_submission(engine);
+
+   engine->execlists.tasklet.func = guc_submission_tasklet;
+
+   engine->park = guc_submission_park;
+   engine->unpark = guc_submission_unpark;
+
+   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+}
+
 int intel_guc_submission_enable(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1302,17 +1325,10 @@ int intel_guc_submission_enable(struct intel_guc *guc)
guc_interrupts_capture(dev_priv);
 
for_each_engine(engine, dev_priv, id) {
-   struct intel_engine_execlists * const execlists =
-   >execlists;
-
-   execlists->tasklet.func = guc_submission_tasklet;
-
engine->reset.prepare = guc_reset_prepare;
+   engine->set_default_submission = guc_set_default_submission;
 
-   engine->park = guc_submission_park;
-   engine->unpark = guc_submission_unpark;
-
-   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+   engine->set_default_submission(engine);
}
 
return 0;
@@ -1326,9 +1342,6 @@ void intel_guc_submission_disable(struct intel_guc *guc)
 
guc_interrupts_release(dev_priv);
guc_clients_doorbell_fini(guc);
-
-   /* Revert back to manual ELSP submission */
-   intel_engines_reset_default_submission(dev_priv);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d6e698d3f858..758126b5a448 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2289,7 +2289,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs 
*engine)
kfree(engine);
 }
 
-static void execlists_set_default_submission(struct intel_engine_cs *engine)
+void execlists_set_default_submission(struct intel_engine_cs *engine)
 {
engine->submit_request = execlists_submit_request;
engine->cancel_requests = execlists_cancel_requests;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 4ec7d8dd13c8..e64f47e612f4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -111,4 +111,6 @@ intel_lr_context_descriptor(struct i915_gem_context *ctx,
return to_intel_context(ctx, engine)->lrc_desc;
 }
 
+void execlists_set_default_submission(struct intel_engine_cs *engine);
+
 #endif /* _INTEL_LRC_H_ */
-- 
2.17.0

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Re: [Intel-gfx] [PATCH v2 5/5] media: platform: Add Chrome OS EC CEC driver

[kbuild test robot]

Hi Neil,

I love your patch! Yet something to improve:

[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.17-rc5 next-20180517]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Neil-Armstrong/Add-ChromeOS-EC-CEC-Support/20180516-180519
base:   git://linuxtv.org/media_tree.git master
config: m68k-allmodconfig (attached as .config)
compiler: m68k-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=m68k 

All errors (new ones prefixed by >>):

   drivers/media//platform/cros-ec-cec/cros-ec-cec.c: In function 
'cros_ec_cec_get_notifier':
>> drivers/media//platform/cros-ec-cec/cros-ec-cec.c:231:33: error: 
>> 'pci_bus_type' undeclared (first use in this function); did you mean 
>> 'pci_pcie_type'?
   d = bus_find_device_by_name(_bus_type, NULL,
^~~~
pci_pcie_type
   drivers/media//platform/cros-ec-cec/cros-ec-cec.c:231:33: note: each 
undeclared identifier is reported only once for each function it appears in

vim +231 drivers/media//platform/cros-ec-cec/cros-ec-cec.c

   217  
   218  static int cros_ec_cec_get_notifier(struct device *dev,
   219  struct cec_notifier **notify)
   220  {
   221  int i;
   222  
   223  for (i = 0 ; i < ARRAY_SIZE(cec_dmi_match_table) ; ++i) {
   224  const struct cec_dmi_match *m = _dmi_match_table[i];
   225  
   226  if (dmi_match(DMI_SYS_VENDOR, m->sys_vendor) &&
   227  dmi_match(DMI_PRODUCT_NAME, m->product_name)) {
   228  struct device *d;
   229  
   230  /* Find the device, bail out if not yet 
registered */
 > 231  d = bus_find_device_by_name(_bus_type, NULL,
   232  m->devname);
   233  if (!d)
   234  return -EPROBE_DEFER;
   235  
   236  *notify = cec_notifier_get_conn(d, m->conn);
   237  return 0;
   238  }
   239  }
   240  
   241  /* Hardware support must be added in the cec_dmi_match_table */
   242  dev_warn(dev, "CEC notifier not configured for this 
hardware\n");
   243  
   244  return -ENODEV;
   245  }
   246  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Keep guc submission permanently engaged

[Chris Wilson]

Quoting Michal Wajdeczko (2018-05-17 18:23:23)
> On Thu, 17 May 2018 18:56:41 +0200, Chris Wilson  
>  wrote:
> 
> > We make a decision at module load whether to use the GuC backend or not,
> > but lose that setup across set-wedge. Currently, the guc doesn't
> > override the engine->set_default_submission hook letting execlists sneak
> > back in temporarily on unwedging leading to an unbalanced park/unpark.
> >
> > Testcase: igt/gem_eio
> > Signed-off-by: Chris Wilson 
> > Cc: Michał Winiarski 
> > Cc: Michal Wajdeczko 
> > ---
> >  drivers/gpu/drm/i915/intel_guc_submission.c | 34 +++--
> >  drivers/gpu/drm/i915/intel_lrc.c|  2 +-
> >  drivers/gpu/drm/i915/intel_lrc.h|  2 ++
> >  3 files changed, 28 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c  
> > b/drivers/gpu/drm/i915/intel_guc_submission.c
> > index 637e852888ec..cbd8caffd271 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> > @@ -1264,6 +1264,29 @@ static void guc_submission_unpark(struct  
> > intel_engine_cs *engine)
> >   intel_engine_pin_breadcrumbs_irq(engine);
> >  }
> > +static void guc_set_default_submission(struct intel_engine_cs *engine)
> > +{
> > + /*
> > +  * We inherit a bunch of functions from execlists that we'd like
> > +  * to keep using:
> > +  *
> > +  *engine->submit_request = execlists_submit_request;
> > +  *engine->cancel_requests = execlists_cancel_requests;
> > +  *engine->schedule = execlists_schedule;
> > +  *
> > +  * But we need to override the actual submission backend in order
> > +  * to talk to the GuC.
> > +  */
> > + execlists_set_default_submission(engine);
> > +
> > + engine->execlists.tasklet.func = guc_submission_tasklet;
> > +
> > + engine->park = guc_submission_park;
> > + engine->unpark = guc_submission_unpark;
> > +
> > + engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
> > +}
> > +
> >  int intel_guc_submission_enable(struct intel_guc *guc)
> >  {
> >   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > @@ -1302,17 +1325,10 @@ int intel_guc_submission_enable(struct intel_guc  
> > *guc)
> >   guc_interrupts_capture(dev_priv);
> >   for_each_engine(engine, dev_priv, id) {
> > - struct intel_engine_execlists * const execlists =
> > - >execlists;
> > -
> > - execlists->tasklet.func = guc_submission_tasklet;
> > -
> >   engine->reset.prepare = guc_reset_prepare;
> > + engine->set_default_submission = guc_set_default_submission;
> > - engine->park = guc_submission_park;
> > - engine->unpark = guc_submission_unpark;
> > -
> > - engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
> > + engine->set_default_submission(engine);
> 
> While this part looks ok (and maybe will help with my [1])
> but what about intel_guc_submission_disable(), where we
> will call intel_engines_reset_default_submission() and
> 'revert' to GuC again... time for nop_submission() ?

If we apply the "once you go GuC, you won't go back" rule, then we might
as well just call i915_gem_set_wedged() (or leave it wedged) on disabling.
So long as any re-enable path goes through a i915_reset, we will be
fine.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode

[Manasi Navare]

On Thu, May 17, 2018 at 10:28:02AM +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, Manasi Navare  wrote:
> > This patch fixes the original commit c0cfb10d9e1de49 ("drm/i915/edp:
> > Do not do link training fallback or prune modes on EDP") that causes
> > a blank screen in case of certain eDP panels (Eg: seen on Dell XPS13 9350)
> > where first link training fails and a retraining is required by falling
> > back to lower link rate/lane count.
> > In case of some panels they advertise higher link rate/lane count
> > than whats required for supporting the panel's native mode.
> > But we always link train at highest link rate/lane count for eDP
> > and if that fails we can still fallback to lower link rate/lane count
> > as long as the fallback link BW still fits the native mode to avoid
> > pruning the panel's native mode yet retraining at fallback values
> > to recover from a blank screen.
> 
> What eDP revision is the faulty panel? Does [1] help for that? Then we'd
> not need this.
>

This is a eDP 1.3 panel and so it wont pick the fast and narrow approach
in [1]. So our assumption that eDP 1.3 and earlier panels support only a single
clock and lane configuration that correspond to the native resolution of
the panel doesnt hold good here.
 
> I think this also ties in with the alternate/downclock mode. It fails
> now and should be reverted [2]. However, if we know the panel has a
> valid mode with lower refresh rate, we might have a mode that actually
> fits a link with reduced bandwidth.
> 
> IMO we need [1], [2], and patches to disconnect downclock mode from drrs
> support (so we/user can choose the downclock mode independent of drrs),
> and finally eDP link fallback selection based on if there's a downclock
> mode and if it fits a link with reduced link rate or lane count.
>

Yes so the intel_find_panel_downclock() needs to be called independently
from intel_dp_drrs_init() right?
After that is done then my function in this patch can also check if the
reduced fallback BW can support downclock mode and if so then allow
link train fallback for eDP.
Does this sound like a correct approach?

Manasi
 
> BR,
> Jani.
>

 
> 
> [1] 
> http://patchwork.freedesktop.org/patch/msgid/20180509071321.28563-1-jani.nik...@intel.com
> [2] 
> http://patchwork.freedesktop.org/patch/msgid/20180516080110.22770-1-jani.nik...@intel.com
> 
> 
> 
> >
> > Cc: Clinton Taylor 
> > Cc: Jani Nikula 
> > Cc: Ville Syrjala 
> > Cc: Daniel Vetter 
> > Cc: Lucas De Marchi 
> > Signed-off-by: Manasi Navare 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   | 25 
> > +
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 26 
> > +-
> >  2 files changed, 34 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 2cc58596..7f7202a 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -387,6 +387,21 @@ static bool intel_dp_link_params_valid(struct intel_dp 
> > *intel_dp, int link_rate,
> > return true;
> >  }
> >  
> > +static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp 
> > *intel_dp,
> > +int link_rate,
> > +uint8_t lane_count)
> > +{
> > +   struct drm_display_mode *fixed_mode = 
> > intel_dp->attached_connector->panel.fixed_mode;
> > +   int mode_rate, max_rate;
> > +
> > +   mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
> > +   max_rate = intel_dp_max_data_rate(link_rate, lane_count);
> > +   if (mode_rate > max_rate)
> > +   return false;
> > +
> > +   return true;
> > +}
> > +
> >  int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> > int link_rate, uint8_t lane_count)
> >  {
> > @@ -396,9 +411,19 @@ int intel_dp_get_link_train_fallback_values(struct 
> > intel_dp *intel_dp,
> > intel_dp->num_common_rates,
> > link_rate);
> > if (index > 0) {
> > +   if (intel_dp_is_edp(intel_dp) &&
> > +   !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> > +
> > intel_dp->common_rates[index-1],
> > + lane_count))
> > +   return -1;
> > intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
> > intel_dp->max_link_lane_count = lane_count;
> > } else if (lane_count > 1) {
> > +   if (intel_dp_is_edp(intel_dp) &&
> > +   !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> > +  

Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 11:02 +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, Dhinakaran Pandiyan  om> wrote:
> > 
> > On Wed, 2018-05-16 at 11:08 +0300, Jani Nikula wrote:
> > > 
> > > I think the patch is now the way it should be. We should not
> > > change
> > > our interpretation based on the value.
> > Is it correct to infer, from your response, that VBT values are not
> > always set based on hardware capability as documented in bspec?
> Correct. I think it was the good intention of the VBT change to only
> allow values that map to valid hardware values, but I think it has
> caused much more trouble than it has helped.
> 
> First, the change was not universally tied to a VBT version, and I've
> seen VBTs in the wild with version >= 209 that still use multiples of
> 100 us. (And the spec is still in contradiction with itself.)
> 
> Second, regardless of mapping or multiples of 100 us we need to
> verify
> our input. Because I've seen VBTs in the wild that are bogus
> regardless
> of how they're supposed to be interpreted.
> 
> Third, we already had the code in place to map multiples of 100 us to
> hardware. We'll need to keep that practically forever. And now we
> need
> to have *another* mapping.
> 
> Fourth, the multiples of 100 us does not require *any* spec change
> when
> hardware changes to support different values. The new mapping
> requires
> changes throughout the stack that looks at the values. (Basically I
> object to any VBT specification that says anything platform
> dependent. It should be generic.)
> 
> Now, the patch at hand uses the best guesses we can make to translate
> whatever the VBT has to microseconds, in intel_bios.c. That part does
> not care about hardware capability. For validity, it only looks at
> what
> we think is according to VBT spec. It should be hardware agnostic,
> except for the IS_GEN9_BC() thing, which should probably include
> gen10+
> too.
> 
> The code in intel_psr.c gets the microseconds as input, and maps that
> to
> hardware capability as best we can, erring towards longer delays.
> 
> Two different abstractions for two different things. One to abstract
> VBT, another to abstract hardware. This is in line with the direction
> I've tried to take intel_bios.c and VBT parsing and the VBT spec (the
> little I've had influence for that) for the longest time. We must not
> let the VBT abstractions to leak into the driver code.

Thanks for the detailed explanation of the problem and the idea behind
the design.

-DK


> 
> BR,
> Jani.
> 
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Re: [Intel-gfx] [PATCH] Revert "drm/i915/edp: Allow alternate fixed mode for eDP if available."

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 10:33 +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Jani Nikula  wrote:
> > 
> > On Wed, 16 May 2018, Dhinakaran Pandiyan  > .com> wrote:
> > > 
> > > On Wed, 2018-05-16 at 11:01 +0300, Jani Nikula wrote:
> > > > 
> > > > This reverts commit dc911f5bd8aacfcf8aabd5c26c88e04c837a938e.
> > > > 
> > > > Per the report, no matter what display mode you select with
> > > > xrandr,
> > > > the
> > > > i915 driver will always select the alternate fixed mode. For
> > > > the
> > > > reporter this means that the display will always run at 40Hz
> > > > which is
> > > > quite annoying. This may be due to the mode comparison.
> > > > 
> > > > But there are some other potential issues. The choice of
> > > > alt_fixed_mode
> > > > seems dubious. It's the first non-preferred mode, but there are
> > > > no
> > > > guarantees that the only difference would be refresh rate.
> > > > Similarly,
> > > > there may be more than one preferred mode in the probed modes
> > > > list,
> > > > and
> > > > the commit changes the preferred mode selection to choose the
> > > > last
> > > > one
> > > > on the list instead of the first.
> > > > 
> > > > (Note that the probed modes list is the raw, unfiltered,
> > > > unsorted
> > > > list
> > > > of modes from drm_add_edid_modes(), not the pretty result after
> > > > a
> > > > drm_helper_probe_single_connector_modes() call.)
> > > > 
> > > > Finally, we already have eerily similar code in place to find
> > > > the
> > > > downclock mode for DRRS that seems like could be reused here.
> > > > 
> > > > Back to the drawing board.
> > > > 
> > > > Note: This is a hand-crafted revert due to conflicts. If it
> > > > fails to
> > > > backport, please just try reverting the original commit
> > > > directly.
> > > > 
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105469
> > > > Reported-by: Rune Petersen 
> > > > Reported-by: Mark Spencer 
> > > > Fixes: dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode
> > > > for
> > > > eDP if available.")
> > > > Cc: Clint Taylor 
> > > > Cc: David Weinehall 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Paulo Zanoni 
> > > > Cc: Jani Nikula 
> > > > Cc: Chris Wilson 
> > > > Cc: Jim Bride 
> > > > Cc: Jani Nikula 
> > > > Cc: Joonas Lahtinen 
> > > > Cc: intel-gfx@lists.freedesktop.org
> > > > Cc:  # v4.14+
> > > > Signed-off-by: Jani Nikula 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c| 38 +-
> > > > --
> > > > --
> > > >  drivers/gpu/drm/i915/intel_drv.h   |  2 --
> > > >  drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
> > > >  drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
> > > >  drivers/gpu/drm/i915/intel_lvds.c  |  3 +--
> > > >  drivers/gpu/drm/i915/intel_panel.c |  6 --
> > > >  6 files changed, 8 insertions(+), 45 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index dde92e4af5d3..8320f0e8e3be 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -1679,23 +1679,6 @@ static int intel_dp_compute_bpp(struct
> > > > intel_dp *intel_dp,
> > > >     return bpp;
> > > >  }
> > > >  
> > > > -static bool intel_edp_compare_alt_mode(struct drm_display_mode
> > > > *m1,
> > > > -      struct drm_display_mode
> > > > *m2)
> > > > -{
> > > > -   bool bres = false;
> > > > -
> > > > -   if (m1 && m2)
> > > > -   bres = (m1->hdisplay == m2->hdisplay &&
> > > > -   m1->hsync_start == m2->hsync_start &&
> > > > -   m1->hsync_end == m2->hsync_end &&
> > > > -   m1->htotal == m2->htotal &&
> > > > -   m1->vdisplay == m2->vdisplay &&
> > > > -   m1->vsync_start == m2->vsync_start &&
> > > > -   m1->vsync_end == m2->vsync_end &&
> > > > -   m1->vtotal == m2->vtotal);
> > > > -   return bres;
> > > > -}
> > > > -
> > > >  /* Adjust link config limits based on compliance test
> > > > requests. */
> > > >  static void
> > > >  intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
> > > > @@ -1860,16 +1843,8 @@ intel_dp_compute_config(struct
> > > > intel_encoder
> > > > *encoder,
> > > >     pipe_config->has_audio = intel_conn_state-
> > > > > 
> > > > > force_audio == HDMI_AUDIO_ON;
> > > >  
> > > >     if (intel_dp_is_edp(intel_dp) && intel_connector-
> > > > > 
> > > > > panel.fixed_mode) {
> > > > -   struct drm_display_mode *panel_mode =
> > > 

Re: [Intel-gfx] [PATCH] Revert "drm/i915/edp: Allow alternate fixed mode for eDP if available."

[Dhinakaran Pandiyan]

On Thu, 2018-05-17 at 10:33 +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Jani Nikula  wrote:
> > 
> > On Wed, 16 May 2018, Dhinakaran Pandiyan  > .com> wrote:
> > > 
> > > On Wed, 2018-05-16 at 11:01 +0300, Jani Nikula wrote:
> > > > 
> > > > This reverts commit dc911f5bd8aacfcf8aabd5c26c88e04c837a938e.
> > > > 
> > > > Per the report, no matter what display mode you select with
> > > > xrandr,
> > > > the
> > > > i915 driver will always select the alternate fixed mode. For
> > > > the
> > > > reporter this means that the display will always run at 40Hz
> > > > which is
> > > > quite annoying. This may be due to the mode comparison.
> > > > 
> > > > But there are some other potential issues. The choice of
> > > > alt_fixed_mode
> > > > seems dubious. It's the first non-preferred mode, but there are
> > > > no
> > > > guarantees that the only difference would be refresh rate.
> > > > Similarly,
> > > > there may be more than one preferred mode in the probed modes
> > > > list,
> > > > and
> > > > the commit changes the preferred mode selection to choose the
> > > > last
> > > > one
> > > > on the list instead of the first.
> > > > 
> > > > (Note that the probed modes list is the raw, unfiltered,
> > > > unsorted
> > > > list
> > > > of modes from drm_add_edid_modes(), not the pretty result after
> > > > a
> > > > drm_helper_probe_single_connector_modes() call.)
> > > > 
> > > > Finally, we already have eerily similar code in place to find
> > > > the
> > > > downclock mode for DRRS that seems like could be reused here.
> > > > 
> > > > Back to the drawing board.
> > > > 
> > > > Note: This is a hand-crafted revert due to conflicts. If it
> > > > fails to
> > > > backport, please just try reverting the original commit
> > > > directly.
> > > > 
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105469
> > > > Reported-by: Rune Petersen 
> > > > Reported-by: Mark Spencer 
> > > > Fixes: dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode
> > > > for
> > > > eDP if available.")
> > > > Cc: Clint Taylor 
> > > > Cc: David Weinehall 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Paulo Zanoni 
> > > > Cc: Jani Nikula 
> > > > Cc: Chris Wilson 
> > > > Cc: Jim Bride 
> > > > Cc: Jani Nikula 
> > > > Cc: Joonas Lahtinen 
> > > > Cc: intel-gfx@lists.freedesktop.org
> > > > Cc:  # v4.14+
> > > > Signed-off-by: Jani Nikula 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c| 38 +-
> > > > --
> > > > --
> > > >  drivers/gpu/drm/i915/intel_drv.h   |  2 --
> > > >  drivers/gpu/drm/i915/intel_dsi.c   |  2 +-
> > > >  drivers/gpu/drm/i915/intel_dvo.c   |  2 +-
> > > >  drivers/gpu/drm/i915/intel_lvds.c  |  3 +--
> > > >  drivers/gpu/drm/i915/intel_panel.c |  6 --
> > > >  6 files changed, 8 insertions(+), 45 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index dde92e4af5d3..8320f0e8e3be 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -1679,23 +1679,6 @@ static int intel_dp_compute_bpp(struct
> > > > intel_dp *intel_dp,
> > > >     return bpp;
> > > >  }
> > > >  
> > > > -static bool intel_edp_compare_alt_mode(struct drm_display_mode
> > > > *m1,
> > > > -      struct drm_display_mode
> > > > *m2)
> > > > -{
> > > > -   bool bres = false;
> > > > -
> > > > -   if (m1 && m2)
> > > > -   bres = (m1->hdisplay == m2->hdisplay &&
> > > > -   m1->hsync_start == m2->hsync_start &&
> > > > -   m1->hsync_end == m2->hsync_end &&
> > > > -   m1->htotal == m2->htotal &&
> > > > -   m1->vdisplay == m2->vdisplay &&
> > > > -   m1->vsync_start == m2->vsync_start &&
> > > > -   m1->vsync_end == m2->vsync_end &&
> > > > -   m1->vtotal == m2->vtotal);
> > > > -   return bres;
> > > > -}
> > > > -
> > > >  /* Adjust link config limits based on compliance test
> > > > requests. */
> > > >  static void
> > > >  intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
> > > > @@ -1860,16 +1843,8 @@ intel_dp_compute_config(struct
> > > > intel_encoder
> > > > *encoder,
> > > >     pipe_config->has_audio = intel_conn_state-
> > > > > 
> > > > > force_audio == HDMI_AUDIO_ON;
> > > >  
> > > >     if (intel_dp_is_edp(intel_dp) && intel_connector-
> > > > > 
> > > > > panel.fixed_mode) {
> > > > -   struct drm_display_mode *panel_mode =
> > > 

Re: [Intel-gfx] [PATCH] drm/i915: Nul-terminate legacy debug string

[Ville Syrjälä]

On Thu, May 17, 2018 at 04:28:24PM +0100, Chris Wilson wrote:
> Make sure that when we don't have any scheduler attributes for the
> request the string is terminated.
> 
> Fixes: 247870ac8ea7 ("drm/i915: Build request info on stack before printk")
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d4e159ae65a6..e78c6e769e8c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1143,7 +1143,7 @@ static void print_request(struct drm_printer *m,
> const char *prefix)
>  {
>   const char *name = rq->fence.ops->get_timeline_name(>fence);
> - char buf[80];
> + char buf[80] = "";
>   int x = 0;
>  
>   x = print_sched_attr(rq->i915, >sched.attr, buf, x, sizeof(buf));
> -- 
> 2.17.0
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Nul-terminate legacy debug string

[Patchwork]

== Series Details ==

Series: drm/i915: Nul-terminate legacy debug string
URL   : https://patchwork.freedesktop.org/series/43341/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4197_full -> Patchwork_9031_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9031_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9031_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43341/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9031_full:

  === IGT changes ===

 Warnings 

igt@drm_read@short-buffer-block:
  shard-snb:  PASS -> SKIP

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9031_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
  shard-hsw:  PASS -> FAIL (fdo#104873)

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-glk:  PASS -> FAIL (fdo#100368)

igt@kms_flip@flip-vs-modeset-vs-hang-interruptible:
  shard-kbl:  PASS -> DMESG-FAIL (fdo#103313)

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103822) +1

igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103313, 
fdo#103558) +2

igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558) +25

igt@kms_frontbuffer_tracking@fbc-suspend:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558, 
fdo#103841)

igt@perf@blocking:
  shard-hsw:  PASS -> FAIL (fdo#102252)


 Possible fixes 

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9031

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9031: cf9bb1a98ae0198ad7e8e947f3e7acd2502597ec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9031/shards.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove unused enable_cmd_parser modparam

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unused enable_cmd_parser modparam
URL   : https://patchwork.freedesktop.org/series/43340/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4197_full -> Patchwork_9030_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9030_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9030_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43340/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9030_full:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@live_hangcheck:
  shard-glk:  PASS -> DMESG-FAIL


 Warnings 

igt@gem_exec_schedule@deep-vebox:
  shard-kbl:  SKIP -> PASS

igt@kms_vblank@pipe-a-wait-busy:
  shard-snb:  PASS -> SKIP

igt@perf_pmu@rc6:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9030_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@flip-vs-cursor-legacy:
  shard-hsw:  PASS -> FAIL (fdo#102670)

igt@kms_flip_tiling@flip-to-x-tiled:
  shard-glk:  PASS -> FAIL (fdo#103822, fdo#104724) +1

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
  shard-hsw:  PASS -> FAIL (fdo#103481)


 Possible fixes 

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9030

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9030: 913921ed0c35df218a49b797c1bcfe0fb67da883 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9030/shards.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for 
HSW/BDW too
URL   : https://patchwork.freedesktop.org/series/43353/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200 -> Patchwork_9035 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43353/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9035 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-kbl-7567u:   FAIL (fdo#104724, fdo#103191) -> PASS


 Warnings 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   DMESG-WARN -> DMESG-FAIL (fdo#102614, fdo#106103)


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9035

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9035: 2749433724c67bb7a20f7bbecb4f237b4d054e35 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

2749433724c6 drm/i915: Rename the remaining gen4 references to g4x in the DP 
code
1cf1eb527fc3 drm/i915: Rename SNB/IVB CPU eDP signal level funcs
2d6c51e9fad4 drm/i915: Check for IVB instead of gen7 when we think about IVB 
CPU eDP
32fe5444b6b8 drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as 
on SKL+
c71dc14d0f43 drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9035/issues.html
___
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Re: [Intel-gfx] [PATCH i-g-t 2/3] igt/gem_blits: Check for blitter support before use

[Antonio Argenziano]

On 17/05/18 01:23, Chris Wilson wrote:

Not all HW supports XY blitter commands, so check before use.

Signed-off-by: Chris Wilson 
---
  lib/i915/gem_submission.c | 16 
  lib/i915/gem_submission.h |  3 +++
  tests/gem_linear_blits.c  |  1 +
  tests/gem_tiled_blits.c   |  1 +
  tests/gem_tiled_fence_blits.c |  1 +
  5 files changed, 22 insertions(+)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index 2fd460d5e..1d1adcf6f 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -229,3 +229,19 @@ void gem_test_engine(int i915, unsigned int engine)
igt_assert(!is_wedged(i915));
close(i915);
  }
+
+bool gem_has_blitter(int i915)
+{
+   unsigned int blt;
+
+   blt = 0;
+   if (intel_gen(intel_get_drm_devid(i915)) >= 6)


Looks like we have a "HAS_BLT_RING" macro we use in other places. Also, 
we have a gem_has_blt() function which is slightly different. Which is 
making things quite confusing for me... I wish I had a better name but I 
think we should add at least a comment to differentiate the two.


With that:
Reviewed-by: Antonio Argenziano 

Thanks,
Antonio


+   blt = I915_EXEC_BLT; > +
+   return gem_has_ring(i915, blt);
+}
+
+void gem_require_blitter(int i915)
+{
+   igt_require(gem_has_blitter(i915));
+}
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index f94eabb20..f2b18d9dc 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -33,6 +33,9 @@ bool gem_has_semaphores(int fd);
  bool gem_has_execlists(int fd);
  bool gem_has_guc_submission(int fd);
  
+bool gem_has_blitter(int i915);

+void gem_require_blitter(int i915);
+
  void gem_test_engine(int fd, unsigned int engine);
  
  int gem_reopen_driver(int fd);

diff --git a/tests/gem_linear_blits.c b/tests/gem_linear_blits.c
index 8297416c0..7d05fa865 100644
--- a/tests/gem_linear_blits.c
+++ b/tests/gem_linear_blits.c
@@ -226,6 +226,7 @@ int main(int argc, char **argv)
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+   gem_require_blitter(fd);
}
  
  	igt_subtest("basic")

diff --git a/tests/gem_tiled_blits.c b/tests/gem_tiled_blits.c
index a81226a15..0d472e3a1 100644
--- a/tests/gem_tiled_blits.c
+++ b/tests/gem_tiled_blits.c
@@ -203,6 +203,7 @@ int main(int argc, char **argv)
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+   gem_require_blitter(fd);
  
  		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);

drm_intel_bufmgr_gem_enable_reuse(bufmgr);
diff --git a/tests/gem_tiled_fence_blits.c b/tests/gem_tiled_fence_blits.c
index 693e96cec..9ab58b5d6 100644
--- a/tests/gem_tiled_fence_blits.c
+++ b/tests/gem_tiled_fence_blits.c
@@ -176,6 +176,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+   gem_require_blitter(fd);
}
  
  	igt_subtest("basic") {



___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Keep guc submission permanently engaged

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Keep guc submission 
permanently engaged
URL   : https://patchwork.freedesktop.org/series/43352/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200 -> Patchwork_9034 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43352/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9034 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-no-display:
  fi-elk-e7500:   PASS -> INCOMPLETE (fdo#103989)


 Possible fixes 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   DMESG-WARN -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-kbl-7567u:   FAIL (fdo#104724, fdo#103191) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4200 -> Patchwork_9034

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9034: 94d5d62f10afa7758aa93e7568b5d85e6489861d @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

94d5d62f10af HAX guc please
92f7337107d8 drm/i915/guc: Keep guc submission permanently engaged

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9034/issues.html
___
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Re: [Intel-gfx] [PATCH] drm/dp: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Jani Nikula]

On Thu, 17 May 2018, "Atwood, Matthew S"  wrote:
> On Thu, 2018-05-17 at 12:50 +0300, Jani Nikula wrote:
>> On Wed, 16 May 2018, Dhinakaran Pandiyan > om> wrote:
>> > Why overwrite all values if this is an expensive operation? From
>> > what I
>> > can see, you'll need to read only h - 5h
> was mostly future proofing, we can get away with only reading 6 values.
> the expense is to read 1, any number after that doesnt cost alot. That
> being said sure thing.

With the dpcd read, memcmp, memcpy, and debug logging written based on
sizeof(dpcd_ext), it'll be trivial to just adjust the size of the local
array if needed.

>> Surely this is not XXX 1.2? ;)
> I found it in a dp1.2 spec that Rodrigo had, I had originally found it
> as a change with dp1.3. Earlier versions of the patch that added
> DP_TRAINING_AUX_RD_MASK has had dp1.3 until he showed me that. If you'd
> like Ill change it.

I'm not looking it up now, but please just update the XXX as best you
can.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Ville Syrjälä]

On Thu, May 17, 2018 at 08:48:49PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > To make the intent more clear, let's rename the signal level funcs for
> > the SNB/IVB CPU eDP.
> >
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 12 ++--
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 263e4b1d1db9..cd4c60bfc4c2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
> > return signal_levels;
> >  }
> >  
> > -/* Gen6's DP voltage swing and pre-emphasis control */
> > +/* SNB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen6_edp_signal_levels(uint8_t train_set)
> > +snb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> > int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
> > }
> >  }
> >  
> > -/* Gen7's DP voltage swing and pre-emphasis control */
> > +/* IVB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen7_edp_signal_levels(uint8_t train_set)
> > +ivb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> > int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp 
> > *intel_dp)
> > } else if (IS_VALLEYVIEW(dev_priv)) {
> > signal_levels = vlv_signal_levels(intel_dp);
> > } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> > -   signal_levels = gen7_edp_signal_levels(train_set);
> > +   signal_levels = ivb_cpu_edp_signal_levels(train_set);
> > mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> > } else if (IS_GEN6(dev_priv) && port == PORT_A) {
> 
> Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

I have considered adding IS_ILK and IS_SNB to make some of
the display code more consistent looking. But I never bothered
to actually write the patch.

> 
> Anyway,
> 
> Reviewed-by: Jani Nikula 
> 
> 
> > -   signal_levels = gen6_edp_signal_levels(train_set);
> > +   signal_levels = snb_cpu_edp_signal_levels(train_set);
> > mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> > } else {
> > signal_levels = gen4_signal_levels(train_set);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> i965 does not have native DP. Let's rename the remaining gen4 references
> in the DP code to g4x.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cd4c60bfc4c2..102070940095 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -56,7 +56,7 @@ struct dp_link_dpll {
>   struct dpll dpll;
>  };
>  
> -static const struct dp_link_dpll gen4_dpll[] = {
> +static const struct dp_link_dpll g4x_dpll[] = {
>   { 162000,
>   { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
>   { 27,
> @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   int i, count = 0;
>  
>   if (IS_G4X(dev_priv)) {
> - divisor = gen4_dpll;
> - count = ARRAY_SIZE(gen4_dpll);
> + divisor = g4x_dpll;
> + count = ARRAY_SIZE(g4x_dpll);
>   } else if (HAS_PCH_SPLIT(dev_priv)) {
>   divisor = pch_dpll;
>   count = ARRAY_SIZE(pch_dpll);
> @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp 
> *intel_dp)
>  }
>  
>  static uint32_t
> -gen4_signal_levels(uint8_t train_set)
> +g4x_signal_levels(uint8_t train_set)
>  {
>   uint32_tsignal_levels = 0;
>  
> @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>   signal_levels = snb_cpu_edp_signal_levels(train_set);
>   mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>   } else {
> - signal_levels = gen4_signal_levels(train_set);
> + signal_levels = g4x_signal_levels(train_set);
>   mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
>   }

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> To make the intent more clear, let's rename the signal level funcs for
> the SNB/IVB CPU eDP.
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 263e4b1d1db9..cd4c60bfc4c2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
>   return signal_levels;
>  }
>  
> -/* Gen6's DP voltage swing and pre-emphasis control */
> +/* SNB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen6_edp_signal_levels(uint8_t train_set)
> +snb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>   int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
>   }
>  }
>  
> -/* Gen7's DP voltage swing and pre-emphasis control */
> +/* IVB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen7_edp_signal_levels(uint8_t train_set)
> +ivb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>   int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>   } else if (IS_VALLEYVIEW(dev_priv)) {
>   signal_levels = vlv_signal_levels(intel_dp);
>   } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> - signal_levels = gen7_edp_signal_levels(train_set);
> + signal_levels = ivb_cpu_edp_signal_levels(train_set);
>   mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
>   } else if (IS_GEN6(dev_priv) && port == PORT_A) {

Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

Anyway,

Reviewed-by: Jani Nikula 


> - signal_levels = gen6_edp_signal_levels(train_set);
> + signal_levels = snb_cpu_edp_signal_levels(train_set);
>   mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>   } else {
>   signal_levels = gen4_signal_levels(train_set);

-- 
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Almost all of the GEN7 checks in the DP code are actually looking for
> IVB. HSW doesn't even take these codepaths, and VLV is excluded on
> account of not having port A. So let's change the checks to IS_IVB to
> make the code less confusing.
>
> Reviewed-by: Jani Nikula 

Yup.

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 538b10084a9d..263e4b1d1db9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1989,7 +1989,7 @@ static void intel_dp_prepare(struct intel_encoder 
> *encoder,
>  
>   /* Split out the IBX/CPU vs CPT settings */
>  
> - if (IS_GEN7(dev_priv) && port == PORT_A) {
> + if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>   if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>   intel_dp->DP |= DP_SYNC_HS_HIGH;
>   if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -2669,7 +2669,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder 
> *encoder,
>   if (!(tmp & DP_PORT_EN))
>   goto out;
>  
> - if (IS_GEN7(dev_priv) && port == PORT_A) {
> + if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>   *pipe = PORT_TO_PIPE_CPT(tmp);
>   } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>   enum pipe p;
> @@ -2908,7 +2908,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>   }
>   I915_WRITE(DP_TP_CTL(port), temp);
>  
> - } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> + } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>  (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>   *DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  
> @@ -3227,7 +3227,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>   return intel_ddi_dp_voltage_max(encoder);
>   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>   return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - else if (IS_GEN7(dev_priv) && port == PORT_A)
> + else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>   return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>   else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
>   return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> @@ -3256,7 +3256,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, 
> uint8_t voltage_swing)
>   default:
>   return DP_TRAIN_PRE_EMPH_LEVEL_0;
>   }
> - } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> + } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>   return DP_TRAIN_PRE_EMPH_LEVEL_2;
> @@ -3565,7 +3565,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>   signal_levels = chv_signal_levels(intel_dp);
>   } else if (IS_VALLEYVIEW(dev_priv)) {
>   signal_levels = vlv_signal_levels(intel_dp);
> - } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> + } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>   signal_levels = gen7_edp_signal_levels(train_set);
>   mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
>   } else if (IS_GEN6(dev_priv) && port == PORT_A) {
> @@ -3655,7 +3655,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  
>   DRM_DEBUG_KMS("\n");
>  
> - if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> + if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>   DP &= ~DP_LINK_TRAIN_MASK_CPT;
>   DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

-- 
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> All DDI platforms support the full set of preemph settings for each
> supported vswing, so let's use the same code for them. We'll also move
> the code into intel_ddi.c so that it sits closer to the actual buf trans
> tables.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 20 
>  drivers/gpu/drm/i915/intel_dp.c  | 30 --
>  drivers/gpu/drm/i915/intel_drv.h |  2 ++
>  3 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b98ac0541f19..1665bc588241 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> +/*
> + * We assume that the full set of pre-emphasis values can be
> + * used on all DDI platforms. Should that change we need to
> + * rethink this code.
> + */
> +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 
> voltage_swing)
> +{
> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> + return DP_TRAIN_PRE_EMPH_LEVEL_3;
> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> + return DP_TRAIN_PRE_EMPH_LEVEL_2;
> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> + return DP_TRAIN_PRE_EMPH_LEVEL_1;
> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> + default:
> + return DP_TRAIN_PRE_EMPH_LEVEL_0;
> + }
> +}
> +
>  static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
>  int level, enum intel_output_type type)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4755bb1b0b40..538b10084a9d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3239,33 +3239,11 @@ uint8_t
>  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  {
>   struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> - enum port port = dp_to_dig_port(intel_dp)->base.port;
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + enum port port = encoder->port;
>  
> - if (INTEL_GEN(dev_priv) >= 9) {
> - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> - return DP_TRAIN_PRE_EMPH_LEVEL_3;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> - return DP_TRAIN_PRE_EMPH_LEVEL_2;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> - return DP_TRAIN_PRE_EMPH_LEVEL_1;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> - return DP_TRAIN_PRE_EMPH_LEVEL_0;
> - default:
> - return DP_TRAIN_PRE_EMPH_LEVEL_0;
> - }
> - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> - return DP_TRAIN_PRE_EMPH_LEVEL_3;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> - return DP_TRAIN_PRE_EMPH_LEVEL_2;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> - return DP_TRAIN_PRE_EMPH_LEVEL_1;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> - default:
> - return DP_TRAIN_PRE_EMPH_LEVEL_0;
> - }
> + if (HAS_DDI(dev_priv)) {
> + return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
>   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 12002fc77235..22af249393a4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct 
> drm_i915_private *dev_priv,
>  u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
> +  u8 voltage_swing);
>  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>bool enable);
>  void icl_map_plls_to_ports(struct drm_crtc *crtc,

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Keep guc submission permanently engaged

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Keep guc submission 
permanently engaged
URL   : https://patchwork.freedesktop.org/series/43352/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
92f7337107d8 drm/i915/guc: Keep guc submission permanently engaged
94d5d62f10af HAX guc please
-:19: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 8 lines checked

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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
> fall through the if ladder in a weird way. This function will look at
> the actual buf trans tables we have for HSW/BDW to determine the max
> vswing level.
>
> It looks to me like the current code leads HSW port A down the IVB port
> A path, HSW port B+ and BDW fall through to the very end. Both cases do
> result in the correct max vswing level 2, but it's very hard to see that
> from the code.
>
> Signed-off-by: Ville Syrjälä 

What a PITA patch to review that there are no functional changes!

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2cc58596ff5a..4755bb1b0b40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3220,12 +3220,12 @@ uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
>  {
>   struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> - enum port port = dp_to_dig_port(intel_dp)->base.port;
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + enum port port = encoder->port;
>  
> - if (INTEL_GEN(dev_priv) >= 9) {
> - struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + if (HAS_DDI(dev_priv))
>   return intel_ddi_dp_voltage_max(encoder);
> - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>   return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>   else if (IS_GEN7(dev_priv) && port == PORT_A)
>   return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;

-- 
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Keep guc submission permanently engaged

[Michal Wajdeczko]

On Thu, 17 May 2018 18:56:41 +0200, Chris Wilson  
 wrote:



We make a decision at module load whether to use the GuC backend or not,
but lose that setup across set-wedge. Currently, the guc doesn't
override the engine->set_default_submission hook letting execlists sneak
back in temporarily on unwedging leading to an unbalanced park/unpark.

Testcase: igt/gem_eio
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 34 +++--
 drivers/gpu/drm/i915/intel_lrc.c|  2 +-
 drivers/gpu/drm/i915/intel_lrc.h|  2 ++
 3 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c  
b/drivers/gpu/drm/i915/intel_guc_submission.c

index 637e852888ec..cbd8caffd271 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1264,6 +1264,29 @@ static void guc_submission_unpark(struct  
intel_engine_cs *engine)

intel_engine_pin_breadcrumbs_irq(engine);
 }
+static void guc_set_default_submission(struct intel_engine_cs *engine)
+{
+   /*
+* We inherit a bunch of functions from execlists that we'd like
+* to keep using:
+*
+*engine->submit_request = execlists_submit_request;
+*engine->cancel_requests = execlists_cancel_requests;
+*engine->schedule = execlists_schedule;
+*
+* But we need to override the actual submission backend in order
+* to talk to the GuC.
+*/
+   execlists_set_default_submission(engine);
+
+   engine->execlists.tasklet.func = guc_submission_tasklet;
+
+   engine->park = guc_submission_park;
+   engine->unpark = guc_submission_unpark;
+
+   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+}
+
 int intel_guc_submission_enable(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1302,17 +1325,10 @@ int intel_guc_submission_enable(struct intel_guc  
*guc)

guc_interrupts_capture(dev_priv);
for_each_engine(engine, dev_priv, id) {
-   struct intel_engine_execlists * const execlists =
-   >execlists;
-
-   execlists->tasklet.func = guc_submission_tasklet;
-
engine->reset.prepare = guc_reset_prepare;
+   engine->set_default_submission = guc_set_default_submission;
-   engine->park = guc_submission_park;
-   engine->unpark = guc_submission_unpark;
-
-   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+   engine->set_default_submission(engine);


While this part looks ok (and maybe will help with my [1])
but what about intel_guc_submission_disable(), where we
will call intel_engines_reset_default_submission() and
'revert' to GuC again... time for nop_submission() ?

Michal


[1] https://patchwork.freedesktop.org/series/41304/


}
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c  
b/drivers/gpu/drm/i915/intel_lrc.c

index 646ecf267411..853fb0b5f73e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2291,7 +2291,7 @@ void intel_logical_ring_cleanup(struct  
intel_engine_cs *engine)

kfree(engine);
 }
-static void execlists_set_default_submission(struct intel_engine_cs  
*engine)

+void execlists_set_default_submission(struct intel_engine_cs *engine)
 {
engine->submit_request = execlists_submit_request;
engine->cancel_requests = execlists_cancel_requests;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h  
b/drivers/gpu/drm/i915/intel_lrc.h

index 4ec7d8dd13c8..e64f47e612f4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -111,4 +111,6 @@ intel_lr_context_descriptor(struct i915_gem_context  
*ctx,

return to_intel_context(ctx, engine)->lrc_desc;
 }
+void execlists_set_default_submission(struct intel_engine_cs *engine);
+
 #endif /* _INTEL_LRC_H_ */

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Re: [Intel-gfx] [PATCH 18/19] drm/i915/execlists: Direct submission (avoid tasklet/ksoftirqd)

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-17 14:13:00)
> 
> On 17/05/2018 08:40, Chris Wilson wrote:
> > Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
> > bottom half"), we came to the conclusion that running our CSB processing
> > and ELSP submission from inside the irq handler was a bad idea. A really
> > bad idea as we could impose nearly 1s latency on other users of the
> > system, on average! Deferring our work to a tasklet allowed us to do the
> > processing with irqs enabled, reducing the impact to an average of about
> > 50us.
> > 
> > We have since eradicated the use of forcewaked mmio from inside the CSB
> > processing and ELSP submission, bringing the impact down to around 5us
> > (on Kabylake); an order of magnitude better than our measurements 2
> > years ago on Broadwell and only about 2x worse on average than the
> > gem_syslatency on an unladen system.
> > 
> > Comparing the impact on the maximum latency observed over a 120s interval,
> > repeated several times (using gem_syslatency, similar to RT's cyclictest)
> > while the system is fully laden with i915 nops, we see that direct
> > submission definitely worsens the response but not to the same outlandish
> > degree as before.
> > 
> > x Unladen baseline
> > + Using tasklet
> > * Direct submission
> > 
> > ++
> > |xx x  +++++ +   *  * *   ** *** *  *|
> > ||A|  |__AM__|   |_A_M___|   |
> > ++
> 
> What are these headers? This one and below, I cannot decipher them at all.

Ministat histogram. The headers being the label for the charts; it's a
bit flat so hard to tell it's a histogram.

> >  N   Min   MaxMedian   AvgStddev
> > x  10 51810   9.3 3.6530049
> > +  1072   120   108 102.9 15.758243
> > *  10   255   348   316 305.7  28.74814
> 
> In micro-seconds? so tasklet is 108us median? Direct submission 316us 
> median?

Yup, more runs required so you have prettier graphs and units.

> > And with a background load
> 
> This is IO background load?

Yes, background writeout.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

[Oscar Mateo Lozano]

On 5/17/2018 9:55 AM, Michel Thierry wrote:

On 5/16/2018 4:39 PM, Paulo Zanoni wrote:

Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:

Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.

Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for leaving
them out. See gen11_service_one_iir() for more info.


I can't find this function. Did you mean something else?



s/gen11_service_one_iir/gen11_reset_one_iir/



Yup, that's right. Thanks Michel, I didn't realize this had been renamed 
in upstream.







v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
   - Rebased
   - Renamed patch
   - Improved the ordering of GENs
   - Improved the printing of per-GEN info
v5: Avoid maybe-unitialized & add comment explaining the lack
 of PM ISR & IIR

Suggested-by: Paulo Zanoni 
Signed-off-by: Oscar Mateo 
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Cc: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/i915_debugfs.c   | 34 -
-
  drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
  drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
  3 files changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d663a9e0..d992dd2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct
seq_file *m, void *unused)
    intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  -    if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
-    pm_ier = I915_READ(GEN6_PMIER);
-    pm_imr = I915_READ(GEN6_PMIMR);
-    pm_isr = I915_READ(GEN6_PMISR);
-    pm_iir = I915_READ(GEN6_PMIIR);
-    pm_mask = I915_READ(GEN6_PMINTRMSK);
-    } else {
+    if (INTEL_GEN(dev_priv) >= 11) {
+    pm_ier =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+    pm_imr =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+    /*
+ * The equivalent to the PM ISR & IIR cannot
be read
+ * without affecting the current state of
the system
+ */
+    pm_isr = 0;
+    pm_iir = 0;
+    } else if (INTEL_GEN(dev_priv) >= 8) {
  pm_ier = I915_READ(GEN8_GT_IER(2));
  pm_imr = I915_READ(GEN8_GT_IMR(2));
  pm_isr = I915_READ(GEN8_GT_ISR(2));
  pm_iir = I915_READ(GEN8_GT_IIR(2));
-    pm_mask = I915_READ(GEN6_PMINTRMSK);
+    } else {
+    pm_ier = I915_READ(GEN6_PMIER);
+    pm_imr = I915_READ(GEN6_PMIMR);
+    pm_isr = I915_READ(GEN6_PMISR);
+    pm_iir = I915_READ(GEN6_PMIIR);
  }
+    pm_mask = I915_READ(GEN6_PMINTRMSK);
+
  seq_printf(m, "Video Turbo Mode: %s\n",
 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
  seq_printf(m, "HW control enabled: %s\n",
@@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file
*m, void *unused)
  seq_printf(m, "SW control enabled: %s\n",
 yesno((rpmodectl &
GEN6_RP_MEDIA_MODE_MASK) ==
    GEN6_RP_MEDIA_SW_MODE));
-    seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
IIR=0x%08x, MASK=0x%08x\n",
-   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+
+    seq_printf(m, "PM IER=0x%08x IMR=0x%08x,
MASK=0x%08x\n",
+   pm_ier, pm_imr, pm_mask);
+    if (INTEL_GEN(dev_priv) < 11) {
+    seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+   pm_isr, pm_iir);
+    }
  seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 rps->pm_intrmsk_mbz);
  seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
gt_perf_status);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b98cd44..d9f2f69 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1675,7 +1675,16 @@ static void capture_reg_state(struct
i915_gpu_state *error)
  }
    /* 4: Everything else */
-    if (INTEL_GEN(dev_priv) >= 8) {
+    if (INTEL_GEN(dev_priv) >= 11) {
+    error->ier = I915_READ(GEN8_DE_MISC_IER);
+    error->gtier[0] =
I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+    error->gtier[1] =
I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+    error->gtier[2] =
I915_READ(GEN11_GUC_SG_INTR_ENABLE);
+    error->gtier[3] =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+    error->gtier[4] =
I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
+    error->gtier[5] =
I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
+    error->ngtier = 6;
+    } else if 

[Intel-gfx] [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Ville Syrjala]

From: Ville Syrjälä 

To make the intent more clear, let's rename the signal level funcs for
the SNB/IVB CPU eDP.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263e4b1d1db9..cd4c60bfc4c2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
return signal_levels;
 }
 
-/* Gen6's DP voltage swing and pre-emphasis control */
+/* SNB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen6_edp_signal_levels(uint8_t train_set)
+snb_cpu_edp_signal_levels(uint8_t train_set)
 {
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
}
 }
 
-/* Gen7's DP voltage swing and pre-emphasis control */
+/* IVB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen7_edp_signal_levels(uint8_t train_set)
+ivb_cpu_edp_signal_levels(uint8_t train_set)
 {
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
} else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp);
} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
-   signal_levels = gen7_edp_signal_levels(train_set);
+   signal_levels = ivb_cpu_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
} else if (IS_GEN6(dev_priv) && port == PORT_A) {
-   signal_levels = gen6_edp_signal_levels(train_set);
+   signal_levels = snb_cpu_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
} else {
signal_levels = gen4_signal_levels(train_set);
-- 
2.16.1

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Re: [Intel-gfx] [PATCH 09/19] drm/i915/execlists: HWACK checking superseded checking port[0].count

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-05-17 11:55:29)
> 
> On 17/05/2018 08:40, Chris Wilson wrote:
> > The HWACK bit more generically solves the problem of resubmitting ESLP
> > while the hardware is still processing the current ELSP write. We no
> > longer need to check port[0].count itself.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 2 --
> >   1 file changed, 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 49283b3d3ebb..857ab04452f0 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -608,8 +608,6 @@ static bool __execlists_dequeue(struct intel_engine_cs 
> > *engine)
> >   GEM_BUG_ON(!execlists_is_active(execlists,
> >   EXECLISTS_ACTIVE_USER));
> >   GEM_BUG_ON(!port_count([0]));
> > - if (port_count([0]) > 1)
> > - return false;
> >   
> >   /*
> >* If we write to ELSP a second time before the HW has had
> > 
> 
> Looks indeed the same behaviour. Both before and after we wait for 
> preempted event before can submit more to the same port.
> 
> Reviewed-by: Tvrtko Ursulin 

Pushed this one as I think it's a nice standalone cleanup and been
meaning to do it for a while.
-Chris
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[Intel-gfx] [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

[Ville Syrjala]

From: Ville Syrjälä 

i965 does not have native DP. Let's rename the remaining gen4 references
in the DP code to g4x.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cd4c60bfc4c2..102070940095 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -56,7 +56,7 @@ struct dp_link_dpll {
struct dpll dpll;
 };
 
-static const struct dp_link_dpll gen4_dpll[] = {
+static const struct dp_link_dpll g4x_dpll[] = {
{ 162000,
{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
{ 27,
@@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
int i, count = 0;
 
if (IS_G4X(dev_priv)) {
-   divisor = gen4_dpll;
-   count = ARRAY_SIZE(gen4_dpll);
+   divisor = g4x_dpll;
+   count = ARRAY_SIZE(g4x_dpll);
} else if (HAS_PCH_SPLIT(dev_priv)) {
divisor = pch_dpll;
count = ARRAY_SIZE(pch_dpll);
@@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp 
*intel_dp)
 }
 
 static uint32_t
-gen4_signal_levels(uint8_t train_set)
+g4x_signal_levels(uint8_t train_set)
 {
uint32_tsignal_levels = 0;
 
@@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = snb_cpu_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
} else {
-   signal_levels = gen4_signal_levels(train_set);
+   signal_levels = g4x_signal_levels(train_set);
mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
}
 
-- 
2.16.1

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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits

[Ville Syrjälä]

On Thu, May 17, 2018 at 12:31:59PM +0300, Jani Nikula wrote:
> On Mon, 14 May 2018, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Clean up the ADPA pipe select bits. To make the whole situation a bit
> > less ugly we'll start to share the same code between .get_hw_state()
> > and the port state asserts.
> >
> > v2: Order the defines shift,mask,value (Jani)
> >
> > Reviewed-by: Jani Nikula 
> 
> Yup, the series looks good.

Cool. Pushed to dinq.

> 
> BR,
> Jani.
> 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 11 +-
> >  drivers/gpu/drm/i915/intel_crt.c | 40 
> > ++--
> >  drivers/gpu/drm/i915/intel_display.c | 24 +-
> >  drivers/gpu/drm/i915/intel_drv.h |  2 ++
> >  4 files changed, 33 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f11bb213ec07..ae3c26216996 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4133,11 +4133,12 @@ enum {
> >  
> >  #define   ADPA_DAC_ENABLE  (1<<31)
> >  #define   ADPA_DAC_DISABLE 0
> > -#define   ADPA_PIPE_SELECT_MASK(1<<30)
> > -#define   ADPA_PIPE_A_SELECT   0
> > -#define   ADPA_PIPE_B_SELECT   (1<<30)
> > -#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
> > -/* CPT uses bits 29:30 for pch transcoder select */
> > +#define   ADPA_PIPE_SEL_SHIFT  30
> > +#define   ADPA_PIPE_SEL_MASK   (1<<30)
> > +#define   ADPA_PIPE_SEL(pipe)  ((pipe) << 30)
> > +#define   ADPA_PIPE_SEL_SHIFT_CPT  29
> > +#define   ADPA_PIPE_SEL_MASK_CPT   (3<<29)
> > +#define   ADPA_PIPE_SEL_CPT(pipe)  ((pipe) << 29)
> >  #define   ADPA_CRT_HOTPLUG_MASK  0x03ff /* bit 25-16 */
> >  #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
> >  #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> > b/drivers/gpu/drm/i915/intel_crt.c
> > index de0e22322c76..211d601cd1b1 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct 
> > drm_connector *connector)
> > return intel_encoder_to_crt(intel_attached_encoder(connector));
> >  }
> >  
> > +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> > +   i915_reg_t adpa_reg, enum pipe *pipe)
> > +{
> > +   u32 val;
> > +
> > +   val = I915_READ(adpa_reg);
> > +
> > +   /* asserts want to know the pipe even if the port is disabled */
> > +   if (HAS_PCH_CPT(dev_priv))
> > +   *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> 
> > ADPA_PIPE_SEL_SHIFT_CPT;
> > +   else
> > +   *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
> > +
> > +   return val & ADPA_DAC_ENABLE;
> > +}
> > +
> >  static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> >enum pipe *pipe)
> >  {
> > -   struct drm_device *dev = encoder->base.dev;
> > -   struct drm_i915_private *dev_priv = to_i915(dev);
> > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_crt *crt = intel_encoder_to_crt(encoder);
> > -   u32 tmp;
> > bool ret;
> >  
> > if (!intel_display_power_get_if_enabled(dev_priv,
> > encoder->power_domain))
> > return false;
> >  
> > -   ret = false;
> > -
> > -   tmp = I915_READ(crt->adpa_reg);
> > -
> > -   if (!(tmp & ADPA_DAC_ENABLE))
> > -   goto out;
> > +   ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
> >  
> > -   if (HAS_PCH_CPT(dev_priv))
> > -   *pipe = PORT_TO_PIPE_CPT(tmp);
> > -   else
> > -   *pipe = PORT_TO_PIPE(tmp);
> > -
> > -   ret = true;
> > -out:
> > intel_display_power_put(dev_priv, encoder->power_domain);
> >  
> > return ret;
> > @@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder 
> > *encoder,
> > if (HAS_PCH_LPT(dev_priv))
> > ; /* Those bits don't exist here */
> > else if (HAS_PCH_CPT(dev_priv))
> > -   adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> > -   else if (crtc->pipe == 0)
> > -   adpa |= ADPA_PIPE_A_SELECT;
> > +   adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
> > else
> > -   adpa |= ADPA_PIPE_B_SELECT;
> > +   adpa |= ADPA_PIPE_SEL(crtc->pipe);
> >  
> > if (!HAS_PCH_SPLIT(dev_priv))
> > I915_WRITE(BCLRPAT(crtc->pipe), 0);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index ad588d564198..6daa8d97a0aa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct 
> > drm_i915_private *dev_priv,
> >  

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

[Ville Syrjala]

From: Ville Syrjälä 

All DDI platforms support the full set of preemph settings for each
supported vswing, so let's use the same code for them. We'll also move
the code into intel_ddi.c so that it sits closer to the actual buf trans
tables.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 
 drivers/gpu/drm/i915/intel_dp.c  | 30 --
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b98ac0541f19..1665bc588241 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+/*
+ * We assume that the full set of pre-emphasis values can be
+ * used on all DDI platforms. Should that change we need to
+ * rethink this code.
+ */
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 
voltage_swing)
+{
+   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+   return DP_TRAIN_PRE_EMPH_LEVEL_3;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+   return DP_TRAIN_PRE_EMPH_LEVEL_2;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+   return DP_TRAIN_PRE_EMPH_LEVEL_1;
+   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+   default:
+   return DP_TRAIN_PRE_EMPH_LEVEL_0;
+   }
+}
+
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
   int level, enum intel_output_type type)
 {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4755bb1b0b40..538b10084a9d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3239,33 +3239,11 @@ uint8_t
 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-   enum port port = dp_to_dig_port(intel_dp)->base.port;
+   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   enum port port = encoder->port;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-   return DP_TRAIN_PRE_EMPH_LEVEL_3;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-   return DP_TRAIN_PRE_EMPH_LEVEL_2;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-   return DP_TRAIN_PRE_EMPH_LEVEL_1;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   default:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   }
-   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-   return DP_TRAIN_PRE_EMPH_LEVEL_3;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-   return DP_TRAIN_PRE_EMPH_LEVEL_2;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-   return DP_TRAIN_PRE_EMPH_LEVEL_1;
-   case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-   default:
-   return DP_TRAIN_PRE_EMPH_LEVEL_0;
-   }
+   if (HAS_DDI(dev_priv)) {
+   return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 12002fc77235..22af249393a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct 
drm_i915_private *dev_priv,
 u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
+u8 voltage_swing);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 bool enable);
 void icl_map_plls_to_ports(struct drm_crtc *crtc,
-- 
2.16.1

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[Intel-gfx] [PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

[Ville Syrjala]

From: Ville Syrjälä 

Almost all of the GEN7 checks in the DP code are actually looking for
IVB. HSW doesn't even take these codepaths, and VLV is excluded on
account of not having port A. So let's change the checks to IS_IVB to
make the code less confusing.

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 538b10084a9d..263e4b1d1db9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1989,7 +1989,7 @@ static void intel_dp_prepare(struct intel_encoder 
*encoder,
 
/* Split out the IBX/CPU vs CPT settings */
 
-   if (IS_GEN7(dev_priv) && port == PORT_A) {
+   if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -2669,7 +2669,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder 
*encoder,
if (!(tmp & DP_PORT_EN))
goto out;
 
-   if (IS_GEN7(dev_priv) && port == PORT_A) {
+   if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
*pipe = PORT_TO_PIPE_CPT(tmp);
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
enum pipe p;
@@ -2908,7 +2908,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
I915_WRITE(DP_TP_CTL(port), temp);
 
-   } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+   } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
@@ -3227,7 +3227,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return intel_ddi_dp_voltage_max(encoder);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-   else if (IS_GEN7(dev_priv) && port == PORT_A)
+   else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
@@ -3256,7 +3256,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, 
uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
-   } else if (IS_GEN7(dev_priv) && port == PORT_A) {
+   } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_2;
@@ -3565,7 +3565,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp);
-   } else if (IS_GEN7(dev_priv) && port == PORT_A) {
+   } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
signal_levels = gen7_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
} else if (IS_GEN6(dev_priv) && port == PORT_A) {
@@ -3655,7 +3655,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
DRM_DEBUG_KMS("\n");
 
-   if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+   if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
-- 
2.16.1

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[Intel-gfx] [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Ville Syrjala]

From: Ville Syrjälä 

Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
fall through the if ladder in a weird way. This function will look at
the actual buf trans tables we have for HSW/BDW to determine the max
vswing level.

It looks to me like the current code leads HSW port A down the IVB port
A path, HSW port B+ and BDW fall through to the very end. Both cases do
result in the correct max vswing level 2, but it's very hard to see that
from the code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2cc58596ff5a..4755bb1b0b40 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3220,12 +3220,12 @@ uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-   enum port port = dp_to_dig_port(intel_dp)->base.port;
+   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   enum port port = encoder->port;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+   if (HAS_DDI(dev_priv))
return intel_ddi_dp_voltage_max(encoder);
-   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-- 
2.16.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw

[Patchwork]

== Series Details ==

Series: drm/i915/icl: Don't update enabled dbuf slices struct until updated in 
hw
URL   : https://patchwork.freedesktop.org/series/43330/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4196_full -> Patchwork_9028_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9028_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9028_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43330/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9028_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd1:
  shard-kbl:  PASS -> SKIP +2

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9028_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
  shard-glk:  PASS -> FAIL (fdo#105703)

igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible:
  shard-hsw:  PASS -> DMESG-WARN (fdo#102614)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167)

igt@perf@polling:
  shard-hsw:  PASS -> FAIL (fdo#102252)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-kbl:  DMESG-FAIL -> PASS
  shard-glk:  DMESG-FAIL -> PASS

igt@gem_exec_store@cachelines-bsd:
  shard-hsw:  FAIL (fdo#17) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#102887) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363) -> PASS +1

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#103822, fdo#104724) -> PASS +2

igt@kms_rotation_crc@sprite-rotation-180:
  shard-hsw:  FAIL (fdo#103925, fdo#104724) -> PASS


  fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4196 -> Patchwork_9028

  CI_DRM_4196: 624ef35328293cfb60f26b5fbc9cc97eeab505b5 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9028: e81bef60683f2aac798bb75836ae7bf0e6d8f89a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9028/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4198 -> Patchwork_9033 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9033 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9033, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43344/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9033:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9033 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@basic-flip-vs-wf_vblank:
  fi-cnl-psr: PASS -> FAIL (fdo#100368)


 Possible fixes 

igt@kms_flip@basic-flip-vs-dpms:
  fi-cnl-y3:  INCOMPLETE (fdo#105086) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4198 -> Patchwork_9033

  CI_DRM_4198: 9f0af9e6938d975b744e3533410bf6398f3ce2d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9033: 272940a885c0c7bfe68e7be018bc5a3a18d806d6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

272940a885c0 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
81caf1d82050 drm/i915/selftests: Wait longer for the old active request

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9033/issues.html
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Re: [Intel-gfx] [PATCH i-g-t 1/3] igt/gem_cpu_reloc: Check HW exists before attempting to use it

[Antonio Argenziano]

On 17/05/18 09:52, Chris Wilson wrote:

Quoting Antonio Argenziano (2018-05-17 17:29:26)



On 17/05/18 08:37, Chris Wilson wrote:

Quoting Antonio Argenziano (2018-05-17 16:08:14)



On 17/05/18 01:23, Chris Wilson wrote:

Confirm we have the available HW before asserting it succeeds.

Signed-off-by: Chris Wilson 
---
tests/gem_cpu_reloc.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
index 882c312d4..e3bbcd239 100644
--- a/tests/gem_cpu_reloc.c
+++ b/tests/gem_cpu_reloc.c
@@ -167,6 +167,7 @@ static void run_test(int fd, int count)
use_blt = 0;


Is this^ meant to be EXEC_DEFAULT?


Depends on your viewpoint. EXEC_DEFAULT is zero.


Just wandering if it should enforce EXEC_RENDER. Which I think is what
we want for gen 5-.


Not really. It just wants the default mixed ring. You definitely don't
want to suggest sending blitter commands down the 3D pipe, that would be
even more confusing.


The comment below answers this question as well.




if (intel_gen(noop) >= 6)
use_blt = I915_EXEC_BLT;
+ gem_require_ring(fd, use_blt);


Are any gens 6+ that do not have a BLT ring? if that is the case
shouldn't we use '0' like we do for 5- gens?


No, it has to match the engine for which the blitter commands are valid. If
that engine does not exist, there is no alternative except to rewrite the
test not to use those commands. If there was, it indeed would be included
in the selection above.


So, just to wrap my head around it, the commands we are talking about
here are allowed on render for gen5- but only on blitter on 6+. Right?


There is no render for gen5- either. There is a universal ringbuffer
that can handle multiple different client commands, and on the odd
machine a bit stream decoder.


I see, I wasn't making any sense then :).

Reviewed-by: Antonio Argenziano 


-Chris


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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Keep guc submission permanently engaged

[Chris Wilson]

We make a decision at module load whether to use the GuC backend or not,
but lose that setup across set-wedge. Currently, the guc doesn't
override the engine->set_default_submission hook letting execlists sneak
back in temporarily on unwedging leading to an unbalanced park/unpark.

Testcase: igt/gem_eio
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 34 +++--
 drivers/gpu/drm/i915/intel_lrc.c|  2 +-
 drivers/gpu/drm/i915/intel_lrc.h|  2 ++
 3 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 637e852888ec..cbd8caffd271 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1264,6 +1264,29 @@ static void guc_submission_unpark(struct intel_engine_cs 
*engine)
intel_engine_pin_breadcrumbs_irq(engine);
 }
 
+static void guc_set_default_submission(struct intel_engine_cs *engine)
+{
+   /*
+* We inherit a bunch of functions from execlists that we'd like
+* to keep using:
+*
+*engine->submit_request = execlists_submit_request;
+*engine->cancel_requests = execlists_cancel_requests;
+*engine->schedule = execlists_schedule;
+*
+* But we need to override the actual submission backend in order
+* to talk to the GuC.
+*/
+   execlists_set_default_submission(engine);
+
+   engine->execlists.tasklet.func = guc_submission_tasklet;
+
+   engine->park = guc_submission_park;
+   engine->unpark = guc_submission_unpark;
+
+   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+}
+
 int intel_guc_submission_enable(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1302,17 +1325,10 @@ int intel_guc_submission_enable(struct intel_guc *guc)
guc_interrupts_capture(dev_priv);
 
for_each_engine(engine, dev_priv, id) {
-   struct intel_engine_execlists * const execlists =
-   >execlists;
-
-   execlists->tasklet.func = guc_submission_tasklet;
-
engine->reset.prepare = guc_reset_prepare;
+   engine->set_default_submission = guc_set_default_submission;
 
-   engine->park = guc_submission_park;
-   engine->unpark = guc_submission_unpark;
-
-   engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+   engine->set_default_submission(engine);
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 646ecf267411..853fb0b5f73e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2291,7 +2291,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs 
*engine)
kfree(engine);
 }
 
-static void execlists_set_default_submission(struct intel_engine_cs *engine)
+void execlists_set_default_submission(struct intel_engine_cs *engine)
 {
engine->submit_request = execlists_submit_request;
engine->cancel_requests = execlists_cancel_requests;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 4ec7d8dd13c8..e64f47e612f4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -111,4 +111,6 @@ intel_lr_context_descriptor(struct i915_gem_context *ctx,
return to_intel_context(ctx, engine)->lrc_desc;
 }
 
+void execlists_set_default_submission(struct intel_engine_cs *engine);
+
 #endif /* _INTEL_LRC_H_ */
-- 
2.17.0

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[Intel-gfx] [PATCH 2/2] HAX guc please

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 6684025b7af8..f535fc87cca9 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.17.0

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Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

[Michel Thierry]

On 5/16/2018 4:39 PM, Paulo Zanoni wrote:

Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:

Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.

Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for leaving
them out. See gen11_service_one_iir() for more info.


I can't find this function. Did you mean something else?



s/gen11_service_one_iir/gen11_reset_one_iir/






v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
   - Rebased
   - Renamed patch
   - Improved the ordering of GENs
   - Improved the printing of per-GEN info
v5: Avoid maybe-unitialized & add comment explaining the lack
 of PM ISR & IIR

Suggested-by: Paulo Zanoni 
Signed-off-by: Oscar Mateo 
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Cc: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/i915_debugfs.c   | 34 -
-
  drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
  drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
  3 files changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d663a9e0..d992dd2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct
seq_file *m, void *unused)
  
  		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  
-		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {

-   pm_ier = I915_READ(GEN6_PMIER);
-   pm_imr = I915_READ(GEN6_PMIMR);
-   pm_isr = I915_READ(GEN6_PMISR);
-   pm_iir = I915_READ(GEN6_PMIIR);
-   pm_mask = I915_READ(GEN6_PMINTRMSK);
-   } else {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   pm_ier =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+   pm_imr =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+   /*
+* The equivalent to the PM ISR & IIR cannot
be read
+* without affecting the current state of
the system
+*/
+   pm_isr = 0;
+   pm_iir = 0;
+   } else if (INTEL_GEN(dev_priv) >= 8) {
pm_ier = I915_READ(GEN8_GT_IER(2));
pm_imr = I915_READ(GEN8_GT_IMR(2));
pm_isr = I915_READ(GEN8_GT_ISR(2));
pm_iir = I915_READ(GEN8_GT_IIR(2));
-   pm_mask = I915_READ(GEN6_PMINTRMSK);
+   } else {
+   pm_ier = I915_READ(GEN6_PMIER);
+   pm_imr = I915_READ(GEN6_PMIMR);
+   pm_isr = I915_READ(GEN6_PMISR);
+   pm_iir = I915_READ(GEN6_PMIIR);
}
+   pm_mask = I915_READ(GEN6_PMINTRMSK);
+
seq_printf(m, "Video Turbo Mode: %s\n",
   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
seq_printf(m, "HW control enabled: %s\n",
@@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file
*m, void *unused)
seq_printf(m, "SW control enabled: %s\n",
   yesno((rpmodectl &
GEN6_RP_MEDIA_MODE_MASK) ==
  GEN6_RP_MEDIA_SW_MODE));
-   seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
IIR=0x%08x, MASK=0x%08x\n",
-  pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+
+   seq_printf(m, "PM IER=0x%08x IMR=0x%08x,
MASK=0x%08x\n",
+  pm_ier, pm_imr, pm_mask);
+   if (INTEL_GEN(dev_priv) < 11) {
+   seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+  pm_isr, pm_iir);
+   }
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
   rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
gt_perf_status);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b98cd44..d9f2f69 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1675,7 +1675,16 @@ static void capture_reg_state(struct
i915_gpu_state *error)
}
  
  	/* 4: Everything else */

-   if (INTEL_GEN(dev_priv) >= 8) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   error->ier = I915_READ(GEN8_DE_MISC_IER);
+   error->gtier[0] =
I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+   error->gtier[1] =
I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+

Re: [Intel-gfx] [PATCH i-g-t 1/3] igt/gem_cpu_reloc: Check HW exists before attempting to use it

[Chris Wilson]

Quoting Antonio Argenziano (2018-05-17 17:29:26)
> 
> 
> On 17/05/18 08:37, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2018-05-17 16:08:14)
> >>
> >>
> >> On 17/05/18 01:23, Chris Wilson wrote:
> >>> Confirm we have the available HW before asserting it succeeds.
> >>>
> >>> Signed-off-by: Chris Wilson 
> >>> ---
> >>>tests/gem_cpu_reloc.c | 1 +
> >>>1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
> >>> index 882c312d4..e3bbcd239 100644
> >>> --- a/tests/gem_cpu_reloc.c
> >>> +++ b/tests/gem_cpu_reloc.c
> >>> @@ -167,6 +167,7 @@ static void run_test(int fd, int count)
> >>>use_blt = 0;
> >>
> >> Is this^ meant to be EXEC_DEFAULT?
> > 
> > Depends on your viewpoint. EXEC_DEFAULT is zero.
> 
> Just wandering if it should enforce EXEC_RENDER. Which I think is what 
> we want for gen 5-.

Not really. It just wants the default mixed ring. You definitely don't
want to suggest sending blitter commands down the 3D pipe, that would be
even more confusing.

> >>>if (intel_gen(noop) >= 6)
> >>>use_blt = I915_EXEC_BLT;
> >>> + gem_require_ring(fd, use_blt);
> >>
> >> Are any gens 6+ that do not have a BLT ring? if that is the case
> >> shouldn't we use '0' like we do for 5- gens?
> > 
> > No, it has to match the engine for which the blitter commands are valid. If
> > that engine does not exist, there is no alternative except to rewrite the
> > test not to use those commands. If there was, it indeed would be included
> > in the selection above.
> 
> So, just to wrap my head around it, the commands we are talking about 
> here are allowed on render for gen5- but only on blitter on 6+. Right?

There is no render for gen5- either. There is a universal ringbuffer
that can handle multiple different client commands, and on the odd
machine a bit stream decoder.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43344/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
81caf1d82050 drm/i915/selftests: Wait longer for the old active request
272940a885c0 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#11: 
<7>[  239.094843] i915_gem_set_wedged   current seqno 19a98, last 19a9a, 
hangcheck 0 [5158 ms]

total: 0 errors, 1 warnings, 0 checks, 9 lines checked

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Re: [Intel-gfx] [PATCH i-g-t 1/3] igt/gem_cpu_reloc: Check HW exists before attempting to use it

[Antonio Argenziano]

On 17/05/18 08:37, Chris Wilson wrote:

Quoting Antonio Argenziano (2018-05-17 16:08:14)



On 17/05/18 01:23, Chris Wilson wrote:

Confirm we have the available HW before asserting it succeeds.

Signed-off-by: Chris Wilson 
---
   tests/gem_cpu_reloc.c | 1 +
   1 file changed, 1 insertion(+)

diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
index 882c312d4..e3bbcd239 100644
--- a/tests/gem_cpu_reloc.c
+++ b/tests/gem_cpu_reloc.c
@@ -167,6 +167,7 @@ static void run_test(int fd, int count)
   use_blt = 0;


Is this^ meant to be EXEC_DEFAULT?


Depends on your viewpoint. EXEC_DEFAULT is zero.


Just wandering if it should enforce EXEC_RENDER. Which I think is what 
we want for gen 5-.





   if (intel_gen(noop) >= 6)
   use_blt = I915_EXEC_BLT;
+ gem_require_ring(fd, use_blt);


Are any gens 6+ that do not have a BLT ring? if that is the case
shouldn't we use '0' like we do for 5- gens?


No, it has to match the engine for which the blitter commands are valid. If
that engine does not exist, there is no alternative except to rewrite the
test not to use those commands. If there was, it indeed would be included
in the selection above.


So, just to wrap my head around it, the commands we are talking about 
here are allowed on render for gen5- but only on blitter on 6+. Right?


Thanks,
Antonio


-Chris


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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43334/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4197 -> Patchwork_9032 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9032 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9032, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43334/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9032:

  === IGT changes ===

 Possible regressions 

igt@gem_exec_fence@await-hang-default:
  fi-blb-e6850:   PASS -> INCOMPLETE


== Known issues ==

  Here are the changes found in Patchwork_9032 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   PASS -> DMESG-FAIL (fdo#102614, fdo#106103)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


 Possible fixes 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: FAIL (fdo#102575) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9032

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9032: cbab86526526d81869250c4c7c673c3d3a8dc051 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

cbab86526526 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
a809889d3010 drm/i915/selftests: Wait longer for the old active request

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9032/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43334/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a809889d3010 drm/i915/selftests: Wait longer for the old active request
cbab86526526 drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#11: 
<7>[  239.094843] i915_gem_set_wedged   current seqno 19a98, last 19a9a, 
hangcheck 0 [5158 ms]

total: 0 errors, 1 warnings, 0 checks, 8 lines checked

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Re: [Intel-gfx] [PATCH v11 0/2] Enabling content-type setting for HDMI displays.

[Ville Syrjälä]

On Tue, May 15, 2018 at 04:59:26PM +0300, StanLis wrote:
> From: Stanislav Lisovskiy 
> 
> Added content type setting property to drm_connector(part 1)
> and enabled transmitting it with HDMI AVI infoframes
> for i915(part 2).
> 
> Stanislav Lisovskiy (2):
>   drm: content-type property for HDMI connector
>   i915: content-type property for HDMI connector

Series pushed to drm-misc-next. Thanks for the patches.

PS. I fixed up a couple of checkpatch warns while applying
the patches. In the future please look through the reported
warnings and fix up the ones that aren't entirely crazy.

> 
>  Documentation/gpu/drm-kms.rst|   6 ++
>  Documentation/gpu/kms-properties.csv |   1 +
>  drivers/gpu/drm/drm_atomic.c |   4 +
>  drivers/gpu/drm/drm_connector.c  | 115 +++
>  drivers/gpu/drm/drm_edid.c   |   8 ++
>  drivers/gpu/drm/i915/intel_atomic.c  |   1 +
>  drivers/gpu/drm/i915/intel_hdmi.c|  18 +++--
>  include/drm/drm_connector.h  |  15 
>  include/drm/drm_mode_config.h|   5 ++
>  include/uapi/drm/drm_mode.h  |   7 ++
>  10 files changed, 174 insertions(+), 6 deletions(-)
> 
> -- 
> 2.17.0

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Nul-terminate legacy debug string

[Patchwork]

== Series Details ==

Series: drm/i915: Nul-terminate legacy debug string
URL   : https://patchwork.freedesktop.org/series/43341/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4197 -> Patchwork_9031 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43341/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9031 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9031

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9031: cf9bb1a98ae0198ad7e8e947f3e7acd2502597ec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

cf9bb1a98ae0 drm/i915: Nul-terminate legacy debug string

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9031/issues.html
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[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Wait longer for the old active request

[Chris Wilson]

When testing reset, we wait for 1s on the main thread for the hang to
start. Meanwhile, we continue submitting requests on all the background
threads, and we may have more threads than cores and so potentially
starve the waiter from being woken within the timeout. As the hang
timeout and the active timeouts are the same, it is hard to distinguish
which caused the timeout. Bump the active thread timeouts to 5s,
compared to the 1s timeout for the hang, so that we preferentially
report the hang timing out, while hopefully ensuring that we do at least
wake up the hang thread first before declaring the background active
timeout.

Signed-off-by: Chris Wilson 
---
 .../gpu/drm/i915/selftests/intel_hangcheck.c  | 48 +--
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 438e0b045a2c..f1dc42a171c8 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -560,6 +560,30 @@ struct active_engine {
 #define TEST_SELF  BIT(2)
 #define TEST_PRIORITY  BIT(3)
 
+static int active_request_put(struct i915_request *rq)
+{
+   int err = 0;
+
+   if (!rq)
+   return 0;
+
+   if (i915_request_wait(rq, 0, 5 * HZ) < 0) {
+   GEM_TRACE("%s timed out waiting for completion of fence 
%llx:%d, seqno %d.\n",
+ rq->engine->name,
+ rq->fence.context,
+ rq->fence.seqno,
+ i915_request_global_seqno(rq));
+   GEM_TRACE_DUMP();
+
+   i915_gem_set_wedged(rq->i915);
+   err = -EIO;
+   }
+
+   i915_request_put(rq);
+
+   return err;
+}
+
 static int active_engine(void *data)
 {
I915_RND_STATE(prng);
@@ -608,24 +632,20 @@ static int active_engine(void *data)
i915_request_add(new);
mutex_unlock(>i915->drm.struct_mutex);
 
-   if (old) {
-   if (i915_request_wait(old, 0, HZ) < 0) {
-   GEM_TRACE("%s timed out.\n", engine->name);
-   GEM_TRACE_DUMP();
-
-   i915_gem_set_wedged(engine->i915);
-   i915_request_put(old);
-   err = -EIO;
-   break;
-   }
-   i915_request_put(old);
-   }
+   err = active_request_put(old);
+   if (err)
+   break;
 
cond_resched();
}
 
-   for (count = 0; count < ARRAY_SIZE(rq); count++)
-   i915_request_put(rq[count]);
+   for (count = 0; count < ARRAY_SIZE(rq); count++) {
+   int err__ = active_request_put(rq[count]);
+
+   /* Keep the first error */
+   if (!err)
+   err = err__;
+   }
 
 err_file:
mock_file_free(engine->i915, file);
-- 
2.17.0

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[Intel-gfx] [PATCH 2/2] drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset

[Chris Wilson]

Inside the live_hangcheck (reset) selftests, we occasionally see
failures like

<7>[  239.094840] i915_gem_set_wedged rcs0
<7>[  239.094843] i915_gem_set_wedged   current seqno 19a98, last 19a9a, 
hangcheck 0 [5158 ms]
<7>[  239.094846] i915_gem_set_wedged   Reset count: 6239 (global 1)
<7>[  239.094848] i915_gem_set_wedged   Requests:
<7>[  239.095052] i915_gem_set_wedged   first  19a99 [e8c:5f] prio=1024 
@ 5159ms: (null)
<7>[  239.095056] i915_gem_set_wedged   last   19a9a [e81:1a] prio=139 
@ 5159ms: igt/rcs0[5977]/1
<7>[  239.095059] i915_gem_set_wedged   active 19a99 [e8c:5f] prio=1024 
@ 5159ms: (null)
<7>[  239.095062] i915_gem_set_wedged   [head 0220, postfix 0280, tail 
02a8, batch 0x_]
<7>[  239.100050] i915_gem_set_wedged   ring->start:  0x00283000
<7>[  239.100053] i915_gem_set_wedged   ring->head:   0x01f8
<7>[  239.100055] i915_gem_set_wedged   ring->tail:   0x02a8
<7>[  239.100057] i915_gem_set_wedged   ring->emit:   0x02a8
<7>[  239.100059] i915_gem_set_wedged   ring->space:  0x0f10
<7>[  239.100085] i915_gem_set_wedged   RING_START: 0x00283000
<7>[  239.100088] i915_gem_set_wedged   RING_HEAD:  0x0260
<7>[  239.100091] i915_gem_set_wedged   RING_TAIL:  0x02a8
<7>[  239.100094] i915_gem_set_wedged   RING_CTL:   0x0001
<7>[  239.100097] i915_gem_set_wedged   RING_MODE:  0x0300 [idle]
<7>[  239.100100] i915_gem_set_wedged   RING_IMR: fefe
<7>[  239.100104] i915_gem_set_wedged   ACTHD:  0x_609c
<7>[  239.100108] i915_gem_set_wedged   BBADDR: 0x_609d
<7>[  239.100111] i915_gem_set_wedged   DMA_FADDR: 0x_00283260
<7>[  239.100114] i915_gem_set_wedged   IPEIR: 0x
<7>[  239.100117] i915_gem_set_wedged   IPEHR: 0x0280
<7>[  239.100120] i915_gem_set_wedged   Execlist status: 0x00044052 0002
<7>[  239.100124] i915_gem_set_wedged   Execlist CSB read 5 [5 cached], write 5 
[5 from hws], interrupt posted? no, tasklet queued? no (enabled)
<7>[  239.100128] i915_gem_set_wedged   ELSP[0] count=1, 
ring->start=00283000, rq: 19a99 [e8c:5f] prio=1024 @ 5164ms: (null)
<7>[  239.100132] i915_gem_set_wedged   ELSP[1] count=1, 
ring->start=00257000, rq: 19a9a [e81:1a] prio=139 @ 5164ms: igt/rcs0[5977]/1
<7>[  239.100135] i915_gem_set_wedged   HW active? 0x5
<7>[  239.100250] i915_gem_set_wedged   E 19a99 [e8c:5f] prio=1024 @ 
5164ms: (null)
<7>[  239.100338] i915_gem_set_wedged   E 19a9a [e81:1a] prio=139 @ 
5164ms: igt/rcs0[5977]/1
<7>[  239.100340] i915_gem_set_wedged   Queue priority: 139
<7>[  239.100343] i915_gem_set_wedged   Q 0 [e98:19] prio=132 @ 5164ms: 
igt/rcs0[5977]/8
<7>[  239.100346] i915_gem_set_wedged   Q 0 [e84:19] prio=121 @ 5165ms: 
igt/rcs0[5977]/2
<7>[  239.100349] i915_gem_set_wedged   Q 0 [e87:19] prio=82 @ 5165ms: 
igt/rcs0[5977]/3
<7>[  239.100352] i915_gem_set_wedged   Q 0 [e84:1a] prio=44 @ 5164ms: 
igt/rcs0[5977]/2
<7>[  239.100356] i915_gem_set_wedged   Q 0 [e8b:19] prio=20 @ 5165ms: 
igt/rcs0[5977]/4
<7>[  239.100362] i915_gem_set_wedged   drv_selftest [5894] waiting for 19a99

where the GPU saw an arbitration point and idles; AND HAS NOT BEEN RESET!
The RING_MODE indicates that is idle and has the STOP_RING bit set, so
try clearing it.

v2: Only clear the bit on restarting the ring, as we want to be sure the
STOP_RING bit is kept if reset fails on wedging.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 646ecf267411..211585187d2f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1773,6 +1773,9 @@ static void enable_execlists(struct intel_engine_cs 
*engine)
I915_WRITE(RING_MODE_GEN7(engine),
   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 
+   I915_WRITE(RING_MI_MODE(engine->mmio_base),
+  _MASKED_BIT_DISABLE(STOP_RING));
+
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
   engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-- 
2.17.0

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: HWACK checking superseded checking port[0].count

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: HWACK checking superseded checking port[0].count
URL   : https://patchwork.freedesktop.org/series/43322/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4196_full -> Patchwork_9027_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9027_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9027_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43322/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_9027_full:

  === IGT changes ===

 Warnings 

igt@gem_exec_schedule@deep-bsd2:
  shard-kbl:  SKIP -> PASS +1

igt@gem_exec_schedule@deep-render:
  shard-kbl:  PASS -> SKIP

igt@kms_force_connector_basic@prune-stale-modes:
  shard-hsw:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_9027_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_create@basic:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558)

igt@kms_cursor_crc@cursor-128x128-suspend:
  shard-kbl:  PASS -> FAIL (fdo#104724, fdo#103232, fdo#103191)

igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#103060) +1

igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
  shard-glk:  PASS -> FAIL (fdo#100368) +2

igt@kms_flip@flip-vs-blocking-wf-vblank:
  shard-hsw:  PASS -> FAIL (fdo#100368)

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
  shard-glk:  PASS -> FAIL (fdo#104724, fdo#103167)

igt@pm_rpm@pm-caching:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103313)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  shard-glk:  DMESG-FAIL -> PASS

igt@gem_exec_store@cachelines-bsd:
  shard-hsw:  FAIL (fdo#17) -> PASS

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#102887) -> PASS

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363) -> PASS +1

igt@kms_flip@plain-flip-fb-recreate-interruptible:
  shard-glk:  FAIL (fdo#100368) -> PASS +1

igt@kms_flip_tiling@flip-x-tiled:
  shard-glk:  FAIL (fdo#104724, fdo#103822) -> PASS +2

igt@kms_rotation_crc@sprite-rotation-180:
  shard-hsw:  FAIL (fdo#104724, fdo#103925) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4196 -> Patchwork_9027

  CI_DRM_4196: 624ef35328293cfb60f26b5fbc9cc97eeab505b5 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9027: bbad01ba6ca9bc8a821e7bd1d7ee04a0059829ff @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9027/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove unused enable_cmd_parser modparam

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unused enable_cmd_parser modparam
URL   : https://patchwork.freedesktop.org/series/43340/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4197 -> Patchwork_9030 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9030 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9030, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43340/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9030:

  === IGT changes ===

 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9030 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_chamelium@dp-edid-read:
  fi-kbl-7500u:   PASS -> FAIL (fdo#103841)


 Possible fixes 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: FAIL (fdo#102575) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9030

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9030: 913921ed0c35df218a49b797c1bcfe0fb67da883 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

913921ed0c35 drm/i915: Remove unused enable_cmd_parser modparam

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9030/issues.html
___
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Re: [Intel-gfx] [PATCH i-g-t 1/3] igt/gem_cpu_reloc: Check HW exists before attempting to use it

[Chris Wilson]

Quoting Antonio Argenziano (2018-05-17 16:08:14)
> 
> 
> On 17/05/18 01:23, Chris Wilson wrote:
> > Confirm we have the available HW before asserting it succeeds.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   tests/gem_cpu_reloc.c | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
> > index 882c312d4..e3bbcd239 100644
> > --- a/tests/gem_cpu_reloc.c
> > +++ b/tests/gem_cpu_reloc.c
> > @@ -167,6 +167,7 @@ static void run_test(int fd, int count)
> >   use_blt = 0;
> 
> Is this^ meant to be EXEC_DEFAULT?

Depends on your viewpoint. EXEC_DEFAULT is zero.

> >   if (intel_gen(noop) >= 6)
> >   use_blt = I915_EXEC_BLT;
> > + gem_require_ring(fd, use_blt);
> 
> Are any gens 6+ that do not have a BLT ring? if that is the case 
> shouldn't we use '0' like we do for 5- gens?

No, it has to match the engine for which the blitter commands are valid. If
that engine does not exist, there is no alternative except to rewrite the
test not to use those commands. If there was, it indeed would be included
in the selection above.
-Chris
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Re: [Intel-gfx] [PATCH] drm/dp: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Atwood, Matthew S]

On Thu, 2018-05-17 at 12:50 +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, Dhinakaran Pandiyan  om> wrote:
> > On Wed, 2018-05-16 at 09:33 -0700, matthew.s.atw...@intel.com
> > wrote:
> > > From: Matt Atwood 
> > > 
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses
> > > in
> > > DPCD
> > > 02200h through 0220Fh shall contain the DPRX's true capability.
> > > These
> > > values will match 0h through Fh, except for DPCD_REV,
> > > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > > 
> > > Read from DPCD once for all 3 values as this is an expensive
> > > operation.
> > > Spec mentions that all of address space 02200h through 0220Fh
> > > should
> > > contain the right information however currently only 3 values can
> > > differ.
> > > 
> > > There is no address space in the intel_dp->dpcd struct for
> > > addresses
> > > 02200h through 0220Fh, and since so much of the data is a
> > > identical,
> > > simply overwrite the values stored in 0h through Fh with
> > > the
> > > values that can be overwritten from addresses 02200h through
> > > 0220Fh
> 
> Without reading the spec, this commit message makes one think there's
> no
> point in any of this. Please mention this is for backward
> compatibility
> with older source devices that trip over because of newer DPCD.
sure thing
> 
> > Why overwrite all values if this is an expensive operation? From
> > what I
> > can see, you'll need to read only h - 5h
was mostly future proofing, we can get away with only reading 6 values.
the expense is to read 1, any number after that doesnt cost alot. That
being said sure thing.
> > 
> > > 
> > > Signed-off-by: Matt Atwood 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 14 ++
> > >  include/drm/drm_dp_helper.h |  5 +++--
> > >  2 files changed, 17 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index dde92e4af5d3..899ebc5cece6 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -3738,6 +3738,20 @@ intel_dp_read_dpcd(struct intel_dp
> > > *intel_dp)
> > >sizeof(intel_dp->dpcd)) < 0)
> > >   return false; /* aux transfer failed */
> > >  
> > > + if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > > + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> > > + intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) {
> > 
> > The same section in the spec also says - "The Extended Receiver
> > Capability registers at DPCD Addresses 02200h through 0220Fh shall
> > contain the DPRX’s true capability, while the original Base
> > Receiver
> > Capability registers at DPCD Addresses 0h through Fh might
> > indicate DPCD r1.1, a MAX_LINK_RATE of 2.7Gbps/lane, and no DFP to
> > avoid interoperability issues ..."
> > 
> > Which means, intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 is
> > probably
> > not going to be true for panels you want to read the extended
> > capabilities for. 
> 
> Agreed. Only check DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT.
sure
> 
> > 
> > > + uint8_t dpcd_ext[16];
> 
> u8.
> 
> > > +
> > > + if (drm_dp_dpcd_read(_dp->aux,
> > > DP_DP13_DPCD_REV,
> > > + _ext, sizeof(dpcd_ext)) < 0)
> > > + return false; /* aux transfer failed */
> 
> Please don't return false here. Just waltz on.
sure
> 
> Like DK said, please read the minimal amount. Please memcmp those six
> bytes against the already read DPCD, and debug log the *old* bytes if
> there's a diff (new bytes debug logged below), and memcpy the new
> parts
> in place.
I really like this idea. thanks!
> 
> > > +
> > > + intel_dp->dpcd[DP_DPCD_REV] =
> > > dpcd_ext[DP_DPCD_REV];
> > > + intel_dp->dpcd[DP_MAX_LINK_RATE] =
> > > dpcd_ext[DP_MAX_LINK_RATE];
> > > + intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] =
> > > + dpcd_ext[DP_DOWNSTREAMPORT_PRESENT];
> > > + }
> > >   DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > > >dpcd),
> > > intel_dp->dpcd);
> > >  
> > >   return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > > diff --git a/include/drm/drm_dp_helper.h
> > > b/include/drm/drm_dp_helper.h
> > > index c01564991a9f..757bd5913f3d 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > 
> > This should be a separate patch as it's outside i915.
no problem
> 
> Yes.
> 
> > 
> > > @@ -123,8 +123,9 @@
> > >  # define DP_FRAMING_CHANGE_CAP   (1 << 1)
> > >  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp
> > > v1.2 or
> > > higher */
> > >  
> > > -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e   /* XXX 1.2?
> > > */
> > > -# define DP_TRAINING_AUX_RD_MASK0x7F/* XXX 1.2?
> > > */
> > > +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e   /* XXX
> > 

[Intel-gfx] [PATCH] drm/i915: Nul-terminate legacy debug string

[Chris Wilson]

Make sure that when we don't have any scheduler attributes for the
request the string is terminated.

Fixes: 247870ac8ea7 ("drm/i915: Build request info on stack before printk")
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d4e159ae65a6..e78c6e769e8c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1143,7 +1143,7 @@ static void print_request(struct drm_printer *m,
  const char *prefix)
 {
const char *name = rq->fence.ops->get_timeline_name(>fence);
-   char buf[80];
+   char buf[80] = "";
int x = 0;
 
x = print_sched_attr(rq->i915, >sched.attr, buf, x, sizeof(buf));
-- 
2.17.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove unused enable_cmd_parser modparam

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unused enable_cmd_parser modparam
URL   : https://patchwork.freedesktop.org/series/43340/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
913921ed0c35 drm/i915: Remove unused enable_cmd_parser modparam
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#12: 
References: 41736a8e3331 ("drm/i915: Use the precomputed value for whether to 
enable command parsing")

-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 41736a8e3331 ("drm/i915: Use the 
precomputed value for whether to enable command parsing")'
#12: 
References: 41736a8e3331 ("drm/i915: Use the precomputed value for whether to 
enable command parsing")

total: 1 errors, 1 warnings, 0 checks, 16 lines checked

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Wait longer for the old active request

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Wait longer for the old 
active request
URL   : https://patchwork.freedesktop.org/series/43334/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4197 -> Patchwork_9029 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9029 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9029, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/43334/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9029:

  === IGT changes ===

 Possible regressions 

igt@gem_exec_fence@await-hang-default:
  fi-blb-e6850:   PASS -> INCOMPLETE


 Warnings 

igt@gem_exec_gttfill@basic:
  fi-pnv-d510:PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_9029 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-4200u:   PASS -> DMESG-FAIL (fdo#102614, fdo#106103)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4197 -> Patchwork_9029

  CI_DRM_4197: 4079eb91298e7ef6b8c3569adc0232b7d2492d78 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9029: 26d41bd6d7ab93e8339977bb551ef6b4396b21bc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

26d41bd6d7ab drm/i915: Flush the RING stop bit after clearing RING_HEAD in reset
ddf6fd832a10 drm/i915/selftests: Wait longer for the old active request

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9029/issues.html
___
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Re: [Intel-gfx] [PATCH] drm/i915: Remove unused enable_cmd_parser modparam

[Jani Nikula]

On Thu, 17 May 2018, Chris Wilson  wrote:
> The command parser is feature complete, stable and required by
> userspace. In commit 41736a8e3331 ("drm/i915: Use the precomputed value
> for whether to enable command parsing") I accidentally removed control
> from the modparam, and as no one has complained, eemove the left
> over modparam completely!
>
> References: 41736a8e3331 ("drm/i915: Use the precomputed value for whether to 
> enable command parsing")
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Jani Nikula 

Another one bites the dust!

Acked-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/i915_params.c | 3 ---
>  drivers/gpu/drm/i915/i915_params.h | 1 -
>  2 files changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index 66ea3552c63e..49fcc4679db6 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -130,9 +130,6 @@ i915_param_named_unsafe(invert_brightness, int, 0600,
>  i915_param_named(disable_display, bool, 0400,
>   "Disable display (default: false)");
>  
> -i915_param_named_unsafe(enable_cmd_parser, bool, 0400,
> - "Enable command parsing (true=enabled [default], false=disabled)");
> -
>  i915_param_named(mmio_debug, int, 0600,
>   "Enable the MMIO debug code for the first N failures (default: off). "
>   "This may negatively affect performance.");
> diff --git a/drivers/gpu/drm/i915/i915_params.h 
> b/drivers/gpu/drm/i915/i915_params.h
> index 6684025b7af8..aebe0469ddaa 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -58,7 +58,6 @@ struct drm_printer;
>   param(unsigned int, inject_load_failure, 0) \
>   /* leave bools at the end to not create holes */ \
>   param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
> - param(bool, enable_cmd_parser, true) \
>   param(bool, enable_hangcheck, true) \
>   param(bool, fastboot, false) \
>   param(bool, prefault_disable, false) \

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH i-g-t 1/3] igt/gem_cpu_reloc: Check HW exists before attempting to use it

[Antonio Argenziano]

On 17/05/18 01:23, Chris Wilson wrote:

Confirm we have the available HW before asserting it succeeds.

Signed-off-by: Chris Wilson 
---
  tests/gem_cpu_reloc.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
index 882c312d4..e3bbcd239 100644
--- a/tests/gem_cpu_reloc.c
+++ b/tests/gem_cpu_reloc.c
@@ -167,6 +167,7 @@ static void run_test(int fd, int count)
use_blt = 0;


Is this^ meant to be EXEC_DEFAULT?


if (intel_gen(noop) >= 6)
use_blt = I915_EXEC_BLT;
+   gem_require_ring(fd, use_blt);


Are any gens 6+ that do not have a BLT ring? if that is the case 
shouldn't we use '0' like we do for 5- gens?


Thanks,
Antonio

  
  	if (intel_gen(noop) >= 8) {

batch = gen8_batch;


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[Intel-gfx] [PATCH] drm/i915: Remove unused enable_cmd_parser modparam

[Chris Wilson]

The command parser is feature complete, stable and required by
userspace. In commit 41736a8e3331 ("drm/i915: Use the precomputed value
for whether to enable command parsing") I accidentally removed control
from the modparam, and as no one has complained, eemove the left
over modparam completely!

References: 41736a8e3331 ("drm/i915: Use the precomputed value for whether to 
enable command parsing")
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_params.c | 3 ---
 drivers/gpu/drm/i915/i915_params.h | 1 -
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 66ea3552c63e..49fcc4679db6 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -130,9 +130,6 @@ i915_param_named_unsafe(invert_brightness, int, 0600,
 i915_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
 
-i915_param_named_unsafe(enable_cmd_parser, bool, 0400,
-   "Enable command parsing (true=enabled [default], false=disabled)");
-
 i915_param_named(mmio_debug, int, 0600,
"Enable the MMIO debug code for the first N failures (default: off). "
"This may negatively affect performance.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 6684025b7af8..aebe0469ddaa 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -58,7 +58,6 @@ struct drm_printer;
param(unsigned int, inject_load_failure, 0) \
/* leave bools at the end to not create holes */ \
param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
-   param(bool, enable_cmd_parser, true) \
param(bool, enable_hangcheck, true) \
param(bool, fastboot, false) \
param(bool, prefault_disable, false) \
-- 
2.17.0

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