[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291_full -> Patchwork_9237_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9237_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9237_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9237_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-dirty-render: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9237_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_atomic_transition@plane-all-modeset-transition-fencing: shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) +1 igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#105454, fdo#106509) igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_flip@plain-flip-fb-recreate: shard-hsw: PASS -> FAIL (fdo#103928) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@gem_eio@hibernate: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-apl: FAIL (fdo#102887, fdo#105363) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS igt@kms_vblank@pipe-c-ts-continuation-modeset: shard-glk: DMESG-WARN (fdo#106247) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4291 -> Patchwork_9237 CI_DRM_4291: 1d2b97e15aaf8a354a58904dc6c4ca7366f78ed1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9237: 60f585b542bcaa77ca0a7356de85a174bad33d6e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9237/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: inline skl_copy_ddb_for_pipe() to its only caller
== Series Details == Series: drm/i915: inline skl_copy_ddb_for_pipe() to its only caller URL : https://patchwork.freedesktop.org/series/5/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291_full -> Patchwork_9236_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9236_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9236_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9236_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-blt: shard-kbl: PASS -> SKIP +1 igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 == Known issues == Here are the changes found in Patchwork_9236_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-apl: PASS -> FAIL (fdo#105347) igt@gem_eio@wait-1us: shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: shard-hsw: PASS -> FAIL (fdo#104873) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_flip@plain-flip-fb-recreate: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@gem_eio@hibernate: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@gem_wait@write-busy-bsd2: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-apl: FAIL (fdo#102887, fdo#105363) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-fb-recreate: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_vblank@pipe-c-ts-continuation-modeset: shard-glk: DMESG-WARN (fdo#106247) -> PASS Warnings igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> FAIL (fdo#105347) fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4291 -> Patchwork_9236 CI_DRM_4291: 1d2b97e15aaf8a354a58904dc6c4ca7366f78ed1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9236: 331503d813d07605c9447a57afc63bac621c3c2e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9236/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291 -> Patchwork_9237 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9237 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9237, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/6/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9237: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9237 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106248, fdo#106725) igt@gem_sync@basic-many-each: fi-cnl-y3: PASS -> INCOMPLETE (fdo#105086) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@gem_ctx_switch@basic-default-heavy: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@gem_exec_flush@basic-uc-set-default: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 == Participating hosts (39 -> 36) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4291 -> Patchwork_9237 CI_DRM_4291: 1d2b97e15aaf8a354a58904dc6c4ca7366f78ed1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9237: 60f585b542bcaa77ca0a7356de85a174bad33d6e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 60f585b542bc drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9237/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 4/6] drm/i915: Add NV12 support to intel_framebuffer_init
On 5/11/2018 2:33 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case
v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.
v6: Rebased (me)
v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.
v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.
v9: Rebased (me)
v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable
v11: Addressed review comments from Shashank Sharma
v12: Adding Reviewed By from Shashank Sharma
v13: Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"
v14: Addressed review comments from Maarten.
Add checks for fb width height for NV12 and fail the fb
creation if check fails. Added reviewed by from
Juha-Pekka Heikkila
v15: Rebased the series
v16: Setting the minimum value during fb creating to 16
as per Bspec for NV12. Earlier minimum was expected
to be > 16. Now changed it to >=16.
v17: Adding restriction to framebuffer_init - the fb
width and height should be a multiplier of 4
v18: Added RB from Maarten. Included Maarten's review comments
Dont allow CCS formats for fb creation of NV12
v19: Review comments from Maarten addressed -
Removing BROXTON support for NV12 due to WA826
Credits-to: Maarten Lankhorst
Tested-by: Clinton Taylor
Reviewed-by: Maarten Lankhorst
Reviewed-by: Shashank Sharma
Reviewed-by: Clinton Taylor
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6c42910..e746948 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14291,6 +14291,20 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_NV12:
+ if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
+ mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
+ DRM_DEBUG_KMS("RC not to be enabled with NV12\n");
+ goto err;
+ }
+ if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
+ IS_BROXTON(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+
drm_get_format_name(mode_cmd->pixel_format,
+ _name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format,
_name));
@@ -14303,6 +14317,14 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
drm_helper_mode_fill_fb_struct(_priv->drm, fb, mode_cmd);
+ if (fb->format->format == DRM_FORMAT_NV12 &&
+ (fb->width < SKL_MIN_YUV_420_SRC_W ||
+fb->height < SKL_MIN_YUV_420_SRC_H ||
+(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+ DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
+ return -EINVAL;
Shouldn't this be 'goto err'? All other early exits before and after
this do the goto to get the reference count clean up.
+ }
+
for (i = 0; i < fb->format->num_planes; i++) {
u32 stride_alignment;
___
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Re: [Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller
Quoting Paulo Zanoni (2018-06-08 00:07:00)
> static void
> skl_print_wm_changes(const struct drm_atomic_state *state)
> {
> @@ -5381,7 +5370,10 @@ static void skl_initial_wm(struct intel_atomic_state
> *state,
> if (cstate->base.active_changed)
> skl_atomic_update_crtc_wm(state, cstate);
>
> - skl_copy_ddb_for_pipe(hw_vals, results, pipe);
> + memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
> + sizeof(hw_vals->ddb.uv_plane[pipe]));
I must be seeing things.
ddb.uv_plane[pipe] must be a pointer, right?
Therefore sizeof(ddb.uv_plane[pipe]) must the size of that pointer and
not of the struct. Do you not mean sizeof(*ddb.uv_plane[pipe]) ?
Definitely time to stop reading code...
-Chris
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. -drivers/gpu/drm/i915/selftests/../i915_drv.h:3669:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3670:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
== Series Details == Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim checkpatch origin/drm-tip 60f585b542bc drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. -:28: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #28: FILE: drivers/gpu/drm/i915/i915_drv.h:648: +#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) ^ total: 0 errors, 0 warnings, 1 checks, 53 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: inline skl_copy_ddb_for_pipe() to its only caller
== Series Details == Series: drm/i915: inline skl_copy_ddb_for_pipe() to its only caller URL : https://patchwork.freedesktop.org/series/5/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4291 -> Patchwork_9236 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9236 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9236, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/5/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9236: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9236 that come from known issues: === IGT changes === Issues hit igt@core_auth@basic-auth: fi-elk-e7500: PASS -> DMESG-WARN (fdo#105225) igt@core_prop_blob@basic: fi-elk-e7500: PASS -> INCOMPLETE (fdo#103989) igt@gem_sync@basic-many-each: fi-cnl-y3: PASS -> INCOMPLETE (fdo#105086) Possible fixes igt@core_auth@basic-auth: fi-bdw-gvtdvm: DMESG-WARN (fdo#105600) -> PASS +2 igt@gem_ctx_switch@basic-default-heavy: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +2 igt@gem_exec_flush@basic-uc-set-default: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS Warnings igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#106724) -> DMESG-WARN (fdo#105719, fdo#106745) fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105225 https://bugs.freedesktop.org/show_bug.cgi?id=105225 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106724 https://bugs.freedesktop.org/show_bug.cgi?id=106724 fdo#106745 https://bugs.freedesktop.org/show_bug.cgi?id=106745 == Participating hosts (39 -> 36) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4291 -> Patchwork_9236 CI_DRM_4291: 1d2b97e15aaf8a354a58904dc6c4ca7366f78ed1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9236: 331503d813d07605c9447a57afc63bac621c3c2e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 331503d813d0 drm/i915: inline skl_copy_ddb_for_pipe() to its only caller == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9236/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn off
for ~400uS during a normal resolution change. The HDMI retimer on the
GLK NUC appears to require at least a full frame of quiet time before a
new faster clock can be correctly sync'd. The worst case scenario appears
to be 23.98Hz modes which requires a wait of 41.25ms. Add a quirk to the
driver for GLK NUC that waits 42ms.
Cc: Imre Deak
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 14 ++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c407366..628491d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -645,6 +645,7 @@ enum intel_sbi_destination {
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
#define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
struct intel_fbdev;
struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b344e0f..61b41c3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1784,6 +1784,9 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
+/* Quirk time computed based on 24fps frame time of 41.25ms */
+#define DDI_DISABLED_QUIRK_TIME 42
+
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder)
{
@@ -1793,6 +1796,11 @@ void intel_ddi_disable_transcoder_func(struct
drm_i915_private *dev_priv,
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
val |= TRANS_DDI_PORT_NONE;
I915_WRITE(reg, val);
+
+ if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME) {
+ msleep(DDI_DISABLED_QUIRK_TIME);
+ DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+ }
}
int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ed29219..0d07c37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14740,6 +14740,17 @@ static void quirk_increase_t12_delay(struct drm_device
*dev)
DRM_INFO("Applying T12 delay quirk\n");
}
+/* GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+ DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
@@ -14826,6 +14837,9 @@ static int intel_dmi_reverse_brightness(const struct
dmi_system_id *id)
/* Toshiba Satellite P50-C-18C */
{ 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+ /* GeminiLake NUC */
+ { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
};
static void intel_init_quirks(struct drm_device *dev)
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller
While things may have been different before, right now the function is
very simple and has a single caller. IMHO any possible benefits from
an abstraction here are gone and not worth the price of the current
indirection while reading the code.
Cc: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 533e6886..018aae9f5769 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5141,17 +5141,6 @@ skl_compute_ddb(struct drm_atomic_state *state)
return 0;
}
-static void
-skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
- struct skl_ddb_values *src,
- enum pipe pipe)
-{
- memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
- sizeof(dst->ddb.uv_plane[pipe]));
- memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
- sizeof(dst->ddb.plane[pipe]));
-}
-
static void
skl_print_wm_changes(const struct drm_atomic_state *state)
{
@@ -5381,7 +5370,10 @@ static void skl_initial_wm(struct intel_atomic_state
*state,
if (cstate->base.active_changed)
skl_atomic_update_crtc_wm(state, cstate);
- skl_copy_ddb_for_pipe(hw_vals, results, pipe);
+ memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],
+ sizeof(hw_vals->ddb.uv_plane[pipe]));
+ memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],
+ sizeof(hw_vals->ddb.plane[pipe]));
mutex_unlock(_priv->wm.wm_mutex);
}
--
2.14.4
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table
== Series Details == Series: drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table URL : https://patchwork.freedesktop.org/series/44435/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290_full -> Patchwork_9235_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9235_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9235_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9235_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9235_full that come from known issues: === IGT changes === Issues hit igt@gem_wait@write-busy-bsd2: shard-snb: SKIP -> INCOMPLETE (fdo#105411) igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: shard-hsw: PASS -> FAIL (fdo#104873) igt@kms_flip@plain-flip-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) Possible fixes igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@plain-flip-fb-recreate: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS Warnings igt@drv_selftest@live_gtt: shard-glk: FAIL (fdo#105347) -> INCOMPLETE (fdo#103359, k.org#198133) igt@kms_sysfs_edid_timing: shard-hsw: FAIL (fdo#100047) -> WARN (fdo#100047) fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4290 -> Patchwork_9235 CI_DRM_4290: fb7bd7a9480b64dd46964ef5a00aeef33410376d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9235: 7347fd680334d350d80b041fb73c2f4bff24552e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9235/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2) URL : https://patchwork.freedesktop.org/series/44288/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290_full -> Patchwork_9233_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9233_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: shard-hsw: PASS -> FAIL (fdo#104873) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) +1 Possible fixes igt@drv_selftest@live_gtt: shard-glk: FAIL (fdo#105347) -> PASS shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS Warnings igt@kms_sysfs_edid_timing: shard-hsw: FAIL (fdo#100047) -> WARN (fdo#100047) fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4290 -> Patchwork_9233 CI_DRM_4290: fb7bd7a9480b64dd46964ef5a00aeef33410376d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9233: ed692445602e01cd5e11ac97572f2e98c354db65 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9233/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9232_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9232_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9232_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9232_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd1: shard-kbl: PASS -> SKIP igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9232_full that come from known issues: === IGT changes === Issues hit igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_cursor_legacy@flip-vs-cursor-atomic: shard-hsw: PASS -> FAIL (fdo#102670) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#103928) igt@kms_flip@modeset-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@perf_pmu@multi-client-vcs1: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@wf_vblank-ts-check: shard-hsw: FAIL (fdo#103928) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9232 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9232: 76562cc5e78b8144582bd5ab2d4697a4936cd277 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9232/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/drv_suspend: Suspend under memory pressure
Recently we discovered that we have a race between swapping and
suspend in our resume path (we might be trying to page in an object
after disabling the block devices). Let's try to exercise that by
exhausting all of system memory before suspend.
v2: Explicitly share the large memory area on forking to avoid running
out of memory inside the suspend helpers (for they fork!)
References: https://bugs.freedesktop.org/show_bug.cgi?id=106640
Signed-off-by: Chris Wilson
Cc: Tomi Sarvela
Reviewed-by: Antonio Argenziano
---
lib/igt_core.c | 34
lib/igt_core.h | 1 +
tests/drv_suspend.c | 54 +
3 files changed, 75 insertions(+), 14 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 5092a3f03..06d8b0370 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -1702,20 +1702,7 @@ void igt_child_done(pid_t pid)
test_children[i] = test_children[i + 1];
}
-/**
- * igt_waitchildren:
- *
- * Wait for all children forked with igt_fork.
- *
- * The magic here is that exit codes from children will be correctly propagated
- * to the main thread, including the relevant exit code if a child thread
failed.
- * Of course if multiple children failed with different exit codes the
resulting
- * exit code will be non-deterministic.
- *
- * Note that igt_skip() will not be forwarded, feature tests need to be done
- * before spawning threads with igt_fork().
- */
-void igt_waitchildren(void)
+int __igt_waitchildren(void)
{
int err = 0;
int count;
@@ -1761,6 +1748,25 @@ void igt_waitchildren(void)
}
num_test_children = 0;
+ return err;
+}
+
+/**
+ * igt_waitchildren:
+ *
+ * Wait for all children forked with igt_fork.
+ *
+ * The magic here is that exit codes from children will be correctly propagated
+ * to the main thread, including the relevant exit code if a child thread
failed.
+ * Of course if multiple children failed with different exit codes the
resulting
+ * exit code will be non-deterministic.
+ *
+ * Note that igt_skip() will not be forwarded, feature tests need to be done
+ * before spawning threads with igt_fork().
+ */
+void igt_waitchildren(void)
+{
+ int err = __igt_waitchildren();
if (err)
igt_fail(err);
}
diff --git a/lib/igt_core.h b/lib/igt_core.h
index bf8cd66ca..a73b06493 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -742,6 +742,7 @@ bool __igt_fork(void);
for (int child = 0; child < (num_children); child++) \
for (; __igt_fork(); exit(0))
void igt_child_done(pid_t pid);
+int __igt_waitchildren(void);
void igt_waitchildren(void);
void igt_waitchildren_timeout(int seconds, const char *reason);
diff --git a/tests/drv_suspend.c b/tests/drv_suspend.c
index 2e39f20ae..9a9ff2005 100644
--- a/tests/drv_suspend.c
+++ b/tests/drv_suspend.c
@@ -160,6 +160,57 @@ test_sysfs_reader(bool hibernate)
igt_stop_helper();
}
+static void
+test_shrink(int fd, unsigned int mode)
+{
+ uint64_t *can_mlock, pin;
+
+ gem_quiescent_gpu(fd);
+ intel_purge_vm_caches(fd);
+
+ pin = (intel_get_total_ram_mb() + 1) << 20;
+
+ igt_debug("Total memory %'"PRIu64" B (%'"PRIu64" MiB)\n",
+ pin, pin >> 20);
+ can_mlock = mmap(NULL, pin, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_require(can_mlock != MAP_FAILED);
+
+ /* Lock all the system memory, forcing the driver into swap and OOM */
+ for (uint64_t inc = 64 << 20; inc >= 4 << 10; inc >>= 1) {
+ igt_debug("Testing+ %'"PRIu64" B (%'"PRIu64" MiB)\n",
+ *can_mlock, *can_mlock >> 20);
+
+ igt_fork(child, 1) {
+ for (uint64_t bytes = *can_mlock;
+bytes <= pin;
+bytes += inc) {
+ if (mlock(can_mlock, bytes))
+ break;
+
+ *can_mlock = bytes;
+ __sync_synchronize();
+ }
+ }
+ __igt_waitchildren();
+ }
+
+ intel_purge_vm_caches(fd);
+
+ igt_require(*can_mlock > 64 << 20);
+ *can_mlock -= 64 << 20;
+
+ igt_debug("Locking %'"PRIu64" B (%'"PRIu64" MiB)\n",
+ *can_mlock, *can_mlock >> 20);
+ igt_assert(!mlock(can_mlock, *can_mlock));
+ igt_info("Locked %'"PRIu64" B (%'"PRIu64" MiB)\n",
+*can_mlock, *can_mlock >> 20);
+
+ intel_purge_vm_caches(fd);
+ igt_system_suspend_autoresume(mode, SUSPEND_TEST_NONE);
+
+ munmap(can_mlock, pin);
+}
+
static void
test_forcewake(int fd, bool hibernate)
{
@@ -199,6 +250,9 @@ igt_main
igt_subtest("sysfs-reader")
test_sysfs_reader(false);
+ igt_subtest("shrink")
+ test_shrink(fd, SUSPEND_STATE_MEM);
+
igt_subtest("forcewake")
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Add warn about unsupported CDCLK rates
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9231_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9231_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9231_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9231_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +1 igt@gem_exec_schedule@deep-render: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9231_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-kbl: PASS -> DMESG-FAIL (fdo#106560) igt@kms_cursor_legacy@flip-vs-cursor-toggle: shard-hsw: PASS -> FAIL (fdo#102670) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) igt@kms_rotation_crc@primary-rotation-270: shard-glk: PASS -> FAIL (fdo#103925, fdo#104724) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS +1 igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@wf_vblank-ts-check: shard-hsw: FAIL (fdo#103928) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9231 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9231: 8586f606e2fc4bf26ffc12a2db5ddf23e62de570 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9231/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table
== Series Details == Series: drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table URL : https://patchwork.freedesktop.org/series/44435/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9235 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44435/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9235 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@gem_exec_flush@basic-wb-rw-before-default: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_busy@basic-flip-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: PASS -> FAIL (fdo#103481) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (38 -> 35) == Additional (1): fi-bdw-5557u Missing(4): fi-byt-squawks fi-ilk-m540 fi-cnl-y3 fi-skl-6700hq == Build changes == * Linux: CI_DRM_4290 -> Patchwork_9235 CI_DRM_4290: fb7bd7a9480b64dd46964ef5a00aeef33410376d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9235: 7347fd680334d350d80b041fb73c2f4bff24552e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7347fd680334 drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9235/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/audio: Add 801Mhz clock entries to dp_aud_n_m table
From: "Sripada, Radhakrishna"
Expand the Maud/Naud table according to DP 1.4 spec to include entries for
810 MHz clock. This is required for audio to work with HBR3.
Cc: Dhinakaran Pandiyan
Cc: Jani Nikula
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_audio.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..6d1c33066987 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -59,6 +59,7 @@
*/
/* DP N/M table */
+#define LC_810M81
#define LC_540M54
#define LC_270M27
#define LC_162M162000
@@ -99,6 +100,15 @@ static const struct dp_aud_n_m dp_aud_n_m[] = {
{ 128000, LC_540M, 4096, 33750 },
{ 176400, LC_540M, 3136, 18750 },
{ 192000, LC_540M, 2048, 11250 },
+ { 32000, LC_810M, 1024, 50625 },
+ { 44100, LC_810M, 784, 28125 },
+ { 48000, LC_810M, 512, 16875 },
+ { 64000, LC_810M, 2048, 50625 },
+ { 88200, LC_810M, 1568, 28125 },
+ { 96000, LC_810M, 1024, 16875 },
+ { 128000, LC_810M, 4096, 50625 },
+ { 176400, LC_810M, 3136, 28125 },
+ { 192000, LC_810M, 2048, 16875 },
};
static const struct dp_aud_n_m *
--
2.9.3
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark the GPU as wedged without error on fault injection
== Series Details == Series: drm/i915: Mark the GPU as wedged without error on fault injection URL : https://patchwork.freedesktop.org/series/44411/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9229_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9229_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9229_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9229_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_9229_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) igt@perf_pmu@multi-client-vcs1: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS +1 igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#103928) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9229 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9229: 4e9a90b9748305fa19ae2c2e7d87c2b265c2e741 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9229/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Store first production revid into device info
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9234 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9234 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9234, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44429/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9234: === IGT changes === Possible regressions igt@drv_module_reload@basic-no-display: fi-cfl-s3: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload: fi-cfl-8700k: PASS -> DMESG-WARN +2 fi-cfl-guc: PASS -> DMESG-WARN +2 igt@drv_module_reload@basic-reload-inject: fi-cfl-u2: PASS -> DMESG-WARN +2 == Known issues == Here are the changes found in Patchwork_9234 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (38 -> 36) == Additional (1): fi-bdw-5557u Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4290 -> Patchwork_9234 CI_DRM_4290: fb7bd7a9480b64dd46964ef5a00aeef33410376d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9234: 72eee4b969e95dc17ef223eeece226074e47172a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 72eee4b969e9 drm/i915: Warn on obsolete revision checks 97c198d6616d drm/i915: Remove kbl preproduction workarounds 819a0e8a100a drm/i915: Add a define for first production revid fb0d40cccdf0 drm/i915: Move chipset definitions to intel_chipset.h 8100f915cd3b drm/i915: Use unknown production revid as alpha quality flag ec78e5bf259c drm/i915: Store first production revid into device info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9234/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.17 next-20180607]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Mark-i915-inject_load_failure-as-being-hit/20180607-174849
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/i915_drv.c:61:36: sparse: incorrect type in initializer
>> (different base types) @@expected int static [signed] [toplevel]
>> i915_load_error_level @@got evel] i915_load_error_level @@
drivers/gpu/drm/i915/i915_drv.c:61:36:expected int static [signed]
[toplevel] i915_load_error_level
drivers/gpu/drm/i915/i915_drv.c:61:36:got char *
>> drivers/gpu/drm/i915/i915_drv.c:72:39: sparse: incorrect type in assignment
>> (different base types) @@expected int static [signed] [toplevel]
>> i915_load_error_level @@got evel] i915_load_error_level @@
drivers/gpu/drm/i915/i915_drv.c:72:39:expected int static [signed]
[toplevel] i915_load_error_level
drivers/gpu/drm/i915/i915_drv.c:72:39:got char *
>> drivers/gpu/drm/i915/i915_drv.c:1425:9: sparse: incorrect type in argument 2
>> (different base types) @@expected char const *level @@got int static
>> [signed]char const *level @@
drivers/gpu/drm/i915/i915_drv.c:1425:9:expected char const *level
drivers/gpu/drm/i915/i915_drv.c:1425:9:got int static [signed]
[toplevel] i915_load_error_level
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/resource_ext.h:17,
from include/linux/acpi.h:26,
from drivers/gpu/drm/i915/i915_drv.c:30:
include/linux/kern_levels.h:5:18: warning: initialization makes integer from
pointer without a cast [-Wint-conversion]
#define KERN_SOH "001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
drivers/gpu/drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR'
static int i915_load_error_level = KERN_ERR;
^~~~
include/linux/kern_levels.h:5:18: error: initializer element is not
computable at load time
#define KERN_SOH "001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
drivers/gpu/drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR'
static int i915_load_error_level = KERN_ERR;
^~~~
drivers/gpu/drm/i915/i915_drv.c: In function '__i915_inject_load_failure':
drivers/gpu/drm/i915/i915_drv.c:72:25: warning: assignment makes integer
from pointer without a cast [-Wint-conversion]
i915_load_error_level = KERN_DEBUG;
^
drivers/gpu/drm/i915/i915_drv.c: In function 'i915_driver_load':
drivers/gpu/drm/i915/i915_drv.c:123:26: warning: passing argument 2 of
'__i915_printk' makes pointer from integer without a cast [-Wint-conversion]
__i915_printk(dev_priv, i915_load_error_level, fmt, ##__VA_ARGS__)
^
drivers/gpu/drm/i915/i915_drv.c:1425:2: note: in expansion of macro
'i915_load_error'
i915_load_error(dev_priv, "Device initialization failed (%d)n", ret);
^~~
drivers/gpu/drm/i915/i915_drv.c:87:1: note: expected 'const char *' but
argument is of type 'int'
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
^
vim +61 drivers/gpu/drm/i915/i915_drv.c
58
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60 static unsigned int i915_load_fail_count;
> 61 static int i915_load_error_level = KERN_ERR;
62
63 bool __i915_inject_load_failure(const char *func, int line)
64 {
65 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
66 return false;
67
68 if (++i915_load_fail_count ==
i915_modparams.inject_load_failure) {
69 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
70 i915_modparams.inject_load_failure, func,
line);
71 i915_modparams.inject_load_failure = 0;
&g
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Store first production revid into device info
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Store first production revid into device info -drivers/gpu/drm/i915/selftests/../i915_drv.h:3669:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void) Commit: drm/i915: Use unknown production revid as alpha quality flag -drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) Commit: drm/i915: Move chipset definitions to intel_chipset.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3477:16: warning: expression using sizeof(void) Commit: drm/i915: Add a define for first production revid Okay! Commit: drm/i915: Remove kbl preproduction workarounds Okay! Commit: drm/i915: Warn on obsolete revision checks Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Store first production revid into device info
== Series Details == Series: series starting with [1/6] drm/i915: Store first production revid into device info URL : https://patchwork.freedesktop.org/series/44429/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec78e5bf259c drm/i915: Store first production revid into device info -:59: WARNING:LONG_LINE: line over 100 characters #59: FILE: drivers/gpu/drm/i915/i915_drv.h:2435: +#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))) -:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #59: FILE: drivers/gpu/drm/i915/i915_drv.h:2435: +#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))) total: 0 errors, 1 warnings, 1 checks, 94 lines checked 8100f915cd3b drm/i915: Use unknown production revid as alpha quality flag fb0d40cccdf0 drm/i915: Move chipset definitions to intel_chipset.h -:231: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #231: new file mode 100644 -:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 's' - possible side-effects? #252: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e' - possible side-effects? #252: FILE: drivers/gpu/drm/i915/intel_chipset.h:17: +#define INTEL_GEN_MASK(s, e) ( \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ + BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -:272: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #272: FILE: drivers/gpu/drm/i915/intel_chipset.h:37: +#define IS_REVID(p, since, until) \ + (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #289: FILE: drivers/gpu/drm/i915/intel_chipset.h:54: +#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -:296: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #296: FILE: drivers/gpu/drm/i915/intel_chipset.h:61: +#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ +(dev_priv)->info.gt == 1) -:310: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #310: FILE: drivers/gpu/drm/i915/intel_chipset.h:75: +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -:312: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #312: FILE: drivers/gpu/drm/i915/intel_chipset.h:77: +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ +((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -:317: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #317: FILE: drivers/gpu/drm/i915/intel_chipset.h:82: +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -:319: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #319: FILE: drivers/gpu/drm/i915/intel_chipset.h:84: +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:321: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #321: FILE: drivers/gpu/drm/i915/intel_chipset.h:86: +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) -:323: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #323: FILE: drivers/gpu/drm/i915/intel_chipset.h:88: +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ +(dev_priv)->info.gt == 3) -:326: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #326: FILE: drivers/gpu/drm/i915/intel_chipset.h:91: +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ +INTEL_DEVID(dev_priv) == 0x0A1E) -:328: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #328: FILE: drivers/gpu/drm/i915/intel_chipset.h:93: +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ +INTEL_DEVID(dev_priv) == 0x1913 || \ +
[Intel-gfx] ✓ Fi.CI.IGT: success for Queued/runnable/running engine stats (rev14)
== Series Details == Series: Queued/runnable/running engine stats (rev14) URL : https://patchwork.freedesktop.org/series/36926/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9228_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9228_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9228_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9228_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +1 igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_9228_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) shard-glk: NOTRUN -> DMESG-FAIL (fdo#106560) igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#106509) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105189) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS +1 igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#103928) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc: shard-glk: FAIL (fdo#103167, fdo#104724) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9228 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9228: a0bcb68e7c4dfe1f5eeadd5b5aa3c5b63a97b67d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9228/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Cancel reset preparations on failed resets (rev2) URL : https://patchwork.freedesktop.org/series/44288/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4290 -> Patchwork_9233 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9233 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9233, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44288/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9233: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9233 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: PASS -> FAIL (fdo#103481) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (38 -> 36) == Additional (1): fi-bdw-5557u Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4290 -> Patchwork_9233 CI_DRM_4290: fb7bd7a9480b64dd46964ef5a00aeef33410376d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4510: d1a93aa7e1507de76c6c71be15931cc4b90111bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9233: ed692445602e01cd5e11ac97572f2e98c354db65 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ed692445602e drm/i915: Add WaKBLVECSSemaphoreWaitPoll 41fcfbcc5c48 drm/i915: Cancel reset preparations on failed resets == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9233/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915: Add a define for first production revid
Make a new named define for each platform which signifies
the first production revid that platform has. Placing
it along the revision ids adds clarity.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 8
drivers/gpu/drm/i915/intel_chipset.h | 3 +++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 850ed40724e2..538f05a7014b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -465,7 +465,7 @@ static const struct intel_device_info intel_cherryview_info
= {
#define SKL_PLATFORM \
GEN9_FEATURES, \
- .first_product_revid = SKL_REVID_G0, \
+ .first_product_revid = SKL_REVID_PRODUCT, \
PLATFORM(INTEL_SKYLAKE)
static const struct intel_device_info intel_skylake_gt1_info = {
@@ -528,7 +528,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .first_product_revid = BXT_REVID_C0,
+ .first_product_revid = BXT_REVID_PRODUCT,
.ddb_size = 512,
};
@@ -542,7 +542,7 @@ static const struct intel_device_info intel_geminilake_info
= {
#define KBL_PLATFORM \
GEN9_FEATURES, \
PLATFORM(INTEL_KABYLAKE), \
- .first_product_revid = KBL_REVID_B0
+ .first_product_revid = KBL_REVID_PRODUCT
static const struct intel_device_info intel_kabylake_gt1_info = {
KBL_PLATFORM,
@@ -563,7 +563,7 @@ static const struct intel_device_info
intel_kabylake_gt3_info = {
#define CFL_PLATFORM \
GEN9_FEATURES, \
PLATFORM(INTEL_COFFEELAKE), \
- .first_product_revid = KBL_REVID_B0
+ .first_product_revid = KBL_REVID_PRODUCT
static const struct intel_device_info intel_coffeelake_gt1_info = {
CFL_PLATFORM,
diff --git a/drivers/gpu/drm/i915/intel_chipset.h
b/drivers/gpu/drm/i915/intel_chipset.h
index 76b5ff1b7131..d6cd7ba7d669 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -137,6 +137,7 @@
#define SKL_REVID_E0 0x4
#define SKL_REVID_F0 0x5
#define SKL_REVID_G0 0x6
+#define SKL_REVID_PRODUCT SKL_REVID_G0
#define SKL_REVID_H0 0x7
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
@@ -146,12 +147,14 @@
#define BXT_REVID_B0 0x3
#define BXT_REVID_B_LAST 0x8
#define BXT_REVID_C0 0x9
+#define BXT_REVID_PRODUCT BXT_REVID_C0
#define IS_BXT_REVID(dev_priv, since, until) \
(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
+#define KBL_REVID_PRODUCT KBL_REVID_B0
#define KBL_REVID_C0 0x2
#define KBL_REVID_D0 0x3
#define KBL_REVID_E0 0x4
--
2.17.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Move chipset definitions to intel_chipset.h
Carve out chipset definitions into new intel_chipset.h Suggested-by: Chris Wilson Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 200 +- drivers/gpu/drm/i915/intel_chipset.h | 208 +++ 2 files changed, 209 insertions(+), 199 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_chipset.h diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f7f6aaddba30..87de072e44cb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -59,6 +59,7 @@ #include "intel_bios.h" #include "intel_device_info.h" +#include "intel_chipset.h" #include "intel_display.h" #include "intel_dpll_mgr.h" #include "intel_lrc.h" @@ -2309,205 +2310,6 @@ intel_info(const struct drm_i915_private *dev_priv) #define INTEL_INFO(dev_priv) intel_info((dev_priv)) -#define INTEL_GEN(dev_priv)((dev_priv)->info.gen) -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) - -#define REVID_FOREVER 0xff -#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) - -#define GEN_FOREVER (0) - -#define INTEL_GEN_MASK(s, e) ( \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ - BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ - GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ - (s) != GEN_FOREVER ? (s) - 1 : 0) \ -) - -/* - * Returns true if Gen is in inclusive range [Start, End]. - * - * Use GEN_FOREVER for unbound start and or end. - */ -#define IS_GEN(dev_priv, s, e) \ - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e - -/* - * Return true if revision is in range [since,until] inclusive. - * - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. - */ -#define IS_REVID(p, since, until) \ - (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) - -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) - -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) -#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001) -#define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ -(dev_priv)->info.gt == 1) -#define IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile) -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ -((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -/* ULX machines are also considered ULT. */ -#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ -(INTEL_DEVID(dev_priv) & 0xf) == 0xe) -#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ -
[Intel-gfx] [PATCH 6/6] drm/i915: Warn on obsolete revision checks
If we are doing revision checks against a preproduction
range, when there is already a product, it is a sign
that there is code to be removed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_chipset.h | 30 +---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_chipset.h
b/drivers/gpu/drm/i915/intel_chipset.h
index d6cd7ba7d669..3f38b052863e 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -130,6 +130,12 @@
#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
#define IS_ALPHA_SUPPORT(intel_info)(FIRST_PRODUCT_REVID(intel_info) ==
PRODUCT_REVID_UNKNOWN)
+#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
+ BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
+(revid) < (production_revid)); \
+ 1; \
+ })
+
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
#define SKL_REVID_C0 0x2
@@ -140,7 +146,9 @@
#define SKL_REVID_PRODUCT SKL_REVID_G0
#define SKL_REVID_H0 0x7
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
+#define IS_SKL_REVID(p, since, until) \
+ (BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
+IS_SKYLAKE(p) && IS_REVID(p, since, until))
#define BXT_REVID_A0 0x0
#define BXT_REVID_A1 0x1
@@ -150,7 +158,8 @@
#define BXT_REVID_PRODUCT BXT_REVID_C0
#define IS_BXT_REVID(dev_priv, since, until) \
- (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, BXT_REVID_PRODUCT) && \
+IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
@@ -160,32 +169,39 @@
#define KBL_REVID_E0 0x4
#define IS_KBL_REVID(dev_priv, since, until) \
- (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, KBL_REVID_PRODUCT) && \
+IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
#define GLK_REVID_A0 0x0
#define GLK_REVID_A1 0x1
#define GLK_REVID_B0 0x3
+#define GLK_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
-#define IS_GLK_REVID(dev_priv, since, until) \
- (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+#define IS_GLK_REVID(dev_priv, since, until) \
+ (BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
+IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
#define CNL_REVID_A0 0x0
#define CNL_REVID_B0 0x1
#define CNL_REVID_C0 0x2
#define CNL_REVID_D0 0x4
#define CNL_REVID_G0 0x5
+#define CNL_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
#define IS_CNL_REVID(p, since, until) \
- (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, CNL_REVID_PRODUCT) && \
+IS_CANNONLAKE(p) && IS_REVID(p, since, until))
#define ICL_REVID_A0 0x0
#define ICL_REVID_A2 0x1
#define ICL_REVID_B0 0x3
#define ICL_REVID_B2 0x4
#define ICL_REVID_C0 0x5
+#define ICL_REVID_PRODUCT PRODUCT_REVID_UNKNOWN
#define IS_ICL_REVID(p, since, until) \
- (IS_ICELAKE(p) && IS_REVID(p, since, until))
+ (BUILD_BUG_ON_REVID_LT(until, ICL_REVID_PRODUCT) && \
+ IS_ICELAKE(p) && IS_REVID(p, since, until))
/*
* The genX designation typically refers to the render engine, so render
--
2.17.0
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[Intel-gfx] [PATCH 2/6] drm/i915: Use unknown production revid as alpha quality flag
We don't need to have distinct flag for alpha quality if
we agree that setting the first production revid to be the
epoch for stepping out from alpha quality on that platform.
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Tomi Sarvela
Cc: Jani Nikula
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 5 -
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 92f244c12f1e..11dc9b6371e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -857,8 +857,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_HSW_EARLY_SDV(dev_priv);
pre |= IS_PREPRODUCTION_HW(dev_priv);
- if (pre && FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))
- != PRODUCT_REVID_UNKNOWN) {
+ if (pre && !IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv))) {
DRM_ERROR("This is a pre-production stepping. "
"It may not be fully functional.\n");
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index abca814ad758..f7f6aaddba30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2428,11 +2428,10 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x0004) ==
0x0004)
-#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
-
#define PRODUCT_REVID_UNKNOWN REVID_FOREVER
#define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+#define IS_ALPHA_SUPPORT(intel_info)(FIRST_PRODUCT_REVID(intel_info) ==
PRODUCT_REVID_UNKNOWN)
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 823668e35f41..850ed40724e2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -603,7 +603,6 @@ static const struct intel_device_info intel_cannonlake_info
= {
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
- .is_alpha_support = 1,
.has_resource_streamer = 0,
.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 9ae9dc553192..3147adf8b070 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -77,7 +77,6 @@ enum intel_platform {
#define DEV_INFO_FOR_EACH_FLAG(func) \
func(is_mobile); \
func(is_lp); \
- func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_aliasing_ppgtt); \
@@ -155,6 +154,10 @@ struct intel_device_info {
* Do not set first product revid unless you are certain
* that testing infrastructure is already on top of production
* revid machines.
+*
+* When set to an actual released first product revision id,
+* IS_ALPHA_SUPPORT macro will start to return false on that
+* platform.
*/
u8 gen;
--
2.17.0
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[Intel-gfx] [PATCH 1/6] drm/i915: Store first production revid into device info
Store first known production revid into the device info.
By doing this we then can do preliminary hardware
checks in code and also prepare to complain automatically
on outdated workarounds etc.
Uninitialized (zero) product revision id means that
there are no known preliminary hardware for this platform,
or that the platform is of gen that we don't care.
This is all pre gen9 platforms.
Unknown product revision maps to REVID_FOREVER on a
gen9+ platforms on default. When the platform
gets the first production revision and our testing
infra is cleaned from preproduction hardware, we can
set a first production revid. At that point we start
to complain about running driver on preliminary hardware.
Suggested-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Tomi Sarvela
Cc: Jani Nikula
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_pci.c | 9 +++--
drivers/gpu/drm/i915/intel_device_info.h | 11 +++
4 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index be71fdf8d92e..92f244c12f1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -855,10 +855,10 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
bool pre = false;
pre |= IS_HSW_EARLY_SDV(dev_priv);
- pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
- pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
+ pre |= IS_PREPRODUCTION_HW(dev_priv);
- if (pre) {
+ if (pre && FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv))
+ != PRODUCT_REVID_UNKNOWN) {
DRM_ERROR("This is a pre-production stepping. "
"It may not be fully functional.\n");
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4073666f1ca..abca814ad758 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2430,6 +2430,10 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
+#define PRODUCT_REVID_UNKNOWN REVID_FOREVER
+#define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
+#define IS_PREPRODUCTION_HW(dev_priv) (INTEL_REVID(dev_priv) <
FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
#define SKL_REVID_C0 0x2
@@ -2461,6 +2465,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define GLK_REVID_A0 0x0
#define GLK_REVID_A1 0x1
+#define GLK_REVID_B0 0x3
#define IS_GLK_REVID(dev_priv, since, until) \
(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
@@ -2468,6 +2473,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define CNL_REVID_A0 0x0
#define CNL_REVID_B0 0x1
#define CNL_REVID_C0 0x2
+#define CNL_REVID_D0 0x4
+#define CNL_REVID_G0 0x5
#define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97a91e6af7e3..823668e35f41 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -465,6 +465,7 @@ static const struct intel_device_info intel_cherryview_info
= {
#define SKL_PLATFORM \
GEN9_FEATURES, \
+ .first_product_revid = SKL_REVID_G0, \
PLATFORM(INTEL_SKYLAKE)
static const struct intel_device_info intel_skylake_gt1_info = {
@@ -518,6 +519,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_reset_engine = 1, \
.has_snoop = true, \
.has_ipc = 1, \
+ .first_product_revid = PRODUCT_REVID_UNKNOWN, \
GEN9_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS, \
@@ -526,6 +528,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
+ .first_product_revid = BXT_REVID_C0,
.ddb_size = 512,
};
@@ -538,7 +541,8 @@ static const struct intel_device_info intel_geminilake_info
= {
#define KBL_PLATFORM \
GEN9_FEATURES, \
- PLATFORM(INTEL_KABYLAKE)
+ PLATFORM(INTEL_KABYLAKE), \
+ .first_product_revid = KBL_REVID_B0
static const struct intel_device_info intel_kabylake_gt1_info = {
KBL_PLATFORM,
@@ -558,7 +562,8 @@ static const struct intel_device_info
intel_kabylake_gt3_info = {
#define CFL_PLATFORM \
GEN9_FEATURES, \
- PLATFORM(INTEL_COFFEELAKE)
+ PLATFORM(INTEL_COFFEELAKE), \
+ .first_product_revid = KBL_REVID_B0
[Intel-gfx] [PATCH 5/6] drm/i915: Remove kbl preproduction workarounds
We don't need kbl preprod workarounds anymore.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 12
drivers/gpu/drm/i915/intel_workarounds.c | 5 -
2 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 091e28f0e024..ffec91cdb1b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1581,18 +1581,6 @@ static u32 *gen9_init_indirectctx_bb(struct
intel_engine_cs *engine, u32 *batch)
GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
*batch++ = MI_NOOP;
- /* WaClearSlmSpaceAtContextSwitch:kbl */
- /* Actual scratch location is at 128 bytes offset */
- if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
- batch = gen8_emit_pipe_control(batch,
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_QW_WRITE,
- i915_ggtt_offset(engine->scratch)
- + 2 * CACHELINE_BYTES);
- }
-
/* WaMediaPoolStateCmdInWABB:bxt,glk */
if (HAS_POOLED_EU(engine->i915)) {
/*
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index b1ab56a1ec31..9df30d6cff30 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -355,11 +355,6 @@ static int kbl_ctx_workarounds_init(struct
drm_i915_private *dev_priv)
if (ret)
return ret;
- /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
- if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FENCE_DEST_SLM_DISABLE);
-
/* WaToEnableHwFixForPushConstHWBug:kbl */
if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
--
2.17.0
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[Intel-gfx] [PATCH 2/2] drm/i915: Add WaKBLVECSSemaphoreWaitPoll
There is a problem with kbl up to rev E0 where a heavy
memory/fabric traffic from adjacent engine(s) can cause an engine
reset to fail. This traffic can be from normal memory accesses
or it can be from heavy polling on a semaphore wait.
For engine hogging causing a fail, we already fallback to
full reset. Which effectively stops all engines and thus
we only add a workaround documentation.
For the semaphore wait loop poll case, we add one microsecond
poll interval to semaphore wait to guarantee bandwidth for
the reset preration. The side effect is that we make semaphore
completion latencies also 1us longer.
v2: Let full reset handle the adjacent engine idling (Chris)
v3: Skip render engine (Joonas), please checkpatch on define (Mika)
References: https://bugs.freedesktop.org/show_bug.cgi?id=106684
References: VTHSD#2227190, HSDES#1604216706, BSID#0917
Cc: Joonas Lahtinen
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Acked-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 13 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0317bde3aab..987def26ce82 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2242,6 +2242,7 @@ enum i915_power_well_id {
#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
#define RESET_CTL_REQUEST_RESET (1 << 0)
#define RESET_CTL_READY_TO_RESET (1 << 1)
+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index bb03f6d8b3d1..b892ca8396e8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2174,6 +2174,8 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv,
unsigned engine_mask)
* Thus assume it is best to stop engines on all gens
* where we have a gpu reset.
*
+* WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
+*
* WaMediaResetMainRingCleanup:ctg,elk (presumably)
*
* FIXME: Wa for more modern gens needs to be validated
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index b1ab56a1ec31..24b929ce3341 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -666,6 +666,19 @@ static void kbl_gt_workarounds_apply(struct
drm_i915_private *dev_priv)
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaKBLVECSSemaphoreWaitPoll:kbl */
+ if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_E0)) {
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+
+ for_each_engine(engine, dev_priv, tmp) {
+ if (engine->id == RCS)
+ continue;
+
+ I915_WRITE(RING_SEMA_WAIT_POLL(engine->mmio_base), 1);
+ }
+ }
}
static void glk_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
2.17.0
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates
On Thu, Jun 07, 2018 at 08:01:14PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote:
> > While checking workarounds related to the CDCLK PLL, I noticed that the
> > DMC firmware bits for WA#1183 are missing for SKL. After that I
> > clarified with HW people that it's not needed on SKL, since it doesn't
> > support eDP1.4 which would be the only thing requiring the problematic
> > CDCLK clock rates. So in theory we shouldn't ever choose these
> > frequencies, but add an assert in any case for catching such cases and
> > for documentation.
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_cdclk.c | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 704ddb4d3ca7..71045c38e233 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> > */
> > cdclk = skl_calc_cdclk(min_cdclk, vco);
> >
> > + /*
> > +* The following CDCLK rates are unsupported on SKL. In theory this
> > +* should never happen since only the eDP1.4 2.16 and 4.32Gbps rates
> > +* require it, but eDP1.4 is not supported on SKL, see display
> > +* WA#1183.
> > +*/
> > + if (IS_SKYLAKE(to_i915(state->dev)) &&
> > + (cdclk == 308571 || cdclk == 617143))
> > + DRM_WARN_ONCE("Unsupported CDCLK rate.\n");
>
> Or just WARN(vco == 864) in eg. skl_set_cdclk()?
Ok, can move it there. cdclk==432MHz is not specifically disallowed, so
wouldn't checking cdclk be clearer? Even if it's not used atm.
> > +
> > intel_state->cdclk.logical.vco = vco;
> > intel_state->cdclk.logical.cdclk = cdclk;
> > intel_state->cdclk.logical.voltage_level =
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9232 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9232 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9232, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44417/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9232: === IGT changes === Warnings igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9232 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@gem_exec_suspend@basic-s4-devices: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) igt@kms_frontbuffer_tracking@basic: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@gem_exec_suspend@basic-s3: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: FAIL (fdo#103481) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (40 -> 36) == Missing(4): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq fi-hsw-4200u == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9232 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9232: 76562cc5e78b8144582bd5ab2d4697a4936cd277 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 76562cc5e78b drm/i915/gtt: Push allocation to hw ppgtt constructor f96fdf964e6b drm/i915: Decouple vma vfuncs from vm 14b9c0e8ab72 drm/i915: Prepare for non-object vma == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9232/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates
On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote:
> While checking workarounds related to the CDCLK PLL, I noticed that the
> DMC firmware bits for WA#1183 are missing for SKL. After that I
> clarified with HW people that it's not needed on SKL, since it doesn't
> support eDP1.4 which would be the only thing requiring the problematic
> CDCLK clock rates. So in theory we shouldn't ever choose these
> frequencies, but add an assert in any case for catching such cases and
> for documentation.
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 704ddb4d3ca7..71045c38e233 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct
> drm_atomic_state *state)
>*/
> cdclk = skl_calc_cdclk(min_cdclk, vco);
>
> + /*
> + * The following CDCLK rates are unsupported on SKL. In theory this
> + * should never happen since only the eDP1.4 2.16 and 4.32Gbps rates
> + * require it, but eDP1.4 is not supported on SKL, see display
> + * WA#1183.
> + */
> + if (IS_SKYLAKE(to_i915(state->dev)) &&
> + (cdclk == 308571 || cdclk == 617143))
> + DRM_WARN_ONCE("Unsupported CDCLK rate.\n");
Or just WARN(vco == 864) in eg. skl_set_cdclk()?
> +
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> intel_state->cdclk.logical.voltage_level =
> --
> 2.13.2
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] RFT mm/oomkill: Don't skip the reaper
Quoting Chris Wilson (2018-05-29 10:55:28) > If we find a task that has already been selected for reaping, consider > that it may still free some memory. Currently, we skip such tasks > believing that we've already extracted as memory free pages as possible > from before hitting a livelock. In practice, at least on single user > systems deliberating exercising oom, such processes have only begun to > recover their pages and are still the worst hogs on the system. If we > skip them, we just select yet more victims, and with sufficient > enthusiasm may end up with all available processes marked for reaping, > panicking in the process. > > Signed-off-by: Chris Wilson > Cc: Michał Winiarski I've stuck this in this topic/core-for-CI for further testing and so we can make some progress on the mlock failures in igt. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2)
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma (rev2) URL : https://patchwork.freedesktop.org/series/44417/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Prepare for non-object vma Okay! Commit: drm/i915: Decouple vma vfuncs from vm Okay! Commit: drm/i915/gtt: Push allocation to hw ppgtt constructor -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Add warn about unsupported CDCLK rates
== Series Details == Series: drm/i915/icl: Add warn about unsupported CDCLK rates URL : https://patchwork.freedesktop.org/series/44421/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9231 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9231 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9231, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44421/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9231: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9231 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_switch@basic-default: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: fi-glk-j4005: PASS -> FAIL (fdo#106765) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106765 https://bugs.freedesktop.org/show_bug.cgi?id=106765 == Participating hosts (40 -> 35) == Missing(5): fi-hsw-4770 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq fi-hsw-4200u == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9231 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9231: 8586f606e2fc4bf26ffc12a2db5ddf23e62de570 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8586f606e2fc drm/i915/icl: Add warn about unsupported CDCLK rates == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9231/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gtt: Push allocation to hw ppgtt constructor
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the
two different generations of hw ppgtt stucts to be of different size,
push the allocation down to the constructor.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
s/kmalloc/kzalloc/
The fixup had slipped into a later patch ("drm/i915/gtt: Subclass
gen6_hw_ppgtt")
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 140 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 16 +-
2 files changed, 83 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 24287cbecfdd..6ac6520b6e9c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1562,32 +1562,36 @@ static int gen8_preallocate_top_level_pdp(struct
i915_hw_ppgtt *ppgtt)
* space.
*
*/
-static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
{
- struct i915_address_space *vm = >vm;
- struct drm_i915_private *dev_priv = vm->i915;
- int ret;
+ struct i915_hw_ppgtt *ppgtt;
+ int err;
+
+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+ if (!ppgtt)
+ return ERR_PTR(-ENOMEM);
- ppgtt->vm.total = USES_FULL_48BIT_PPGTT(dev_priv) ?
+ ppgtt->vm.i915 = i915;
+ ppgtt->vm.dma = >drm.pdev->dev;
+
+ ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
1ULL << 48 :
1ULL << 32;
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
ppgtt->vm.pt_kmap_wc = true;
- ret = gen8_init_scratch(>vm);
- if (ret) {
- ppgtt->vm.total = 0;
- return ret;
- }
+ err = gen8_init_scratch(>vm);
+ if (err)
+ goto err_free;
- if (use_4lvl(vm)) {
- ret = setup_px(>vm, >pml4);
- if (ret)
- goto free_scratch;
+ if (use_4lvl(>vm)) {
+ err = setup_px(>vm, >pml4);
+ if (err)
+ goto err_scratch;
gen8_initialize_pml4(>vm, >pml4);
@@ -1595,15 +1599,15 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
} else {
- ret = __pdp_init(>vm, >pdp);
- if (ret)
- goto free_scratch;
+ err = __pdp_init(>vm, >pdp);
+ if (err)
+ goto err_scratch;
- if (intel_vgpu_active(dev_priv)) {
- ret = gen8_preallocate_top_level_pdp(ppgtt);
- if (ret) {
+ if (intel_vgpu_active(i915)) {
+ err = gen8_preallocate_top_level_pdp(ppgtt);
+ if (err) {
__pdp_fini(>pdp);
- goto free_scratch;
+ goto err_scratch;
}
}
@@ -1612,7 +1616,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
}
- if (intel_vgpu_active(dev_priv))
+ if (intel_vgpu_active(i915))
gen8_ppgtt_notify_vgt(ppgtt, true);
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
@@ -1623,11 +1627,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->vm.vma_ops.clear_pages = clear_pages;
- return 0;
+ return ppgtt;
-free_scratch:
+err_scratch:
gen8_free_scratch(>vm);
- return ret;
+err_free:
+ kfree(ppgtt);
+ return ERR_PTR(err);
}
static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
@@ -1638,8 +1644,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
u32 pd_entry, pte, pde;
u32 start = 0, length = ppgtt->vm.total;
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
-I915_CACHE_LLC, 0);
+ scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
gen6_for_each_pde(unused, >pd, start, length, pde) {
u32 expected;
@@ -2027,36 +2032,41 @@ static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt,
ppgtt->pd.page_table[pde] = ppgtt->vm.scratch_pt;
}
-static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
-
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Prepare for non-object vma
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma URL : https://patchwork.freedesktop.org/series/44417/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9230 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9230 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9230, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44417/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9230: === IGT changes === Possible regressions igt@core_auth@basic-auth: fi-ivb-3520m: PASS -> INCOMPLETE fi-hsw-4200u: PASS -> INCOMPLETE fi-hsw-4770:PASS -> INCOMPLETE fi-ivb-3770:PASS -> INCOMPLETE fi-snb-2600:PASS -> INCOMPLETE fi-hsw-4770r: PASS -> INCOMPLETE Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9230 that come from known issues: === IGT changes === Issues hit igt@core_auth@basic-auth: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) fi-byt-n2820: PASS -> INCOMPLETE (fdo#102657) igt@gem_exec_gttfill@basic: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) +1 igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) Possible fixes igt@gem_exec_suspend@basic-s3: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: FAIL (fdo#103481) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (40 -> 36) == Missing(4): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9230 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9230: cfd175e0b834b4b6b5c256102b30a75289ad3881 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cfd175e0b834 drm/i915/gtt: Push allocation to hw ppgtt constructor 79f0386bc850 drm/i915: Decouple vma vfuncs from vm a57eedbfbcc9 drm/i915: Prepare for non-object vma == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9230/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Add warn about unsupported CDCLK rates
While checking workarounds related to the CDCLK PLL, I noticed that the
DMC firmware bits for WA#1183 are missing for SKL. After that I
clarified with HW people that it's not needed on SKL, since it doesn't
support eDP1.4 which would be the only thing requiring the problematic
CDCLK clock rates. So in theory we shouldn't ever choose these
frequencies, but add an assert in any case for catching such cases and
for documentation.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_cdclk.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 704ddb4d3ca7..71045c38e233 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct
drm_atomic_state *state)
*/
cdclk = skl_calc_cdclk(min_cdclk, vco);
+ /*
+* The following CDCLK rates are unsupported on SKL. In theory this
+* should never happen since only the eDP1.4 2.16 and 4.32Gbps rates
+* require it, but eDP1.4 is not supported on SKL, see display
+* WA#1183.
+*/
+ if (IS_SKYLAKE(to_i915(state->dev)) &&
+ (cdclk == 308571 || cdclk == 617143))
+ DRM_WARN_ONCE("Unsupported CDCLK rate.\n");
+
intel_state->cdclk.logical.vco = vco;
intel_state->cdclk.logical.cdclk = cdclk;
intel_state->cdclk.logical.voltage_level =
--
2.13.2
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Prepare for non-object vma
== Series Details == Series: series starting with [CI,1/3] drm/i915: Prepare for non-object vma URL : https://patchwork.freedesktop.org/series/44417/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Prepare for non-object vma Okay! Commit: drm/i915: Decouple vma vfuncs from vm Okay! Commit: drm/i915/gtt: Push allocation to hw ppgtt constructor -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915: Prepare for non-object vma
In order to allow ourselves to use VMA to wrap other entities other than
GEM objects, we need to allow for the vma->obj backpointer to be NULL.
In most cases, we know we are operating on a GEM object and its vma, but
we need the core code (such as i915_vma_pin/insert/bind/unbind) to work
regardless of the innards.
The remaining eyesore here is vma->obj->cache_level and related (but
less of an issue) vma->obj->gt_ro. With a bit of care we should mirror
those on the vma itself.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +
drivers/gpu/drm/i915/i915_vma.c | 96 ---
drivers/gpu/drm/i915/i915_vma.h | 2 +-
4 files changed, 65 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 284ae9574f03..7d527b569d28 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3588,8 +3588,11 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
if (!i915_vma_unbind(vma))
continue;
- WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
- WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
+ WARN_ON(i915_vma_bind(vma,
+ obj ? obj->cache_level : 0,
+ PIN_UPDATE));
+ if (obj)
+ WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
}
ggtt->vm.closed = false;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 758234d20f4e..df524c9cad40 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1050,6 +1050,9 @@ static u32 capture_error_bo(struct drm_i915_error_buffer
*err,
int i = 0;
list_for_each_entry(vma, head, vm_link) {
+ if (!vma->obj)
+ continue;
+
if (pinned_only && !i915_vma_is_pinned(vma))
continue;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 912f16ffe7ee..b71265066cd1 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -345,7 +345,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
void i915_vma_unpin_iomap(struct i915_vma *vma)
{
- lockdep_assert_held(>obj->base.dev->struct_mutex);
+ lockdep_assert_held(>vm->i915->drm.struct_mutex);
GEM_BUG_ON(vma->iomap == NULL);
@@ -365,6 +365,7 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma)
return;
obj = vma->obj;
+ GEM_BUG_ON(!obj);
i915_vma_unpin(vma);
i915_vma_close(vma);
@@ -489,7 +490,7 @@ static int
i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *dev_priv = vma->vm->i915;
- struct drm_i915_gem_object *obj = vma->obj;
+ unsigned int cache_level;
u64 start, end;
int ret;
@@ -524,16 +525,21 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
* attempt to find space.
*/
if (size > end) {
- DRM_DEBUG("Attempting to bind an object larger than the
aperture: request=%llu [object=%zd] > %s aperture=%llu\n",
- size, obj->base.size,
- flags & PIN_MAPPABLE ? "mappable" : "total",
+ DRM_DEBUG("Attempting to bind an object larger than the
aperture: request=%llu > %s aperture=%llu\n",
+ size, flags & PIN_MAPPABLE ? "mappable" : "total",
end);
return -ENOSPC;
}
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- return ret;
+ if (vma->obj) {
+ ret = i915_gem_object_pin_pages(vma->obj);
+ if (ret)
+ return ret;
+
+ cache_level = vma->obj->cache_level;
+ } else {
+ cache_level = 0;
+ }
GEM_BUG_ON(vma->pages);
@@ -550,7 +556,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
ret = i915_gem_gtt_reserve(vma->vm, >node,
- size, offset, obj->cache_level,
+ size, offset, cache_level,
flags);
if (ret)
goto err_clear;
@@ -589,7 +595,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
ret = i915_gem_gtt_insert(vma->vm, >node,
- size, alignment,
[Intel-gfx] [CI 3/3] drm/i915/gtt: Push allocation to hw ppgtt constructor
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the
two different generations of hw ppgtt stucts to be of different size,
push the allocation down to the constructor.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 140 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 16 +-
2 files changed, 83 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 24287cbecfdd..20173e1d0472 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1562,32 +1562,36 @@ static int gen8_preallocate_top_level_pdp(struct
i915_hw_ppgtt *ppgtt)
* space.
*
*/
-static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
{
- struct i915_address_space *vm = >vm;
- struct drm_i915_private *dev_priv = vm->i915;
- int ret;
+ struct i915_hw_ppgtt *ppgtt;
+ int err;
+
+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+ if (!ppgtt)
+ return ERR_PTR(-ENOMEM);
+
+ ppgtt->vm.i915 = i915;
+ ppgtt->vm.dma = >drm.pdev->dev;
- ppgtt->vm.total = USES_FULL_48BIT_PPGTT(dev_priv) ?
+ ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
1ULL << 48 :
1ULL << 32;
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
ppgtt->vm.pt_kmap_wc = true;
- ret = gen8_init_scratch(>vm);
- if (ret) {
- ppgtt->vm.total = 0;
- return ret;
- }
+ err = gen8_init_scratch(>vm);
+ if (err)
+ goto err_free;
- if (use_4lvl(vm)) {
- ret = setup_px(>vm, >pml4);
- if (ret)
- goto free_scratch;
+ if (use_4lvl(>vm)) {
+ err = setup_px(>vm, >pml4);
+ if (err)
+ goto err_scratch;
gen8_initialize_pml4(>vm, >pml4);
@@ -1595,15 +1599,15 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
} else {
- ret = __pdp_init(>vm, >pdp);
- if (ret)
- goto free_scratch;
+ err = __pdp_init(>vm, >pdp);
+ if (err)
+ goto err_scratch;
- if (intel_vgpu_active(dev_priv)) {
- ret = gen8_preallocate_top_level_pdp(ppgtt);
- if (ret) {
+ if (intel_vgpu_active(i915)) {
+ err = gen8_preallocate_top_level_pdp(ppgtt);
+ if (err) {
__pdp_fini(>pdp);
- goto free_scratch;
+ goto err_scratch;
}
}
@@ -1612,7 +1616,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
}
- if (intel_vgpu_active(dev_priv))
+ if (intel_vgpu_active(i915))
gen8_ppgtt_notify_vgt(ppgtt, true);
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
@@ -1623,11 +1627,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->vm.vma_ops.clear_pages = clear_pages;
- return 0;
+ return ppgtt;
-free_scratch:
+err_scratch:
gen8_free_scratch(>vm);
- return ret;
+err_free:
+ kfree(ppgtt);
+ return ERR_PTR(err);
}
static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
@@ -1638,8 +1644,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
u32 pd_entry, pte, pde;
u32 start = 0, length = ppgtt->vm.total;
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
-I915_CACHE_LLC, 0);
+ scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
gen6_for_each_pde(unused, >pd, start, length, pde) {
u32 expected;
@@ -2027,36 +2032,41 @@ static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt,
ppgtt->pd.page_table[pde] = ppgtt->vm.scratch_pt;
}
-static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
- struct drm_i915_private *dev_priv = ppgtt->vm.i915;
- struct i915_ggtt *ggtt = _priv->ggtt;
- int
[Intel-gfx] [CI 2/3] drm/i915: Decouple vma vfuncs from vm
To allow for future non-object backed vma, we need to be able to
specialise the callbacks for binding, et al, the vma. For example,
instead of calling vma->vm->bind_vma(), we now call
vma->ops->bind_vma(). This gives us the opportunity to later override the
operation for a custom vma.
v2: flip order of unbind/bind
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 57 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 27 +++
drivers/gpu/drm/i915/i915_vma.c | 11 +++--
drivers/gpu/drm/i915/i915_vma.h | 1 +
drivers/gpu/drm/i915/selftests/mock_gtt.c | 18 +++
5 files changed, 66 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7d527b569d28..24287cbecfdd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1616,12 +1616,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
gen8_ppgtt_notify_vgt(ppgtt, true);
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
- ppgtt->vm.bind_vma = gen8_ppgtt_bind_vma;
- ppgtt->vm.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.set_pages = ppgtt_set_pages;
- ppgtt->vm.clear_pages = clear_pages;
ppgtt->debug_dump = gen8_dump_ppgtt;
+ ppgtt->vm.vma_ops.bind_vma= gen8_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->vm.vma_ops.clear_pages = clear_pages;
+
return 0;
free_scratch:
@@ -2059,13 +2060,14 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->vm.insert_entries = gen6_ppgtt_insert_entries;
- ppgtt->vm.bind_vma = gen6_ppgtt_bind_vma;
- ppgtt->vm.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.set_pages = ppgtt_set_pages;
- ppgtt->vm.clear_pages = clear_pages;
ppgtt->vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->debug_dump = gen6_dump_ppgtt;
+ ppgtt->vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->vm.vma_ops.clear_pages = clear_pages;
+
DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
ppgtt->node.size >> 20,
ppgtt->node.start / PAGE_SIZE);
@@ -2793,11 +2795,11 @@ int i915_gem_init_aliasing_ppgtt(struct
drm_i915_private *i915)
i915->mm.aliasing_ppgtt = ppgtt;
- GEM_BUG_ON(ggtt->vm.bind_vma != ggtt_bind_vma);
- ggtt->vm.bind_vma = aliasing_gtt_bind_vma;
+ GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
+ ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
- GEM_BUG_ON(ggtt->vm.unbind_vma != ggtt_unbind_vma);
- ggtt->vm.unbind_vma = aliasing_gtt_unbind_vma;
+ GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
+ ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
return 0;
@@ -2817,8 +2819,8 @@ void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915)
i915_ppgtt_put(ppgtt);
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
+ ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
+ ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
}
int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
@@ -3310,10 +3312,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
ggtt->vm.cleanup = gen6_gmch_remove;
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
- ggtt->vm.set_pages = ggtt_set_pages;
- ggtt->vm.clear_pages = clear_pages;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
@@ -3331,6 +3329,11 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->invalidate = gen6_ggtt_invalidate;
+ ggtt->vm.vma_ops.bind_vma= ggtt_bind_vma;
+ ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
+ ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
+ ggtt->vm.vma_ops.clear_pages = clear_pages;
+
setup_private_pat(dev_priv);
return ggtt_probe_common(ggtt, size);
@@ -3370,10 +3373,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
- ggtt->vm.set_pages = ggtt_set_pages;
- ggtt->vm.clear_pages =
Re: [Intel-gfx] [PATCH i-g-t] igt/gem_exec_await: Tag the final batch in the GTT
Quoting Chris Wilson (2018-06-07 16:27:22) > Batches are contained in their position within the GTT by the kernel, constrained > and if they are in an invalid poistion will be unbound and rebound position > before execution. In our test setup, we therefore need to place the > batch into a valid poistion within the GTT before we fill the ring with > busyspinners. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/gem_exec_await: Tag the final batch in the GTT
Batches are contained in their position within the GTT by the kernel, and if they are in an invalid poistion will be unbound and rebound before execution. In our test setup, we therefore need to place the batch into a valid poistion within the GTT before we fill the ring with busyspinners. Signed-off-by: Chris Wilson --- tests/gem_exec_await.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/gem_exec_await.c b/tests/gem_exec_await.c index b0d5c9045..5cfeb8ec8 100644 --- a/tests/gem_exec_await.c +++ b/tests/gem_exec_await.c @@ -135,6 +135,9 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags) gem_write(fd, obj[nengine*ring_size].handle, 0, , sizeof(bbe)); memset(, 0, sizeof(execbuf)); + execbuf.buffers_ptr = to_user_pointer([nengine*ring_size]); + execbuf.buffer_count = 1; + gem_execbuf(fd, ); /* tag the object as a batch in the GTT */ execbuf.buffers_ptr = to_user_pointer(obj); execbuf.buffer_count = nengine*ring_size + 1; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Update preproduction steppings
On Wed, 06 Jun 2018, Chris Wilson wrote: > Quoting Mika Kuoppala (2018-06-06 15:18:24) >> Update preproduction steppings detection so that >> we get the warning and taint correctly for more >> recent platforms. > > Before crying foul, I suggest we check INTEL_INFO()->is_alpha_support. > We don't want to taint SDP boxes as we work on them for stabilisation. Agreed. > -Chris > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter
Quoting Tvrtko Ursulin (2018-06-07 14:25:28) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests currently executing > on the GPU. > > This is useful to analyze the overall load of the system. > > v2: > * Rebase. > * Drop floating point constant. (Chris Wilson) > > v3: > * Change scale to 1024 for faster arithmetics. (Chris Wilson) > > v4: > * Refactored for timer period accounting. > > v5: > * Avoid 64-division. (Chris Wilson) > > v6: > * Do fewer divisions by accumulating in qd.ns units. (Chris Wilson) > * Change counter scale to avoid multiplication in readout and increase >counter headroom. > > Signed-off-by: Tvrtko Ursulin I can't spot any nits to pick. That means I actually have to review it now, right? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark the GPU as wedged without error on fault injection
== Series Details == Series: drm/i915: Mark the GPU as wedged without error on fault injection URL : https://patchwork.freedesktop.org/series/44411/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9229 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9229 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9229, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44411/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9229: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9229 that come from known issues: === IGT changes === Issues hit igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) Possible fixes igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +2 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (40 -> 37) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9229 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9229: 4e9a90b9748305fa19ae2c2e7d87c2b265c2e741 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4e9a90b97483 drm/i915: Mark the GPU as wedged without error on fault injection == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9229/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning
Quoting Patchwork (2018-06-07 15:12:34) > == Series Details == > > Series: series starting with [01/20] drm/i915: Apply batch location > restrictions before pinning > URL : https://patchwork.freedesktop.org/series/44393/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9227_full = > > == Summary - FAILURE == > > Serious unknown changes coming with Patchwork_9227_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_9227_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. The big change here that wasn't previous reported is: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9227/pig-hsw-4770r/run0.log No new failures. On previous runs there were GPU hangs. \o/ > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_9227_full: > > === IGT changes === > > Possible regressions > > igt@drv_selftest@live_hangcheck: > shard-hsw: PASS -> DMESG-FAIL Still no better. Expected, but still disappointing. > igt@gem_exec_await@wide-all: > shard-hsw: PASS -> FAIL (fdo#105900) > shard-glk: PASS -> FAIL (fdo#105900) > shard-apl: PASS -> FAIL (fdo#105900) > shard-kbl: PASS -> FAIL (fdo#105900) Hmm, looks I need to fix this igt (I probably said has_full_ppgtt in calculating the number of requests/contexts I can use instead of has_execlists). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4289_full -> Patchwork_9227_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9227_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9227_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9227_full: === IGT changes === Possible regressions igt@drv_selftest@live_hangcheck: shard-hsw: PASS -> DMESG-FAIL Warnings igt@drv_hangman@hangcheck-unterminated: shard-hsw: SKIP -> PASS +1 igt@gem_exec_schedule@deep-blt: shard-kbl: PASS -> SKIP +1 igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_9227_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) igt@gem_exec_await@wide-all: shard-hsw: PASS -> FAIL (fdo#105900) shard-glk: PASS -> FAIL (fdo#105900) shard-apl: PASS -> FAIL (fdo#105900) shard-kbl: PASS -> FAIL (fdo#105900) igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#106509, fdo#105454) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) +2 Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS +1 igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#103928) -> PASS +1 igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc: shard-glk: FAIL (fdo#103167, fdo#104724) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9227 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9227: ccf9cf25f2e01521e4a792d5304587a71ea27deb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9227/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Queued/runnable/running engine stats (rev14)
== Series Details == Series: Queued/runnable/running engine stats (rev14) URL : https://patchwork.freedesktop.org/series/36926/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9228 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9228 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9228, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/36926/revisions/14/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9228: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9228 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) +2 igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#106000) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-cfl-s3: PASS -> FAIL (fdo#103481) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) Possible fixes igt@gem_exec_suspend@basic-s3: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: FAIL (fdo#103481) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 == Participating hosts (40 -> 37) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9228 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9228: a0bcb68e7c4dfe1f5eeadd5b5aa3c5b63a97b67d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a0bcb68e7c4d drm/i915: Engine queues query 96fbd1d34956 drm/i915/pmu: Add running counter 8a1c70584497 drm/i915/pmu: Add runnable counter a2f6d02d7479 drm/i915/pmu: Add queued counter d9a4aa2db316 drm/i915: Keep a count of requests submitted from userspace aaa1b93ef39b drm/i915: Keep a count of requests waiting for a slot on GPU 41210304d3a4 drm/i915/pmu: Fix enable count array size and bounds checking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9228/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Mark the GPU as wedged without error on fault injection
Quoting Chris Wilson (2018-06-07 14:45:58) > If we have been instructed (by CI) to inject a fault to load the module > with a wedged GPU, do so quietly less we upset CI. s/less/lest/ -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Mark the GPU as wedged without error on fault injection
If we have been instructed (by CI) to inject a fault to load the module
with a wedged GPU, do so quietly less we upset CI.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fd882eb389d2..4187e0688e50 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5491,6 +5491,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
}
if (i915_inject_load_failure()) {
+ DRM_DEBUG_DRIVER("Marking the driver as wedged\n");
+ i915_gem_set_wedged(dev_priv); /* Fail silently! */
ret = -EIO;
goto err_init_hw;
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter
From: Tvrtko Ursulin
We add a PMU counter to expose the number of requests currently executing
on the GPU.
This is useful to analyze the overall load of the system.
v2:
* Rebase.
* Drop floating point constant. (Chris Wilson)
v3:
* Change scale to 1024 for faster arithmetics. (Chris Wilson)
v4:
* Refactored for timer period accounting.
v5:
* Avoid 64-division. (Chris Wilson)
v6:
* Do fewer divisions by accumulating in qd.ns units. (Chris Wilson)
* Change counter scale to avoid multiplication in readout and increase
counter headroom.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 20 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
include/uapi/drm/i915_drm.h | 5 +
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index bdfb430909b4..73b6fe7cc6af 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -17,7 +17,8 @@
BIT(I915_SAMPLE_WAIT) | \
BIT(I915_SAMPLE_SEMA) | \
BIT(I915_SAMPLE_QUEUED) | \
-BIT(I915_SAMPLE_RUNNABLE))
+BIT(I915_SAMPLE_RUNNABLE) | \
+BIT(I915_SAMPLE_RUNNING))
#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
@@ -222,6 +223,11 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
add_sample_mult(>pmu.sample[I915_SAMPLE_RUNNABLE],
engine->request_stats.runnable,
period_ns);
+
+ if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNING))
+
add_sample_mult(>pmu.sample[I915_SAMPLE_RUNNING],
+ last_seqno - current_seqno,
+ period_ns);
}
if (fw)
@@ -337,6 +343,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_WAIT:
case I915_SAMPLE_QUEUED:
case I915_SAMPLE_RUNNABLE:
+ case I915_SAMPLE_RUNNING:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -556,11 +563,14 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = engine->pmu.sample[sample].cur;
if (sample == I915_SAMPLE_QUEUED ||
- sample == I915_SAMPLE_RUNNABLE) {
+ sample == I915_SAMPLE_RUNNABLE ||
+ sample == I915_SAMPLE_RUNNING) {
BUILD_BUG_ON(NSEC_PER_SEC %
I915_SAMPLE_QUEUED_DIVISOR);
BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
I915_SAMPLE_RUNNABLE_DIVISOR);
+ BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
+I915_SAMPLE_RUNNING_DIVISOR);
/* to qd */
val = div_u64(val,
NSEC_PER_SEC /
@@ -862,6 +872,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char
*name,
/* No brackets or quotes below please. */
#define I915_SAMPLE_QUEUED_SCALE 0.001
#define I915_SAMPLE_RUNNABLE_SCALE 0.001
+#define I915_SAMPLE_RUNNING_SCALE 0.001
static struct attribute **
create_event_attributes(struct drm_i915_private *i915)
@@ -889,6 +900,8 @@ create_event_attributes(struct drm_i915_private *i915)
__stringify(I915_SAMPLE_QUEUED_SCALE)),
__engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable",
__stringify(I915_SAMPLE_RUNNABLE_SCALE)),
+ __engine_event_scale(I915_SAMPLE_RUNNING, "running",
+__stringify(I915_SAMPLE_RUNNING_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -904,6 +917,9 @@ create_event_attributes(struct drm_i915_private *i915)
BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR !=
(1 / I915_SAMPLE_RUNNABLE_SCALE));
+ BUILD_BUG_ON(I915_SAMPLE_RUNNING_DIVISOR !=
+(1 / I915_SAMPLE_RUNNING_SCALE));
+
/* Count how many counters we will be exposing. */
for (i = 0; i < ARRAY_SIZE(events); i++) {
if (!config_status(i915, events[i].config))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 703cea694f0d..bff20cfd6870 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -420,7 +420,7 @@ struct intel_engine_cs {
*
* Our internal timer stores the current counters in this field.
*/
-#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1)
[Intel-gfx] [PATCH 5/7] drm/i915/pmu: Add runnable counter
From: Tvrtko Ursulin
We add a PMU counter to expose the number of requests with resolved
dependencies waiting for a slot on the GPU to run.
This is useful to analyze the overall load of the system.
v2: Don't limit to gen8+.
v3:
* Rebase for dynamic sysfs.
* Drop currently executing requests.
v4:
* Sync with internal renaming.
* Drop floating point constant. (Chris Wilson)
v5:
* Change scale to 1024 for faster arithmetics. (Chris Wilson)
v6:
* Refactored for timer period accounting.
v7:
* Avoid 64-division. (Chris Wilson)
v8:
* Do fewer divisions by accumulating in qd.ns units. (Chris Wilson)
* Change counter scale to avoid multiplication in readout and increase
counter headroom.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 20 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
include/uapi/drm/i915_drm.h | 7 ++-
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index f8a819600ebc..bdfb430909b4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -16,7 +16,8 @@
(BIT(I915_SAMPLE_BUSY) | \
BIT(I915_SAMPLE_WAIT) | \
BIT(I915_SAMPLE_SEMA) | \
-BIT(I915_SAMPLE_QUEUED))
+BIT(I915_SAMPLE_QUEUED) | \
+BIT(I915_SAMPLE_RUNNABLE))
#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
@@ -216,6 +217,11 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
add_sample_mult(>pmu.sample[I915_SAMPLE_QUEUED],
atomic_read(>request_stats.queued),
period_ns);
+
+ if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNABLE))
+
add_sample_mult(>pmu.sample[I915_SAMPLE_RUNNABLE],
+ engine->request_stats.runnable,
+ period_ns);
}
if (fw)
@@ -330,6 +336,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_BUSY:
case I915_SAMPLE_WAIT:
case I915_SAMPLE_QUEUED:
+ case I915_SAMPLE_RUNNABLE:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -548,9 +555,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
} else {
val = engine->pmu.sample[sample].cur;
- if (sample == I915_SAMPLE_QUEUED) {
+ if (sample == I915_SAMPLE_QUEUED ||
+ sample == I915_SAMPLE_RUNNABLE) {
BUILD_BUG_ON(NSEC_PER_SEC %
I915_SAMPLE_QUEUED_DIVISOR);
+ BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
+I915_SAMPLE_RUNNABLE_DIVISOR);
/* to qd */
val = div_u64(val,
NSEC_PER_SEC /
@@ -851,6 +861,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char
*name,
/* No brackets or quotes below please. */
#define I915_SAMPLE_QUEUED_SCALE 0.001
+#define I915_SAMPLE_RUNNABLE_SCALE 0.001
static struct attribute **
create_event_attributes(struct drm_i915_private *i915)
@@ -876,6 +887,8 @@ create_event_attributes(struct drm_i915_private *i915)
__engine_event(I915_SAMPLE_WAIT, "wait"),
__engine_event_scale(I915_SAMPLE_QUEUED, "queued",
__stringify(I915_SAMPLE_QUEUED_SCALE)),
+ __engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable",
+__stringify(I915_SAMPLE_RUNNABLE_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -888,6 +901,9 @@ create_event_attributes(struct drm_i915_private *i915)
BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
(1 / I915_SAMPLE_QUEUED_SCALE));
+ BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR !=
+(1 / I915_SAMPLE_RUNNABLE_SCALE));
+
/* Count how many counters we will be exposing. */
for (i = 0; i < ARRAY_SIZE(events); i++) {
if (!config_status(i915, events[i].config))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 902b63eeaf50..703cea694f0d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -420,7 +420,7 @@ struct intel_engine_cs {
*
* Our internal timer stores the current counters in this field.
*/
-#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1)
+#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1)
struct i915_pmu_sample
[Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter
From: Tvrtko Ursulin
We add a PMU counter to expose the number of requests which have been
submitted from userspace but are not yet runnable due dependencies and
unsignaled fences.
This is useful to analyze the overall load of the system.
v2:
* Rebase for name change and re-order.
* Drop floating point constant. (Chris Wilson)
v3:
* Change scale to 1024 for faster arithmetics. (Chris Wilson)
v4:
* Refactored for timer period accounting.
v5:
* Avoid 64-division. (Chris Wilson)
v6:
* Do fewer divisions by accumulating in qd.ns units. (Chris Wilson)
* Change counter scale to avoid multiplication in readout and increase
counter headroom.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 58 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
include/uapi/drm/i915_drm.h | 9 +++-
3 files changed, 57 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index b8c6953867ee..f8a819600ebc 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -15,7 +15,8 @@
#define ENGINE_SAMPLE_MASK \
(BIT(I915_SAMPLE_BUSY) | \
BIT(I915_SAMPLE_WAIT) | \
-BIT(I915_SAMPLE_SEMA))
+BIT(I915_SAMPLE_SEMA) | \
+BIT(I915_SAMPLE_QUEUED))
#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
@@ -161,6 +162,12 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
sample->cur += val;
}
+static void
+add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
+{
+ sample->cur += mul_u32_u32(val, mul);
+}
+
static void
engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
{
@@ -204,6 +211,11 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
if (val & RING_WAIT_SEMAPHORE)
add_sample(>pmu.sample[I915_SAMPLE_SEMA],
period_ns);
+
+ if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED))
+ add_sample_mult(>pmu.sample[I915_SAMPLE_QUEUED],
+
atomic_read(>request_stats.queued),
+ period_ns);
}
if (fw)
@@ -212,12 +224,6 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned
int period_ns)
intel_runtime_pm_put(dev_priv);
}
-static void
-add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
-{
- sample->cur += mul_u32_u32(val, mul);
-}
-
static void
frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
{
@@ -323,6 +329,7 @@ engine_event_status(struct intel_engine_cs *engine,
switch (sample) {
case I915_SAMPLE_BUSY:
case I915_SAMPLE_WAIT:
+ case I915_SAMPLE_QUEUED:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -540,6 +547,15 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = ktime_to_ns(intel_engine_get_busy_time(engine));
} else {
val = engine->pmu.sample[sample].cur;
+
+ if (sample == I915_SAMPLE_QUEUED) {
+ BUILD_BUG_ON(NSEC_PER_SEC %
+I915_SAMPLE_QUEUED_DIVISOR);
+ /* to qd */
+ val = div_u64(val,
+ NSEC_PER_SEC /
+ I915_SAMPLE_QUEUED_DIVISOR);
+ }
}
} else {
switch (event->attr.config) {
@@ -796,6 +812,16 @@ static const struct attribute_group
*i915_pmu_attr_groups[] = {
{ \
.sample = (__sample), \
.name = (__name), \
+ .suffix = "unit", \
+ .value = "ns", \
+}
+
+#define __engine_event_scale(__sample, __name, __scale) \
+{ \
+ .sample = (__sample), \
+ .name = (__name), \
+ .suffix = "scale", \
+ .value = (__scale), \
}
static struct i915_ext_attribute *
@@ -823,6 +849,9 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char
*name,
return ++attr;
}
+/* No brackets or quotes below please. */
+#define I915_SAMPLE_QUEUED_SCALE 0.001
+
static struct attribute **
create_event_attributes(struct drm_i915_private *i915)
{
@@ -839,10 +868,14 @@ create_event_attributes(struct drm_i915_private *i915)
static const struct {
enum drm_i915_pmu_engine_sample sample;
char *name;
+ char *suffix;
+ char *value;
} engine_events[] = {
__engine_event(I915_SAMPLE_BUSY, "busy"),
__engine_event(I915_SAMPLE_SEMA, "sema"),
__engine_event(I915_SAMPLE_WAIT, "wait"),
+ __engine_event_scale(I915_SAMPLE_QUEUED, "queued",
+
[Intel-gfx] [PATCH i-g-t] HAX igt/drv_module_reload: Revamp fault-injection
The current method of checking for a failed module load is flawed, as we
only report the error on probing it is not being reported back by
modprobe. So we have to dig inside the module_parameters while the
module is still loaded to discover the error.
v2: Expect i915.inject_load_failure to be zero on success
w/o display
---
tests/drv_module_reload.c | 47 ++-
1 file changed, 42 insertions(+), 5 deletions(-)
diff --git a/tests/drv_module_reload.c b/tests/drv_module_reload.c
index 3046d8227..d88851b68 100644
--- a/tests/drv_module_reload.c
+++ b/tests/drv_module_reload.c
@@ -234,6 +234,40 @@ reload(const char *opts_i915)
return err;
}
+static int open_parameters(const char *module_name)
+{
+ char path[256];
+
+ snprintf(path, sizeof(path), "/sys/module/%s/parameters", module_name);
+ return open(path, O_RDONLY);
+}
+
+static int
+inject_fault(const char *module_name, const char *opt, int fault)
+{
+ char buf[1024];
+ int dir;
+
+ igt_assert(fault > 0);
+ snprintf(buf, sizeof(buf), "%s=%d disable_display=1", opt, fault);
+
+ if (igt_kmod_load(module_name, buf)) {
+ igt_warn("Failed to load module '%s' with options '%s'\n",
+module_name, buf);
+ return 1;
+ }
+
+ dir = open_parameters(module_name);
+ igt_sysfs_scanf(dir, opt, "%d", );
+ close(dir);
+
+ igt_debug("Loaded '%s %s', result=%d\n", module_name, buf, fault);
+
+ igt_kmod_unload(module_name, 0);
+
+ return fault;
+}
+
static void
gem_sanitycheck(void)
{
@@ -320,12 +354,15 @@ igt_main
igt_assert_eq(reload("disable_display=1"), 0);
igt_subtest("basic-reload-inject") {
- char buf[64];
int i = 0;
- do {
- snprintf(buf, sizeof(buf),
-"inject_load_failure=%d", ++i);
- } while (reload(buf));
+
+ igt_i915_driver_unload();
+
+ while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+ ;
+
+ /* We expect to hit at least one fault! */
+ igt_assert(i > 1);
}
igt_fixture {
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/drv_module_reload: Revamp fault-injection
The current method of checking for a failed module load is flawed, as we
only report the error on probing it is not being reported back by
modprobe. So we have to dig inside the module_parameters while the
module is still loaded to discover the error.
v2: Expect i915.inject_load_failure to be zero on success
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Imre Deak
Reviewed-by: Michał Winiarski
---
tests/drv_module_reload.c | 47 ++-
1 file changed, 42 insertions(+), 5 deletions(-)
diff --git a/tests/drv_module_reload.c b/tests/drv_module_reload.c
index 3046d8227..57e5b50ec 100644
--- a/tests/drv_module_reload.c
+++ b/tests/drv_module_reload.c
@@ -234,6 +234,40 @@ reload(const char *opts_i915)
return err;
}
+static int open_parameters(const char *module_name)
+{
+ char path[256];
+
+ snprintf(path, sizeof(path), "/sys/module/%s/parameters", module_name);
+ return open(path, O_RDONLY);
+}
+
+static int
+inject_fault(const char *module_name, const char *opt, int fault)
+{
+ char buf[1024];
+ int dir;
+
+ igt_assert(fault > 0);
+ snprintf(buf, sizeof(buf), "%s=%d", opt, fault);
+
+ if (igt_kmod_load(module_name, buf)) {
+ igt_warn("Failed to load module '%s' with options '%s'\n",
+module_name, buf);
+ return 1;
+ }
+
+ dir = open_parameters(module_name);
+ igt_sysfs_scanf(dir, opt, "%d", );
+ close(dir);
+
+ igt_debug("Loaded '%s %s', result=%d\n", module_name, buf, fault);
+
+ igt_kmod_unload(module_name, 0);
+
+ return fault;
+}
+
static void
gem_sanitycheck(void)
{
@@ -320,12 +354,15 @@ igt_main
igt_assert_eq(reload("disable_display=1"), 0);
igt_subtest("basic-reload-inject") {
- char buf[64];
int i = 0;
- do {
- snprintf(buf, sizeof(buf),
-"inject_load_failure=%d", ++i);
- } while (reload(buf));
+
+ igt_i915_driver_unload();
+
+ while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+ ;
+
+ /* We expect to hit at least one fault! */
+ igt_assert(i > 1);
}
igt_fixture {
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit
Hi Chris, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.17 next-20180606] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Mark-i915-inject_load_failure-as-being-hit/20180607-174849 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-x018-201822 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All error/warnings (new ones prefixed by >>): In file included from include/linux/printk.h:7:0, from include/linux/kernel.h:14, from include/linux/list.h:9, from include/linux/resource_ext.h:17, from include/linux/acpi.h:26, from drivers/gpu/drm/i915/i915_drv.c:30: >> include/linux/kern_levels.h:5:18: warning: initialization makes integer from >> pointer without a cast [-Wint-conversion] #define KERN_SOH "\001" /* ASCII Start Of Header */ ^ include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH' #define KERN_ERR KERN_SOH "3" /* error conditions */ ^~~~ >> drivers/gpu/drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR' static int i915_load_error_level = KERN_ERR; ^~~~ >> include/linux/kern_levels.h:5:18: error: initializer element is not >> computable at load time #define KERN_SOH "\001" /* ASCII Start Of Header */ ^ include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH' #define KERN_ERR KERN_SOH "3" /* error conditions */ ^~~~ >> drivers/gpu/drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR' static int i915_load_error_level = KERN_ERR; ^~~~ drivers/gpu/drm/i915/i915_drv.c: In function '__i915_inject_load_failure': >> drivers/gpu/drm/i915/i915_drv.c:72:25: warning: assignment makes integer >> from pointer without a cast [-Wint-conversion] i915_load_error_level = KERN_DEBUG; ^ drivers/gpu/drm/i915/i915_drv.c: In function 'i915_driver_load': >> drivers/gpu/drm/i915/i915_drv.c:123:26: warning: passing argument 2 of >> '__i915_printk' makes pointer from integer without a cast [-Wint-conversion] __i915_printk(dev_priv, i915_load_error_level, fmt, ##__VA_ARGS__) ^ >> drivers/gpu/drm/i915/i915_drv.c:1425:2: note: in expansion of macro >> 'i915_load_error' i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); ^~~ drivers/gpu/drm/i915/i915_drv.c:87:1: note: expected 'const char *' but argument is of type 'int' __i915_printk(struct drm_i915_private *dev_priv, const char *level, ^ -- In file included from include/linux/printk.h:7:0, from include/linux/kernel.h:14, from include/linux/list.h:9, from include/linux/resource_ext.h:17, from include/linux/acpi.h:26, from drivers/gpu//drm/i915/i915_drv.c:30: >> include/linux/kern_levels.h:5:18: warning: initialization makes integer from >> pointer without a cast [-Wint-conversion] #define KERN_SOH "\001" /* ASCII Start Of Header */ ^ include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH' #define KERN_ERR KERN_SOH "3" /* error conditions */ ^~~~ drivers/gpu//drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR' static int i915_load_error_level = KERN_ERR; ^~~~ >> include/linux/kern_levels.h:5:18: error: initializer element is not >> computable at load time #define KERN_SOH "\001" /* ASCII Start Of Header */ ^ include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH' #define KERN_ERR KERN_SOH "3" /* error conditions */ ^~~~ drivers/gpu//drm/i915/i915_drv.c:61:36: note: in expansion of macro 'KERN_ERR' static int i915_load_error_level = KERN_ERR; ^~~~ drivers/gpu//drm/i915/i915_drv.c: In function '__i915_inject_load_failure': drivers/gpu//drm/i915/i915_drv.c:72:25: warning: assignment makes integer from pointer without a cast [-Wint-conversion] i915_load_error_level = KERN_DEBUG; ^ drivers/gpu//drm/i915/i915_drv.c: In function
Re: [Intel-gfx] [PATCH v2] drm/i915: Mark i915.inject_load_failure as being hit
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17 next-20180606]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Mark-i915-inject_load_failure-as-being-hit/20180607-174849
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-n0-201822 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/resource_ext.h:17,
from include/linux/acpi.h:26,
from drivers/gpu//drm/i915/i915_drv.c:30:
include/linux/kern_levels.h:5:18: error: initialization makes integer from
pointer without a cast [-Werror=int-conversion]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~
drivers/gpu//drm/i915/i915_drv.c:61:36: note: in expansion of macro
'KERN_ERR'
static int i915_load_error_level = KERN_ERR;
^~~~
drivers/gpu//drm/i915/i915_drv.c: In function '__i915_inject_load_failure':
>> drivers/gpu//drm/i915/i915_drv.c:72:25: error: assignment makes integer from
>> pointer without a cast [-Werror=int-conversion]
i915_load_error_level = KERN_DEBUG;
^
drivers/gpu//drm/i915/i915_drv.c: In function 'i915_driver_load':
>> drivers/gpu//drm/i915/i915_drv.c:123:26: error: passing argument 2 of
>> '__i915_printk' makes pointer from integer without a cast
>> [-Werror=int-conversion]
__i915_printk(dev_priv, i915_load_error_level, fmt, ##__VA_ARGS__)
^
drivers/gpu//drm/i915/i915_drv.c:1425:2: note: in expansion of macro
'i915_load_error'
i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
^~~
drivers/gpu//drm/i915/i915_drv.c:87:1: note: expected 'const char *' but
argument is of type 'int'
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
^
cc1: all warnings being treated as errors
vim +/__i915_printk +123 drivers/gpu//drm/i915/i915_drv.c
58
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60 static unsigned int i915_load_fail_count;
> 61 static int i915_load_error_level = KERN_ERR;
62
63 bool __i915_inject_load_failure(const char *func, int line)
64 {
65 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
66 return false;
67
68 if (++i915_load_fail_count ==
i915_modparams.inject_load_failure) {
69 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
70 i915_modparams.inject_load_failure, func,
line);
71 i915_modparams.inject_load_failure = 0;
> 72 i915_load_error_level = KERN_DEBUG;
73 return true;
74 }
75
76 return false;
77 }
78 #else
79 #define i915_load_error_level KERN_ERR
80 #endif
81
82 #define FDO_BUG_URL
"https://bugs.freedesktop.org/enter_bug.cgi?product=DRI;
83 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against
DRM/Intel " \
84 "providing the dmesg log by booting with
drm.debug=0xf"
85
86 void
87 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
88const char *fmt, ...)
89 {
90 static bool shown_bug_once;
91 struct device *kdev = dev_priv->drm.dev;
92 bool is_error = level[1] <= KERN_ERR[1];
93 bool is_debug = level[1] == KERN_DEBUG[1];
94 struct va_format vaf;
95 va_list args;
96
97 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
98 return;
99
100 va_start(args, fmt);
101
102 vaf.fmt = fmt;
103 vaf.va =
104
105 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
106 __builtin_return_address(0), );
107
108 if (is_error && !shown_bug_once) {
109 /*
110 * Ask the user to file a bug report for the error,
excep
[Intel-gfx] [PATCH i-g-t] igt/drv_module_reload: Revamp fault-injection
The current method of checking for a failed module load is flawed, as we
only report the error on probing it is not being reported back by
modprobe. So we have to dig inside the module_parameters while the
module is still loaded to discover the error.
v2: Expect i915.inject_load_failure to be zero on success
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Imre Deak
Reviewed-by: Michał Winiarski
---
tests/drv_module_reload.c | 45 ++-
1 file changed, 40 insertions(+), 5 deletions(-)
diff --git a/tests/drv_module_reload.c b/tests/drv_module_reload.c
index 3046d8227..5d6680b0b 100644
--- a/tests/drv_module_reload.c
+++ b/tests/drv_module_reload.c
@@ -234,6 +234,38 @@ reload(const char *opts_i915)
return err;
}
+static int open_parameters(const char *module_name)
+{
+ char path[256];
+
+ snprintf(path, sizeof(path), "/sys/module/%s/parameters", module_name);
+ return open(path, O_RDONLY);
+}
+
+static int
+inject_fault(const char *module_name, const char *opt, int fault)
+{
+ char buf[1024];
+ int dir;
+
+ igt_assert(fault > 0);
+ snprintf(buf, sizeof(buf), "%s=%d", opt, fault);
+
+ if (igt_kmod_load(module_name, buf)) {
+ igt_warn("Failed to load module '%s' with options '%s'\n",
+module_name, buf);
+ return 1;
+ }
+
+ dir = open_parameters(module_name);
+ igt_sysfs_scanf(dir, opt, "%d", );
+ close(dir);
+
+ igt_kmod_unload(module_name, 0);
+
+ return fault;
+}
+
static void
gem_sanitycheck(void)
{
@@ -320,12 +352,15 @@ igt_main
igt_assert_eq(reload("disable_display=1"), 0);
igt_subtest("basic-reload-inject") {
- char buf[64];
int i = 0;
- do {
- snprintf(buf, sizeof(buf),
-"inject_load_failure=%d", ++i);
- } while (reload(buf));
+
+ igt_i915_driver_unload();
+
+ while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+ ;
+
+ /* We expect to hit at least one fault! */
+ igt_assert(i > 1);
}
igt_fixture {
--
2.17.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4287_full -> Patchwork_9226_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9226_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9226_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9226_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS +1 igt@gem_mocs_settings@mocs-rc6-bsd1: shard-kbl: PASS -> SKIP igt@kms_vblank@pipe-b-wait-forked: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9226_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip@wf_vblank-ts-check-interruptible: shard-hsw: PASS -> FAIL (fdo#103928) +2 igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887) -> PASS +1 igt@kms_flip@dpms-vs-vblank-race: shard-glk: FAIL (fdo#103060) -> PASS igt@kms_flip@modeset-vs-vblank-race: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt: shard-glk: FAIL (fdo#103167, fdo#104724) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4287 -> Patchwork_9226 CI_DRM_4287: 3da21a5f843f8c11efe3326f3f7854df8ecd72c0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9226: 2dd0b7205b8cc0789023a6645b6b704689a50b01 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9226/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4289 -> Patchwork_9227 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9227 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9227, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44393/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9227: === IGT changes === Warnings igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9227 that come from known issues: === IGT changes === Issues hit igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: PASS -> FAIL (fdo#102575) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-flip-vs-wf_vblank: fi-hsw-4770:PASS -> FAIL (fdo#100368) Possible fixes igt@gem_exec_basic@gtt-render: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@gem_sync@basic-many-each: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: FAIL (fdo#103481) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 == Participating hosts (40 -> 37) == Missing(3): fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * Linux: CI_DRM_4289 -> Patchwork_9227 CI_DRM_4289: 0e963d962be75b4e3d3d1c884e1bf4600473096d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9227: ccf9cf25f2e01521e4a792d5304587a71ea27deb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ccf9cf25f2e0 RFT drm/i915/gtt: Enable full-ppgtt by default everywhere 7a9269727bc6 drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt 6d297e0bf808 drm/i915/gtt: Reduce a pair of runtime asserts 44e308bafd23 drm/i915/gtt: Cache the PTE encoding of the scratch page 9b51f6bbad47 drm/i915/gtt: Skip initializing PT with scratch if full 1d28eeadf9d4 drm/i915/gtt: Free unused page tables on unbind the context fae591d1cd18 drm/i915/gtt: Lazily allocate page directories for gen7 0e44e5e8faac drm/i915/gtt: Only keep gen6 page directories pinned while active 9c96b92bda92 drm/i915/gtt: Make gen6 page directories evictable a3eb4e1bf700 drm/i915/gtt: Reorder aliasing_ppgtt fini 6fad86032eae drm/i915/gtt Onionify error handling for gen6_ppgtt_create a2a68e253e31 drm/i915/gtt: Subclass gen6_hw_ppgtt eb526be320e6 drm/i915/gtt: Push allocation to hw ppgtt constructor f62164cc5953 drm/i915: Decouple vma vfuncs from vm f2324756fad9 drm/i915: Prepare for non-object vma 10cd08182691 drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories 33fd97510d89 drm/i915/ringbuffer: Force restore of mm after failed context switch 5921c8fab546 drm/i915/ringbuffer: Brute force context restore 168b29bb8025 drm/i915/ringbuffer: Make order of mmio to CCID/PP_DIR consistent with switch_context() 97656113bc83 drm/i915: Apply batch location restrictions before pinning == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9227/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create
Quoting Matthew Auld (2018-06-07 11:17:14) > On 7 June 2018 at 10:58, Chris Wilson wrote: > > Pull the empty stubs together into the top level gen6_ppgtt_create, and > > tear each one down on error in proper onion order (rather than use > > Joonas' pet hate of calling the cleanup function in indeterminable > > state). > > > > Signed-off-by: Chris Wilson > > Cc: Joonas Lahtinen > > Cc: Mika Kuoppala > > Cc: Matthew Auld > > Reviewed-by: Matthew Auld > > s/gtt Onionify/gtt: Onionify/ /o\ Sorry, I thought I had fixed it, I intended to when adding your r-b. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning
== Series Details == Series: series starting with [01/20] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44393/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Apply batch location restrictions before pinning Okay! Commit: drm/i915/ringbuffer: Make order of mmio to CCID/PP_DIR consistent with switch_context() Okay! Commit: drm/i915/ringbuffer: Brute force context restore Okay! Commit: drm/i915/ringbuffer: Force restore of mm after failed context switch Okay! Commit: drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories Okay! Commit: drm/i915: Prepare for non-object vma Okay! Commit: drm/i915: Decouple vma vfuncs from vm Okay! Commit: drm/i915/gtt: Push allocation to hw ppgtt constructor -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1644:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Subclass gen6_hw_ppgtt -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1913:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1913:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1914:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1914:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2031:9: warning: expression using sizeof(void) Commit: drm/i915/gtt Onionify error handling for gen6_ppgtt_create Okay! Commit: drm/i915/gtt: Reorder aliasing_ppgtt fini Okay! Commit: drm/i915/gtt: Make gen6 page directories evictable -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2022:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2022:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Only keep gen6 page directories pinned while active Okay! Commit: drm/i915/gtt: Lazily allocate page directories for gen7 Okay! Commit: drm/i915/gtt: Free unused page tables on unbind the context -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1827:36: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1896:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1896:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1827:42: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1906:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1906:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Skip initializing PT with scratch if full Okay! Commit: drm/i915/gtt: Cache the PTE encoding of the scratch page Okay! Commit: drm/i915/gtt: Reduce a pair of runtime asserts Okay! Commit: drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt Okay! Commit: RFT drm/i915/gtt: Enable full-ppgtt by default everywhere Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create
On 7 June 2018 at 10:58, Chris Wilson wrote: > Pull the empty stubs together into the top level gen6_ppgtt_create, and > tear each one down on error in proper onion order (rather than use > Joonas' pet hate of calling the cleanup function in indeterminable > state). > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld > Reviewed-by: Matthew Auld s/gtt Onionify/gtt: Onionify/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Apply batch location restrictions before pinning
== Series Details ==
Series: series starting with [01/20] drm/i915: Apply batch location
restrictions before pinning
URL : https://patchwork.freedesktop.org/series/44393/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
97656113bc83 drm/i915: Apply batch location restrictions before pinning
-:30: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#30: FILE: drivers/gpu/drm/i915/i915_gem_execbuffer.c:493:
+ unsigned int i, unsigned batch_idx,
total: 0 errors, 1 warnings, 0 checks, 86 lines checked
168b29bb8025 drm/i915/ringbuffer: Make order of mmio to CCID/PP_DIR consistent
with switch_context()
5921c8fab546 drm/i915/ringbuffer: Brute force context restore
33fd97510d89 drm/i915/ringbuffer: Force restore of mm after failed context
switch
10cd08182691 drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page
directories
f2324756fad9 drm/i915: Prepare for non-object vma
f62164cc5953 drm/i915: Decouple vma vfuncs from vm
eb526be320e6 drm/i915/gtt: Push allocation to hw ppgtt constructor
a2a68e253e31 drm/i915/gtt: Subclass gen6_hw_ppgtt
-:327: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible
side-effects?
#327: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:419:
+#define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
total: 0 errors, 0 warnings, 1 checks, 356 lines checked
6fad86032eae drm/i915/gtt Onionify error handling for gen6_ppgtt_create
a3eb4e1bf700 drm/i915/gtt: Reorder aliasing_ppgtt fini
9c96b92bda92 drm/i915/gtt: Make gen6 page directories evictable
0e44e5e8faac drm/i915/gtt: Only keep gen6 page directories pinned while active
fae591d1cd18 drm/i915/gtt: Lazily allocate page directories for gen7
1d28eeadf9d4 drm/i915/gtt: Free unused page tables on unbind the context
9b51f6bbad47 drm/i915/gtt: Skip initializing PT with scratch if full
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#9:
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 14826673247e ("drm/i915: Only
initialize partially filled pagetables")'
#9:
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
44e308bafd23 drm/i915/gtt: Cache the PTE encoding of the scratch page
6d297e0bf808 drm/i915/gtt: Reduce a pair of runtime asserts
-:39: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#39: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:470:
+ GEM_BUG_ON(offset_in_page(addr|length));
^
total: 0 errors, 0 warnings, 1 checks, 18 lines checked
7a9269727bc6 drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
ccf9cf25f2e0 RFT drm/i915/gtt: Enable full-ppgtt by default everywhere
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[Intel-gfx] Oops with i915
Hi All, We are running v4.14.47 kernel and recently in one of our test cycle we saw the below trace. I know this is not the usual way to raise a BUG report, but since this was seen only once in one of the automated test cycle so I donot have anything else apart from this trace. Is this a known issue? Will appreciate any help in understanding what the problem might be. [ 1176.909543] BUG: unable to handle kernel paging request at 8298fb0a [ 1176.916565] IP: queued_spin_lock_slowpath+0xfc/0x142 [ 1176.922111] *pdpt = 3367a001 *pde = [ 1176.928534] Oops: 0002 [#1] PREEMPT SMP [ 1177.002434] CPU: 2 PID: 24688 Comm: kworker/u8:4 Tainted: G U O 4.14.47-20180606-a6b8390e8cc1de032b8314d1a5b193fe9e21f325 #1 [ 1177.024120] Workqueue: events_unbound intel_atomic_commit_work [ 1177.030630] task: ef2ee200 task.stack: efbf4000 [ 1177.035685] EIP: queued_spin_lock_slowpath+0xfc/0x142 [ 1177.041327] EFLAGS: 00010087 CPU: 2 [ 1177.045212] EAX: 8298fb0a EBX: 3ba0 ECX: ee82489c EDX: f4656fc0 [ 1177.052215] ESI: 000c EDI: 0001 EBP: efbf5e88 ESP: efbf5e78 [ 1177.059217] DS: 007b ES: 007b FS: 00d8 GS: SS: 0068 [ 1177.065239] CR0: 80050033 CR2: 8298fb0a CR3: 2e8ed320 CR4: 001006f0 [ 1177.072240] Call Trace: [ 1177.074973] _raw_spin_lock_irqsave+0x28/0x2d [ 1177.079840] complete_all+0x12/0x36 [ 1177.083737] drm_atomic_helper_commit_hw_done+0x3c/0x43 [ 1177.089576] intel_atomic_commit_tail+0xa5f/0xbd9 [ 1177.094832] ? wait_woken+0x5a/0x5a [ 1177.098727] ? wait_woken+0x5a/0x5a [ 1177.102622] intel_atomic_commit_work+0xb/0xd [ 1177.107489] ? intel_atomic_commit_work+0xb/0xd [ 1177.112551] process_one_work+0x109/0x1ee [ 1177.117029] worker_thread+0x1a4/0x257 [ 1177.121215] kthread+0xee/0xf3 [ 1177.124625] ? rescuer_thread+0x207/0x207 [ 1177.129103] ? kthread_create_on_node+0x1a/0x1a [ 1177.134165] ret_from_fork+0x2e/0x38 [ 1177.138156] Code: 12 09 de 89 f0 89 75 f0 c1 e8 10 66 87 41 02 89 c3 c1 e3 10 74 51 83 e0 03 c1 eb 12 6b c0 0c 05 c0 1f 7e c1 03 04 9d d8 b1 6c c1 <89> 10 8b 42 04 85 c0 75 04 f3 90 eb f5 8b 1a 85 db 74 03 0f 0d [ 1177.159204] EIP: queued_spin_lock_slowpath+0xfc/0x142 SS:ESP: 0068:efbf5e78 [ 1177.166983] CR2: 8298fb0a -- Regards Sudip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/20] drm/i915/gtt: Cache the PTE encoding of the scratch page
As the most frequent PTE encoding is for the scratch page, cache it upon
creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 20a8e48dbb05..a15cda2fa02e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -640,11 +640,10 @@ static void gen8_initialize_pt(struct i915_address_space
*vm,
gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC));
}
-static void gen6_initialize_pt(struct i915_address_space *vm,
+static void gen6_initialize_pt(struct gen6_hw_ppgtt *ppgtt,
struct i915_page_table *pt)
{
- fill32_px(vm, pt,
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
+ fill32_px(>base.vm, pt, ppgtt->scratch_pte);
}
static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
@@ -1631,9 +1630,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
- struct i915_address_space *vm = >vm;
- const gen6_pte_t scratch_pte =
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ const gen6_pte_t scratch_pte = ppgtt->scratch_pte;
struct i915_page_table *pt;
u32 pte, pde;
@@ -1819,8 +1816,7 @@ static void gen6_ppgtt_clear_range(struct
i915_address_space *vm,
unsigned int pde = first_entry / GEN6_PTES;
unsigned int pte = first_entry % GEN6_PTES;
unsigned int num_entries = length >> PAGE_SHIFT;
- const gen6_pte_t scratch_pte =
- vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ const gen6_pte_t scratch_pte = ppgtt->scratch_pte;
while (num_entries) {
struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
@@ -1912,7 +1908,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
goto unwind_out;
if (count < GEN6_PTES)
- gen6_initialize_pt(vm, pt);
+ gen6_initialize_pt(ppgtt, pt);
ppgtt->base.pd.page_table[pde] = pt;
if (i915_vma_is_bound(ppgtt->vma,
@@ -1950,13 +1946,17 @@ static int gen6_ppgtt_init_scratch(struct gen6_hw_ppgtt
*ppgtt)
if (ret)
return ret;
+ ppgtt->scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr,
+ I915_CACHE_NONE, PTE_READ_ONLY);
+
vm->scratch_pt = alloc_pt(vm);
if (IS_ERR(vm->scratch_pt)) {
cleanup_scratch_page(vm);
return PTR_ERR(vm->scratch_pt);
}
- gen6_initialize_pt(vm, vm->scratch_pt);
+ gen6_initialize_pt(ppgtt, vm->scratch_pt);
gen6_for_all_pdes(unused, >base.pd, pde)
ppgtt->base.pd.page_table[pde] = vm->scratch_pt;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index dc98830fae69..c50bbde007f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -412,6 +412,7 @@ struct gen6_hw_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
+ gen6_pte_t scratch_pte;
unsigned int pin_count;
bool scan_for_unused_pt;
--
2.17.1
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[Intel-gfx] [PATCH 16/20] drm/i915/gtt: Skip initializing PT with scratch if full
If we will completely overwrite the PT with PTEs for the object, we can
forgo filling it with scratch entries.
References: 14826673247e ("drm/i915: Only initialize partially filled
pagetables")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 838ac936d843..20a8e48dbb05 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1911,7 +1911,8 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
if (IS_ERR(pt))
goto unwind_out;
- gen6_initialize_pt(vm, pt);
+ if (count < GEN6_PTES)
+ gen6_initialize_pt(vm, pt);
ppgtt->base.pd.page_table[pde] = pt;
if (i915_vma_is_bound(ppgtt->vma,
--
2.17.1
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[Intel-gfx] [PATCH 18/20] drm/i915/gtt: Reduce a pair of runtime asserts
We can stop asserting using WARN_ON as given sufficient CI coverage, we
can rely on using GEM_BUG_ON() to catch problems before merging.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a15cda2fa02e..75c8cb75a0ce 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2868,7 +2868,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915)
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
- if (WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
+ if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
err = -ENODEV;
goto err_ppgtt;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c50bbde007f8..37f565a38d3e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -466,8 +466,8 @@ static inline u32 i915_pte_count(u64 addr, u64 length,
unsigned int pde_shift)
const u64 mask = ~((1ULL << pde_shift) - 1);
u64 end;
- WARN_ON(length == 0);
- WARN_ON(offset_in_page(addr|length));
+ GEM_BUG_ON(length == 0);
+ GEM_BUG_ON(offset_in_page(addr|length));
end = addr + length;
--
2.17.1
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[Intel-gfx] [PATCH 15/20] drm/i915/gtt: Free unused page tables on unbind the context
As we cannot reliably change used page tables while the context is
active, the earliest opportunity we have to recover excess pages is when
the context becomes idle. So whenever we unbind the context (it must be
idle, and indeed being evicted) free the unused ptes.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 44 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 660596ebd3c1..838ac936d843 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1814,20 +1814,28 @@ static void gen6_ppgtt_enable(struct drm_i915_private
*dev_priv)
static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
u64 start, u64 length)
{
- struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
unsigned int first_entry = start >> PAGE_SHIFT;
unsigned int pde = first_entry / GEN6_PTES;
unsigned int pte = first_entry % GEN6_PTES;
unsigned int num_entries = length >> PAGE_SHIFT;
- gen6_pte_t scratch_pte =
+ const gen6_pte_t scratch_pte =
vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
while (num_entries) {
- struct i915_page_table *pt = ppgtt->pd.page_table[pde++];
- unsigned int end = min(pte + num_entries, GEN6_PTES);
+ struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
+ const unsigned int end = min(pte + num_entries, GEN6_PTES);
+ const unsigned int count = end - pte;
gen6_pte_t *vaddr;
- num_entries -= end - pte;
+ GEM_BUG_ON(pt == vm->scratch_pt);
+
+ num_entries -= count;
+
+ GEM_BUG_ON(count > pt->used_ptes);
+ pt->used_ptes -= count;
+ if (!pt->used_ptes)
+ ppgtt->scan_for_unused_pt = true;
/*
* Note that the hw doesn't support removing PDE on the fly
@@ -1859,6 +1867,8 @@ static void gen6_ppgtt_insert_entries(struct
i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma);
gen6_pte_t *vaddr;
+ GEM_BUG_ON(ppgtt->pd.page_table[act_pt] == vm->scratch_pt);
+
vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
do {
vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
@@ -1894,6 +1904,8 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
bool flush = false;
gen6_for_each_pde(pt, >base.pd, start, length, pde) {
+ const unsigned int count = gen6_pte_count(start, length);
+
if (pt == vm->scratch_pt) {
pt = alloc_pt(vm);
if (IS_ERR(pt))
@@ -1907,7 +1919,11 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
gen6_write_pde(ppgtt, pde, pt);
flush = true;
}
+
+ GEM_BUG_ON(pt->used_ptes);
}
+
+ pt->used_ptes += count;
}
if (flush) {
@@ -2009,6 +2025,24 @@ static int pd_vma_bind(struct i915_vma *vma,
static void pd_vma_unbind(struct i915_vma *vma)
{
+ struct gen6_hw_ppgtt *ppgtt = vma->private;
+ struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt;
+ struct i915_page_table *pt;
+ unsigned int pde;
+
+ if (!ppgtt->scan_for_unused_pt)
+ return;
+
+ /* Free all no longer used page tables */
+ gen6_for_all_pdes(pt, >base.pd, pde) {
+ if (pt->used_ptes || pt == scratch_pt)
+ continue;
+
+ free_pt(>base.vm, pt);
+ ppgtt->base.pd.page_table[pde] = scratch_pt;
+ }
+
+ ppgtt->scan_for_unused_pt = false;
}
static const struct i915_vma_ops pd_vma_ops = {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c20a4f06db37..dc98830fae69 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -414,6 +414,7 @@ struct gen6_hw_ppgtt {
gen6_pte_t __iomem *pd_addr;
unsigned int pin_count;
+ bool scan_for_unused_pt;
int (*switch_mm)(struct gen6_hw_ppgtt *ppgtt, struct i915_request *rq);
};
--
2.17.1
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[Intel-gfx] [PATCH 19/20] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
If we know that the user cannot access the GGTT, by virtue of having a segregated memory area, we can skip clearing the unused entries as they cannot be accessed. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 75c8cb75a0ce..51352b90de2b 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3458,7 +3458,9 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->vm.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; - ggtt->vm.clear_range = gen6_ggtt_clear_range; + ggtt->vm.clear_range = nop_clear_range; + if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) + ggtt->vm.clear_range = gen6_ggtt_clear_range; ggtt->vm.insert_page = gen6_ggtt_insert_page; ggtt->vm.insert_entries = gen6_ggtt_insert_entries; ggtt->vm.cleanup = gen6_gmch_remove; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/20] drm/i915/gtt: Reorder aliasing_ppgtt fini
To allow ourselves to use a first class vma for the aliasing_ppgtt page directory, we have to reorder the shutdown on module unload to remove and unpin the aliasing_ppgtt before complaining about any objects left in the GGTT. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f9f0bffa727e..bd338bccf706 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2891,15 +2891,11 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) ggtt->vm.closed = true; mutex_lock(_priv->drm.struct_mutex); + i915_gem_fini_aliasing_ppgtt(dev_priv); + GEM_BUG_ON(!list_empty(>vm.active_list)); list_for_each_entry_safe(vma, vn, >vm.inactive_list, vm_link) WARN_ON(i915_vma_unbind(vma)); - mutex_unlock(_priv->drm.struct_mutex); - - i915_gem_cleanup_stolen(_priv->drm); - - mutex_lock(_priv->drm.struct_mutex); - i915_gem_fini_aliasing_ppgtt(dev_priv); if (drm_mm_node_allocated(>error_capture)) drm_mm_remove_node(>error_capture); @@ -2921,6 +2917,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) arch_phys_wc_del(ggtt->mtrr); io_mapping_fini(>iomap); + + i915_gem_cleanup_stolen(_priv->drm); } static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/20] drm/i915/gtt: Subclass gen6_hw_ppgtt
The legacy gen6 ppgtt needs a little more hand holding than gen8+, and
so requires a larger structure. As I intend to make this slightly more
complicated in the future, separate the gen6 from the core gen8 hw
struct by subclassing. This patch moves the gen6 only features out to
gen6_hw_ppgtt and pipes the new type everywhere that needs it.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 108 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 21 +++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 -
5 files changed, 79 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 93bd64e5deb3..49e02dee07e0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1636,20 +1636,20 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
return ERR_PTR(err);
}
-static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
+static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
{
- struct i915_address_space *vm = >vm;
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+ struct i915_address_space *vm = >vm;
struct i915_page_table *unused;
gen6_pte_t scratch_pte;
u32 pd_entry, pte, pde;
- u32 start = 0, length = ppgtt->vm.total;
scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
- gen6_for_each_pde(unused, >pd, start, length, pde) {
+ gen6_for_all_pdes(unused, >pd, pde) {
u32 expected;
gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
+ const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
pd_entry = readl(ppgtt->pd_addr + pde);
expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
@@ -1660,7 +1660,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
expected);
seq_printf(m, "\tPDE: %x\n", pd_entry);
- pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]);
+ pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
for (pte = 0; pte < GEN6_PTES; pte+=4) {
unsigned long va =
@@ -1688,7 +1688,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
}
/* Write pde (index) from the page directory @pd to the page table @pt */
-static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt,
+static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
const unsigned int pde,
const struct i915_page_table *pt)
{
@@ -1699,26 +1699,27 @@ static inline void gen6_write_pde(const struct
i915_hw_ppgtt *ppgtt,
/* Write all the page tables found in the ppgtt structure to incrementing page
* directories. */
-static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
+static void gen6_write_page_range(struct i915_hw_ppgtt *base,
u32 start, u32 length)
{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_page_table *pt;
unsigned int pde;
- gen6_for_each_pde(pt, >pd, start, length, pde)
+ gen6_for_each_pde(pt, >pd, start, length, pde)
gen6_write_pde(ppgtt, pde, pt);
- mark_tlbs_dirty(ppgtt);
- gen6_ggtt_invalidate(ppgtt->vm.i915);
+ mark_tlbs_dirty(base);
+ gen6_ggtt_invalidate(base->vm.i915);
}
-static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
+static inline u32 get_pd_offset(struct gen6_hw_ppgtt *ppgtt)
{
- GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
- return ppgtt->pd.base.ggtt_offset << 10;
+ GEM_BUG_ON(ppgtt->base.pd.base.ggtt_offset & 0x3f);
+ return ppgtt->base.pd.base.ggtt_offset << 10;
}
-static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
struct intel_engine_cs *engine = rq->engine;
@@ -1740,7 +1741,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
return 0;
}
-static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt,
struct i915_request *rq)
{
struct intel_engine_cs *engine = rq->engine;
@@ -1762,7 +1763,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
return 0;
}
-static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
+static int gen6_mm_switch(struct gen6_hw_ppgtt *ppgtt,
[Intel-gfx] [PATCH 08/20] drm/i915/gtt: Push allocation to hw ppgtt constructor
In the next patch, we will subclass the gen6 hw_ppgtt. In order, for the
two different generations of hw ppgtt stucts to be of different size,
push the allocation down to the constructor.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 140 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 16 +-
2 files changed, 83 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b9306220724d..93bd64e5deb3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1562,32 +1562,36 @@ static int gen8_preallocate_top_level_pdp(struct
i915_hw_ppgtt *ppgtt)
* space.
*
*/
-static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
{
- struct i915_address_space *vm = >vm;
- struct drm_i915_private *dev_priv = vm->i915;
- int ret;
+ struct i915_hw_ppgtt *ppgtt;
+ int err;
+
+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+ if (!ppgtt)
+ return ERR_PTR(-ENOMEM);
+
+ ppgtt->vm.i915 = i915;
+ ppgtt->vm.dma = >drm.pdev->dev;
- ppgtt->vm.total = USES_FULL_48BIT_PPGTT(dev_priv) ?
+ ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
1ULL << 48 :
1ULL << 32;
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
ppgtt->vm.pt_kmap_wc = true;
- ret = gen8_init_scratch(>vm);
- if (ret) {
- ppgtt->vm.total = 0;
- return ret;
- }
+ err = gen8_init_scratch(>vm);
+ if (err)
+ goto err_free;
- if (use_4lvl(vm)) {
- ret = setup_px(>vm, >pml4);
- if (ret)
- goto free_scratch;
+ if (use_4lvl(>vm)) {
+ err = setup_px(>vm, >pml4);
+ if (err)
+ goto err_scratch;
gen8_initialize_pml4(>vm, >pml4);
@@ -1595,15 +1599,15 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
} else {
- ret = __pdp_init(>vm, >pdp);
- if (ret)
- goto free_scratch;
+ err = __pdp_init(>vm, >pdp);
+ if (err)
+ goto err_scratch;
- if (intel_vgpu_active(dev_priv)) {
- ret = gen8_preallocate_top_level_pdp(ppgtt);
- if (ret) {
+ if (intel_vgpu_active(i915)) {
+ err = gen8_preallocate_top_level_pdp(ppgtt);
+ if (err) {
__pdp_fini(>pdp);
- goto free_scratch;
+ goto err_scratch;
}
}
@@ -1612,7 +1616,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
}
- if (intel_vgpu_active(dev_priv))
+ if (intel_vgpu_active(i915))
gen8_ppgtt_notify_vgt(ppgtt, true);
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
@@ -1623,11 +1627,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->vm.vma_ops.clear_pages = clear_pages;
- return 0;
+ return ppgtt;
-free_scratch:
+err_scratch:
gen8_free_scratch(>vm);
- return ret;
+err_free:
+ kfree(ppgtt);
+ return ERR_PTR(err);
}
static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
@@ -1638,8 +1644,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
u32 pd_entry, pte, pde;
u32 start = 0, length = ppgtt->vm.total;
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
-I915_CACHE_LLC, 0);
+ scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
gen6_for_each_pde(unused, >pd, start, length, pde) {
u32 expected;
@@ -2027,36 +2032,41 @@ static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt,
ppgtt->pd.page_table[pde] = ppgtt->vm.scratch_pt;
}
-static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
- struct drm_i915_private *dev_priv = ppgtt->vm.i915;
- struct i915_ggtt *ggtt = _priv->ggtt;
- int
[Intel-gfx] [PATCH 07/20] drm/i915: Decouple vma vfuncs from vm
To allow for future non-object backed vma, we need to be able to
specialise the callbacks for binding, et al, the vma. For example,
instead of calling vma->vm->bind_vma(), we now call
vma->ops->bind_vma(). This gives us the opportunity to later override the
operation for a custom vma.
v2: flip order of unbind/bind
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 57 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 27 +++
drivers/gpu/drm/i915/i915_vma.c | 11 +++--
drivers/gpu/drm/i915/i915_vma.h | 1 +
drivers/gpu/drm/i915/selftests/mock_gtt.c | 18 +++
5 files changed, 66 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1a158bdf858b..b9306220724d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1616,12 +1616,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
gen8_ppgtt_notify_vgt(ppgtt, true);
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
- ppgtt->vm.bind_vma = gen8_ppgtt_bind_vma;
- ppgtt->vm.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.set_pages = ppgtt_set_pages;
- ppgtt->vm.clear_pages = clear_pages;
ppgtt->debug_dump = gen8_dump_ppgtt;
+ ppgtt->vm.vma_ops.bind_vma= gen8_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->vm.vma_ops.clear_pages = clear_pages;
+
return 0;
free_scratch:
@@ -2059,13 +2060,14 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->vm.insert_entries = gen6_ppgtt_insert_entries;
- ppgtt->vm.bind_vma = gen6_ppgtt_bind_vma;
- ppgtt->vm.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.set_pages = ppgtt_set_pages;
- ppgtt->vm.clear_pages = clear_pages;
ppgtt->vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->debug_dump = gen6_dump_ppgtt;
+ ppgtt->vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->vm.vma_ops.clear_pages = clear_pages;
+
DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
ppgtt->node.size >> 20,
ppgtt->node.start / PAGE_SIZE);
@@ -2793,11 +2795,11 @@ int i915_gem_init_aliasing_ppgtt(struct
drm_i915_private *i915)
i915->mm.aliasing_ppgtt = ppgtt;
- GEM_BUG_ON(ggtt->vm.bind_vma != ggtt_bind_vma);
- ggtt->vm.bind_vma = aliasing_gtt_bind_vma;
+ GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
+ ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
- GEM_BUG_ON(ggtt->vm.unbind_vma != ggtt_unbind_vma);
- ggtt->vm.unbind_vma = aliasing_gtt_unbind_vma;
+ GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
+ ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
return 0;
@@ -2817,8 +2819,8 @@ void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915)
i915_ppgtt_put(ppgtt);
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
+ ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
+ ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
}
int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
@@ -3310,10 +3312,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
ggtt->vm.cleanup = gen6_gmch_remove;
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
- ggtt->vm.set_pages = ggtt_set_pages;
- ggtt->vm.clear_pages = clear_pages;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
@@ -3331,6 +3329,11 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->invalidate = gen6_ggtt_invalidate;
+ ggtt->vm.vma_ops.bind_vma= ggtt_bind_vma;
+ ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
+ ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
+ ggtt->vm.vma_ops.clear_pages = clear_pages;
+
setup_private_pat(dev_priv);
return ggtt_probe_common(ggtt, size);
@@ -3370,10 +3373,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
- ggtt->vm.bind_vma = ggtt_bind_vma;
- ggtt->vm.unbind_vma = ggtt_unbind_vma;
- ggtt->vm.set_pages = ggtt_set_pages;
- ggtt->vm.clear_pages =
[Intel-gfx] [PATCH 05/20] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories
When we update the gen6 ppgtt page directories, we do so by writing the
new address into a reserved slot in the GGTT. It appears that when the
GPU reads that entry from the gsm, it uses its small cache and that we
need to invalidate that cache after writing. We don't see an issue
currently as we prefill the ppgtt page directories on creation; and only
create the single aliasing_ppgtt long before we start using the GGTT
(and so before the cache mayhave a conflicting entry).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 284ae9574f03..60a127af9871 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1687,8 +1687,8 @@ static inline void gen6_write_pde(const struct
i915_hw_ppgtt *ppgtt,
const struct i915_page_table *pt)
{
/* Caller needs to make sure the write completes if necessary */
- writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
- ppgtt->pd_addr + pde);
+ iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
+ ppgtt->pd_addr + pde);
}
/* Write all the page tables found in the ppgtt structure to incrementing page
@@ -1703,7 +1703,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt,
gen6_write_pde(ppgtt, pde, pt);
mark_tlbs_dirty(ppgtt);
- wmb();
+ gen6_ggtt_invalidate(ppgtt->vm.i915);
}
static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1919,7 +1919,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
if (flush) {
mark_tlbs_dirty(ppgtt);
- wmb();
+ gen6_ggtt_invalidate(ppgtt->vm.i915);
}
return 0;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/20] drm/i915: Prepare for non-object vma
In order to allow ourselves to use VMA to wrap other entities other than
GEM objects, we need to allow for the vma->obj backpointer to be NULL.
In most cases, we know we are operating on a GEM object and its vma, but
we need the core code (such as i915_vma_pin/insert/bind/unbind) to work
regardless of the innards.
The remaining eyesore here is vma->obj->cache_level and related (but
less of an issue) vma->obj->gt_ro. With a bit of care we should mirror
those on the vma itself.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +
drivers/gpu/drm/i915/i915_vma.c | 96 ---
drivers/gpu/drm/i915/i915_vma.h | 2 +-
4 files changed, 65 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 60a127af9871..1a158bdf858b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3588,8 +3588,11 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
if (!i915_vma_unbind(vma))
continue;
- WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
- WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
+ WARN_ON(i915_vma_bind(vma,
+ obj ? obj->cache_level : 0,
+ PIN_UPDATE));
+ if (obj)
+ WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
}
ggtt->vm.closed = false;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 758234d20f4e..df524c9cad40 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1050,6 +1050,9 @@ static u32 capture_error_bo(struct drm_i915_error_buffer
*err,
int i = 0;
list_for_each_entry(vma, head, vm_link) {
+ if (!vma->obj)
+ continue;
+
if (pinned_only && !i915_vma_is_pinned(vma))
continue;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 912f16ffe7ee..b71265066cd1 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -345,7 +345,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
void i915_vma_unpin_iomap(struct i915_vma *vma)
{
- lockdep_assert_held(>obj->base.dev->struct_mutex);
+ lockdep_assert_held(>vm->i915->drm.struct_mutex);
GEM_BUG_ON(vma->iomap == NULL);
@@ -365,6 +365,7 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma)
return;
obj = vma->obj;
+ GEM_BUG_ON(!obj);
i915_vma_unpin(vma);
i915_vma_close(vma);
@@ -489,7 +490,7 @@ static int
i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
struct drm_i915_private *dev_priv = vma->vm->i915;
- struct drm_i915_gem_object *obj = vma->obj;
+ unsigned int cache_level;
u64 start, end;
int ret;
@@ -524,16 +525,21 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
* attempt to find space.
*/
if (size > end) {
- DRM_DEBUG("Attempting to bind an object larger than the
aperture: request=%llu [object=%zd] > %s aperture=%llu\n",
- size, obj->base.size,
- flags & PIN_MAPPABLE ? "mappable" : "total",
+ DRM_DEBUG("Attempting to bind an object larger than the
aperture: request=%llu > %s aperture=%llu\n",
+ size, flags & PIN_MAPPABLE ? "mappable" : "total",
end);
return -ENOSPC;
}
- ret = i915_gem_object_pin_pages(obj);
- if (ret)
- return ret;
+ if (vma->obj) {
+ ret = i915_gem_object_pin_pages(vma->obj);
+ if (ret)
+ return ret;
+
+ cache_level = vma->obj->cache_level;
+ } else {
+ cache_level = 0;
+ }
GEM_BUG_ON(vma->pages);
@@ -550,7 +556,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
ret = i915_gem_gtt_reserve(vma->vm, >node,
- size, offset, obj->cache_level,
+ size, offset, cache_level,
flags);
if (ret)
goto err_clear;
@@ -589,7 +595,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
ret = i915_gem_gtt_insert(vma->vm, >node,
- size, alignment,
[Intel-gfx] [PATCH 10/20] drm/i915/gtt Onionify error handling for gen6_ppgtt_create
Pull the empty stubs together into the top level gen6_ppgtt_create, and
tear each one down on error in proper onion order (rather than use
Joonas' pet hate of calling the cleanup function in indeterminable
state).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 81 ++---
1 file changed, 39 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 49e02dee07e0..f9f0bffa727e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1936,7 +1936,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
return -ENOMEM;
}
-static int gen6_init_scratch(struct i915_address_space *vm)
+static int gen6_ppgtt_init_scratch(struct i915_address_space *vm)
{
int ret;
@@ -1955,33 +1955,37 @@ static int gen6_init_scratch(struct i915_address_space
*vm)
return 0;
}
-static void gen6_free_scratch(struct i915_address_space *vm)
+static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
{
free_pt(vm, vm->scratch_pt);
cleanup_scratch_page(vm);
}
-static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt)
{
- struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
struct i915_page_table *pt;
u32 pde;
- drm_mm_remove_node(>node);
-
gen6_for_all_pdes(pt, >base.pd, pde)
- if (pt != vm->scratch_pt)
- free_pt(vm, pt);
+ if (pt != ppgtt->base.vm.scratch_pt)
+ free_pt(>base.vm, pt);
+}
- gen6_free_scratch(vm);
+static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
+
+ drm_mm_remove_node(>node);
+
+ gen6_ppgtt_free_pd(ppgtt);
+ gen6_ppgtt_free_scratch(vm);
}
static int gen6_ppgtt_allocate_page_directories(struct gen6_hw_ppgtt *ppgtt)
{
- struct i915_address_space *vm = >base.vm;
struct drm_i915_private *dev_priv = ppgtt->base.vm.i915;
struct i915_ggtt *ggtt = _priv->ggtt;
- int ret;
+ int err;
/* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -1989,17 +1993,13 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
*/
BUG_ON(!drm_mm_initialized(>vm.mm));
- ret = gen6_init_scratch(vm);
- if (ret)
- return ret;
-
- ret = i915_gem_gtt_insert(>vm, >node,
+ err = i915_gem_gtt_insert(>vm, >node,
GEN6_PD_SIZE, GEN6_PD_ALIGN,
I915_COLOR_UNEVICTABLE,
0, ggtt->vm.total,
PIN_HIGH);
- if (ret)
- goto err_out;
+ if (err)
+ return err;
if (ppgtt->node.start < ggtt->mappable_end)
DRM_DEBUG("Forced to use aperture for PDEs\n");
@@ -2011,15 +2011,6 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
ppgtt->base.pd.base.ggtt_offset / sizeof(gen6_pte_t);
return 0;
-
-err_out:
- gen6_free_scratch(vm);
- return ret;
-}
-
-static int gen6_ppgtt_alloc(struct gen6_hw_ppgtt *ppgtt)
-{
- return gen6_ppgtt_allocate_page_directories(ppgtt);
}
static void gen6_scratch_va_range(struct gen6_hw_ppgtt *ppgtt,
@@ -2045,6 +2036,18 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.i915 = i915;
ppgtt->base.vm.dma = >drm.pdev->dev;
+ ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+
+ ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
+ ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
+ ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
+ ppgtt->base.debug_dump = gen6_dump_ppgtt;
+
+ ppgtt->base.vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
+
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
if (intel_vgpu_active(i915) || IS_GEN6(i915))
ppgtt->switch_mm = gen6_mm_switch;
@@ -2055,28 +2058,20 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
else
BUG();
- err = gen6_ppgtt_alloc(ppgtt);
+ err = gen6_ppgtt_init_scratch(>base.vm);
if (err)
goto err_free;
- ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+ err =
[Intel-gfx] [PATCH 14/20] drm/i915/gtt: Lazily allocate page directories for gen7
As we were only supporting aliasing_ppgtt on gen7 for some time, we
saved a few checks by preallocating the page directories on creation.
However, since we need 2MiB of page directories for each ppgtt, to
support arbitrary numbers of user contexts, we need to be more prudent
in our allocations, and defer the page allocation until it is used. We
don't recover unused pages yet as we found that doing so on the fly
(i.e. altering TLB entries) would confuse the GPU.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++--
1 file changed, 26 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a69cd1b5f8f2..660596ebd3c1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -190,11 +190,19 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
return 1;
}
-static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 unused)
+static int ppgtt_bind_vma(struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 unused)
{
u32 pte_flags;
+ int err;
+
+ if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
+ err = vma->vm->allocate_va_range(vma->vm,
+vma->node.start, vma->size);
+ if (err)
+ return err;
+ }
/* Currently applicable only to VLV */
pte_flags = 0;
@@ -206,22 +214,6 @@ static int gen6_ppgtt_bind_vma(struct i915_vma *vma,
return 0;
}
-static int gen8_ppgtt_bind_vma(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 unused)
-{
- int ret;
-
- if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
- ret = vma->vm->allocate_va_range(vma->vm,
-vma->node.start, vma->size);
- if (ret)
- return ret;
- }
-
- return gen6_ppgtt_bind_vma(vma, cache_level, unused);
-}
-
static void ppgtt_unbind_vma(struct i915_vma *vma)
{
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
@@ -1622,7 +1614,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
ppgtt->debug_dump = gen8_dump_ppgtt;
- ppgtt->vm.vma_ops.bind_vma= gen8_ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.bind_vma= ppgtt_bind_vma;
ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->vm.vma_ops.clear_pages = clear_pages;
@@ -1837,7 +1829,8 @@ static void gen6_ppgtt_clear_range(struct
i915_address_space *vm,
num_entries -= end - pte;
- /* Note that the hw doesn't support removing PDE on the fly
+ /*
+* Note that the hw doesn't support removing PDE on the fly
* (they are cached inside the context with no means to
* invalidate the cache), so we can only reset the PTE
* entries back to scratch.
@@ -2113,12 +2106,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+ ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.debug_dump = gen6_dump_ppgtt;
- ppgtt->base.vm.vma_ops.bind_vma= gen6_ppgtt_bind_vma;
+ ppgtt->base.vm.vma_ops.bind_vma= ppgtt_bind_vma;
ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
@@ -2143,14 +2137,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
goto err_scratch;
}
- err = gen6_alloc_va_range(>base.vm, 0, ppgtt->base.vm.total);
- if (err)
- goto err_vma;
-
return >base;
-err_vma:
- i915_vma_destroy(ppgtt->vma);
err_scratch:
gen6_ppgtt_free_scratch(>base.vm);
err_free:
@@ -2746,8 +2734,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
if (flags & I915_VMA_LOCAL_BIND) {
struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
- if (!(vma->flags & I915_VMA_LOCAL_BIND) &&
- appgtt->vm.allocate_va_range) {
+ if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
[Intel-gfx] [PATCH 13/20] drm/i915/gtt: Only keep gen6 page directories pinned while active
In order to be able to evict the gen6 ppgtt, we have to unpin it at some
point. We can simply use our context activity tracking to know when the
ppgtt is no longer in use by hardware, and so only keep it pinned while
being used a request.
For the kernel_context (and thus aliasing_ppgtt), it remains pinned at
all times, as the kernel_context itself is pinned at all times.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++
3 files changed, 54 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4e27e9950e45..a69cd1b5f8f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1973,7 +1973,6 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
- i915_vma_unpin(ppgtt->vma);
i915_vma_destroy(ppgtt->vma);
gen6_ppgtt_free_pd(ppgtt);
@@ -2065,10 +2064,19 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
return vma;
}
-static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+ /*
+* Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
+* which will be pinned into every active context.
+* (When vma->pin_count becomes atomic, I expect we will naturally
+* need a larger, unpacked, type and kill this redundancy.)
+*/
+ if (ppgtt->pin_count++)
+ return 0;
+
/*
* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -2079,6 +2087,17 @@ static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
PIN_GLOBAL | PIN_HIGH);
}
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+
+ GEM_BUG_ON(!ppgtt->pin_count);
+ if (--ppgtt->pin_count)
+ return;
+
+ i915_vma_unpin(ppgtt->vma);
+}
+
static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
struct i915_ggtt * const ggtt = >ggtt;
@@ -2128,21 +2147,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (err)
goto err_vma;
- err = gen6_ppgtt_pin(>base);
- if (err)
- goto err_pd;
-
- DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
-ppgtt->vma->node.size >> 20,
-ppgtt->vma->node.start / PAGE_SIZE);
-
- DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
-ppgtt->base.pd.base.ggtt_offset << 10);
-
return >base;
-err_pd:
- gen6_ppgtt_free_pd(ppgtt);
err_vma:
i915_vma_destroy(ppgtt->vma);
err_scratch:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c2f270c90bea..c20a4f06db37 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -413,6 +413,8 @@ struct gen6_hw_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
+ unsigned int pin_count;
+
int (*switch_mm)(struct gen6_hw_ppgtt *ppgtt, struct i915_request *rq);
};
@@ -627,6 +629,9 @@ static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt)
kref_put(>ref, i915_ppgtt_release);
}
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
+
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d4ba522dd52f..c881af3d5f59 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1195,6 +1195,27 @@ static void intel_ring_context_destroy(struct
intel_context *ce)
__i915_gem_object_release_unless_active(ce->state->obj);
}
+static int __context_pin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+ int err = 0;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+ if (ppgtt)
+ err = gen6_ppgtt_pin(ppgtt);
+
+ return err;
+}
+
+static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+
[Intel-gfx] [PATCH 12/20] drm/i915/gtt: Make gen6 page directories evictable
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the creation of a custom vma to wrap the page
directory as opposed to a GEM object.
In this patch, we leave the page directories pinned upon creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 263
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 7 +
3 files changed, 161 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd338bccf706..4e27e9950e45 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1640,50 +1640,55 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base,
struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_address_space *vm = >vm;
- struct i915_page_table *unused;
- gen6_pte_t scratch_pte;
- u32 pd_entry, pte, pde;
-
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
-
- gen6_for_all_pdes(unused, >pd, pde) {
- u32 expected;
- gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
- pd_entry = readl(ppgtt->pd_addr + pde);
- expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
-
- if (pd_entry != expected)
- seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
- pde,
- pd_entry,
- expected);
- seq_printf(m, "\tPDE: %x\n", pd_entry);
-
- pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
-
- for (pte = 0; pte < GEN6_PTES; pte+=4) {
- unsigned long va =
- (pde * PAGE_SIZE * GEN6_PTES) +
- (pte * PAGE_SIZE);
+ const gen6_pte_t scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ struct i915_page_table *pt;
+ u32 pte, pde;
+
+ gen6_for_all_pdes(pt, >pd, pde) {
+ gen6_pte_t *vaddr;
+
+ if (pt == base->vm.scratch_pt)
+ continue;
+
+ if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
+ u32 expected =
+ GEN6_PDE_ADDR_ENCODE(px_dma(pt)) |
+ GEN6_PDE_VALID;
+ u32 pd_entry = readl(ppgtt->pd_addr + pde);
+
+ if (pd_entry != expected)
+ seq_printf(m,
+ "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
+ pde,
+ pd_entry,
+ expected);
+
+ seq_printf(m, "\tPDE: %x\n", pd_entry);
+ }
+
+ vaddr = kmap_atomic_px(base->pd.page_table[pde]);
+ for (pte = 0; pte < GEN6_PTES; pte += 4) {
int i;
- bool found = false;
+
for (i = 0; i < 4; i++)
- if (pt_vaddr[pte + i] != scratch_pte)
- found = true;
- if (!found)
+ if (vaddr[pte + i] != scratch_pte)
+ break;
+ if (i == 4)
continue;
- seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
+ seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
+ pde, pte,
+ (pde * GEN6_PTES + pte) * PAGE_SIZE);
for (i = 0; i < 4; i++) {
- if (pt_vaddr[pte + i] != scratch_pte)
- seq_printf(m, " %08x", pt_vaddr[pte +
i]);
+ if (vaddr[pte + i] != scratch_pte)
+ seq_printf(m, " %08x", vaddr[pte + i]);
else
- seq_puts(m, " SCRATCH ");
+ seq_puts(m, " SCRATCH");
}
seq_puts(m, "\n");
}
- kunmap_atomic(pt_vaddr);
+ kunmap_atomic(vaddr);
}
}
@@ -1697,22 +1702,6 @@
[Intel-gfx] [PATCH 01/20] drm/i915: Apply batch location restrictions before pinning
We special case the position of the batch within the GTT to prevent
negative self-relocation deltas from underflowing. However, that
restriction is being applied after a trial pin of the batch in its
current position. Thus we are not rejecting an invalid location if the
batch has been before, leading to an assertion if we happen to need to
rearrange the entire payload. In the worst case, this may cause a GPU
hang on gen7 or perhaps missing state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=105720
Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the
execobjects array")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Martin Peres
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 49 --
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index eefd449502e2..2d2eb3075960 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -489,7 +489,9 @@ eb_validate_vma(struct i915_execbuffer *eb,
}
static int
-eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
+eb_add_vma(struct i915_execbuffer *eb,
+ unsigned int i, unsigned batch_idx,
+ struct i915_vma *vma)
{
struct drm_i915_gem_exec_object2 *entry = >exec[i];
int err;
@@ -522,6 +524,24 @@ eb_add_vma(struct i915_execbuffer *eb, unsigned int i,
struct i915_vma *vma)
eb->flags[i] = entry->flags;
vma->exec_flags = >flags[i];
+ /*
+* SNA is doing fancy tricks with compressing batch buffers, which leads
+* to negative relocation deltas. Usually that works out ok since the
+* relocate address is still positive, except when the batch is placed
+* very low in the GTT. Ensure this doesn't happen.
+*
+* Note that actual hangs have only been observed on gen7, but for
+* paranoia do it everywhere.
+*/
+ if (i == batch_idx) {
+ if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
+ eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
+ if (eb->reloc_cache.has_fence)
+ eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
+
+ eb->batch = vma;
+ }
+
err = 0;
if (eb_pin_vma(eb, entry, vma)) {
if (entry->offset != vma->node.start) {
@@ -716,7 +736,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = >ctx->handles_vma;
struct drm_i915_gem_object *obj;
- unsigned int i;
+ unsigned int i, batch;
int err;
if (unlikely(i915_gem_context_is_closed(eb->ctx)))
@@ -728,6 +748,8 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
INIT_LIST_HEAD(>relocs);
INIT_LIST_HEAD(>unbound);
+ batch = eb_batch_index(eb);
+
for (i = 0; i < eb->buffer_count; i++) {
u32 handle = eb->exec[i].handle;
struct i915_lut_handle *lut;
@@ -770,33 +792,16 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
lut->handle = handle;
add_vma:
- err = eb_add_vma(eb, i, vma);
+ err = eb_add_vma(eb, i, batch, vma);
if (unlikely(err))
goto err_vma;
GEM_BUG_ON(vma != eb->vma[i]);
GEM_BUG_ON(vma->exec_flags != >flags[i]);
+ GEM_BUG_ON(drm_mm_node_allocated(>node) &&
+ eb_vma_misplaced(>exec[i], vma, eb->flags[i]));
}
- /* take note of the batch buffer before we might reorder the lists */
- i = eb_batch_index(eb);
- eb->batch = eb->vma[i];
- GEM_BUG_ON(eb->batch->exec_flags != >flags[i]);
-
- /*
-* SNA is doing fancy tricks with compressing batch buffers, which leads
-* to negative relocation deltas. Usually that works out ok since the
-* relocate address is still positive, except when the batch is placed
-* very low in the GTT. Ensure this doesn't happen.
-*
-* Note that actual hangs have only been observed on gen7, but for
-* paranoia do it everywhere.
-*/
- if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
- eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
- if (eb->reloc_cache.has_fence)
- eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
-
eb->args->flags |= __EXEC_VALIDATED;
return eb_reserve(eb);
--
2.17.1
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[Intel-gfx] [PATCH 03/20] drm/i915/ringbuffer: Brute force context restore
An issue encountered with switching mm on gen7 is that the GPU likes to
hang (with the VS unit busy) when told to force restore the current
context. We can simply workaround this by substituting the
MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
forcing the context to be saved and restored; thereby reloading the
PP_DIR registers and updating the modified page directory!
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 917ca1552600..3df802cc3710 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1458,6 +1458,7 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
INTEL_INFO(i915)->num_rings - 1 :
0;
+ bool force_restore = false;
int len;
u32 *cs;
@@ -1471,6 +1472,12 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+ if (flags & MI_FORCE_RESTORE) {
+ GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
+ flags &= ~MI_FORCE_RESTORE;
+ force_restore = true;
+ len += 2;
+ }
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1496,6 +1503,20 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
}
*cs++ = MI_NOOP;
+ if (force_restore) {
+ /*
+* The HW doesn't handle being told to restore the current
+* context very well. Quite often it likes goes to go off and
+* sulk, especially when it is meant to be reloading PP_DIR.
+* A very simple fix to force the reload is to simply switch
+* away from the current context and back again.
+*/
+ *cs++ = MI_SET_CONTEXT;
+ *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
+ engine)->state) |
+ MI_MM_SPACE_GTT |
+ MI_RESTORE_INHIBIT;
+ }
*cs++ = MI_SET_CONTEXT;
*cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
/*
@@ -1585,11 +1606,14 @@ static int switch_context(struct i915_request *rq)
to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
engine->legacy_active_ppgtt = to_mm;
- hw_flags = MI_FORCE_RESTORE;
+
+ if (to_ctx == from_ctx) {
+ hw_flags = MI_FORCE_RESTORE;
+ from_ctx = NULL;
+ }
}
- if (rq->hw_context->state &&
- (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
+ if (rq->hw_context->state && to_ctx != from_ctx) {
GEM_BUG_ON(engine->id != RCS);
/*
--
2.17.1
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[Intel-gfx] [PATCH 02/20] drm/i915/ringbuffer: Make order of mmio to CCID/PP_DIR consistent with switch_context()
When using CS commands, PP_DIR is not sampled until the context is
loaded, but when doing manual mmio after reset we load the context
before the mm. Let's switch this over for consistency.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 65811e2fa7da..917ca1552600 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -574,16 +574,7 @@ static void reset_ring(struct intel_engine_cs *engine,
struct intel_context *ce = request->hw_context;
struct i915_hw_ppgtt *ppgtt;
- if (ce->state) {
- I915_WRITE(CCID,
- i915_ggtt_offset(ce->state) |
- BIT(8) /* must be set! */ |
- CCID_EXTENDED_STATE_SAVE |
- CCID_EXTENDED_STATE_RESTORE |
- CCID_EN);
- }
-
- ppgtt = request->gem_context->ppgtt ?:
engine->i915->mm.aliasing_ppgtt;
+ ppgtt = request->gem_context->ppgtt ?:
dev_priv->mm.aliasing_ppgtt;
if (ppgtt) {
u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
@@ -600,6 +591,15 @@ static void reset_ring(struct intel_engine_cs *engine,
ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
}
+ if (ce->state) {
+ I915_WRITE(CCID,
+ i915_ggtt_offset(ce->state) |
+ BIT(8) /* must be set! */ |
+ CCID_EXTENDED_STATE_SAVE |
+ CCID_EXTENDED_STATE_RESTORE |
+ CCID_EN);
+ }
+
/* If the rq hung, jump to its breadcrumb and skip the batch */
if (request->fence.error == -EIO)
request->ring->head = request->postfix;
--
2.17.1
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[Intel-gfx] [PATCH 04/20] drm/i915/ringbuffer: Force restore of mm after failed context switch
If we interrupt the context switch and unwind, we leave the to_mm
believing that we have cleared the dirty bit for this engine (but the
LRI will never take place). Just in case we immediately reload the same
context, mark this engine as dirty so that we force the LRI to reload
the PD.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3df802cc3710..93b5f4a8316d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1591,6 +1591,7 @@ static int switch_context(struct i915_request *rq)
to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
struct i915_gem_context *from_ctx = engine->legacy_active_context;
struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
+ unsigned int unwind_mm = 0;
u32 hw_flags = 0;
int ret, i;
@@ -1604,7 +1605,11 @@ static int switch_context(struct i915_request *rq)
if (ret)
goto err;
- to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
+ if (to_mm->pd_dirty_rings & intel_engine_flag(engine)) {
+ unwind_mm = intel_engine_flag(engine);
+ to_mm->pd_dirty_rings &= ~unwind_mm;
+ }
+
engine->legacy_active_ppgtt = to_mm;
if (to_ctx == from_ctx) {
@@ -1651,6 +1656,8 @@ static int switch_context(struct i915_request *rq)
err_ctx:
engine->legacy_active_context = from_ctx;
err_mm:
+ if (unwind_mm)
+ to_mm->pd_dirty_rings |= unwind_mm;
engine->legacy_active_ppgtt = from_mm;
err:
return ret;
--
2.17.1
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[Intel-gfx] [PATCH 20/20] RFT drm/i915/gtt: Enable full-ppgtt by default everywhere
Let's see if we have all the kinks worked out and full-ppgtt now works
reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
let userspace have full control over their own ppgtt, it makes softpinning
far more effective, in turn making GPU dispatch far more efficient and
more secure (due to better mm segregation).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 51352b90de2b..24542b535d52 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
return 0;
}
- if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
- if (has_full_48bit_ppgtt)
- return 3;
+ if (has_full_48bit_ppgtt)
+ return 3;
- if (has_full_ppgtt)
- return 2;
- }
+ if (has_full_ppgtt)
+ return 2;
return 1;
}
--
2.17.1
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[Intel-gfx] Guess what? HSW full-ppgtt. Almost.
In this edition, I think I have solved the mystery mesa hang; having identified a suspect in MI_SET_CONTEXT | FORCE_RESTORE. But the hang on reset with a dirty PD is still there, and I'm still fighting byt which fails to switch mm once every few hours. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Enabling i915.fastboot=1 by default
Hi, On 06-06-18 20:12, Rodrigo Vivi wrote: On Wed, Jun 06, 2018 at 02:12:36PM +0200, Hans de Goede wrote: Hi, On 06-06-18 12:43, Maarten Lankhorst wrote: Op 06-06-18 om 11:54 schreef Hans de Goede: Hi, On 06-06-18 11:36, Maarten Lankhorst wrote: Op 06-06-18 om 11:09 schreef Hans de Goede: Hi All, So I'm working on making Linux boot in a complete flickerfree manner (no modesets, no black screens). I have this working on various machines with Intel gfx, but I need to pass i915.fastboot=1 on the kernel commandline. I know there was some talk about enabling this by default a while ago, but it seems that that still has not happened (yet?). I'm wondering what is holding this back ? Maybe we can change it from a bool to an int, init it to -1 and when it is -1 have some automatic detection code which disables it where it is known to be troublesome and otherwise enables it by default? Main reason are bugs like https://bugs.freedesktop.org/show_bug.cgi?id=103781 and our hw readout not being perfect. On some haswell/broadwell eDP laptops we stop generating vblanks when we fastboot, and in general we don't trust our code enough for that. The automatic detection code is already in place, we modeset if the mode is not compatible enough, but we don't catch all the cases where this might happen. Right but the "mode is not compatible" check will be always necessary, because e.g. some BIOs-es insist in bringing up the display in 1024x768 instead of its native mode. It's not just the mode we're checking, any parameter in intel_pipe_config_compare is checked and adjusted. This code is also run after each modeset. If the panel fitter is used we don't need to modeset from 1024x768, we will just disable the panel fitter. What I meant is, something like check which generation we are on (and maybe if a specific type of output is used or not if that does not convolute the code too much). E.g. you mention vblank issues with haswell/broadwell eDP, so if i915.fastboot=-1 we would then disable fastboot if we are on a haswell or broadwell and eDP is used. I think we shouldn't put any code in adding workarounds or detection, but fix those bugs and then retry enabling things. But enabling it for all generations at once feels to me like we will never end up enabling it because of an issue on some generations only. There are plenty of other cases where features are enabled by default on a generation by generation basis. I agree that ideally we end up enabling this everywhere, but enabling it by default everywhere at once feel like you are aiming a bit too high. I agree with Hans on this point. It is not a matter of workaround or detection, but a matter of bandwidth to deal with validation and incoming bugs, specially when the behaviour changes for different gens. Ok, so perhaps we can try to enable this now on some hardware? Say skylake+ and byt + cht + apollo-lake ? Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add WaKBLVECSSemaphoreWaitPoll
Quoting Mika Kuoppala (2018-06-05 19:03:57) > There is a problem with kbl up to rev E0 where a heavy > memory/fabric traffic from adjacent engine(s) can cause an engine > reset to fail. This traffic can be from normal memory accesses > or it can be from heavy polling on a semaphore wait. > > For engine hogging causing a fail, we already fallback to > full reset. Which effectively stops all engines and thus > we only add a workaround documentation. > > For the semaphore wait loop poll case, we add one microsecond > poll interval to semaphore wait to guarantee bandwidth for > the reset preration. The side effect is that we make semaphore > completion latencies also 1us longer. > > v2: Let full reset handle the adjacent engine idling (Chris) > > References: https://bugs.freedesktop.org/show_bug.cgi?id=106684 > References: VTHSD#2227190, HSDES#1604216706, BSID#0917 > Signed-off-by: Mika Kuoppala Skip the RCS engine and this is; Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4287 -> Patchwork_9226 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44392/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9226 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@gem_sync@basic-many-each: fi-cnl-y3: NOTRUN -> INCOMPLETE (fdo#105086) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@debugfs_test@read_all_entries: fi-cnl-y3: INCOMPLETE (fdo#105086) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (41 -> 37) == Missing(4): fi-byt-squawks fi-bdw-gvtdvm fi-ilk-m540 fi-skl-6700hq == Build changes == * Linux: CI_DRM_4287 -> Patchwork_9226 CI_DRM_4287: 3da21a5f843f8c11efe3326f3f7854df8ecd72c0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4509: c8f1ae58e1b7da17af4722a5ce5a9cd8b9a34059 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9226: 2dd0b7205b8cc0789023a6645b6b704689a50b01 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2dd0b7205b8c drm/i915/ringbuffer: Brute force context restore b79de1db57c5 drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9226/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()
== Series Details == Series: series starting with [1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() URL : https://patchwork.freedesktop.org/series/44392/ State : warning == Summary == $ dim checkpatch origin/drm-tip b79de1db57c5 drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context() -:51: CHECK:LINE_SPACING: Please don't use multiple blank lines #51: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:603: + + total: 0 errors, 0 warnings, 1 checks, 33 lines checked 2dd0b7205b8c drm/i915/ringbuffer: Brute force context restore ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Change i915_gem_fault() to return vm_fault_t
Quoting Matthew Auld (2018-06-06 23:39:07)
> On 6 June 2018 at 22:45, Chris Wilson wrote:
> > In preparation for vm_fault_t becoming a distinct type, convert the
> > fault handler (i915_gem_fault()) over to the new interface.
> >
> > Based on a patch by Souptick Joarder
> >
> > References: 1c8f422059ae ("mm: change return type to vm_fault_t")
> > Signed-off-by: Chris Wilson
> > Cc: Souptick Joarder
> > Cc: Joonas Lahtinen
> > Cc: Matthew Auld
> Reviewed-by: Matthew Auld
Thanks for the patch and review, pushed to dinq for 4.19.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Use GEM suspend when aborting initialisation
Quoting Michał Winiarski (2018-06-07 08:39:39) > On Wed, Jun 06, 2018 at 03:54:41PM +0100, Chris Wilson wrote: > > As part of our GEM initialisation now, we send a request to the hardware > > in order to record the initial GPU state. This coupled with deferred > > idle workers, makes aborting on error tricky. We already have the > > mechanism in place to wait on the GPU and cancel all the deferred > > workers for suspend, so let's reuse it during the error teardown. It is > > already used in places for later init error handling, but doing so at > > this point is slightly ugly due to the mutex dance (it's ok, the module > > load is still single threaded). > > > > Testcase: igt/drv_module_reload/basic-reload-inject > > Signed-off-by: Chris Wilson > > Cc: Michał Winiarski > > Reviewed-by: Michał Winiarski And pushed. Now let's see how close we are to making CI great again! Quick! Where's my coffee? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use GEM suspend when aborting initialisation
On Wed, Jun 06, 2018 at 03:54:41PM +0100, Chris Wilson wrote: > As part of our GEM initialisation now, we send a request to the hardware > in order to record the initial GPU state. This coupled with deferred > idle workers, makes aborting on error tricky. We already have the > mechanism in place to wait on the GPU and cancel all the deferred > workers for suspend, so let's reuse it during the error teardown. It is > already used in places for later init error handling, but doing so at > this point is slightly ugly due to the mutex dance (it's ok, the module > load is still single threaded). > > Testcase: igt/drv_module_reload/basic-reload-inject > Signed-off-by: Chris Wilson > Cc: Michał Winiarski Reviewed-by: Michał Winiarski -Michał > --- > drivers/gpu/drm/i915/i915_gem.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 86f1f9aaa119..1074f47e6cda 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -5514,8 +5514,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv) >* driver doesn't explode during runtime. >*/ > err_init_hw: > - i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); > - i915_gem_contexts_lost(dev_priv); > + mutex_unlock(_priv->drm.struct_mutex); > + > + WARN_ON(i915_gem_suspend(dev_priv)); > + i915_gem_suspend_late(dev_priv); > + > + mutex_lock(_priv->drm.struct_mutex); > intel_uc_fini_hw(dev_priv); > err_uc_init: > intel_uc_fini(dev_priv); > -- > 2.17.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()
Mark order? I have no idea. Let me go get some coffee.
Quoting Chris Wilson (2018-06-07 08:30:24)
> When using CS commands, PP_DIR is not sampled until the context is
> loaded, but when doing manual mmio after reset we load the context
> before the mm. Let's switch this over for consistency.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 21 +++--
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 65811e2fa7da..4051fb55a2cf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -574,16 +574,7 @@ static void reset_ring(struct intel_engine_cs *engine,
> struct intel_context *ce = request->hw_context;
> struct i915_hw_ppgtt *ppgtt;
>
> - if (ce->state) {
> - I915_WRITE(CCID,
> - i915_ggtt_offset(ce->state) |
> - BIT(8) /* must be set! */ |
> - CCID_EXTENDED_STATE_SAVE |
> - CCID_EXTENDED_STATE_RESTORE |
> - CCID_EN);
> - }
> -
> - ppgtt = request->gem_context->ppgtt ?:
> engine->i915->mm.aliasing_ppgtt;
> + ppgtt = request->gem_context->ppgtt ?:
> dev_priv->mm.aliasing_ppgtt;
> if (ppgtt) {
> u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
>
> @@ -600,6 +591,16 @@ static void reset_ring(struct intel_engine_cs *engine,
> ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
> }
>
> + if (ce->state) {
> + I915_WRITE(CCID,
> + i915_ggtt_offset(ce->state) |
> + BIT(8) /* must be set! */ |
> + CCID_EXTENDED_STATE_SAVE |
> + CCID_EXTENDED_STATE_RESTORE |
> + CCID_EN);
> + }
> +
> +
> /* If the rq hung, jump to its breadcrumb and skip the batch
> */
> if (request->fence.error == -EIO)
> request->ring->head = request->postfix;
> --
> 2.17.1
>
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[Intel-gfx] [PATCH 2/2] drm/i915/ringbuffer: Brute force context restore
An issue encountered with switching mm on gen7 is that the GPU likes to
hang (with the VS unit busy) when told to force restore the current
context. We can simply workaround this by substituting the
MI_FORCE_RESTORE flag with a round-trip through the kernel_context,
forcing the context to be saved and restored; thereby reloading the
PP_DIR registers and updating the modified page directory!
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4051fb55a2cf..9e6883606b1f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1459,6 +1459,7 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
INTEL_INFO(i915)->num_rings - 1 :
0;
+ bool force_restore = false;
int len;
u32 *cs;
@@ -1472,6 +1473,12 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
len = 4;
if (IS_GEN7(i915))
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+ if (flags & MI_FORCE_RESTORE) {
+ GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
+ flags &= ~MI_FORCE_RESTORE;
+ force_restore = true;
+ len += 2;
+ }
cs = intel_ring_begin(rq, len);
if (IS_ERR(cs))
@@ -1497,6 +1504,20 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
}
*cs++ = MI_NOOP;
+ if (force_restore) {
+ /*
+* The HW doesn't handle being told to restore the current
+* context very well. Quite often it likes goes to go off and
+* sulk, especially when it is meant to be reloading PP_DIR.
+* A very simple fix to force the reload is to simply switch
+* away from the current context and back again.
+*/
+ *cs++ = MI_SET_CONTEXT;
+ *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
+ engine)->state) |
+ MI_MM_SPACE_GTT |
+ MI_RESTORE_INHIBIT;
+ }
*cs++ = MI_SET_CONTEXT;
*cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
/*
@@ -1586,11 +1607,14 @@ static int switch_context(struct i915_request *rq)
to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
engine->legacy_active_ppgtt = to_mm;
- hw_flags = MI_FORCE_RESTORE;
+
+ if (to_ctx == from_ctx) {
+ hw_flags = MI_FORCE_RESTORE;
+ from_ctx = NULL;
+ }
}
- if (rq->hw_context->state &&
- (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
+ if (rq->hw_context->state && to_ctx != from_ctx) {
GEM_BUG_ON(engine->id != RCS);
/*
--
2.17.1
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[Intel-gfx] [PATCH 1/2] drm/i915: Mark order of mmio to CCID/PP_DIR with switch_context()
When using CS commands, PP_DIR is not sampled until the context is
loaded, but when doing manual mmio after reset we load the context
before the mm. Let's switch this over for consistency.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 65811e2fa7da..4051fb55a2cf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -574,16 +574,7 @@ static void reset_ring(struct intel_engine_cs *engine,
struct intel_context *ce = request->hw_context;
struct i915_hw_ppgtt *ppgtt;
- if (ce->state) {
- I915_WRITE(CCID,
- i915_ggtt_offset(ce->state) |
- BIT(8) /* must be set! */ |
- CCID_EXTENDED_STATE_SAVE |
- CCID_EXTENDED_STATE_RESTORE |
- CCID_EN);
- }
-
- ppgtt = request->gem_context->ppgtt ?:
engine->i915->mm.aliasing_ppgtt;
+ ppgtt = request->gem_context->ppgtt ?:
dev_priv->mm.aliasing_ppgtt;
if (ppgtt) {
u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
@@ -600,6 +591,16 @@ static void reset_ring(struct intel_engine_cs *engine,
ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
}
+ if (ce->state) {
+ I915_WRITE(CCID,
+ i915_ggtt_offset(ce->state) |
+ BIT(8) /* must be set! */ |
+ CCID_EXTENDED_STATE_SAVE |
+ CCID_EXTENDED_STATE_RESTORE |
+ CCID_EN);
+ }
+
+
/* If the rq hung, jump to its breadcrumb and skip the batch */
if (request->fence.error == -EIO)
request->ring->head = request->postfix;
--
2.17.1
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