[Intel-gfx] ✓ Fi.CI.IGT: success for Perma-pin uC firmware and re-enable global reset (rev3)
== Series Details == Series: Perma-pin uC firmware and re-enable global reset (rev3) URL : https://patchwork.freedesktop.org/series/59255/ State : success == Summary == CI Bug Log - changes from CI_DRM_5961_full -> Patchwork_12849_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12849_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-kbl: PASS -> DMESG-WARN [fdo#108566] * igt@gem_eio@in-flight-suspend: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +2 * igt@i915_pm_rpm@gem-idle: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +2 * igt@kms_busy@basic-flip-d: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@basic-modeset-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-glk: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-apl: PASS -> FAIL [fdo#103060] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_flip@flip-vs-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#109507] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +6 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +44 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-glk: NOTRUN -> SKIP [fdo#109271] +23 * igt@kms_lease@atomic_implicit_crtc: - shard-skl: NOTRUN -> FAIL [fdo#110279] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#108145] +5 * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#108145] / [fdo#110403] +1 * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr@psr2_basic: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_setmode@basic: - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@perf@blocking: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] * igt@perf_pmu@busy-accuracy-98-vcs1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +126 * igt@perf_pmu@busy-check-all-vecs0: - shard-snb: NOTRUN -> SKIP [fdo#109271] +29 Possible fixes * igt@gem_workarounds@suspend-resume: - shard-apl: DMESG-WARN [fdo#108566] -> PASS +2 * igt@i915_pm_rpm@gem-evict-pwrite: - shard-skl: INCOMPLETE [fdo#107807] -> PASS * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: SKIP [fdo#109349] -> PASS * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: FAIL [fdo#103060] -> PASS * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-glk: SKIP [fdo#109271] -> PASS * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS * igt@kms_psr@no_drrs: - shard-iclb: FAIL [fdo#108341] -> PASS * igt@kms_psr@psr2_cursor_blt: - shard-iclb: SKIP [fdo#109441] -> PASS +1 * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS * igt@perf@oa-exponents: - shard-glk: FAIL [fdo#105483] -> PASS [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103167]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
== Series Details == Series: drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt URL : https://patchwork.freedesktop.org/series/59773/ State : success == Summary == CI Bug Log - changes from CI_DRM_5960_full -> Patchwork_12848_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12848_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@basic-default: - shard-iclb: NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#108569] * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +9 * igt@gem_pwrite@huge-cpu-fbr: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +1 * igt@gem_stolen@stolen-fill-purge: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@gem_userptr_blits@readonly-pwrite-unsync: - shard-iclb: NOTRUN -> SKIP [fdo#110426] * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> SKIP [fdo#109303] * igt@kms_atomic_transition@5x-modeset-transitions: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_atomic_transition@6x-modeset-transitions: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +6 * igt@kms_chamelium@dp-hpd-storm-disable: - shard-glk: NOTRUN -> SKIP [fdo#109271] +93 * igt@kms_chamelium@hdmi-cmp-nv12: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +2 * igt@kms_color@pipe-a-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-256x256-sliding: - shard-glk: NOTRUN -> FAIL [fdo#103232] +2 * igt@kms_cursor_crc@cursor-512x512-dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109279] +1 * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-snb: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +6 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] +1 * igt@kms_flip@flip-vs-suspend: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +1 * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: - shard-skl: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-snb: PASS -> SKIP [fdo#109271] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-snb: NOTRUN -> SKIP [fdo#109271] +37 * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-iclb: PASS -> FAIL [fdo#103167] / [fdo#110378] * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +18 * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move: - shard-skl: NOTRUN -> SKIP [fdo#109271] +78 * igt@kms_panel_fitting@legacy: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +21 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#108145] +7 * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-glk: NOTRUN -> FAIL [fdo#108145] * igt@kms_psr@psr2_dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109441] * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_setmode@basic: - shard-skl: PASS -> FAIL [fdo#99912] - shard-iclb: NOTRUN -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: NOTRUN -> FAIL [fdo#100047] * igt@kms_vblank@pipe-c-wait-idle-hang: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4 * igt@kms_vrr@flip-dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109502] * igt@perf@per-context-mode-unprivileged: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +1 * igt@prime_nv_api@nv_self_import: - shard-iclb: NOTRUN -> SKIP [fdo#109291] +2 Possible fixes * igt@gem_eio@in-flight-suspend: - shard-glk: FAIL [fdo#105957] -> PASS * igt@gem_eio@unwedge-stress: - shard-snb: FAIL [fdo#109661] -> PASS
[Intel-gfx] ✓ Fi.CI.BAT: success for Perma-pin uC firmware and re-enable global reset (rev3)
== Series Details == Series: Perma-pin uC firmware and re-enable global reset (rev3) URL : https://patchwork.freedesktop.org/series/59255/ State : success == Summary == CI Bug Log - changes from CI_DRM_5961 -> Patchwork_12849 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59255/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12849 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-multi-fence: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +26 * igt@amdgpu/amd_basic@userptr: - fi-whl-u: NOTRUN -> SKIP [fdo#109271] +41 * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@basic-vebox: - fi-ivb-3770:NOTRUN -> SKIP [fdo#109271] +48 * igt@gem_exec_basic@readonly-bsd: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +71 * igt@gem_exec_parse@basic-rejected: - fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_store@basic-bsd1: - fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_mmap_gtt@basic-write-cpu-read-gtt: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +46 * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_execlists: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@i915_selftest@live_hangcheck: - fi-icl-y: PASS -> INCOMPLETE [fdo#107713] / [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@common-hpd-after-suspend: - fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47 - fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_force_connector_basic@force-edid: - fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-whl-u: NOTRUN -> FAIL [fdo#103375] +1 * igt@kms_psr@cursor_plane_move: - fi-whl-u: NOTRUN -> FAIL [fdo#107383] +3 * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@i915_hangman@error-state-basic: - fi-kbl-guc: SKIP [fdo#109271] -> PASS - fi-cfl-guc: SKIP [fdo#109271] -> PASS +1 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-skl-guc: SKIP [fdo#109271] -> PASS +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (34 -> 34) -- Additional (9): fi-bxt-dsi fi-byt-j1900 fi-apl-guc fi-hsw-4770 fi-whl-u fi-ivb-3770 fi-icl-u3 fi-pnv-d510 fi-kbl-r Missing(9): fi-ilk-m540 fi-bsw-n3050 fi-byt-squawks fi-ctg-p8600 fi-bxt-j4205 fi-gdg-551 fi-bsw-kefka fi-byt-n2820 fi-bdw-samus Build changes - * Linux: CI_DRM_5961 -> Patchwork_12849 CI_DRM_5961: c5fdcd8bd5c596bfc70b6be93e6f04d910c51308 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12849: 18f65425d76cf341a88c22d8cbd6d9473b97b8d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 18f65425d76c drm/i915/selftests: Check that gpu reset is usable from
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Perma-pin uC firmware and re-enable global reset (rev3)
== Series Details == Series: Perma-pin uC firmware and re-enable global reset (rev3) URL : https://patchwork.freedesktop.org/series/59255/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/uc: Rename uC firmware init/fini functions Okay! Commit: drm/i915/uc: Reserve upper range of GGTT -O:drivers/gpu/drm/i915/i915_gem_gtt.c:3380:34: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:3382:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:3382:25: warning: expression using sizeof(void) Commit: drm/i915/uc: Place uC firmware in upper range of GGTT Okay! Commit: Revert "drm/i915/guc: Disable global reset" Okay! Commit: drm/i915/selftests: Check that gpu reset is usable from atomic context Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 4/5] Revert "drm/i915/guc: Disable global reset"
This reverts commit fe62365f9f80a1c1d438c54fba21f5108a182de8.
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/i915_reset.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 677d59304e78..1092d16c289c 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -641,9 +641,6 @@ int intel_gpu_reset(struct drm_i915_private *i915,
bool intel_has_gpu_reset(struct drm_i915_private *i915)
{
- if (USES_GUC(i915))
- return false;
-
if (!i915_modparams.reset)
return NULL;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/5] drm/i915/uc: Reserve upper range of GGTT
GuC and HuC depend on struct_mutex for device
reinitialization. Moving away from this dependency
requires perma-pinning the firmware images in GGTT.
The upper portion of the GuC address space has
a sizeable hole (several MB) that is inaccessible
by GuC. Reserve this range within GGTT as it can
comfortably hold GuC/HuC firmware images.
v2: Reserve node rather than insert (Chris)
Simpler determination of node start/size (Daniele)
Move reserve/release out to intel_guc.* files
v3: Reserve starting at GUC_GGTT_TOP only and bail if this
fails (Chris)
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/intel_guc.c| 28
drivers/gpu/drm/i915/intel_guc.h| 2 ++
4 files changed, 43 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8f460cc4cc1f..0b4c22e68574 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2752,6 +2752,12 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
if (ret)
return ret;
+ if (USES_GUC(dev_priv)) {
+ ret = intel_guc_reserve_ggtt_top(_priv->guc);
+ if (ret)
+ goto err_reserve;
+ }
+
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
@@ -2766,12 +2772,14 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
ret = i915_gem_init_aliasing_ppgtt(dev_priv);
if (ret)
- goto err;
+ goto err_appgtt;
}
return 0;
-err:
+err_appgtt:
+ intel_guc_release_ggtt_top(_priv->guc);
+err_reserve:
drm_mm_remove_node(>error_capture);
return ret;
}
@@ -2797,6 +2805,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
if (drm_mm_node_allocated(>error_capture))
drm_mm_remove_node(>error_capture);
+ intel_guc_release_ggtt_top(_priv->guc);
+
if (drm_mm_initialized(>vm.mm)) {
intel_vgt_deballoon(dev_priv);
i915_address_space_fini(>vm);
@@ -3369,17 +3379,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
-* This is easier than doing range restriction on the fly, as we
-* currently don't have any bits spare to pass in this upper
-* restriction!
-*/
- if (USES_GUC(dev_priv)) {
- ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
- ggtt->mappable_end =
- min_t(u64, ggtt->mappable_end, ggtt->vm.total);
- }
-
if ((ggtt->vm.total - 1) >> 32) {
DRM_ERROR("We never expected a Global GTT with more than 32bits"
" of address space! Found %lldM!\n",
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f597f35b109b..b51e779732c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -384,6 +384,7 @@ struct i915_ggtt {
u32 pin_bias;
struct drm_mm_node error_capture;
+ struct drm_mm_node uc_fw;
};
struct i915_hw_ppgtt {
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index d81a02b0f525..299b6aa4fe28 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -721,3 +721,31 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
{
return guc_to_i915(guc)->wopcm.guc.size;
}
+
+int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
+{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct i915_ggtt *ggtt = >ggtt;
+ u64 size;
+ int ret;
+
+ size = ggtt->vm.total - GUC_GGTT_TOP;
+
+ ret = i915_gem_gtt_reserve(>vm, >uc_fw, size,
+ GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
+ PIN_NOEVICT);
+
+ if (ret)
+ DRM_DEBUG_DRIVER("GuC: failed to reserve top of ggtt\n");
+
+ return ret;
+}
+
+void intel_guc_release_ggtt_top(struct intel_guc *guc)
+{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct i915_ggtt *ggtt = >ggtt;
+
+ if (drm_mm_node_allocated(>uc_fw))
+ drm_mm_remove_node(>uc_fw);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 2c59ff8d9f39..2494e84831a2 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -173,6 +173,8 @@ int intel_guc_suspend(struct
[Intel-gfx] [PATCH v3 0/5] Perma-pin uC firmware and re-enable global reset
The intent is to move the GuC and HuC firmware images to the top of the address space. This portion is inaccessible during normal GuC operations and should be relatively safe to house both firmware images. By making the move we can re-enable the full gpu reset with GuC enabled. Placing the firmware images above GUC_GGTT_TOP was discussed previously here: https://patchwork.freedesktop.org/patch/273616/ v3: Bindings are only needed for xfer v2: The decision to rename both the uc_fw init and fini functions made it easier to pull the bind/unbind operations out of intel_guc_fw.* and intel_huc_fw.*. The bind/unbind will now take place within the newly repurposed intel_uc_fw_init/fini. All other changes should be called out in their respective patches and should be the direct result of a review comment. Cc: Chris Wilson Cc: Daniele Ceraolo Spurio Fernando Pacheco (5): drm/i915/uc: Rename uC firmware init/fini functions drm/i915/uc: Reserve upper range of GGTT drm/i915/uc: Place uC firmware in upper range of GGTT Revert "drm/i915/guc: Disable global reset" drm/i915/selftests: Check that gpu reset is usable from atomic context drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + drivers/gpu/drm/i915/i915_reset.c | 3 - drivers/gpu/drm/i915/intel_guc.c | 41 ++- drivers/gpu/drm/i915/intel_guc.h | 2 + drivers/gpu/drm/i915/intel_guc_fw.c | 20 ++-- drivers/gpu/drm/i915/intel_huc.c | 74 +--- drivers/gpu/drm/i915/intel_huc.h | 6 +- drivers/gpu/drm/i915/intel_huc_fw.c | 49 +--- drivers/gpu/drm/i915/intel_uc.c | 23 +++- drivers/gpu/drm/i915/intel_uc_fw.c| 107 +- drivers/gpu/drm/i915/intel_uc_fw.h| 10 +- .../gpu/drm/i915/selftests/intel_hangcheck.c | 6 +- 13 files changed, 267 insertions(+), 100 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/5] drm/i915/uc: Place uC firmware in upper range of GGTT
Currently we pin the GuC or HuC firmware image just
before uploading. Perma-pin during uC initialization
instead and use the range reserved at the top of the
address space.
Moving the firmware resulted in needing to:
- use an additional pinning for the rsa signature which will
be used during HuC auth as addresses above GUC_GGTT_TOP
do not map through GTT.
v2: Remove call to set to gtt domain
Do not restore fw gtt mapping unconditionally
Separate out pin/unpin functions and drop usage of pin/unpin
Use uc_fw init/fini functions to bind/unbind fw object
v3: Bind is only needed during xfer (Chris)
Remove attempts to bind outside of xfer (Chris)
Mark fw bind/unbind static
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/intel_guc.c| 9 ++-
drivers/gpu/drm/i915/intel_guc_fw.c | 18 ++---
drivers/gpu/drm/i915/intel_huc.c| 74 +++-
drivers/gpu/drm/i915/intel_huc.h| 4 ++
drivers/gpu/drm/i915/intel_huc_fw.c | 47 +
drivers/gpu/drm/i915/intel_uc.c | 23 +--
drivers/gpu/drm/i915/intel_uc_fw.c | 103
drivers/gpu/drm/i915/intel_uc_fw.h | 7 +-
8 files changed, 212 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 299b6aa4fe28..3bbf45a3bf78 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -189,9 +189,13 @@ int intel_guc_init(struct intel_guc *guc)
struct drm_i915_private *dev_priv = guc_to_i915(guc);
int ret;
- ret = guc_shared_data_create(guc);
+ ret = intel_uc_fw_init(>fw);
if (ret)
goto err_fetch;
+
+ ret = guc_shared_data_create(guc);
+ if (ret)
+ goto err_fw;
GEM_BUG_ON(!guc->shared_data);
ret = intel_guc_log_create(>log);
@@ -220,6 +224,8 @@ int intel_guc_init(struct intel_guc *guc)
intel_guc_log_destroy(>log);
err_shared:
guc_shared_data_destroy(guc);
+err_fw:
+ intel_uc_fw_fini(>fw);
err_fetch:
intel_uc_fw_cleanup_fetch(>fw);
return ret;
@@ -237,6 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
guc_shared_data_destroy(guc);
+ intel_uc_fw_fini(>fw);
intel_uc_fw_cleanup_fetch(>fw);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 4385d9ef02bb..8b2dcc70b956 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -122,14 +122,16 @@ static void guc_prepare_xfer(struct intel_guc *guc)
}
/* Copy RSA signature from the fw image to HW for verification */
-static void guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
+static void guc_xfer_rsa(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uc_fw *fw = >fw;
+ struct sg_table *pages = fw->obj->mm.pages;
u32 rsa[UOS_RSA_SCRATCH_COUNT];
int i;
- sg_pcopy_to_buffer(vma->pages->sgl, vma->pages->nents,
- rsa, sizeof(rsa), guc->fw.rsa_offset);
+ sg_pcopy_to_buffer(pages->sgl, pages->nents,
+ rsa, sizeof(rsa), fw->rsa_offset);
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
@@ -201,7 +203,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
* transfer between GTT locations. This functionality is left out of the API
* for now as there is no need for it.
*/
-static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
+static int guc_xfer_ucode(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_uc_fw *guc_fw = >fw;
@@ -214,7 +216,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct
i915_vma *vma)
I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
/* Set the source address for the new blob */
- offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
+ offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0x);
@@ -233,7 +235,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct
i915_vma *vma)
/*
* Load the GuC firmware blob into the MinuteIA.
*/
-static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
+static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -250,9 +252,9 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct
i915_vma *vma)
* by the DMA engine in one operation, whereas the RSA signature is
* loaded via MMIO.
*/
-
[Intel-gfx] [PATCH v3 5/5] drm/i915/selftests: Check that gpu reset is usable from atomic context
GPU reset is now available with GuC enabled,
so re-enable our check that this reset is usable
from atomic context.
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 050bd1e19e02..2fd33aad8683 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -1814,9 +1814,6 @@ static int igt_atomic_reset(void *arg)
/* Check that the resets are usable from atomic context */
- if (USES_GUC_SUBMISSION(i915))
- return 0; /* guc is dead; long live the guc */
-
igt_global_reset_lock(i915);
mutex_lock(>drm.struct_mutex);
wakeref = intel_runtime_pm_get(i915);
@@ -1846,6 +1843,9 @@ static int igt_atomic_reset(void *arg)
force_reset(i915);
}
+ if (USES_GUC_SUBMISSION(i915))
+ goto unlock;
+
if (intel_has_reset_engine(i915)) {
struct intel_engine_cs *engine;
enum intel_engine_id id;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/5] drm/i915/uc: Rename uC firmware init/fini functions
The uC firmware init function is called during
GuC/HuC init early phases. Rename to include "_early"
and properly reflect which phase we are at.
The uC firmware fini function is cleaning up the
state set/created on firmware fetch. Replace
"_fini" with "_cleanup_fetch".
v2: also rename uC fw fini function
Signed-off-by: Fernando Pacheco
---
drivers/gpu/drm/i915/intel_guc.c| 6 +++---
drivers/gpu/drm/i915/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/intel_huc.h| 2 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/intel_uc_fw.c | 4 ++--
drivers/gpu/drm/i915/intel_uc_fw.h | 5 +++--
6 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3aabfa2d9198..d81a02b0f525 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -154,7 +154,7 @@ int intel_guc_init_misc(struct intel_guc *guc)
void intel_guc_fini_misc(struct intel_guc *guc)
{
- intel_uc_fw_fini(>fw);
+ intel_uc_fw_cleanup_fetch(>fw);
guc_fini_wq(guc);
}
@@ -221,7 +221,7 @@ int intel_guc_init(struct intel_guc *guc)
err_shared:
guc_shared_data_destroy(guc);
err_fetch:
- intel_uc_fw_fini(>fw);
+ intel_uc_fw_cleanup_fetch(>fw);
return ret;
}
@@ -237,7 +237,7 @@ void intel_guc_fini(struct intel_guc *guc)
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(>log);
guc_shared_data_destroy(guc);
- intel_uc_fw_fini(>fw);
+ intel_uc_fw_cleanup_fetch(>fw);
}
static u32 guc_ctl_debug_flags(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 792a551450c7..4385d9ef02bb 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -90,7 +90,7 @@ void intel_guc_fw_init_early(struct intel_guc *guc)
{
struct intel_uc_fw *guc_fw = >fw;
- intel_uc_fw_init(guc_fw, INTEL_UC_FW_TYPE_GUC);
+ intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
guc_fw_select(guc_fw);
}
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 7e41d870b509..ce129e301961 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -42,7 +42,7 @@ int intel_huc_check_status(struct intel_huc *huc);
static inline void intel_huc_fini_misc(struct intel_huc *huc)
{
- intel_uc_fw_fini(>fw);
+ intel_uc_fw_cleanup_fetch(>fw);
}
static inline int intel_huc_sanitize(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 68d47c105939..80a176d91edc 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -89,7 +89,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
{
struct intel_uc_fw *huc_fw = >fw;
- intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
+ intel_uc_fw_init_early(huc_fw, INTEL_UC_FW_TYPE_HUC);
huc_fw_select(huc_fw);
}
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
b/drivers/gpu/drm/i915/intel_uc_fw.c
index becf05ebae4d..e3e74207a102 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -274,13 +274,13 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
}
/**
- * intel_uc_fw_fini - cleanup uC firmware
+ * intel_uc_fw_cleanup_fetch - cleanup uC firmware
*
* @uc_fw: uC firmware
*
* Cleans up uC firmware by releasing the firmware GEM obj.
*/
-void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
+void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
{
struct drm_i915_gem_object *obj;
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
b/drivers/gpu/drm/i915/intel_uc_fw.h
index 0e3bd580e267..e6fa8599757c 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -102,7 +102,8 @@ static inline const char *intel_uc_fw_type_repr(enum
intel_uc_fw_type type)
}
static inline
-void intel_uc_fw_init(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type)
+void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
+ enum intel_uc_fw_type type)
{
uc_fw->path = NULL;
uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
@@ -144,10 +145,10 @@ static inline u32 intel_uc_fw_get_upload_size(struct
intel_uc_fw *uc_fw)
void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct intel_uc_fw *uc_fw);
+void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw);
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
int (*xfer)(struct intel_uc_fw *uc_fw,
struct i915_vma *vma));
-void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
#endif
--
2.21.0
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Expose the busyspin durations for i915_wait_request (rev2)
== Series Details == Series: drm/i915: Expose the busyspin durations for i915_wait_request (rev2) URL : https://patchwork.freedesktop.org/series/34364/ State : success == Summary == CI Bug Log - changes from CI_DRM_5958_full -> Patchwork_12847_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12847_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +3 * igt@gem_exec_schedule@preempt-self-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@gem_workarounds@suspend-resume: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_chamelium@hdmi-crc-fast: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +2 * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions: - shard-iclb: NOTRUN -> SKIP [fdo#109274] * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible: - shard-skl: PASS -> FAIL [fdo#105312] * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: PASS -> INCOMPLETE [fdo#109507] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: - shard-iclb: PASS -> FAIL [fdo#103167] +3 * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_pipe_crc_basic@read-crc-pipe-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14 * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +3 * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: PASS -> SKIP [fdo#109441] +2 * igt@kms_psr@psr2_cursor_render: - shard-iclb: NOTRUN -> SKIP [fdo#109441] +1 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@kms_vrr@flip-suspend: - shard-skl: NOTRUN -> SKIP [fdo#109271] +154 * igt@prime_vgem@fence-write-hang: - shard-iclb: NOTRUN -> SKIP [fdo#109295] * igt@tools_test@sysfs_l3_parity: - shard-iclb: NOTRUN -> SKIP [fdo#109307] Possible fixes * igt@i915_pm_rpm@gem-execbuf: - shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: DMESG-WARN [fdo#108566] -> PASS +4 * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled: - shard-skl: FAIL [fdo#103184] -> PASS * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: FAIL [fdo#100368] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: FAIL [fdo#103167] -> PASS +4 * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: SKIP [fdo#109441] -> PASS +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: FAIL [fdo#109016] -> PASS * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS * igt@kms_sysfs_edid_timing: - shard-iclb: FAIL [fdo#100047] -> PASS * igt@prime_busy@hang-default: - shard-snb: FAIL [fdo#108807] -> PASS Warnings * igt@gem_tiled_swapping@non-threaded: - shard-iclb: DMESG-WARN [fdo#108686] -> FAIL [fdo#108686] [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105312]: https://bugs.freedesktop.org/show_bug.cgi?id=105312 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#108807]: https://bugs.freedesktop.org/show_bug.cgi?id=108807 [fdo#109016]:
Re: [Intel-gfx] [PATCH] drm/i915/icl: Prevent possibe de-reference in skl_check_pipe_max_pixel_clock.
On Fri, Apr 19, 2019 at 10:12:02PM +0100, Chris Wilson wrote: > Quoting Matt Roper (2019-04-19 22:06:05) > > On Mon, Apr 15, 2019 at 08:12:50PM -0700, clinton.a.tay...@intel.com wrote: > > > From: Clint Taylor > > > > > > Add protections to prevent NULL de-reference for a couple variables used > > > in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring > > > during some IGT tests. > > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=109084 > > > > > > Cc: Rodrigo Vivi > > > Cc: Martin Peres > > > Signed-off-by: Clint Taylor > > > --- > > > drivers/gpu/drm/i915/intel_display.c | 4 > > > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > > > 2 files changed, 7 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > > b/drivers/gpu/drm/i915/intel_display.c > > > index 3bd40a4a6739..945861cef520 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -11377,6 +11377,10 @@ static int intel_crtc_atomic_check(struct > > > drm_crtc *crtc, > > > > > > if (!ret) > > > ret = icl_check_nv12_planes(pipe_config); > > > + > > > + if (WARN_ON(!intel_crtc)) > > > > If intel_crtc is NULL, then crtc should also be NULL as well, and we > > already dereferenced that earlier: > > > > struct drm_i915_private *dev_priv = to_i915(crtc->dev); > > > > So if crtc/intel_crtc were the problem, I believe this check would still > > be too late to catch and prevent a crash. > > > > > > > + return -EINVAL; > > > + > > > if (!ret) > > > ret = skl_check_pipe_max_pixel_rate(intel_crtc, > > > pipe_config); > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index 7357bddf9ad9..df5d01d4345b 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4160,6 +4160,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc > > > *intel_crtc, > > > uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8); > > > int bpp; > > > > > > + if (WARN_ON(!pstate)) > > > + return -EINVAL; > > > > The pstate here comes from drm_atomic_crtc_state_for_each_plane_state, > > which does a 'for_each_if' to only execute the loop body if pstate is > > non-NULL, so I don't see how this one could be possible either. > > > > > > Do you see the driver tripping over either of these guards once this > > patch is applied? If we've got a backtrace for a gp fault, can we > > convert the RIP back into a specific line of code that triggered the > > fault? > > The bug is not for a NULL pointer dereference, but a use-after-free -- > so 0x6b6b6b6b6b6b6b not 0x0. > -Chris Okay, that makes more sense then. But in that case I don't think the WARN_ON tests being added in this patch will help since they're only checking for NULL. Matt -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Prevent possibe de-reference in skl_check_pipe_max_pixel_clock.
Quoting Matt Roper (2019-04-19 22:06:05) > On Mon, Apr 15, 2019 at 08:12:50PM -0700, clinton.a.tay...@intel.com wrote: > > From: Clint Taylor > > > > Add protections to prevent NULL de-reference for a couple variables used > > in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring > > during some IGT tests. > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=109084 > > > > Cc: Rodrigo Vivi > > Cc: Martin Peres > > Signed-off-by: Clint Taylor > > --- > > drivers/gpu/drm/i915/intel_display.c | 4 > > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 3bd40a4a6739..945861cef520 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -11377,6 +11377,10 @@ static int intel_crtc_atomic_check(struct drm_crtc > > *crtc, > > > > if (!ret) > > ret = icl_check_nv12_planes(pipe_config); > > + > > + if (WARN_ON(!intel_crtc)) > > If intel_crtc is NULL, then crtc should also be NULL as well, and we > already dereferenced that earlier: > > struct drm_i915_private *dev_priv = to_i915(crtc->dev); > > So if crtc/intel_crtc were the problem, I believe this check would still > be too late to catch and prevent a crash. > > > > + return -EINVAL; > > + > > if (!ret) > > ret = skl_check_pipe_max_pixel_rate(intel_crtc, > > pipe_config); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 7357bddf9ad9..df5d01d4345b 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4160,6 +4160,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc > > *intel_crtc, > > uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8); > > int bpp; > > > > + if (WARN_ON(!pstate)) > > + return -EINVAL; > > The pstate here comes from drm_atomic_crtc_state_for_each_plane_state, > which does a 'for_each_if' to only execute the loop body if pstate is > non-NULL, so I don't see how this one could be possible either. > > > Do you see the driver tripping over either of these guards once this > patch is applied? If we've got a backtrace for a gp fault, can we > convert the RIP back into a specific line of code that triggered the > fault? The bug is not for a NULL pointer dereference, but a use-after-free -- so 0x6b6b6b6b6b6b6b not 0x0. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Prevent possibe de-reference in skl_check_pipe_max_pixel_clock.
On Mon, Apr 15, 2019 at 08:12:50PM -0700, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > Add protections to prevent NULL de-reference for a couple variables used > in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring > during some IGT tests. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=109084 > > Cc: Rodrigo Vivi > Cc: Martin Peres > Signed-off-by: Clint Taylor > --- > drivers/gpu/drm/i915/intel_display.c | 4 > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 3bd40a4a6739..945861cef520 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11377,6 +11377,10 @@ static int intel_crtc_atomic_check(struct drm_crtc > *crtc, > > if (!ret) > ret = icl_check_nv12_planes(pipe_config); > + > + if (WARN_ON(!intel_crtc)) If intel_crtc is NULL, then crtc should also be NULL as well, and we already dereferenced that earlier: struct drm_i915_private *dev_priv = to_i915(crtc->dev); So if crtc/intel_crtc were the problem, I believe this check would still be too late to catch and prevent a crash. > + return -EINVAL; > + > if (!ret) > ret = skl_check_pipe_max_pixel_rate(intel_crtc, > pipe_config); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7357bddf9ad9..df5d01d4345b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4160,6 +4160,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc > *intel_crtc, > uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8); > int bpp; > > + if (WARN_ON(!pstate)) > + return -EINVAL; The pstate here comes from drm_atomic_crtc_state_for_each_plane_state, which does a 'for_each_if' to only execute the loop body if pstate is non-NULL, so I don't see how this one could be possible either. Do you see the driver tripping over either of these guards once this patch is applied? If we've got a backtrace for a gp fault, can we convert the RIP back into a specific line of code that triggered the fault? Matt > + > if (!intel_wm_plane_visible(cstate, > to_intel_plane_state(pstate))) > continue; > -- > 2.19.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
== Series Details == Series: drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt URL : https://patchwork.freedesktop.org/series/59773/ State : success == Summary == CI Bug Log - changes from CI_DRM_5960 -> Patchwork_12848 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59773/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12848 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@gtt-bsd: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] +98 * igt@gem_exec_basic@gtt-bsd1: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_module_load@reload: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] * igt@kms_busy@basic-flip-c: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@hdmi-edid-read: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +24 * igt@kms_force_connector_basic@force-edid: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 * igt@kms_psr@primary_page_flip: - fi-skl-lmem:NOTRUN -> SKIP [fdo#109271] +37 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (35 -> 32) -- Additional (4): fi-icl-y fi-skl-lmem fi-bxt-j4205 fi-bwr-2160 Missing(7): fi-ilk-m540 fi-icl-u2 fi-snb-2520m fi-ctg-p8600 fi-hsw-4770 fi-cfl-8109u fi-bdw-samus Build changes - * Linux: CI_DRM_5960 -> Patchwork_12848 CI_DRM_5960: fa2ef64bd2b4890021eda01248a2de4290248522 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12848: 45a2b940a818d709b784ba3c9d065603efa557d2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 45a2b940a818 drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12848/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context (rev2)
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE
*before* switch context (rev2)
URL : https://patchwork.freedesktop.org/series/59752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5958_full -> Patchwork_12845_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12845_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-skl: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12845_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@preempt-self-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +3
* igt@i915_suspend@debugfs-reader:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +4
* igt@i915_suspend@forcewake:
- shard-snb: PASS -> DMESG-WARN [fdo#102365]
* igt@kms_ccs@pipe-b-crc-primary-basic:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-snb: PASS -> SKIP [fdo#109271] +3
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-iclb: PASS -> FAIL [fdo#103167] +8
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@kms_pipe_crc_basic@read-crc-pipe-e:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +4
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: NOTRUN -> SKIP [fdo#109441] +1
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +178
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> SKIP [fdo#109295]
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
Possible fixes
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: DMESG-WARN [fdo#108686] -> PASS
* igt@i915_pm_rpm@gem-idle:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +3
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: FAIL [fdo#100368] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS +1
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: SKIP [fdo#109642] -> PASS
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
* igt@prime_busy@hang-default:
- shard-snb: FAIL [fdo#108807] -> PASS
Warnings
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-skl: SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]
{name}: This element is suppressed. This
[Intel-gfx] [CI] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
If we know that the user cannot access the GGTT, by virtue of having a segregated memory area, we can skip clearing the unused entries as they cannot be accessed. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 8f460cc4cc1f..10558bc8bf90 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3280,7 +3280,9 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE; - ggtt->vm.clear_range = gen6_ggtt_clear_range; + ggtt->vm.clear_range = nop_clear_range; + if (!HAS_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) + ggtt->vm.clear_range = gen6_ggtt_clear_range; ggtt->vm.insert_page = gen6_ggtt_insert_page; ggtt->vm.insert_entries = gen6_ggtt_insert_entries; ggtt->vm.cleanup = gen6_gmch_remove; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V2 23/29] tracing: Simplify stack trace retrieval
On Thu, 18 Apr 2019 10:41:42 +0200 Thomas Gleixner wrote: > Replace the indirection through struct stack_trace by using the storage > array based interfaces. > > Signed-off-by: Thomas Gleixner > Cc: Steven Rostedt Reviewed-by: Steven Rostedt (VMware) -- Steve ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V2 24/29] tracing: Remove the last struct stack_trace usage
On Thu, 18 Apr 2019 10:41:43 +0200 Thomas Gleixner wrote: > Simplify the stack retrieval code by using the storage array based > interface. > > Signed-off-by: Thomas Gleixner Reviewed-by: Steven Rostedt (VMware) -- Steve ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 00/19] GuC 32.0.3
Quoting Michal Wajdeczko (2019-04-17 06:39:45) > New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface. > > Note: For correct bisecting, patches 3-8 can be squashed, as Gen9 GuC > support will be broken during update of GuC firmware definitions. > > v2: only HuC authentication is supported > v3: never allow to turn on GuC submission mode So one thing that Joonas said was imperative was that HuC authentication is not broken at any point along the series. What igt do we have to verify userspace can talk to the HuC, or whatever is required? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5958_full -> Patchwork_12844_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12844_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-skl: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12844_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_exec_schedule@preempt-self-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +3
* igt@i915_pm_rpm@universal-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@kms_busy@extended-modeset-hang-oldfb-render-b:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#106509] / [fdo#107409]
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@kms_pipe_crc_basic@read-crc-pipe-e:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#108145] / [fdo#110403]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#108341]
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: NOTRUN -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +162
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> SKIP [fdo#109295]
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
Possible fixes
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: DMESG-WARN [fdo#108686] -> PASS
* igt@i915_pm_rpm@gem-execbuf:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: SKIP [fdo#109271] -> PASS +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS +1
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
* igt@prime_busy@hang-default:
- shard-snb: FAIL [fdo#108807] ->
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose the busyspin durations for i915_wait_request (rev2)
== Series Details == Series: drm/i915: Expose the busyspin durations for i915_wait_request (rev2) URL : https://patchwork.freedesktop.org/series/34364/ State : success == Summary == CI Bug Log - changes from CI_DRM_5958 -> Patchwork_12847 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/34364/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12847 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +50 * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@gtt-bsd: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] +98 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 - fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47 * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_evict: - fi-bsw-kefka: NOTRUN -> DMESG-WARN [fdo#107709] * igt@i915_selftest@live_execlists: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 * igt@kms_psr@primary_page_flip: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +48 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] * igt@runner@aborted: - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602] - fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709] / [fdo#110446] - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109309]:
Re: [Intel-gfx] [PATCH] drm/i915: Fix skl+ max plane width
On Thu, 2019-04-18 at 22:59 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The spec has changed since skl_max_plane_width() was written.
> Now the SKL limits are lower than what they were initially, and
> GLK and ICL have different limits. Update the code to match the
> spec.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 73 ++--
>
> 1 file changed, 48 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3bd40a4a6739..bedddbeead75 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2964,41 +2964,56 @@ static int skl_max_plane_width(const struct
> drm_framebuffer *fb,
> switch (fb->modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> - switch (cpp) {
> - case 8:
> - return 4096;
> - case 4:
> - case 2:
> - case 1:
> - return 8192;
> - default:
> - MISSING_CASE(cpp);
> - break;
> - }
> - break;
> + return 4096;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> /* FIXME AUX plane? */
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> - switch (cpp) {
> - case 8:
> + if (cpp == 8)
> return 2048;
> - case 4:
> + else
> return 4096;
> - case 2:
> - case 1:
> - return 8192;
> - default:
> - MISSING_CASE(cpp);
> - break;
> - }
> - break;
> default:
> MISSING_CASE(fb->modifier);
> + return 2048;
> }
> +}
>
> - return 2048;
> +
> +static int glk_max_plane_width(const struct drm_framebuffer *fb,
> +int color_plane,
> +unsigned int rotation)
> +{
> + int cpp = fb->format->cpp[color_plane];
> +
> + switch (fb->modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + case I915_FORMAT_MOD_X_TILED:
> + if (cpp == 8)
> + return 4096;
> + else
> + return 5120;
> + case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Yf_TILED_CCS:
> + /* FIXME AUX plane? */
> + case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_Yf_TILED:
> + if (cpp == 8)
> + return 2048;
> + else
> + return 5120;
> + default:
> + MISSING_CASE(fb->modifier);
> + return 2048;
> + }
> +}
> +
> +static int icl_max_plane_width(const struct drm_framebuffer *fb,
> +int color_plane,
> +unsigned int rotation)
> +{
> + return 5120;
> }
>
> static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> *plane_state,
> @@ -3041,16 +3056,24 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>
> static int skl_check_main_surface(struct intel_plane_state
> *plane_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(plane_state-
> >base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> int x = plane_state->base.src.x1 >> 16;
> int y = plane_state->base.src.y1 >> 16;
> int w = drm_rect_width(_state->base.src) >> 16;
> int h = drm_rect_height(_state->base.src) >> 16;
> - int max_width = skl_max_plane_width(fb, 0, rotation);
> + int max_width;
> int max_height = 4096;
> u32 alignment, offset, aux_offset = plane_state-
> >color_plane[1].offset;
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + max_width = icl_max_plane_width(fb, 0, rotation);
> + else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + max_width = glk_max_plane_width(fb, 0, rotation);
> + else
> + max_width = skl_max_plane_width(fb, 0, rotation);
> +
> if (w > max_width || h > max_height) {
> DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too
> big (limit %dx%d)\n",
> w, h, max_width, max_height);
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Expose the busyspin durations for i915_wait_request (rev2)
== Series Details == Series: drm/i915: Expose the busyspin durations for i915_wait_request (rev2) URL : https://patchwork.freedesktop.org/series/34364/ State : warning == Summary == $ dim checkpatch origin/drm-tip d77eb390e6fb drm/i915: Expose the busyspin durations for i915_wait_request -:36: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #36: References: http://events.linuxfoundation.org/sites/events/files/slides/lemoal-nvme-polling-vault-2017-final_0.pdf -:61: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #61: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 55 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-buf: Remove unused sync_dump()
== Series Details == Series: dma-buf: Remove unused sync_dump() URL : https://patchwork.freedesktop.org/series/59765/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5958 -> Patchwork_12846 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12846 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12846, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/59765/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12846: ### IGT changes ### Possible regressions * igt@i915_selftest@live_hugepages: - fi-apl-guc: NOTRUN -> DMESG-WARN * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12846 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +50 * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@gtt-bsd: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] +98 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +44 - fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47 * igt@i915_selftest@live_guc: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] * igt@i915_selftest@live_hangcheck: - fi-icl-y: NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#108569] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-glk-dsi: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 * igt@kms_psr@primary_page_flip: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +48 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#110189]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context (rev2) URL : https://patchwork.freedesktop.org/series/59752/ State : success == Summary == CI Bug Log - changes from CI_DRM_5958 -> Patchwork_12845 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59752/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12845 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-7500u: PASS -> DMESG-WARN [fdo#105128] / [fdo#107139] * igt@gem_mmap_gtt@basic-write-cpu-read-gtt: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +48 * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: PASS -> FAIL [fdo#108511] * igt@i915_selftest@live_execlists: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@common-hpd-after-suspend: - fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47 * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602] Possible fixes * igt@gem_ctx_create@basic: - fi-elk-e7500: SKIP [fdo#109271] -> PASS +5 * igt@gem_ctx_exec@basic: - fi-ilk-650: SKIP [fdo#109271] -> PASS +5 * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-glk-dsi: FAIL [fdo#103191] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (36 -> 32) -- Additional (6): fi-bxt-dsi fi-bsw-n3050 fi-byt-j1900 fi-apl-guc fi-snb-2520m fi-hsw-4770 Missing(10): fi-ilk-m540 fi-hsw-peppy fi-byt-squawks fi-skl-6260u fi-ctg-p8600 fi-whl-u fi-bxt-j4205 fi-gdg-551 fi-icl-u3 fi-bdw-samus Build changes - * Linux: CI_DRM_5958 -> Patchwork_12845 CI_DRM_5958: dabbe59fd2bb5dca3d2607c49369161ec7160df3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12845: 6878f8a9284efe2167acd0b11aea0b565c63ef65 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6878f8a9284e drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) 6b9436fbada4 drm/i915: Enable render context support for Ironlake (gen5) 260bff3d0251 drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12845/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Expose the busyspin durations for i915_wait_request
An interesting discussion regarding "hybrid interrupt polling" for NVMe came to the conclusion that the ideal busyspin before sleeping was half of the expected request latency (and better if it was already halfway through that request). This suggested that we too should look again at our tradeoff between spinning and waiting. Currently, our spin simply tries to hide the cost of enabling the interrupt, which is good to avoid penalising nop requests (i.e. test throughput) and not much else. Studying real world workloads suggests that a spin of upto 500us can dramatically boost performance, but the suggestion is that this is not from avoiding interrupt latency per-se, but from secondary effects of sleeping such as allowing the CPU reduce cstate and context switch away. In a truly hybrid interrupt polling scheme, we would aim to sleep until just before the request completed and then wake up in advance of the interrupt and do a quick poll to handle completion. This is tricky for ourselves at the moment as we are not recording request times, and since we allow preemption, our requests are not on as a nicely ordered timeline as IO. However, the idea is interesting, for it will certainly help us decide when busyspinning is worthwhile. v2: Expose the spin setting via Kconfig options for easier adjustment and testing. v3: Don't get caught sneaking in a change to the busyspin parameters. v4: Explain more about the "hybrid interrupt polling" scheme that we want to migrate towards. Suggested-by: Sagar Kamble References: http://events.linuxfoundation.org/sites/events/files/slides/lemoal-nvme-polling-vault-2017-final_0.pdf Signed-off-by: Chris Wilson Cc: Sagar Kamble Cc: Eero Tamminen Cc: Tvrtko Ursulin Cc: Ben Widawsky Cc: Joonas Lahtinen Cc: Michał Winiarski Reviewed-by: Sagar Kamble --- drivers/gpu/drm/i915/Kconfig | 6 ++ drivers/gpu/drm/i915/Kconfig.profile | 13 + drivers/gpu/drm/i915/i915_request.c | 27 +-- 3 files changed, 44 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/i915/Kconfig.profile diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 148be8e1a090..f0556310b851 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -133,3 +133,9 @@ depends on DRM_I915 depends on EXPERT source "drivers/gpu/drm/i915/Kconfig.debug" endmenu + +menu "drm/i915 Profile Guided Optimisation" + visible if EXPERT + depends on DRM_I915 + source "drivers/gpu/drm/i915/Kconfig.profile" +endmenu diff --git a/drivers/gpu/drm/i915/Kconfig.profile b/drivers/gpu/drm/i915/Kconfig.profile new file mode 100644 index ..0e5db98da8f3 --- /dev/null +++ b/drivers/gpu/drm/i915/Kconfig.profile @@ -0,0 +1,13 @@ +config DRM_I915_SPIN_REQUEST + int + default 5 # microseconds + help + Before sleeping waiting for a request (GPU operation) to complete, + we may spend some time polling for its completion. As the IRQ may + take a non-negligible time to setup, we do a short spin first to + check if the request will complete in the time it would have taken + us to enable the interrupt. + + May be 0 to disable the initial spin. In practice, we estimate + the cost of enabling the interrupt (if currently disabled) to be + a few microseconds. diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index b836721d3b13..b1f00b59bb95 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1340,8 +1340,31 @@ long i915_request_wait(struct i915_request *rq, trace_i915_request_wait_begin(rq, flags); - /* Optimistic short spin before touching IRQs */ - if (__i915_spin_request(rq, state, 5)) + /* +* Optimistic spin before touching IRQs. +* +* We may use a rather large value here to offset the penalty of +* switching away from the active task. Frequently, the client will +* wait upon an old swapbuffer to throttle itself to remain within a +* frame of the gpu. If the client is running in lockstep with the gpu, +* then it should not be waiting long at all, and a sleep now will incur +* extra scheduler latency in producing the next frame. To try to +* avoid adding the cost of enabling/disabling the interrupt to the +* short wait, we first spin to see if the request would have completed +* in the time taken to setup the interrupt. +* +* We need upto 5us to enable the irq, and upto 20us to hide the +* scheduler latency of a context switch, ignoring the secondary +* impacts from a context switch such as cache eviction. +* +* The scheme used for low-latency IO is called "hybrid interrupt +* polling". The suggestion there is to sleep until just before you +* expect to be woken by the
[Intel-gfx] [PATCH] dma-buf: Remove unused sync_dump()
sync_dump() is an unused, unexported, function that adds 64k to the
kernel image and doesn't even provide locking around the global array it
uses.
add/remove: 0/2 grow/shrink: 0/0 up/down: 0/-65734 (-65734)
Function old new delta
sync_dump198 --198
sync_dump_buf 65536 - -65536
Signed-off-by: Chris Wilson
Cc: Sumit Semwal
Cc: Gustavo Padovan
---
drivers/dma-buf/sync_debug.c | 26 --
drivers/dma-buf/sync_debug.h | 1 -
2 files changed, 27 deletions(-)
diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c
index c0abf37df88b..434a66518e0d 100644
--- a/drivers/dma-buf/sync_debug.c
+++ b/drivers/dma-buf/sync_debug.c
@@ -197,29 +197,3 @@ static __init int sync_debugfs_init(void)
return 0;
}
late_initcall(sync_debugfs_init);
-
-#define DUMP_CHUNK 256
-static char sync_dump_buf[64 * 1024];
-void sync_dump(void)
-{
- struct seq_file s = {
- .buf = sync_dump_buf,
- .size = sizeof(sync_dump_buf) - 1,
- };
- int i;
-
- sync_info_debugfs_show(, NULL);
-
- for (i = 0; i < s.count; i += DUMP_CHUNK) {
- if ((s.count - i) > DUMP_CHUNK) {
- char c = s.buf[i + DUMP_CHUNK];
-
- s.buf[i + DUMP_CHUNK] = 0;
- pr_cont("%s", s.buf + i);
- s.buf[i + DUMP_CHUNK] = c;
- } else {
- s.buf[s.count] = 0;
- pr_cont("%s", s.buf + i);
- }
- }
-}
diff --git a/drivers/dma-buf/sync_debug.h b/drivers/dma-buf/sync_debug.h
index 05e33f937ad0..6176e52ba2d7 100644
--- a/drivers/dma-buf/sync_debug.h
+++ b/drivers/dma-buf/sync_debug.h
@@ -68,6 +68,5 @@ void sync_timeline_debug_add(struct sync_timeline *obj);
void sync_timeline_debug_remove(struct sync_timeline *obj);
void sync_file_debug_add(struct sync_file *fence);
void sync_file_debug_remove(struct sync_file *fence);
-void sync_dump(void);
#endif /* _LINUX_SYNC_H */
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details == Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59761/ State : success == Summary == CI Bug Log - changes from CI_DRM_5958 -> Patchwork_12844 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59761/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12844 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +50 * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@gtt-bsd: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] +98 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 - fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47 * igt@i915_selftest@live_execlists: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_busy@basic-flip-c: - fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-glk-dsi: PASS -> FAIL [fdo#103191] * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 * igt@kms_psr@primary_page_flip: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +48 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-glk-dsi: FAIL [fdo#103191] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 Participating hosts (36 -> 41) -- Additional (10): fi-bxt-dsi fi-byt-j1900 fi-icl-u2 fi-bwr-2160 fi-apl-guc fi-snb-2520m fi-byt-clapper fi-hsw-4770 fi-icl-y fi-bsw-kefka Missing(5): fi-ilk-m540 fi-byt-squawks fi-ctg-p8600 fi-ivb-3770 fi-bdw-samus Build changes - * Linux: CI_DRM_5958 -> Patchwork_12844 CI_DRM_5958: dabbe59fd2bb5dca3d2607c49369161ec7160df3 @ git://anongit.freedesktop.org/gfx-ci/linux
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details == Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59761/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Disable preemption and sleeping while using the punit sideband -drivers/gpu/drm/i915/selftests/../i915_drv.h:3618:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3619:16: warning: expression using sizeof(void) Commit: drm/i915: Lift acquiring the vlv punit magic to a common sb-get -drivers/gpu/drm/i915/selftests/../i915_drv.h:3619:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void) Commit: drm/i915: Lift sideband locking for vlv_punit_(read|write) Okay! Commit: drm/i915: Reduce RPS update frequency on Valleyview/Cherryview Okay! Commit: Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3" Okay! Commit: drm/i915: Replace pcu_lock with sb_lock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void) Commit: drm/i915: Separate sideband declarations to intel_sideband.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3587:16: warning: expression using sizeof(void) Commit: drm/i915: Merge sbi read/write into a single accessor Okay! Commit: drm/i915: Merge sandybridge_pcode_(read|write) Okay! Commit: drm/i915: Move sandybride pcode access to intel_sideband.c -drivers/gpu/drm/i915/selftests/../i915_drv.h:3587:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3577:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a0358d2f0eb drm/i915: Disable preemption and sleeping while using the punit
sideband
ac0bbbdf8ffd drm/i915: Lift acquiring the vlv punit magic to a common sb-get
996c149bc68c drm/i915: Lift sideband locking for vlv_punit_(read|write)
17d443c65fc8 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
5158724f31b4 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail
v3"
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#17:
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on
Baytrail v3")
-:17: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6067a27d1f01 ("drm/i915: Avoid
tweaking evaluation thresholds on Baytrail v3")'
#17:
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on
Baytrail v3")
total: 1 errors, 1 warnings, 0 checks, 19 lines checked
9e3f2a44bd33 drm/i915: Replace pcu_lock with sb_lock
cbd87000b066 drm/i915: Separate sideband declarations to intel_sideband.h
-:324: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#324:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 402 lines checked
0cc59105d0b5 drm/i915: Merge sbi read/write into a single accessor
ce383cc80b7e drm/i915: Merge sandybridge_pcode_(read|write)
07ec1cc6ae6f drm/i915: Move sandybride pcode access to intel_sideband.c
___
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[Intel-gfx] [PATCH] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimising the amount of state it needs to reload and manually save
across batches.
v2: CONSTANT_BUFFER woes
Running through piglit turned up an interesting issue, a GPU hang inside
the context load. The context image includes the CONSTANT_BUFFER command
that loads an address into a on-gpu buffer, and the context load was
executing that immediately. However, since it was reading from the GTT
there is no guarantee that the GTT retains the same configuration as
when the context was saved, resulting in stray reads and a GPU hang.
Having tried issuing a CONSTANT_BUFFER (to disable the command) from the
ring before saving the context to no avail, we resort to patching out
the instruction inside the context image before loading.
This does impose that gen4 always reissues CONSTANT_BUFFER commands on
each batch, but due to the use of a shared GTT that was and will remain
a requirement.
v3: ECOSKPD to the rescue
Ville found the magic bit in the ECOSKPD to disable saving and restoring
the CONSTANT_BUFFER from the context image, thereby completely avoiding
the GPU hangs from chasing invalid pointers. This appears to be the
default behaviour for gen5, and so we just need to tweak gen4 to match.
v4: Fix spelling of ECOSKPD and discover it already exists
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Kenneth Graunke
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..6f0a0866c802 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2870,6 +2870,7 @@ enum i915_power_well_id {
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
#define ECOSKPD_MMIO(0x21d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
#define ECO_GATING_CX_ONLY (1 << 3)
#define ECO_FLIP_DONE(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index fc8be2fcb4e6..f9db2e0bca12 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -211,6 +211,7 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ case 4:
/*
* There is a discrepancy here between the size reported
* by the register and the size of the context layout
@@ -227,7 +228,6 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
- case 4:
case 3:
case 2:
/* For the special day when i810 gets merged. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2d2e33cd3fae..a19c50147f6c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -832,6 +832,20 @@ static int init_render_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ /*
+* Disable CONSTANT_BUFFER before it is loaded from the context
+* image. For as it is loaded, it is executed and the stored
+* address may no longer be valid, leading to a GPU hang.
+*
+* This imposes the requirement that userspace reload their
+* CONSTANT_BUFFER on every batch, fortunately a requirement
+* they are already accustomed to from before contexts were
+* enabled.
+*/
+ if (IS_GEN(dev_priv, 4))
+ I915_WRITE(ECOSKPD,
+ _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
+
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
if (IS_GEN_RANGE(dev_priv, 4, 6))
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
--
2.20.1
___
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Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/uc: Reserve upper range of GGTT
Quoting Fernando Pacheco (2019-04-19 18:14:21)
>
> On 4/19/19 12:14 AM, Chris Wilson wrote:
> > Quoting Fernando Pacheco (2019-04-19 00:31:48)
> >> - /* Trim the GGTT to fit the GuC mappable upper range (when
> >> enabled).
> >> -* This is easier than doing range restriction on the fly, as we
> >> -* currently don't have any bits spare to pass in this upper
> >> -* restriction!
> >> -*/
> >> - if (USES_GUC(dev_priv)) {
> >> - ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
> >> - ggtt->mappable_end =
> >> - min_t(u64, ggtt->mappable_end, ggtt->vm.total);
> >> - }
[snip
> It is unlikely, but should there be a check in case GUC_GGTT_TOP exceeds
> vm.total and
> adjust the start accordingly? Or should we let this bail? GEM_BUG_ON?
If GUC_GGTT_TOP is outside the range of vm.total, that should give us a
bogus address for the drm_mm_reserve_node, and that should fail. That
seems reasonable, if we can't support the guc with the current GGTT
setup we probably do want to bail and get it fixed (as something would
be very wrong with the GGTT probe, one presumes).
-Chris
___
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Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/uc: Reserve upper range of GGTT
On 4/19/19 12:14 AM, Chris Wilson wrote:
> Quoting Fernando Pacheco (2019-04-19 00:31:48)
>> GuC and HuC depend on struct_mutex for device
>> reinitialization. Moving away from this dependency
>> requires perma-pinning the firmware images in GGTT.
>> The upper portion of the GuC address space has
>> a sizeable hole (several MB) that is inaccessible
>> by GuC. Reserve this range within GGTT as it can
>> comfortably hold GuC/HuC firmware images.
>>
>> v2: Reserve node rather than insert (Chris)
>> Simpler determination of node start/size (Daniele)
>> Move reserve/release out to intel_guc.* files
>>
>> Signed-off-by: Fernando Pacheco
>> ---
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 25
>> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
>> drivers/gpu/drm/i915/intel_guc.c| 45 +
>> drivers/gpu/drm/i915/intel_guc.h| 2 ++
>> 4 files changed, 60 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 8f460cc4cc1f..0b4c22e68574 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2752,6 +2752,12 @@ int i915_gem_init_ggtt(struct drm_i915_private
>> *dev_priv)
>> if (ret)
>> return ret;
>>
>> + if (USES_GUC(dev_priv)) {
>> + ret = intel_guc_reserve_ggtt_top(_priv->guc);
>> + if (ret)
>> + goto err_reserve;
>> + }
>> +
>> /* Clear any non-preallocated blocks */
>> drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
>> DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
>> @@ -2766,12 +2772,14 @@ int i915_gem_init_ggtt(struct drm_i915_private
>> *dev_priv)
>> if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>> ret = i915_gem_init_aliasing_ppgtt(dev_priv);
>> if (ret)
>> - goto err;
>> + goto err_appgtt;
>> }
>>
>> return 0;
>>
>> -err:
>> +err_appgtt:
>> + intel_guc_release_ggtt_top(_priv->guc);
>> +err_reserve:
>> drm_mm_remove_node(>error_capture);
>> return ret;
>> }
>> @@ -2797,6 +2805,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
>> *dev_priv)
>> if (drm_mm_node_allocated(>error_capture))
>> drm_mm_remove_node(>error_capture);
>>
>> + intel_guc_release_ggtt_top(_priv->guc);
>> +
>> if (drm_mm_initialized(>vm.mm)) {
>> intel_vgt_deballoon(dev_priv);
>> i915_address_space_fini(>vm);
>> @@ -3369,17 +3379,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private
>> *dev_priv)
>> if (ret)
>> return ret;
>>
>> - /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
>> -* This is easier than doing range restriction on the fly, as we
>> -* currently don't have any bits spare to pass in this upper
>> -* restriction!
>> -*/
>> - if (USES_GUC(dev_priv)) {
>> - ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
>> - ggtt->mappable_end =
>> - min_t(u64, ggtt->mappable_end, ggtt->vm.total);
>> - }
>> -
>> if ((ggtt->vm.total - 1) >> 32) {
>> DRM_ERROR("We never expected a Global GTT with more than
>> 32bits"
>> " of address space! Found %lldM!\n",
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
>> b/drivers/gpu/drm/i915/i915_gem_gtt.h
>> index f597f35b109b..b51e779732c3 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
>> @@ -384,6 +384,7 @@ struct i915_ggtt {
>> u32 pin_bias;
>>
>> struct drm_mm_node error_capture;
>> + struct drm_mm_node uc_fw;
>> };
>>
>> struct i915_hw_ppgtt {
>> diff --git a/drivers/gpu/drm/i915/intel_guc.c
>> b/drivers/gpu/drm/i915/intel_guc.c
>> index d81a02b0f525..ddd246dc3f14 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -721,3 +721,48 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
>> {
>> return guc_to_i915(guc)->wopcm.guc.size;
>> }
>> +
>> +static u32 __intel_guc_ggtt_top_offset(struct intel_guc *guc)
>> +{
>> + struct drm_i915_private *i915 = guc_to_i915(guc);
>> + struct i915_ggtt *ggtt = >ggtt;
>> + struct intel_huc *huc = >huc;
>> + u32 guc_fw_size, huc_fw_size;
>> + u32 min_reserved_size;
>> +
>> + guc_fw_size = round_up(guc->fw.size, I915_GTT_PAGE_SIZE);
>> + huc_fw_size = round_up(huc->fw.size, I915_GTT_PAGE_SIZE);
>> +
>> + min_reserved_size = guc_fw_size + huc_fw_size;
> In this patch, you should only be using GUC_GGTT_TOP so that the only
> change is from excluding the zone to using a reserved node.
>
>
> So why reserve room for both fw? You should only be binding them
[Intel-gfx] [PATCH 06/10] drm/i915: Replace pcu_lock with sb_lock
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pcu_lock is now redudant
and can be separated from its other use to regulate RPS (essentially
giving RPS a lock all of its own).
v2: Extract a couple of minor bug fixes.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++---
drivers/gpu/drm/i915/intel_cdclk.c | 28 --
drivers/gpu/drm/i915/intel_display.c| 6 --
drivers/gpu/drm/i915/intel_hdcp.c | 2 -
drivers/gpu/drm/i915/intel_pm.c | 128
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 --
drivers/gpu/drm/i915/intel_sideband.c | 4 -
10 files changed, 83 insertions(+), 166 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 83253928e69d..93fd82a6ac2b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1045,8 +1045,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 rpmodectl, freq_sts;
- mutex_lock(_priv->pcu_lock);
-
rpmodectl = I915_READ(GEN6_RP_CONTROL);
seq_printf(m, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
@@ -1081,7 +1079,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv, rps->efficient_freq));
- mutex_unlock(_priv->pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
@@ -1486,12 +1483,9 @@ static int gen6_drpc_info(struct seq_file *m)
gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(dev_priv) <= 7) {
- mutex_lock(_priv->pcu_lock);
+ if (INTEL_GEN(dev_priv) <= 7)
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
);
- mutex_unlock(_priv->pcu_lock);
- }
seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -1755,17 +1749,10 @@ static int i915_ring_freq_table(struct seq_file *m,
void *unused)
unsigned int max_gpu_freq, min_gpu_freq;
intel_wakeref_t wakeref;
int gpu_freq, ia_freq;
- int ret;
if (!HAS_LLC(dev_priv))
return -ENODEV;
- wakeref = intel_runtime_pm_get(dev_priv);
-
- ret = mutex_lock_interruptible(_priv->pcu_lock);
- if (ret)
- goto out;
-
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
@@ -1776,6 +1763,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring
freq (MHz)\n");
+ wakeref = intel_runtime_pm_get(dev_priv);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
sandybridge_pcode_read(dev_priv,
@@ -1789,12 +1777,9 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
((ia_freq >> 0) & 0xff) * 100,
((ia_freq >> 8) & 0xff) * 100);
}
-
- mutex_unlock(_priv->pcu_lock);
-
-out:
intel_runtime_pm_put(dev_priv, wakeref);
- return ret;
+
+ return 0;
}
static int i915_opregion(struct seq_file *m, void *unused)
@@ -2031,13 +2016,11 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- mutex_lock(_priv->pcu_lock);
vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
- mutex_unlock(_priv->pcu_lock);
} else {
act_freq = intel_get_cagf(dev_priv,
I915_READ(GEN6_RPSTAT1));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index
[Intel-gfx] [PATCH 09/10] drm/i915: Merge sandybridge_pcode_(read|write)
These routines are identical except in the nature of the value parameter.
For writes it is a pure in-param, but for a read, we need an out-param.
Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 115 +++-
1 file changed, 40 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9a810d0683f7..c9a321aa5d26 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9714,12 +9714,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_UNIMPLEMENTED_CMD:
@@ -9732,17 +9730,15 @@ static inline int gen6_check_mailbox_status(struct
drm_i915_private *dev_priv)
case GEN6_PCODE_TIMEOUT:
return -ETIMEDOUT;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_ILLEGAL_CMD:
@@ -9754,19 +9750,21 @@ static inline int gen7_check_mailbox_status(struct
drm_i915_private *dev_priv)
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static int
-__sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
+ u32 mbox, u32 *val,
+ int fast_timeout_us,
+ int slow_timeout_ms,
+ bool is_read)
{
- int status;
-
lockdep_assert_held(_priv->sb_lock);
- /* GEN6_PCODE_* are outside of the forcewake domain, we can
+ /*
+* GEN6_PCODE_* are outside of the forcewake domain, we can
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
@@ -9780,70 +9778,37 @@ __sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u32 mbox, u32 *val)
if (__intel_wait_for_register_fw(_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY,
0,
-500, 0, NULL))
+fast_timeout_us,
+slow_timeout_ms,
+))
return -ETIMEDOUT;
- *val = I915_READ_FW(GEN6_PCODE_DATA);
- I915_WRITE_FW(GEN6_PCODE_DATA, 0);
+ if (is_read)
+ *val = I915_READ_FW(GEN6_PCODE_DATA);
if (INTEL_GEN(dev_priv) > 6)
- status = gen7_check_mailbox_status(dev_priv);
+ return gen7_check_mailbox_status(dev_priv, mbox);
else
- status = gen6_check_mailbox_status(dev_priv);
-
- return status;
+ return gen6_check_mailbox_status(dev_priv, mbox);
}
int
sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
{
- int status;
+ int err;
mutex_lock(_priv->sb_lock);
- status = __sandybridge_pcode_read(dev_priv, mbox, val);
+ err = __sandybridge_pcode_rw(dev_priv, mbox, val,
+500, 0,
+true);
mutex_unlock(_priv->sb_lock);
- if (status) {
+ if (err) {
DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox
access failed for %ps: %d\n",
-mbox, __builtin_return_address(0), status);
+mbox, __builtin_return_address(0), err);
}
- return status;
-}
-
-static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
-u32 mbox, u32 val,
-
[Intel-gfx] [PATCH 05/10] Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
With the vlv sideband fixed to avoid sleeping while we talk to the
punit, the system should be much more stable and be able to utilise the
punit without risk.
This reverts commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation
thresholds on Baytrail v3")
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on
Baytrail v3")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Len Brown
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: frit...@xbmc.org
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ba6d3d1adf6c..df33555b8053 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6606,12 +6606,6 @@ static void rps_set_power(struct drm_i915_private
*dev_priv, int new_power)
ei_down <<= 2;
}
- /* When byt can survive without system hang with dynamic
-* sw freq adjustments, this restriction can be lifted.
-*/
- if (IS_VALLEYVIEW(dev_priv))
- goto skip_hw_write;
-
I915_WRITE(GEN6_RP_UP_EI,
GT_INTERVAL_FROM_US(dev_priv, ei_up));
I915_WRITE(GEN6_RP_UP_THRESHOLD,
@@ -6632,7 +6626,6 @@ static void rps_set_power(struct drm_i915_private
*dev_priv, int new_power)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
-skip_hw_write:
rps->power.mode = new_power;
rps->power.up_threshold = threshold_up;
rps->power.down_threshold = threshold_down;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Nefarious Baytrail
This allows my byt-j1900 to run gem_concurrent_blit without a hard lockup, ymmv. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h
Split the sideback declarations out of the ginormous i915_drv.h
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile.header-test | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 120
drivers/gpu/drm/i915/i915_sysfs.c | 2 +
drivers/gpu/drm/i915/intel_cdclk.c| 1 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 13 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 2 +
drivers/gpu/drm/i915/intel_sideband.h | 130 ++
drivers/gpu/drm/i915/vlv_dsi.c| 2 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c| 4 +-
16 files changed, 157 insertions(+), 126 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_sideband.h
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
index c1c391816fa7..20ee9321dbb3 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -31,6 +31,7 @@ header_test := \
intel_pipe_crc.h \
intel_pm.h \
intel_psr.h \
+ intel_sideband.h \
intel_sdvo.h \
intel_sprite.h \
intel_tv.h \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 93fd82a6ac2b..850ad072d1e0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -41,6 +41,7 @@
#include "intel_hdmi.h"
#include "intel_pm.h"
#include "intel_psr.h"
+#include "intel_sideband.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6eb12f11ab65..f4879fb41aa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -541,11 +541,6 @@ enum intel_pch {
PCH_ICP,/* Ice Lake PCH */
};
-enum intel_sbi_destination {
- SBI_ICLK,
- SBI_MPHY,
-};
-
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
@@ -3442,121 +3437,6 @@ int sandybridge_pcode_write_timeout(struct
drm_i915_private *dev_priv, u32 mbox,
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-/* intel_sideband.c */
-
-enum {
- VLV_IOSF_SB_BUNIT,
- VLV_IOSF_SB_CCK,
- VLV_IOSF_SB_CCU,
- VLV_IOSF_SB_DPIO,
- VLV_IOSF_SB_FLISDSI,
- VLV_IOSF_SB_GPIO,
- VLV_IOSF_SB_NC,
- VLV_IOSF_SB_PUNIT,
-};
-
-void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
- u8 port, u32 reg, u32 val);
-void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
-
-static inline void vlv_bunit_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_bunit_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-static inline void vlv_cck_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
-void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_cck_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-static inline void vlv_ccu_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_ccu_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-static inline void vlv_dpio_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *i915,
- enum pipe pipe, int reg, u32 val);
-
-static inline void vlv_dpio_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
-}
-
-u32 vlv_flisdsi_read(struct
[Intel-gfx] [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idle) doesn't provide a sufficient barrier to ensure that all core
are indeed awake (out of Cstate) and that the package is awake. To do so,
we need to supplement the pm_qos with a manual ping on_each_cpu.
v2: Restrict the heavy-weight wakeup to just the ISOF_PORT_PUNIT, there
is insufficient evidence to implicate a wider problem atm. Similarly,
restrict the w/a to Valleyview, as Cherryview doesn't have an angry cadre
of users.
The working theory, courtesy of Ville and Hans, is the issue lies within
the power delivery and so is likely to be unit and board specific and
occurs when both the unit/fw require extra power at the same time as the
cpu package is changing its own power state.
References: https://bugzilla.kernel.org/show_bug.cgi?id=109051
References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
References: https://bugzilla.kernel.org/show_bug.cgi?id=195255
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Hans de Goede
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 203 +-
3 files changed, 139 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5e2ae2300454..9e657a0410c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -884,6 +884,9 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(_priv->backlight_lock);
mutex_init(_priv->sb_lock);
+ pm_qos_add_request(_priv->sb_qos,
+ PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+
mutex_init(_priv->av_mutex);
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
@@ -943,6 +946,9 @@ static void i915_driver_cleanup_early(struct
drm_i915_private *dev_priv)
i915_gem_cleanup_early(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
+
+ pm_qos_remove_request(_priv->sb_qos);
+ mutex_destroy(_priv->sb_lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71612e7fc8bc..afb979ff416f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1561,6 +1561,7 @@ struct drm_i915_private {
/* Sideband mailbox protection */
struct mutex sb_lock;
+ struct pm_qos_request sb_qos;
/** Cached value of IMR to avoid reads in updating the bitfield */
union {
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 57de41b1f989..fc8913461622 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -22,6 +22,8 @@
*
*/
+#include
+
#include "i915_drv.h"
#include "intel_drv.h"
@@ -39,19 +41,50 @@
/* Private register write, double-word addressing, non-posted */
#define SB_CRWRDA_NP 0x07
-static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
- u32 port, u32 opcode, u32 addr, u32 *val)
+static void ping(void *info)
{
- u32 cmd, be = 0xf, bar = 0;
- bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
+}
- cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
- (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
- (bar << IOSF_BAR_SHIFT);
+static void __vlv_punit_get(struct drm_i915_private *i915)
+{
+ iosf_mbi_punit_acquire();
- WARN_ON(!mutex_is_locked(_priv->sb_lock));
+ /*
+* Prevent the cpu from sleeping while we use this sideband, otherwise
+* the punit may cause a machine hang. The issue appears to be isolated
+* with changing the power state of the CPU package while changing
+* the power state via the punit, and we have only observed it
+* reliably on 4-core Baytail systems suggesting the issue is in the
+* power delivery mechanism and likely to be be board/function
+* specific. Hence we presume the workaround needs only be applied
+* to the Valleyview P-unit and not all sideband communications.
+*/
+ if (IS_VALLEYVIEW(i915)) {
+ pm_qos_update_request(>sb_qos, 0);
+ on_each_cpu(ping, NULL, 1);
+ }
+}
- if (intel_wait_for_register(_priv->uncore,
+static void __vlv_punit_put(struct drm_i915_private *i915)
+{
+ if (IS_VALLEYVIEW(i915))
+ pm_qos_update_request(>sb_qos, PM_QOS_DEFAULT_VALUE);
+
+ iosf_mbi_punit_release();
+}
+
+static int vlv_sideband_rw(struct drm_i915_private *i915,
+ u32 devfn, u32 port, u32 opcode,
+
[Intel-gfx] [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write)
Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
into their callers, so that we can lock the sideband once for a sequence
of operations, rather than perform the heavyweight acquisition on each
request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++
drivers/gpu/drm/i915/i915_sysfs.c | 14
drivers/gpu/drm/i915/intel_cdclk.c | 23 ++---
drivers/gpu/drm/i915/intel_display.c| 16 +
drivers/gpu/drm/i915/intel_pm.c | 46 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++
drivers/gpu/drm/i915/intel_sideband.c | 18 ++
7 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..83253928e69d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1056,7 +1056,10 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
+ vlv_punit_get(dev_priv);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
+
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -2029,8 +2032,10 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
mutex_lock(_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
mutex_unlock(_priv->pcu_lock);
} else {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..bfabb3de4808 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -259,25 +259,25 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
intel_wakeref_t wakeref;
- int ret;
+ u32 freq;
wakeref = intel_runtime_pm_get(dev_priv);
mutex_lock(_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- u32 freq;
+ vlv_punit_get(dev_priv);
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
+ vlv_punit_put(dev_priv);
+
+ freq = (freq >> 8) & 0xff;
} else {
- ret = intel_gpu_freq(dev_priv,
-intel_get_cagf(dev_priv,
- I915_READ(GEN6_RPSTAT1)));
+ freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1));
}
mutex_unlock(_priv->pcu_lock);
intel_runtime_pm_put(dev_priv, wakeref);
- return snprintf(buf, PAGE_SIZE, "%d\n", ret);
+ return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
}
static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 5845d0a37599..9dd22203a7e8 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -464,13 +464,19 @@ static void vlv_get_cdclk(struct drm_i915_private
*dev_priv,
{
u32 val;
+ mutex_lock(_priv->pcu_lock);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
+
cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_state->vco);
- mutex_lock(_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
+
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
mutex_unlock(_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv))
@@ -545,6 +551,11 @@ static void vlv_set_cdclk(struct drm_i915_private
*dev_priv,
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) |
+ BIT(VLV_IOSF_SB_BUNIT) |
+ BIT(VLV_IOSF_SB_PUNIT));
+
mutex_lock(_priv->pcu_lock);
val = vlv_punit_read(dev_priv,
[Intel-gfx] [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get
As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and release, moving it from the lowlevel punit rw
routine to the callers. In the first step, we move the punit magic into
the common sideband lock so that we can acquire a bunch of ports
simultaneously, and if need be extend the workaround protection later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 124 +---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +-
drivers/gpu/drm/i915/intel_display.c| 37 +++
drivers/gpu/drm/i915/intel_dp.c | 4 +-
drivers/gpu/drm/i915/intel_dpio_phy.c | 37 +++
drivers/gpu/drm/i915/intel_dsi_vbt.c| 8 +-
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
drivers/gpu/drm/i915/intel_sideband.c | 45 ++---
drivers/gpu/drm/i915/vlv_dsi.c | 8 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c | 14 +--
12 files changed, 206 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index afb979ff416f..162d988dbceb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3449,25 +3449,119 @@ int skl_pcode_request(struct drm_i915_private
*dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
/* intel_sideband.c */
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
-int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
-u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg,
u32 val);
-u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int
reg, u32 val);
+
+enum {
+ VLV_IOSF_SB_BUNIT,
+ VLV_IOSF_SB_CCK,
+ VLV_IOSF_SB_CCU,
+ VLV_IOSF_SB_DPIO,
+ VLV_IOSF_SB_FLISDSI,
+ VLV_IOSF_SB_GPIO,
+ VLV_IOSF_SB_NC,
+ VLV_IOSF_SB_PUNIT,
+};
+
+void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
+u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *i915,
+ u8 port, u32 reg, u32 val);
+void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
+
+static inline void vlv_bunit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_bunit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+static inline void vlv_cck_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
+void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_cck_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+static inline void vlv_ccu_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_ccu_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+static inline void vlv_dpio_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *i915,
+ enum pipe pipe, int reg, u32 val);
+
+static inline void vlv_dpio_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
+void
[Intel-gfx] [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
Valleyview and Cherryview update the GPU frequency via the punit, which
is very expensive as we have to ensure the cores do not sleep during the
comms. If we perform frequent RPS evaluations, the frequent punit
requests cause measurable system overhead for little benefit, so
increase the evaluation intervals to reduce the number of times we try
and change frequency.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9db39ea9bd83..ba6d3d1adf6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6593,6 +6593,19 @@ static void rps_set_power(struct drm_i915_private
*dev_priv, int new_power)
break;
}
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ /*
+* Baytrail and Braswell control the gpu frequency via the
+* punit, which is very slow and expensive to communicate with,
+* as we synchronously force the package to C0. If we try and
+* update the gpufreq too often we cause measurable system
+* load for little benefit (effectively stealing CPU time for
+* the GPU, negatively impacting overall throughput).
+*/
+ ei_up <<= 2;
+ ei_down <<= 2;
+ }
+
/* When byt can survive without system hang with dynamic
* sw freq adjustments, this restriction can be lifted.
*/
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor
Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.
v2: Restore vlv_flisdsi_read() lost during rebasing.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_sideband.c | 94 +++
1 file changed, 38 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 5c3ae5185a01..7113fb8850d6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -273,81 +273,63 @@ void vlv_flisdsi_write(struct drm_i915_private *i915, u32
reg, u32 val)
}
/* SBI access */
-u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
- enum intel_sbi_destination destination)
+static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination,
+ u32 *val, bool is_read)
{
- u32 value = 0;
+ struct intel_uncore *uncore = >uncore;
+ u32 cmd;
- lockdep_assert_held(_priv->sb_lock);
+ lockdep_assert_held(>sb_lock);
- if (intel_wait_for_register(_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
+ if (intel_wait_for_register_fw(uncore,
+ SBI_CTL_STAT, SBI_BUSY, 0,
+ 100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
- return 0;
+ return -EBUSY;
}
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, 0);
+ intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
+ intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
if (destination == SBI_ICLK)
- value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
+ cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
else
- value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
- I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
-
- if (intel_wait_for_register(_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
+ cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
+ if (!is_read)
+ cmd |= BIT(8);
+ intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
+
+ if (__intel_wait_for_register_fw(uncore,
+SBI_CTL_STAT, SBI_BUSY, 0,
+100, 100, )) {
DRM_ERROR("timeout waiting for SBI to complete read\n");
- return 0;
+ return -ETIMEDOUT;
}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+ if (cmd & SBI_RESPONSE_FAIL) {
DRM_ERROR("error during SBI read of reg %x\n", reg);
- return 0;
+ return -ENXIO;
}
- return I915_READ(SBI_DATA);
+ if (is_read)
+ *val = intel_uncore_read_fw(uncore, SBI_DATA);
+
+ return 0;
}
-void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
-enum intel_sbi_destination destination)
+u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination)
{
- u32 tmp;
+ u32 result = 0;
- lockdep_assert_held(_priv->sb_lock);
+ intel_sbi_rw(i915, reg, destination, , true);
- if (intel_wait_for_register(_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to become ready\n");
- return;
- }
-
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, value);
-
- if (destination == SBI_ICLK)
- tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
- else
- tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
- I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
-
- if (intel_wait_for_register(_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to complete write\n");
- return;
- }
+ return result;
+}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
- DRM_ERROR("error during SBI write of %x to reg %x\n",
- value, reg);
- return;
- }
+void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
+enum intel_sbi_destination destination)
+{
+ intel_sbi_rw(i915, reg,
[Intel-gfx] [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c
sandybride_pcode is another sideband, so move it to their new home.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 195 -
drivers/gpu/drm/i915/intel_sideband.c | 196 ++
drivers/gpu/drm/i915/intel_sideband.h | 10 ++
5 files changed, 207 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4879fb41aa6..45c998870b87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3427,16 +3427,6 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_display_error_state
*error);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32
*val);
-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32
mbox,
- u32 val, int fast_timeout_us,
- int slow_timeout_ms);
-#define sandybridge_pcode_write(dev_priv, mbox, val) \
- sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
-
-int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms);
-
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 2476e867981d..ca5982e45e3e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -16,6 +16,7 @@
#include "i915_reg.h"
#include "intel_drv.h"
#include "intel_hdcp.h"
+#include "intel_sideband.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c9a321aa5d26..0904f5ff2deb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9714,201 +9714,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_UNIMPLEMENTED_CMD:
- return -ENODEV;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- case GEN6_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN7_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- case GEN7_PCODE_ILLEGAL_DATA:
- return -EINVAL;
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
- u32 mbox, u32 *val,
- int fast_timeout_us,
- int slow_timeout_ms,
- bool is_read)
-{
- lockdep_assert_held(_priv->sb_lock);
-
- /*
-* GEN6_PCODE_* are outside of the forcewake domain, we can
-* use te fw I915_READ variants to reduce the amount of work
-* required when reading/writing.
-*/
-
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
- return -EAGAIN;
-
- I915_WRITE_FW(GEN6_PCODE_DATA, *val);
- I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
- I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
-
- if (__intel_wait_for_register_fw(_priv->uncore,
-GEN6_PCODE_MAILBOX, GEN6_PCODE_READY,
0,
-fast_timeout_us,
-slow_timeout_ms,
-))
- return -ETIMEDOUT;
-
- if (is_read)
- *val = I915_READ_FW(GEN6_PCODE_DATA);
-
- if (INTEL_GEN(dev_priv) > 6)
-
Re: [Intel-gfx] [PATCH v3] drm/i915: add immutable zpos plane properties
On Thursday, April 18, 2019 8:20 AM, Simon Ser wrote: > On Wednesday, April 17, 2019 11:35 PM, Simon Ser cont...@emersion.fr wrote: > > > In terms of graphs, if a plane is a node and a two-plane overlap is an > > edge, it means we want a complete graph (each node has an edge to all > > other nodes). If we only have square planes, it's already impossible to > > get a solution for 4 planes (the graph contains an edge that crosses > > another edge [1]). > > The following is only true if all planes have an identical size (the > transformation from planes to the graph is lossy otherwise). It's > possible to choose different plane sizes and still be able to find a > solution without an alpha channel for 4 planes [1]. Thanks Léo Andrès > for pointing this out! > > Will investigate a little bit more, to see if I can find a general > formula for n planes. > > [1]: https://www.zapashcanon.fr/~leo/lohi2.png Discussed with Ville, and this solution won't work as older hardware doesn't have an alpha channel for overlay planes. Discussed with Martin, and the most reasonable solution seems to keep it simple and draw as many frames as there are planes. Frame i would show plane i as fullscreen and all planes but plane i as small squares on top or under it. This simple approach makes it easier to debug and still uses just a few frames. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
On Friday, April 19, 2019 4:16:01 AM PDT Chris Wilson wrote:
> Broadwater and the rest of gen4 do support being able to saving and
> reloading context specific registers between contexts, providing isolation
> of the basic GPU state (as programmable by userspace). This allows
> userspace to assume that the GPU retains their state from one batch to the
> next, minimising the amount of state it needs to reload and manually save
> across batches.
>
> v2: CONSTANT_BUFFER woes
>
> Running through piglit turned up an interesting issue, a GPU hang inside
> the context load. The context image includes the CONSTANT_BUFFER command
> that loads an address into a on-gpu buffer, and the context load was
> executing that immediately. However, since it was reading from the GTT
> there is no guarantee that the GTT retains the same configuration as
> when the context was saved, resulting in stray reads and a GPU hang.
>
> Having tried issuing a CONSTANT_BUFFER (to disable the command) from the
> ring before saving the context to no avail, we resort to patching out
> the instruction inside the context image before loading.
>
> This does impose that gen4 always reissues CONSTANT_BUFFER commands on
> each batch, but due to the use of a shared GTT that was and will remain
> a requirement.
>
> v3: ECOSPKD to the rescue
>
> Ville found the magic bit in the ECOSPKD to disable saving and restoring
> the CONSTANT_BUFFER from the context image, thereby completely avoiding
> the GPU hangs from chasing invalid pointers. This appears to be the
> default behaviour for gen5, and so we just need to tweak gen4 to match.
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Kenneth Graunke
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74824f0b5b1..5815703ac35f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2665,6 +2665,9 @@ enum i915_power_well_id {
> # define MODE_IDLE (1 << 9)
> # define STOP_RING (1 << 8)
>
> +#define ECOSPKD _MMIO(0x21d0)
> +# define CONSTANT_BUFFER_SR_DISABLE BIT(4)
> +
The name of this register is ECOSKPD (Scratch Pad, or SK PD).
The G45 PRM says it's DevBW-C1+. I can't recall if earlier ones
shipped or not. If so, we might be in trouble. But I've seen a
lot of DevBW-A/B warnings that I'm pretty sure I've safely ignored...
With the typo fixed, this patch is:
Reviewed-by: Kenneth Graunke
> #define GEN6_GT_MODE _MMIO(0x20d0)
> #define GEN7_GT_MODE _MMIO(0x7008)
> #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) <<
> 7))
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fc8be2fcb4e6..f9db2e0bca12 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -211,6 +211,7 @@ __intel_engine_context_size(struct drm_i915_private
> *dev_priv, u8 class)
> return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
> PAGE_SIZE);
> case 5:
> + case 4:
> /*
>* There is a discrepancy here between the size reported
>* by the register and the size of the context layout
> @@ -227,7 +228,6 @@ __intel_engine_context_size(struct drm_i915_private
> *dev_priv, u8 class)
>cxt_size * 64,
>cxt_size - 1);
> return round_up(cxt_size * 64, PAGE_SIZE);
> - case 4:
> case 3:
> case 2:
> /* For the special day when i810 gets merged. */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2d2e33cd3fae..26b276ed00b3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -832,6 +832,20 @@ static int init_render_ring(struct intel_engine_cs
> *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
>
> + /*
> + * Disable CONSTANT_BUFFER before it is loaded from the context
> + * image. For as it is loaded, it is executed and the stored
> + * address may no longer be valid, leading to a GPU hang.
> + *
> + * This imposes the requirement that userspace reload their
> + * CONSTANT_BUFFER on every batch, fortunately a requirement
> + * they are already accustomed to from before contexts were
> + * enabled.
> + */
> + if (IS_GEN(dev_priv, 4))
> + I915_WRITE(ECOSPKD,
> +
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming
On Fri, Apr 19, 2019 at 07:29:05PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote:
> > On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> > > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > > > Fix the order of lane, port parameters passed to the register
> > > > macro.
> > > >
> > > > Note that this was already partly fixed by commit
> > > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> > > > parameters order")
> > > >
> > > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> > > > consistent")
> > > > Cc: José Roberto de Souza
> > > > Cc: Lucas De Marchi
> > > > Cc: Aditya Swarup
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > drivers/gpu/drm/i915/intel_ddi.c | 18 --
> > > > 1 file changed, 8 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index 24f9106efcc6..f181c26f62fd 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -2905,21 +2905,20 @@ static void
> > > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > base.base.dev);
> > > > enum port port = dig_port->base.port;
> > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> > > > port) };
> > > > u32 val;
> > > > - int i;
> > > > + int ln;
> > > >
> > > > if (tc_port == PORT_TC_NONE)
> > > > return;
> > > >
> > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > > - val = I915_READ(mg_regs[i]);
> > > > + for (ln = 0; ln < 2; ln++) {
> > > > + val = I915_READ(MG_DP_MODE(ln, port));
> > > > val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> > > >MG_DP_MODE_CFG_TRPWR_GATING |
> > > >MG_DP_MODE_CFG_CLNPWR_GATING |
> > > >MG_DP_MODE_CFG_DIGPWR_GATING |
> > > >MG_DP_MODE_CFG_GAONPWR_GATING;
> > > > - I915_WRITE(mg_regs[i], val);
> > > > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > > > }
> > > >
> > > > val = I915_READ(MG_MISC_SUS0(tc_port));
> > > > @@ -2938,21 +2937,20 @@ static void
> > > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > base.base.dev);
> > > > enum port port = dig_port->base.port;
> > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> > > > 1) };
> > >
> > > I would split this fix from the change dropping mg_regs or at least
> > > tell that while you were fixing it you changed the way it reads
> > > each MG_DP_MODE line.
> >
> > I don't think it's worth a separate patch, since it's a small change
> > and quite obvious what and how changed. I can add a note to the
> > commit
> > message about making things simpler.
>
> I suggested split because this will probably be backported so would be
> nice to be as clean as possible but I'm also okay if you add it to the
> commit description.
No need to backport this, the regressing commit won't make it to 5.1.
Even if it had this fix would still go through -fixes since we're still
only in -rc5, and so we wouldn't need to backport anything. So this
change along with the rest of related macro param shuffling patches
won't appear until 5.2.
For the future: git fetch stable; git fetch linus-upstream followed by
git tag --contains makes it easy to see if something
needs backporting.
>
> >
> > >
> > > > u32 val;
> > > > - int i;
> > > > + int ln;
> > > >
> > > > if (tc_port == PORT_TC_NONE)
> > > > return;
> > > >
> > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > > - val = I915_READ(mg_regs[i]);
> > > > + for (ln = 0; ln < 2; ln++) {
> > > > + val = I915_READ(MG_DP_MODE(ln, port));
> > > > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> > > > MG_DP_MODE_CFG_TRPWR_GATING |
> > > > MG_DP_MODE_CFG_CLNPWR_GATING |
> > > > MG_DP_MODE_CFG_DIGPWR_GATING |
> > > > MG_DP_MODE_CFG_GAONPWR_GATING);
> > > > - I915_WRITE(mg_regs[i], val);
> > > > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > > > }
> > > >
> > > > val = I915_READ(MG_MISC_SUS0(tc_port));
> >
> >
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming
On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote:
> On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > > Fix the order of lane, port parameters passed to the register
> > > macro.
> > >
> > > Note that this was already partly fixed by commit
> > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> > > parameters order")
> > >
> > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> > > consistent")
> > > Cc: José Roberto de Souza
> > > Cc: Lucas De Marchi
> > > Cc: Aditya Swarup
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/intel_ddi.c | 18 --
> > > 1 file changed, 8 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 24f9106efcc6..f181c26f62fd 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2905,21 +2905,20 @@ static void
> > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > base.base.dev);
> > > enum port port = dig_port->base.port;
> > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> > > port) };
> > > u32 val;
> > > - int i;
> > > + int ln;
> > >
> > > if (tc_port == PORT_TC_NONE)
> > > return;
> > >
> > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > - val = I915_READ(mg_regs[i]);
> > > + for (ln = 0; ln < 2; ln++) {
> > > + val = I915_READ(MG_DP_MODE(ln, port));
> > > val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> > > MG_DP_MODE_CFG_TRPWR_GATING |
> > > MG_DP_MODE_CFG_CLNPWR_GATING |
> > > MG_DP_MODE_CFG_DIGPWR_GATING |
> > > MG_DP_MODE_CFG_GAONPWR_GATING;
> > > - I915_WRITE(mg_regs[i], val);
> > > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > > }
> > >
> > > val = I915_READ(MG_MISC_SUS0(tc_port));
> > > @@ -2938,21 +2937,20 @@ static void
> > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > base.base.dev);
> > > enum port port = dig_port->base.port;
> > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> > > 1) };
> >
> > I would split this fix from the change dropping mg_regs or at least
> > tell that while you were fixing it you changed the way it reads
> > each MG_DP_MODE line.
>
> I don't think it's worth a separate patch, since it's a small change
> and quite obvious what and how changed. I can add a note to the
> commit
> message about making things simpler.
I suggested split because this will probably be backported so would be
nice to be as clean as possible but I'm also okay if you add it to the
commit description.
>
> >
> > > u32 val;
> > > - int i;
> > > + int ln;
> > >
> > > if (tc_port == PORT_TC_NONE)
> > > return;
> > >
> > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > > - val = I915_READ(mg_regs[i]);
> > > + for (ln = 0; ln < 2; ln++) {
> > > + val = I915_READ(MG_DP_MODE(ln, port));
> > > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> > >MG_DP_MODE_CFG_TRPWR_GATING |
> > >MG_DP_MODE_CFG_CLNPWR_GATING |
> > >MG_DP_MODE_CFG_DIGPWR_GATING |
> > >MG_DP_MODE_CFG_GAONPWR_GATING);
> > > - I915_WRITE(mg_regs[i], val);
> > > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > > }
> > >
> > > val = I915_READ(MG_MISC_SUS0(tc_port));
>
>
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Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Fri, Apr 19, 2019 at 11:07:17AM +0200, Peter Zijlstra wrote: > On Fri, Apr 19, 2019 at 10:32:30AM +0200, Thomas Gleixner wrote: > > On Fri, 19 Apr 2019, Peter Zijlstra wrote: > > > On Thu, Apr 18, 2019 at 10:41:47AM +0200, Thomas Gleixner wrote: > > > > > > > +typedef bool (*stack_trace_consume_fn)(void *cookie, unsigned long > > > > addr, > > > > + bool reliable); > > > > > > > +void arch_stack_walk(stack_trace_consume_fn consume_entry, void > > > > *cookie, > > > > +struct task_struct *task, struct pt_regs *regs); > > > > +int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, > > > > void *cookie, > > > > +struct task_struct *task); > > > > > > This bugs me a little; ideally the _reliable() thing would not exists. > > > > > > Thomas said that the existing __save_stack_trace_reliable() is different > > > enough for the unification to be non-trivial, but maybe Josh can help > > > out? > > > > > > >From what I can see the biggest significant differences are: > > > > > > - it looks at the regs sets on the stack and for FP bails early > > > - bails for khreads and idle (after it does all the hard work!?!) That's done for a reason, see the "Success path" comments. > > > The first (FP checking for exceptions) should probably be reflected in > > > consume_fn(.reliable) anyway -- although that would mean a lot of extra > > > '?' entries where there are none today. > > > > > > And the second (KTHREAD/IDLE) is something that the generic code can > > > easily do before calling into the arch unwinder. > > > > And looking at the powerpc version of it, that has even more interesting > > extra checks in that function. > > Right, but not fundamentally different from determining @reliable I > think. > > Anyway, it would be good if someone knowledgable could have a look at > this. Yeah, we could probably do that. The flow would need to be changed a bit -- some of the errors are soft errors which most users don't care about because they just want a best effort. The soft errors can be remembered without breaking out of the loop, and just returned at the end. Most users could just ignore the return code. The only thing I'd be worried about is performance for the non-livepatch users, but I guess those checks don't look very expensive. And the x86 unwinders are already pretty slow anyway... -- Josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming
On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > Fix the order of lane, port parameters passed to the register macro.
> >
> > Note that this was already partly fixed by commit
> > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> > parameters order")
> >
> > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> > consistent")
> > Cc: José Roberto de Souza
> > Cc: Lucas De Marchi
> > Cc: Aditya Swarup
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 18 --
> > 1 file changed, 8 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 24f9106efcc6..f181c26f62fd 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2905,21 +2905,20 @@ static void
> > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > enum port port = dig_port->base.port;
> > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> > port) };
> > u32 val;
> > - int i;
> > + int ln;
> >
> > if (tc_port == PORT_TC_NONE)
> > return;
> >
> > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > - val = I915_READ(mg_regs[i]);
> > + for (ln = 0; ln < 2; ln++) {
> > + val = I915_READ(MG_DP_MODE(ln, port));
> > val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> >MG_DP_MODE_CFG_TRPWR_GATING |
> >MG_DP_MODE_CFG_CLNPWR_GATING |
> >MG_DP_MODE_CFG_DIGPWR_GATING |
> >MG_DP_MODE_CFG_GAONPWR_GATING;
> > - I915_WRITE(mg_regs[i], val);
> > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > }
> >
> > val = I915_READ(MG_MISC_SUS0(tc_port));
> > @@ -2938,21 +2937,20 @@ static void
> > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > enum port port = dig_port->base.port;
> > enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> > 1) };
>
> I would split this fix from the change dropping mg_regs or at least
> tell that while you were fixing it you changed the way it reads
> each MG_DP_MODE line.
I don't think it's worth a separate patch, since it's a small change
and quite obvious what and how changed. I can add a note to the commit
message about making things simpler.
>
>
> > u32 val;
> > - int i;
> > + int ln;
> >
> > if (tc_port == PORT_TC_NONE)
> > return;
> >
> > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> > - val = I915_READ(mg_regs[i]);
> > + for (ln = 0; ln < 2; ln++) {
> > + val = I915_READ(MG_DP_MODE(ln, port));
> > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> > MG_DP_MODE_CFG_TRPWR_GATING |
> > MG_DP_MODE_CFG_CLNPWR_GATING |
> > MG_DP_MODE_CFG_DIGPWR_GATING |
> > MG_DP_MODE_CFG_GAONPWR_GATING);
> > - I915_WRITE(mg_regs[i], val);
> > + I915_WRITE(MG_DP_MODE(ln, port), val);
> > }
> >
> > val = I915_READ(MG_MISC_SUS0(tc_port));
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming
On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> Fix the order of lane, port parameters passed to the register macro.
>
> Note that this was already partly fixed by commit
> 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> parameters order")
>
> Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically
> consistent")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Aditya Swarup
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 18 --
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 24f9106efcc6..f181c26f62fd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2905,21 +2905,20 @@ static void
> icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
> struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> enum port port = dig_port->base.port;
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1,
> port) };
> u32 val;
> - int i;
> + int ln;
>
> if (tc_port == PORT_TC_NONE)
> return;
>
> - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> - val = I915_READ(mg_regs[i]);
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_DP_MODE(ln, port));
> val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> MG_DP_MODE_CFG_TRPWR_GATING |
> MG_DP_MODE_CFG_CLNPWR_GATING |
> MG_DP_MODE_CFG_DIGPWR_GATING |
> MG_DP_MODE_CFG_GAONPWR_GATING;
> - I915_WRITE(mg_regs[i], val);
> + I915_WRITE(MG_DP_MODE(ln, port), val);
> }
>
> val = I915_READ(MG_MISC_SUS0(tc_port));
> @@ -2938,21 +2937,20 @@ static void
> icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> enum port port = dig_port->base.port;
> enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
I would split this fix from the change dropping mg_regs or at least
tell that while you were fixing it you changed the way it reads
each MG_DP_MODE line.
> u32 val;
> - int i;
> + int ln;
>
> if (tc_port == PORT_TC_NONE)
> return;
>
> - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> - val = I915_READ(mg_regs[i]);
> + for (ln = 0; ln < 2; ln++) {
> + val = I915_READ(MG_DP_MODE(ln, port));
> val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
>MG_DP_MODE_CFG_TRPWR_GATING |
>MG_DP_MODE_CFG_CLNPWR_GATING |
>MG_DP_MODE_CFG_DIGPWR_GATING |
>MG_DP_MODE_CFG_GAONPWR_GATING);
> - I915_WRITE(mg_regs[i], val);
> + I915_WRITE(MG_DP_MODE(ln, port), val);
> }
>
> val = I915_READ(MG_MISC_SUS0(tc_port));
signature.asc
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Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Fri, Apr 19, 2019 at 09:02:11AM +0200, Peter Zijlstra wrote: > On Thu, Apr 18, 2019 at 05:42:55PM +0200, Thomas Gleixner wrote: > > On Thu, 18 Apr 2019, Josh Poimboeuf wrote: > > > > Another idea I had (but never got a chance to work on) was to extend the > > > x86 unwind interface to all arches. So instead of the callbacks, each > > > arch would implement something like this API: > > > I surely thought about that, but after staring at all incarnations of > > arch/*/stacktrace.c I just gave up. > > > > Aside of that quite some archs already have callback based unwinders > > because they use them for more than stacktracing and just have a single > > implementation of that loop. > > > > I'm fine either way. We can start with x86 and then let archs convert over > > their stuff, but I wouldn't hold my breath that this will be completed in > > the forseeable future. > > I suggested the same to Thomas early on, and I even spend the time to > convert some $random arch to the iterator interface, and while it is > indeed entirely feasible, it is _far_ more work. > > The callback thing OTOH is flexible enough to do what we want to do now, > and allows converting most archs to it without too much pain (as Thomas > said, many archs are already in this form and only need minor API > adjustments), which gets us in a far better place than we are now. > > And we can always go to iterators later on. But I think getting the > generic unwinder improved across all archs is a really important first > step here. Fair enough. -- Josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
== Series Details ==
Series: drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
URL : https://patchwork.freedesktop.org/series/59753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5956_full -> Patchwork_12843_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12843_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> FAIL
* {igt@audio@hdmi-integrity-after-suspend}:
- shard-apl: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12843_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +5
* igt@gem_exec_capture@capture-bsd2:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +79
* igt@gem_media_vme:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +66
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@basic-flip-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_cursor_crc@cursor-512x512-random:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +75
* igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-skl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_lease@cursor_implicit_plane:
- shard-apl: NOTRUN -> FAIL [fdo#110278]
* igt@kms_lease@page_flip_implicit_plane:
- shard-apl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] +1
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_psr@psr2_dpms:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
Possible fixes
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: FAIL [fdo#108686] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: FAIL [fdo#103167] -> PASS +11
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#108145] / [fdo#110403] -> PASS
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: SKIP [fdo#109642] -> PASS
* igt@kms_psr@psr2_primary_render:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +4
Warnings
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-FAIL [fdo#110271] -> FAIL [fdo#104097]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
== Series Details == Series: drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info URL : https://patchwork.freedesktop.org/series/59753/ State : success == Summary == CI Bug Log - changes from CI_DRM_5956 -> Patchwork_12843 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59753/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12843 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +71 * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] Possible fixes * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: FAIL [fdo#108511] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#103191] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (46 -> 43) -- Additional (3): fi-byt-j1900 fi-bsw-n3050 fi-pnv-d510 Missing(6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_5956 -> Patchwork_12843 CI_DRM_5956: 84826560c8c7420ccf497f5ecce91862f357fac1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12843: b91f70cb967f435f77fb190e4387984835dc7482 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b91f70cb967f drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12843/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
== Series Details == Series: drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info URL : https://patchwork.freedesktop.org/series/59753/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info -drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3618:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
For consistency (and elegance!), add intel_device_info.has_rps.
The immediate boon is that RPS support is now emitted along the other
capabilities in the debug log and after errors.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 5 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 7 +--
4 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 066fd2a12851..71612e7fc8bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2585,6 +2585,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
+#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
+
#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f893c2cbce15..ffa2ee70a03d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -370,6 +370,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+ .has_rps = true, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
.ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \
@@ -417,6 +418,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+ .has_rps = true, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
@@ -470,6 +472,7 @@ static const struct intel_device_info intel_valleyview_info
= {
.num_pipes = 2,
.has_runtime_pm = 1,
.has_rc6 = 1,
+ .has_rps = true,
.display.has_gmch = 1,
.display.has_hotplug = 1,
.ppgtt_type = INTEL_PPGTT_FULL,
@@ -565,6 +568,7 @@ static const struct intel_device_info intel_cherryview_info
= {
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
+ .has_rps = true,
.has_logical_ring_contexts = 1,
.display.has_gmch = 1,
.ppgtt_type = INTEL_PPGTT_FULL,
@@ -640,6 +644,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_runtime_pm = 1, \
.display.has_csr = 1, \
.has_rc6 = 1, \
+ .has_rps = true, \
.display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0e579f158016..7a2f14eff699 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -118,6 +118,7 @@ enum intel_ppgtt_type {
func(has_pooled_eu); \
func(has_rc6); \
func(has_rc6p); \
+ func(has_rps); \
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 87f6fc6d5502..7aa9a8c12b54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7013,8 +7013,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
struct intel_device_info *info = mkwrite_device_info(i915);
/* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(i915))
+ if (intel_vgpu_active(i915)) {
info->has_rc6 = 0;
+ info->has_rps = false;
+ }
if (info->has_rc6 &&
IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
@@ -8716,7 +8718,8 @@ void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv)
if (HAS_RC6(dev_priv))
intel_enable_rc6(dev_priv);
- intel_enable_rps(dev_priv);
+ if (HAS_RPS(dev_priv))
+ intel_enable_rps(dev_priv);
if (HAS_LLC(dev_priv))
intel_enable_llc_pstate(dev_priv);
--
2.20.1
___
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Re: [Intel-gfx] [patch V2 22/29] tracing: Make ftrace_trace_userstack() static and conditional
On Thu, 18 Apr 2019 10:41:41 +0200
Thomas Gleixner wrote:
> It's only used in trace.c and there is absolutely no point in compiling it
> in when user space stack traces are not supported.
>
> Signed-off-by: Thomas Gleixner
> Cc: Steven Rostedt
Funny, these were moved out to global functions along with the
ftrace_trace_stack() but I guess they were never used.
This basically just does a partial revert of:
c0a0d0d3f6528 ("tracing/core: Make the stack entry helpers global")
> ---
> kernel/trace/trace.c | 14 --
> kernel/trace/trace.h |8
> 2 files changed, 8 insertions(+), 14 deletions(-)
>
> --- a/kernel/trace/trace.c
> +++ b/kernel/trace/trace.c
> @@ -159,6 +159,8 @@ static union trace_eval_map_item *trace_
> #endif /* CONFIG_TRACE_EVAL_MAP_FILE */
>
> static int tracing_set_tracer(struct trace_array *tr, const char *buf);
> +static void ftrace_trace_userstack(struct ring_buffer *buffer,
> +unsigned long flags, int pc);
>
> #define MAX_TRACER_SIZE 100
> static char bootup_tracer_buf[MAX_TRACER_SIZE] __initdata;
> @@ -2905,9 +2907,10 @@ void trace_dump_stack(int skip)
> }
> EXPORT_SYMBOL_GPL(trace_dump_stack);
>
> +#ifdef CONFIG_USER_STACKTRACE_SUPPORT
> static DEFINE_PER_CPU(int, user_stack_count);
>
> -void
> +static void
> ftrace_trace_userstack(struct ring_buffer *buffer, unsigned long flags, int
> pc)
> {
> struct trace_event_call *call = _user_stack;
> @@ -2958,13 +2961,12 @@ ftrace_trace_userstack(struct ring_buffe
> out:
> preempt_enable();
> }
> -
> -#ifdef UNUSED
Strange, I never knew about this ifdef. I would have nuked it when I
saw it.
Anyway,
Reviewed-by: Steven Rostedt (VMware)
-- Steve
> -static void __trace_userstack(struct trace_array *tr, unsigned long flags)
> +#else /* CONFIG_USER_STACKTRACE_SUPPORT */
> +static void ftrace_trace_userstack(struct ring_buffer *buffer,
> +unsigned long flags, int pc)
> {
> - ftrace_trace_userstack(tr, flags, preempt_count());
> }
> -#endif /* UNUSED */
> +#endif /* !CONFIG_USER_STACKTRACE_SUPPORT */
>
> #endif /* CONFIG_STACKTRACE */
>
> --- a/kernel/trace/trace.h
> +++ b/kernel/trace/trace.h
> @@ -782,17 +782,9 @@ void update_max_tr_single(struct trace_a
> #endif /* CONFIG_TRACER_MAX_TRACE */
>
> #ifdef CONFIG_STACKTRACE
> -void ftrace_trace_userstack(struct ring_buffer *buffer, unsigned long flags,
> - int pc);
> -
> void __trace_stack(struct trace_array *tr, unsigned long flags, int skip,
> int pc);
> #else
> -static inline void ftrace_trace_userstack(struct ring_buffer *buffer,
> - unsigned long flags, int pc)
> -{
> -}
> -
> static inline void __trace_stack(struct trace_array *tr, unsigned long flags,
>int skip, int pc)
> {
>
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE
*before* switch context
URL : https://patchwork.freedesktop.org/series/59752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5956_full -> Patchwork_12842_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12842_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> TIMEOUT
* {igt@audio@hdmi-integrity-after-suspend}:
- shard-apl: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12842_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_capture@capture-bsd2:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +42
* igt@i915_suspend@debugfs-reader:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +5
* igt@i915_suspend@forcewake:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#108566]
* igt@kms_busy@basic-flip-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_busy@extended-pageflip-hang-newfb-render-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-snb: PASS -> SKIP [fdo#109271]
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#109507]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +100
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_lease@cursor_implicit_plane:
- shard-apl: NOTRUN -> FAIL [fdo#110278]
* igt@kms_lease@page_flip_implicit_plane:
- shard-apl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#108341]
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_sysfs_edid_timing:
- shard-iclb: PASS -> FAIL [fdo#100047]
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@tools_test@tools_test:
- shard-apl: PASS -> SKIP [fdo#109271]
Possible fixes
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: FAIL [fdo#108686] -> PASS
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: SKIP [fdo#109349] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: FAIL [fdo#103167] -> PASS +9
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#108145] / [fdo#110403] -> PASS
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +4
Warnings
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-FAIL [fdo#110271] -> FAIL [fdo#104097]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#105363]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
== Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context URL : https://patchwork.freedesktop.org/series/59752/ State : success == Summary == CI Bug Log - changes from CI_DRM_5956 -> Patchwork_12842 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59752/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12842 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@gem_ctx_create@basic: - fi-elk-e7500: SKIP [fdo#109271] -> PASS +5 * igt@gem_ctx_exec@basic: - fi-bwr-2160:SKIP [fdo#109271] -> PASS +5 * igt@gem_ctx_param@basic-default: - fi-ilk-650: SKIP [fdo#109271] -> PASS +5 * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: FAIL [fdo#108511] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#103191] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (46 -> 36) -- Additional (1): fi-bsw-n3050 Missing(11): fi-ilk-m540 fi-hsw-peppy fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-icl-u3 fi-byt-n2820 fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_5956 -> Patchwork_12842 CI_DRM_5956: 84826560c8c7420ccf497f5ecce91862f357fac1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12842: 5123afc5f51d36b59e8132f25709b8e6a1678672 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5123afc5f51d drm/i915: Enable render context support for gen4 (Broadwater to Cantiga) ea8c760fb66f drm/i915: Enable render context support for Ironlake (gen5) 6469fe48fe5a drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12842/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest
== Series Details == Series: series starting with [1/4] drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest URL : https://patchwork.freedesktop.org/series/59751/ State : failure == Summary == Applying: drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest Using index info to reconstruct a base tree... Falling back to patching base and 3-way merge... CONFLICT (add/add): Merge conflict in integration-manifest Auto-merging integration-manifest error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimising the amount of state it needs to reload and manually save
across batches.
v2: CONSTANT_BUFFER woes
Running through piglit turned up an interesting issue, a GPU hang inside
the context load. The context image includes the CONSTANT_BUFFER command
that loads an address into a on-gpu buffer, and the context load was
executing that immediately. However, since it was reading from the GTT
there is no guarantee that the GTT retains the same configuration as
when the context was saved, resulting in stray reads and a GPU hang.
Having tried issuing a CONSTANT_BUFFER (to disable the command) from the
ring before saving the context to no avail, we resort to patching out
the instruction inside the context image before loading.
This does impose that gen4 always reissues CONSTANT_BUFFER commands on
each batch, but due to the use of a shared GTT that was and will remain
a requirement.
v3: ECOSPKD to the rescue
Ville found the magic bit in the ECOSPKD to disable saving and restoring
the CONSTANT_BUFFER from the context image, thereby completely avoiding
the GPU hangs from chasing invalid pointers. This appears to be the
default behaviour for gen5, and so we just need to tweak gen4 to match.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..5815703ac35f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2665,6 +2665,9 @@ enum i915_power_well_id {
# define MODE_IDLE (1 << 9)
# define STOP_RING (1 << 8)
+#define ECOSPKD_MMIO(0x21d0)
+# define CONSTANT_BUFFER_SR_DISABLE BIT(4)
+
#define GEN6_GT_MODE _MMIO(0x20d0)
#define GEN7_GT_MODE _MMIO(0x7008)
#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) <<
7))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index fc8be2fcb4e6..f9db2e0bca12 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -211,6 +211,7 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ case 4:
/*
* There is a discrepancy here between the size reported
* by the register and the size of the context layout
@@ -227,7 +228,6 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
- case 4:
case 3:
case 2:
/* For the special day when i810 gets merged. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2d2e33cd3fae..26b276ed00b3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -832,6 +832,20 @@ static int init_render_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ /*
+* Disable CONSTANT_BUFFER before it is loaded from the context
+* image. For as it is loaded, it is executed and the stored
+* address may no longer be valid, leading to a GPU hang.
+*
+* This imposes the requirement that userspace reload their
+* CONSTANT_BUFFER on every batch, fortunately a requirement
+* they are already accustomed to from before contexts were
+* enabled.
+*/
+ if (IS_GEN(dev_priv, 4))
+ I915_WRITE(ECOSPKD,
+ _MASKED_BIT_ENABLE(CONSTANT_BUFFER_SR_DISABLE));
+
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
if (IS_GEN_RANGE(dev_priv, 4, 6))
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest
Quoting Chris Wilson (2019-04-19 12:15:58) > From: Eric Anholt Hmm, wrong base. Apologies for the noise. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
Despite what I think the prm recommends, commit f2253bd9859b
("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
to be a huge mistake when enabling Ironlake contexts as the GPU would
hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
simple rendercopies with igt, do not suffer).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3844581f622c..8feb2d9b7b60 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1882,12 +1882,12 @@ static int ring_request_alloc(struct i915_request
*request)
*/
request->reserved_space += LEGACY_REQUEST_SIZE;
- ret = switch_context(request);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
if (ret)
return ret;
- /* Unconditionally invalidate GPU caches and TLBs. */
- ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
+ ret = switch_context(request);
if (ret)
return ret;
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Enable render context support for Ironlake (gen5)
Ironlake does support being able to saving and reloading context specific
registers between contexts, providing isolation of the basic GPU state
(as programmable by userspace). This allows userspace to assume that the
GPU retains their state from one batch to the next, minimising the
amount of state it needs to reload, or manually save and restore.
v2: Fix off-by-one in reading CXT_SIZE, and add a comment that the
CXT_SIZE and context-layout do not match in bspec, but the difference is
irrelevant as we overallocate the full page anyway (Ville).
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Kenneth Graunke
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_engine_cs.c | 16
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index eea9bec04f1b..fc8be2fcb4e6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -211,6 +211,22 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ /*
+* There is a discrepancy here between the size reported
+* by the register and the size of the context layout
+* in the docs. Both are described as authorative!
+*
+* The discrepancy is on the order of a few cachelines,
+* but the total is under one page (4k), which is our
+* minimum allocation anyway so it should all come
+* out in the wash.
+*/
+ cxt_size = I915_READ(CXT_SIZE) + 1;
+ DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+INTEL_GEN(dev_priv),
+cxt_size * 64,
+cxt_size - 1);
+ return round_up(cxt_size * 64, PAGE_SIZE);
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8feb2d9b7b60..2d2e33cd3fae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1640,11 +1640,14 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
/* These flags are for resource streamer on HSW+ */
flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
else
+ /* We need to save the extended state for powersaving modes */
flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
len = 4;
if (IS_GEN(i915, 7))
len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
+ else if (IS_GEN(i915, 5))
+ len += 2;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
flags &= ~MI_FORCE_RESTORE;
@@ -1673,6 +1676,14 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+ } else if (IS_GEN(i915, 5)) {
+ /*
+* This w/a is only listed for pre-production ilk a/b steppings,
+* but is also mentioned for programming the powerctx. To be
+* safe, just apply the workaround; we do not use SyncFlush so
+* this should never take effect and so be a no-op!
+*/
+ *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
if (force_restore) {
@@ -1726,6 +1737,8 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ } else if (IS_GEN(i915, 5)) {
+ *cs++ = MI_SUSPEND_FLUSH;
}
intel_ring_advance(rq, cs);
--
2.20.1
___
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[Intel-gfx] [PATCH 1/4] drm-tip: 2019y-04m-18d-17h-03m-51s UTC integration manifest
From: Eric Anholt --- integration-manifest | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 integration-manifest diff --git a/integration-manifest b/integration-manifest new file mode 100644 index ..09ab7d222dde --- /dev/null +++ b/integration-manifest @@ -0,0 +1,30 @@ +drm drm-fixes 00fd14ff3017f64a9a03a08291e4be0d87bedc17 + Merge branch 'drm-fixes-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-fixes +drm-misc drm-misc-fixes f5a9ed867c83875546c9aadd4ed8e785e9adcc3c + drm/sun4i: Fix component unbinding and component master deletion +drm-intel drm-intel-fixes f5c58ba18ab8ea2169670ed880e4d31ed772ad10 + drm/i915: Restore correct bxt_ddi_phy_calc_lane_lat_optim_mask() calculation +drm-amd drm-amd-fixes 2b702e72e33bbdec0764cfb6e1dd00fe1142ae55 + Merge tag 'drm-misc-fixes-2017-09-28-1' of git://anongit.freedesktop.org/git/drm-misc into drm-fixes +drm drm-next dbb92471674a48892f5e50779425e03388073ab9 + Revert "drm: allow render capable master with DRM_AUTH ioctls" +drm-misc drm-misc-next-fixes c34674a23d1e8674ac532bf3397333f24a41e7b2 + drm/qxl: remove conflicting framebuffers earlier +drm-intel drm-intel-next-fixes ca22f32a6296cbfa29de56328c8505560a18cfa8 + drm/i915: Relax mmap VMA check +drm-amd drm-amd-next-fixes 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e + Linux 4.14-rc1 +drm-misc drm-misc-next dffa9b7a78c4361e55e21b3acb54e0d34ad15ea0 + drm/v3d: Add missing implicit synchronization. +drm-intel drm-intel-next-queued 26ddc068de47e2a7cbbd06c915dca7a0dc22c499 + drm/i915: Setup the RCS ring prior to execution +drm-intel drm-intel-next ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 + drm/i915: Update DRIVER_DATE to 20190417 +drm-amd drm-amd-next 754270c7c56292e97d0eff924a5d5d83f92add07 + Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next +sound-upstream for-linus b26e36b7ef36a8a3a147b1609b2505f8a4ecf511 + ALSA: hda/realtek - add two more pin configuration sets to quirk table +sound-upstream for-next 442e321ed223d9c01a444c6f874e32fb283c17d2 + ALSA: ps3: Remove set but not used variables 'start_vaddr' and 'pcm_index' +drm-intel topic/core-for-CI b573fba52f339dc4fadef7282af4a9413fd6173d + ICL HACK: Disable ACPI idle driver -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: Enable render context support for Ironlake (gen5)
Ironlake does support being able to saving and reloading context specific
registers between contexts, providing isolation of the basic GPU state
(as programmable by userspace). This allows userspace to assume that the
GPU retains their state from one batch to the next, minimising the
amount of state it needs to reload, or manually save and restore.
v2: Fix off-by-one in reading CXT_SIZE, and add a comment that the
CXT_SIZE and context-layout do not match in bspec, but the difference is
irrelevant as we overallocate the full page anyway (Ville).
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Kenneth Graunke
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_engine_cs.c | 16
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index eea9bec04f1b..fc8be2fcb4e6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -211,6 +211,22 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ /*
+* There is a discrepancy here between the size reported
+* by the register and the size of the context layout
+* in the docs. Both are described as authorative!
+*
+* The discrepancy is on the order of a few cachelines,
+* but the total is under one page (4k), which is our
+* minimum allocation anyway so it should all come
+* out in the wash.
+*/
+ cxt_size = I915_READ(CXT_SIZE) + 1;
+ DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+INTEL_GEN(dev_priv),
+cxt_size * 64,
+cxt_size - 1);
+ return round_up(cxt_size * 64, PAGE_SIZE);
case 4:
case 3:
case 2:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8feb2d9b7b60..2d2e33cd3fae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1640,11 +1640,14 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
/* These flags are for resource streamer on HSW+ */
flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
else
+ /* We need to save the extended state for powersaving modes */
flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
len = 4;
if (IS_GEN(i915, 7))
len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
+ else if (IS_GEN(i915, 5))
+ len += 2;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
flags &= ~MI_FORCE_RESTORE;
@@ -1673,6 +1676,14 @@ static inline int mi_set_context(struct i915_request
*rq, u32 flags)
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
+ } else if (IS_GEN(i915, 5)) {
+ /*
+* This w/a is only listed for pre-production ilk a/b steppings,
+* but is also mentioned for programming the powerctx. To be
+* safe, just apply the workaround; we do not use SyncFlush so
+* this should never take effect and so be a no-op!
+*/
+ *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
}
if (force_restore) {
@@ -1726,6 +1737,8 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ } else if (IS_GEN(i915, 5)) {
+ *cs++ = MI_SUSPEND_FLUSH;
}
intel_ring_advance(rq, cs);
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
Despite what I think the prm recommends, commit f2253bd9859b
("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
to be a huge mistake when enabling Ironlake contexts as the GPU would
hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
simple rendercopies with igt, do not suffer).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3844581f622c..8feb2d9b7b60 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1882,12 +1882,12 @@ static int ring_request_alloc(struct i915_request
*request)
*/
request->reserved_space += LEGACY_REQUEST_SIZE;
- ret = switch_context(request);
+ /* Unconditionally invalidate GPU caches and TLBs. */
+ ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
if (ret)
return ret;
- /* Unconditionally invalidate GPU caches and TLBs. */
- ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
+ ret = switch_context(request);
if (ret)
return ret;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimising the amount of state it needs to reload and manually save
across batches.
v2: CONSTANT_BUFFER woes
Running through piglit turned up an interesting issue, a GPU hang inside
the context load. The context image includes the CONSTANT_BUFFER command
that loads an address into a on-gpu buffer, and the context load was
executing that immediately. However, since it was reading from the GTT
there is no guarantee that the GTT retains the same configuration as
when the context was saved, resulting in stray reads and a GPU hang.
Having tried issuing a CONSTANT_BUFFER (to disable the command) from the
ring before saving the context to no avail, we resort to patching out
the instruction inside the context image before loading.
This does impose that gen4 always reissues CONSTANT_BUFFER commands on
each batch, but due to the use of a shared GTT that was and will remain
a requirement.
v3: ECOSPKD to the rescue
Ville found the magic bit in the ECOSPKD to disable saving and restoring
the CONSTANT_BUFFER from the context image, thereby completely avoiding
the GPU hangs from chasing invalid pointers. This appears to be the
default behaviour for gen5, and so we just need to tweak gen4 to match.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..5815703ac35f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2665,6 +2665,9 @@ enum i915_power_well_id {
# define MODE_IDLE (1 << 9)
# define STOP_RING (1 << 8)
+#define ECOSPKD_MMIO(0x21d0)
+# define CONSTANT_BUFFER_SR_DISABLE BIT(4)
+
#define GEN6_GT_MODE _MMIO(0x20d0)
#define GEN7_GT_MODE _MMIO(0x7008)
#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) <<
7))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index fc8be2fcb4e6..f9db2e0bca12 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -211,6 +211,7 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
case 5:
+ case 4:
/*
* There is a discrepancy here between the size reported
* by the register and the size of the context layout
@@ -227,7 +228,6 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
- case 4:
case 3:
case 2:
/* For the special day when i810 gets merged. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2d2e33cd3fae..26b276ed00b3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -832,6 +832,20 @@ static int init_render_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ /*
+* Disable CONSTANT_BUFFER before it is loaded from the context
+* image. For as it is loaded, it is executed and the stored
+* address may no longer be valid, leading to a GPU hang.
+*
+* This imposes the requirement that userspace reload their
+* CONSTANT_BUFFER on every batch, fortunately a requirement
+* they are already accustomed to from before contexts were
+* enabled.
+*/
+ if (IS_GEN(dev_priv, 4))
+ I915_WRITE(ECOSPKD,
+ _MASKED_BIT_ENABLE(CONSTANT_BUFFER_SR_DISABLE));
+
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
if (IS_GEN_RANGE(dev_priv, 4, 6))
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Fri, Apr 19, 2019 at 10:32:30AM +0200, Thomas Gleixner wrote: > On Fri, 19 Apr 2019, Peter Zijlstra wrote: > > On Thu, Apr 18, 2019 at 10:41:47AM +0200, Thomas Gleixner wrote: > > > > > +typedef bool (*stack_trace_consume_fn)(void *cookie, unsigned long addr, > > > + bool reliable); > > > > > +void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, > > > + struct task_struct *task, struct pt_regs *regs); > > > +int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, void > > > *cookie, > > > + struct task_struct *task); > > > > This bugs me a little; ideally the _reliable() thing would not exists. > > > > Thomas said that the existing __save_stack_trace_reliable() is different > > enough for the unification to be non-trivial, but maybe Josh can help > > out? > > > > >From what I can see the biggest significant differences are: > > > > - it looks at the regs sets on the stack and for FP bails early > > - bails for khreads and idle (after it does all the hard work!?!) > > > > The first (FP checking for exceptions) should probably be reflected in > > consume_fn(.reliable) anyway -- although that would mean a lot of extra > > '?' entries where there are none today. > > > > And the second (KTHREAD/IDLE) is something that the generic code can > > easily do before calling into the arch unwinder. > > And looking at the powerpc version of it, that has even more interesting > extra checks in that function. Right, but not fundamentally different from determining @reliable I think. Anyway, it would be good if someone knowledgable could have a look at this. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix MG_DP_MODE() register programming
== Series Details ==
Series: drm/i915/icl: Fix MG_DP_MODE() register programming
URL : https://patchwork.freedesktop.org/series/59744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12840_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12840_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity-after-suspend}:
- shard-glk: TIMEOUT -> FAIL
Known issues
Here are the changes found in Patchwork_12840_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +3
* igt@i915_pm_rpm@gem-execbuf-stress:
- shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807]
* igt@i915_pm_rpm@system-suspend:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#107807]
* igt@kms_busy@basic-flip-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: PASS -> SKIP [fdo#109349]
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-skl: NOTRUN -> FAIL [fdo#103184]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +19
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +117
* igt@kms_lease@atomic_implicit_crtc:
- shard-snb: NOTRUN -> FAIL [fdo#110279]
* igt@kms_lease@setcrtc_implicit_plane:
- shard-snb: NOTRUN -> FAIL [fdo#110281]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +40
* igt@perf_pmu@rc6:
- shard-kbl: PASS -> SKIP [fdo#109271]
Possible fixes
* igt@gem_softpin@noreloc-s3:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +2
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107773]:
Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Fri, 19 Apr 2019, Peter Zijlstra wrote: > On Thu, Apr 18, 2019 at 10:41:47AM +0200, Thomas Gleixner wrote: > > > +typedef bool (*stack_trace_consume_fn)(void *cookie, unsigned long addr, > > + bool reliable); > > > +void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, > > +struct task_struct *task, struct pt_regs *regs); > > +int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, void > > *cookie, > > +struct task_struct *task); > > This bugs me a little; ideally the _reliable() thing would not exists. > > Thomas said that the existing __save_stack_trace_reliable() is different > enough for the unification to be non-trivial, but maybe Josh can help > out? > > >From what I can see the biggest significant differences are: > > - it looks at the regs sets on the stack and for FP bails early > - bails for khreads and idle (after it does all the hard work!?!) > > The first (FP checking for exceptions) should probably be reflected in > consume_fn(.reliable) anyway -- although that would mean a lot of extra > '?' entries where there are none today. > > And the second (KTHREAD/IDLE) is something that the generic code can > easily do before calling into the arch unwinder. And looking at the powerpc version of it, that has even more interesting extra checks in that function. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix MG_DP_MODE() register programming
== Series Details == Series: drm/i915/icl: Fix MG_DP_MODE() register programming URL : https://patchwork.freedesktop.org/series/59744/ State : success == Summary == CI Bug Log - changes from CI_DRM_5954 -> Patchwork_12840 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59744/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12840 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +3 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@gem_exec_basic@readonly-bsd: - fi-icl-u2: INCOMPLETE [fdo#107713] -> PASS * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#103191] -> PASS +1 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (48 -> 43) -- Additional (1): fi-bxt-j4205 Missing(6): fi-ilk-m540 fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_5954 -> Patchwork_12840 CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12840: d26cc79d0b12c09f18764d40b5a496230ad7fc4d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d26cc79d0b12 drm/i915/icl: Fix MG_DP_MODE() register programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12840/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix MG_DP_MODE() register programming
== Series Details ==
Series: drm/i915/icl: Fix MG_DP_MODE() register programming
URL : https://patchwork.freedesktop.org/series/59744/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d26cc79d0b12 drm/i915/icl: Fix MG_DP_MODE() register programming
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters
order")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 37fc7845df7b ("drm/i915: Call
MG_DP_MODE() macro with the right parameters order")'
#12:
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters
order")
total: 1 errors, 1 warnings, 0 checks, 50 lines checked
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Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Thu, Apr 18, 2019 at 10:41:47AM +0200, Thomas Gleixner wrote: > +typedef bool (*stack_trace_consume_fn)(void *cookie, unsigned long addr, > + bool reliable); > +void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, > + struct task_struct *task, struct pt_regs *regs); > +int arch_stack_walk_reliable(stack_trace_consume_fn consume_entry, void > *cookie, > + struct task_struct *task); This bugs me a little; ideally the _reliable() thing would not exists. Thomas said that the existing __save_stack_trace_reliable() is different enough for the unification to be non-trivial, but maybe Josh can help out? From what I can see the biggest significant differences are: - it looks at the regs sets on the stack and for FP bails early - bails for khreads and idle (after it does all the hard work!?!) The first (FP checking for exceptions) should probably be reflected in consume_fn(.reliable) anyway -- although that would mean a lot of extra '?' entries where there are none today. And the second (KTHREAD/IDLE) is something that the generic code can easily do before calling into the arch unwinder. Hmm? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/uc: Place uC firmware in upper range of GGTT
Quoting Fernando Pacheco (2019-04-19 00:31:49) > Currently we pin the GuC or HuC firmware image just > before uploading. Perma-pin during uC initialization > instead and use the range reserved at the top of the > address space. > > Moving the firmware resulted in needing to: > - restore the ggtt mapping during the suspend/resume path. > - use an additional pinning for the rsa signature which will > be used during HuC auth as addresses above GUC_GGTT_TOP > do not map through GTT. > > v2: Remove call to set to gtt domain > Do not restore fw gtt mapping unconditionally > Separate out pin/unpin functions and drop usage of pin/unpin > Use uc_fw init/fini functions to bind/unbind fw object > > Signed-off-by: Fernando Pacheco > --- > drivers/gpu/drm/i915/i915_gem.c | 2 + > drivers/gpu/drm/i915/intel_guc.c| 9 ++- > drivers/gpu/drm/i915/intel_guc_fw.c | 18 +++-- > drivers/gpu/drm/i915/intel_huc.c| 74 + > drivers/gpu/drm/i915/intel_huc.h| 4 + > drivers/gpu/drm/i915/intel_huc_fw.c | 47 --- > drivers/gpu/drm/i915/intel_uc.c | 39 - > drivers/gpu/drm/i915/intel_uc.h | 1 + > drivers/gpu/drm/i915/intel_uc_fw.c | 118 +--- > drivers/gpu/drm/i915/intel_uc_fw.h | 9 ++- > 10 files changed, 247 insertions(+), 74 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index e5462639de0b..0e06a2c7d65f 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4508,6 +4508,8 @@ void i915_gem_resume(struct drm_i915_private *i915) > i915_gem_restore_gtt_mappings(i915); > i915_gem_restore_fences(i915); > > + intel_uc_restore_ggtt_mapping(i915); Nope. They do not need to be restored as the bindings are only required for the xfer. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V2 12/29] dma/debug: Simplify stracktrace retrieval
Please fix up the > 80 char line. Otherwise: Reviewed-by: Christoph Hellwig ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/uc: Reserve upper range of GGTT
Quoting Fernando Pacheco (2019-04-19 00:31:48)
> GuC and HuC depend on struct_mutex for device
> reinitialization. Moving away from this dependency
> requires perma-pinning the firmware images in GGTT.
> The upper portion of the GuC address space has
> a sizeable hole (several MB) that is inaccessible
> by GuC. Reserve this range within GGTT as it can
> comfortably hold GuC/HuC firmware images.
>
> v2: Reserve node rather than insert (Chris)
> Simpler determination of node start/size (Daniele)
> Move reserve/release out to intel_guc.* files
>
> Signed-off-by: Fernando Pacheco
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 25
> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
> drivers/gpu/drm/i915/intel_guc.c| 45 +
> drivers/gpu/drm/i915/intel_guc.h| 2 ++
> 4 files changed, 60 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8f460cc4cc1f..0b4c22e68574 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2752,6 +2752,12 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> if (ret)
> return ret;
>
> + if (USES_GUC(dev_priv)) {
> + ret = intel_guc_reserve_ggtt_top(_priv->guc);
> + if (ret)
> + goto err_reserve;
> + }
> +
> /* Clear any non-preallocated blocks */
> drm_mm_for_each_hole(entry, >vm.mm, hole_start, hole_end) {
> DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
> @@ -2766,12 +2772,14 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> if (ret)
> - goto err;
> + goto err_appgtt;
> }
>
> return 0;
>
> -err:
> +err_appgtt:
> + intel_guc_release_ggtt_top(_priv->guc);
> +err_reserve:
> drm_mm_remove_node(>error_capture);
> return ret;
> }
> @@ -2797,6 +2805,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
> *dev_priv)
> if (drm_mm_node_allocated(>error_capture))
> drm_mm_remove_node(>error_capture);
>
> + intel_guc_release_ggtt_top(_priv->guc);
> +
> if (drm_mm_initialized(>vm.mm)) {
> intel_vgt_deballoon(dev_priv);
> i915_address_space_fini(>vm);
> @@ -3369,17 +3379,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private
> *dev_priv)
> if (ret)
> return ret;
>
> - /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
> -* This is easier than doing range restriction on the fly, as we
> -* currently don't have any bits spare to pass in this upper
> -* restriction!
> -*/
> - if (USES_GUC(dev_priv)) {
> - ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
> - ggtt->mappable_end =
> - min_t(u64, ggtt->mappable_end, ggtt->vm.total);
> - }
> -
> if ((ggtt->vm.total - 1) >> 32) {
> DRM_ERROR("We never expected a Global GTT with more than
> 32bits"
> " of address space! Found %lldM!\n",
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index f597f35b109b..b51e779732c3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -384,6 +384,7 @@ struct i915_ggtt {
> u32 pin_bias;
>
> struct drm_mm_node error_capture;
> + struct drm_mm_node uc_fw;
> };
>
> struct i915_hw_ppgtt {
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index d81a02b0f525..ddd246dc3f14 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -721,3 +721,48 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
> {
> return guc_to_i915(guc)->wopcm.guc.size;
> }
> +
> +static u32 __intel_guc_ggtt_top_offset(struct intel_guc *guc)
> +{
> + struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct i915_ggtt *ggtt = >ggtt;
> + struct intel_huc *huc = >huc;
> + u32 guc_fw_size, huc_fw_size;
> + u32 min_reserved_size;
> +
> + guc_fw_size = round_up(guc->fw.size, I915_GTT_PAGE_SIZE);
> + huc_fw_size = round_up(huc->fw.size, I915_GTT_PAGE_SIZE);
> +
> + min_reserved_size = guc_fw_size + huc_fw_size;
In this patch, you should only be using GUC_GGTT_TOP so that the only
change is from excluding the zone to using a reserved node.
So why reserve room for both fw? You should only be binding them for the
xfer (so that you do not have to insert extraneous code outside of
reset).
-Chris
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[Intel-gfx] [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming
Fix the order of lane, port parameters passed to the register macro.
Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters
order")
Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 24f9106efcc6..f181c26f62fd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct
intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
u32 val;
- int i;
+ int ln;
if (tc_port == PORT_TC_NONE)
return;
- for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
- val = I915_READ(mg_regs[i]);
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_DP_MODE(ln, port));
val |= MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING;
- I915_WRITE(mg_regs[i], val);
+ I915_WRITE(MG_DP_MODE(ln, port), val);
}
val = I915_READ(MG_MISC_SUS0(tc_port));
@@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct
intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
u32 val;
- int i;
+ int ln;
if (tc_port == PORT_TC_NONE)
return;
- for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
- val = I915_READ(mg_regs[i]);
+ for (ln = 0; ln < 2; ln++) {
+ val = I915_READ(MG_DP_MODE(ln, port));
val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING);
- I915_WRITE(mg_regs[i], val);
+ I915_WRITE(MG_DP_MODE(ln, port), val);
}
val = I915_READ(MG_MISC_SUS0(tc_port));
--
2.13.2
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Re: [Intel-gfx] [patch V2 28/29] stacktrace: Provide common infrastructure
On Thu, Apr 18, 2019 at 05:42:55PM +0200, Thomas Gleixner wrote: > On Thu, 18 Apr 2019, Josh Poimboeuf wrote: > > Another idea I had (but never got a chance to work on) was to extend the > > x86 unwind interface to all arches. So instead of the callbacks, each > > arch would implement something like this API: > I surely thought about that, but after staring at all incarnations of > arch/*/stacktrace.c I just gave up. > > Aside of that quite some archs already have callback based unwinders > because they use them for more than stacktracing and just have a single > implementation of that loop. > > I'm fine either way. We can start with x86 and then let archs convert over > their stuff, but I wouldn't hold my breath that this will be completed in > the forseeable future. I suggested the same to Thomas early on, and I even spend the time to convert some $random arch to the iterator interface, and while it is indeed entirely feasible, it is _far_ more work. The callback thing OTOH is flexible enough to do what we want to do now, and allows converting most archs to it without too much pain (as Thomas said, many archs are already in this form and only need minor API adjustments), which gets us in a far better place than we are now. And we can always go to iterators later on. But I think getting the generic unwinder improved across all archs is a really important first step here. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
