[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/selftests: Remove accidental serialization between gpu_fill (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Remove accidental
serialization between gpu_fill (rev2)
URL : https://patchwork.freedesktop.org/series/65888/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14207
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14207/
Known issues
Here are the changes found in Patchwork_14207 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14207/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#106766])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14207/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#109483] / [fdo#109635 ]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14207/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106766]: https://bugs.freedesktop.org/show_bug.cgi?id=106766
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (51 -> 44)
--
Additional (2): fi-hsw-peppy fi-gdg-551
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-tgl-u fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6794 -> Patchwork_14207
CI-20190529: 20190529
CI_DRM_6794: a1a45a21f6fef00f6150dc151c23555aa851bf74 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14207: 069d7928496b33fde1cdb0b9225a59ab557e7d97 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
069d7928496b drm/i915/selftests: Try to recycle context allocations
be18076c005b drm/i915/selftests: Remove accidental serialization between
gpu_fill
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14207/
___
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Re: [Intel-gfx] mmotm 2019-08-24-16-02 uploaded (intel_drv.h header check)
On 8/24/19 4:03 PM, a...@linux-foundation.org wrote: > The mm-of-the-moment snapshot 2019-08-24-16-02 has been uploaded to > >http://www.ozlabs.org/~akpm/mmotm/ > > mmotm-readme.txt says > > README for mm-of-the-moment: > > http://www.ozlabs.org/~akpm/mmotm/ > > This is a snapshot of my -mm patch queue. Uploaded at random hopefully > more than once a week. > > You will need quilt to apply these patches to the latest Linus release (5.x > or 5.x-rcY). The series file is in broken-out.tar.gz and is duplicated in > http://ozlabs.org/~akpm/mmotm/series > > The file broken-out.tar.gz contains two datestamp files: .DATE and > .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, > followed by the base kernel version against which this patch series is to > be applied. > > This tree is partially included in linux-next. To see which patches are > included in linux-next, consult the `series' file. Only the patches > within the #NEXT_PATCHES_START/#NEXT_PATCHES_END markers are included in > linux-next. on x86_64 or i386: CC drivers/gpu/drm/i915/intel_drv.h.s In file included from :0:0: ./../drivers/gpu/drm/i915/intel_drv.h:402:24: error: field ‘force_audio’ has incomplete type enum hdmi_force_audio force_audio; ^~~ ./../drivers/gpu/drm/i915/intel_drv.h:1228:20: error: field ‘tc_type’ has incomplete type enum tc_port_type tc_type; ^~~ -- ~Randy ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [RFC PATCH] iommu/vt-d: Fix IOMMU field not populated on device hot re-plug
Hi Janusz, On 8/27/19 5:35 PM, Janusz Krzysztofik wrote: Hi Lu, On Monday, August 26, 2019 10:29:12 AM CEST Lu Baolu wrote: Hi Janusz, On 8/26/19 4:15 PM, Janusz Krzysztofik wrote: Hi Lu, On Friday, August 23, 2019 3:51:11 AM CEST Lu Baolu wrote: Hi, On 8/22/19 10:29 PM, Janusz Krzysztofik wrote: When a perfectly working i915 device is hot unplugged (via sysfs) and hot re-plugged again, its dev->archdata.iommu field is not populated again with an IOMMU pointer. As a result, the device probe fails on DMA mapping error during scratch page setup. It looks like that happens because devices are not detached from their MMUIO bus before they are removed on device unplug. Then, when an already registered device/IOMMU association is identified by the reinstantiated device's bus and function IDs on IOMMU bus re-attach attempt, the device's archdata is not populated with IOMMU information and the bad happens. I'm not sure if this is a proper fix but it works for me so at least it confirms correctness of my analysis results, I believe. So far I haven't been able to identify a good place where the possibly missing IOMMU bus detach on device unplug operation could be added. Which kernel version are you testing with? Does it contain below commit? commit 458b7c8e0dde12d140e3472b80919cbb9ae793f4 Author: Lu Baolu Date: Thu Aug 1 11:14:58 2019 +0800 I was using an internal branch based on drm-tip which didn't contain this commit yet. Fortunately it has been already merged into drm-tip over last weekend and has effectively fixed the issue. Thanks for testing this. My testing appeared not sufficiently exhaustive. The fix indeed resolved my initially discovered issue of not being able to rebind the i915 driver to a re-plugged device, however it brought another, probably more serious problem to light. When an open i915 device is hot unplugged, IOMMU bus notifier now cleans up IOMMU info for the device on PCI device remove while the i915 driver is still not released, kept by open file descriptors. Then, on last device close, cleanup attempts lead to kernel panic raised from intel_unmap() on unresolved IOMMU domain. We should avoid kernel panic when a intel_unmap() is called against a non-existent domain. But we shouldn't expect the IOMMU driver not cleaning up the domain info when a device remove notification comes and wait until all file descriptors being closed, right? Best regards, Baolu With commit 458b7c8e0dde reverted and my fix applied, both late device close and device re-plug work for me. However, I can realize that's probably still not a complete solution, possibly missing some protection against reuse of a removed device other than for cleanup. If you think that's the right way to go, I can work more on that. I've had a look at other drivers and found AMD is using somehow similar approach. On the other hand, looking at the IOMMU common code I couldn't identify any arrangement that would support deferred device cleanup. If that approach is not acceptable for Intel IOMMU, please suggest a way you'd like to have it resolved and I can try to implement it. Thanks, Janusz Best regards, Lu Baolu
[Intel-gfx] [PATCH 0/3] Add/modify checks within intel_uc_fini_hw
The third patch in the series attempts to downgrade the check for is_guc_running to is_fw_available within intel_uc_fini_hw. We cannot rely on is_guc_running because we will completely skip our attempt to fini uC hw during unload. However, this exposes a new set of problems due to the driver being able to continue after GuC initialization failures: we can now try to disable submission or communication that was never enabled in the first place. The first two patches attempt to resolve those issues by adding (hopefully stronger) checks around submission_disable and communication_disable. Thanks, Fernando Cc: Chris Wilson Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Fernando Pacheco (3): drm/i915/uc: Extract common code from GuC stop/disable comm drm/i915/uc: Disable GuC submission only if currently enabled drm/i915/uc: Fini hw even if GuC is not running .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 + .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 34 +++ 3 files changed, 44 insertions(+), 14 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/uc: Extract common code from GuC stop/disable comm
During normal driver unload we attempt to disable GuC communication
while it is currently stopped. This results in a nop'd call to
intel_guc_ct_disable within guc_disable_communication because
stop/disable rely on the same flag to prevent further comms with CT.
We can avoid the call to disable and still leave communication in a
satisfactory state by extracting a set of shared steps from stop/disable.
This set can include guc_disable_interrupts as we do not require the
single caller of guc_stop_communication to be atomic:
"drm/i915/selftests: Fixup atomic reset checking".
This situation (stop -> disable) only occurs during intel_uc_fini_hw,
so during fini, call guc_disable_communication only if currently enabled.
The symmetric calls to enable/disable remain unmodified for all other
scenarios.
Signed-off-by: Fernando Pacheco
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 30 ---
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 71ee7ab035cc..29a9eec60d2e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -224,17 +224,7 @@ static int guc_enable_communication(struct intel_guc *guc)
return 0;
}
-static void guc_stop_communication(struct intel_guc *guc)
-{
- intel_guc_ct_stop(>ct);
-
- guc->send = intel_guc_send_nop;
- guc->handler = intel_guc_to_host_event_handler_nop;
-
- guc_clear_mmio_msg(guc);
-}
-
-static void guc_disable_communication(struct intel_guc *guc)
+static void __guc_stop_communication(struct intel_guc *guc)
{
/*
* Events generated during or after CT disable are logged by guc in
@@ -247,6 +237,20 @@ static void guc_disable_communication(struct intel_guc
*guc)
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
+}
+
+static void guc_stop_communication(struct intel_guc *guc)
+{
+ intel_guc_ct_stop(>ct);
+
+ __guc_stop_communication(guc);
+
+ DRM_INFO("GuC communication stopped\n");
+}
+
+static void guc_disable_communication(struct intel_guc *guc)
+{
+ __guc_stop_communication(guc);
intel_guc_ct_disable(>ct);
@@ -537,7 +541,9 @@ void intel_uc_fini_hw(struct intel_uc *uc)
if (intel_uc_supports_guc_submission(uc))
intel_guc_submission_disable(guc);
- guc_disable_communication(guc);
+ if (guc_communication_enabled(guc))
+ guc_disable_communication(guc);
+
__uc_sanitize(uc);
}
--
2.23.0
___
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[Intel-gfx] [PATCH 2/3] drm/i915/uc: Disable GuC submission only if currently enabled
It is not enough to check that uc supports GuC submission now
that we can continue to load the driver after GuC initialization
failure (support != enabled). Instead we should explicitly check
that we enabled GuC submission.
Signed-off-by: Fernando Pacheco
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..d4aff9a96c7a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -191,6 +191,16 @@ static bool __doorbell_valid(struct intel_guc *guc, u16
db_id)
return intel_uncore_read(uncore, GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
}
+static bool __doorbell_enabled(struct intel_guc_client *client)
+{
+ struct guc_doorbell_info *doorbell;
+
+ GEM_BUG_ON(!has_doorbell(client));
+
+ doorbell = __get_doorbell(client);
+ return doorbell->db_status == GUC_DOORBELL_ENABLED;
+}
+
static void __init_doorbell(struct intel_guc_client *client)
{
struct guc_doorbell_info *doorbell;
@@ -1112,6 +1122,19 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
}
+bool intel_guc_is_submission_enabled(struct intel_guc *guc)
+{
+ if (!intel_guc_is_submission_supported(guc))
+ return false;
+
+ /*
+* Use the fact that we enable the guc execbuf_client
+* and its doorbell when enabling GuC submission as a proxy
+* for the latter.
+*/
+ return guc->execbuf_client && __doorbell_enabled(guc->execbuf_client);
+}
+
int intel_guc_submission_enable(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
index 54d716828352..80b18a2c885a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
@@ -58,6 +58,7 @@ struct intel_guc_client {
void intel_guc_submission_init_early(struct intel_guc *guc);
int intel_guc_submission_init(struct intel_guc *guc);
+bool intel_guc_is_submission_enabled(struct intel_guc *guc);
int intel_guc_submission_enable(struct intel_guc *guc);
void intel_guc_submission_disable(struct intel_guc *guc);
void intel_guc_submission_fini(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 29a9eec60d2e..b2eb340ce87e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -538,7 +538,7 @@ void intel_uc_fini_hw(struct intel_uc *uc)
if (!intel_guc_is_running(guc))
return;
- if (intel_uc_supports_guc_submission(uc))
+ if (intel_guc_is_submission_enabled(guc))
intel_guc_submission_disable(guc);
if (guc_communication_enabled(guc))
--
2.23.0
___
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[Intel-gfx] [PATCH 3/3] drm/i915/uc: Fini hw even if GuC is not running
We should not be skipping uc_fini_hw on finding GuC
is no longer running. There is plenty of hw and internal
state that can be cleaned up without having to communicate
with GuC.
v2: better to check if fw is available (Michal)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
Signed-off-by: Fernando Pacheco
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b2eb340ce87e..ad5b928fe36a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -535,7 +535,7 @@ void intel_uc_fini_hw(struct intel_uc *uc)
{
struct intel_guc *guc = >guc;
- if (!intel_guc_is_running(guc))
+ if (!intel_uc_fw_is_available(>fw))
return;
if (intel_guc_is_submission_enabled(guc))
--
2.23.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add module parameter to reduce engine instances
== Series Details == Series: Add module parameter to reduce engine instances URL : https://patchwork.freedesktop.org/series/65900/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7377558e7eee drm/i915: WARN rather than BUG with unexpected media engines 43af249229a9 drm/i915: Add ring_mask module parameter -:22: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #22: FILE: drivers/gpu/drm/i915/i915_params.c:182: +i915_param_named_unsafe(ring_mask, uint, 0400, + "Mask of engine rings to enable. (default: all supported engines enabled)"); total: 0 errors, 0 warnings, 1 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Add module parameter to reduce engine instances
Add a new module parameter, ring_mask, to allow users to disable certain engines for a platform. By default this mask is set to all engines enabled. Bits in the mask are aligned with the intel_engine_id enums. As a prerequisite to the patch which adds the module parameter, change the BUG_ON to a WARN_ON in the event a VDbox or VEbox engine for a platform does not match the total number of engines of these catagories supported in the corresponding fuses. Stuart Summers (2): drm/i915: WARN rather than BUG with unexpected media engines drm/i915: Add ring_mask module parameter drivers/gpu/drm/i915/i915_params.c | 3 +++ drivers/gpu/drm/i915/i915_params.h | 3 ++- drivers/gpu/drm/i915/intel_device_info.c | 10 -- 3 files changed, 13 insertions(+), 3 deletions(-) -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: WARN rather than BUG with unexpected media engines
Instead of preventing driver load when media engines enabled
for a platform do not match the fuse values for those media
engines, WARN_ON to indicate the observation but continue
with driver load.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..caef01b1da23 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1023,7 +1023,7 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
}
DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
vdbox_mask, VDBOX_MASK(dev_priv));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
+ GEM_WARN_ON(vdbox_mask != VDBOX_MASK(dev_priv));
for (i = 0; i < I915_MAX_VECS; i++) {
if (!HAS_ENGINE(dev_priv, _VECS(i)))
@@ -1036,5 +1036,5 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
}
DRM_DEBUG_DRIVER("vebox enable: %04x, instances: %04lx\n",
vebox_mask, VEBOX_MASK(dev_priv));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
+ GEM_WARN_ON(vebox_mask != VEBOX_MASK(dev_priv));
}
--
2.22.0
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Add ring_mask module parameter
Add a new module parameter, ring_mask, to allow for disabling
engines during i915 load. This mask follows the intel_engine_id
enum and can be used to hide specified engines from i915 and
from userspace.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_params.c | 3 +++
drivers/gpu/drm/i915/i915_params.h | 3 ++-
drivers/gpu/drm/i915/intel_device_info.c | 6 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..6a17fe6ea3a2 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -178,6 +178,9 @@ i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host
support(default:false)");
#endif
+i915_param_named_unsafe(ring_mask, uint, 0400,
+ "Mask of engine rings to enable. (default: all supported engines
enabled)");
+
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..d803bf5faac4 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -77,7 +77,8 @@ struct drm_printer;
param(bool, verbose_state_checks, true) \
param(bool, nuclear_pageflip, false) \
param(bool, enable_dp_mst, true) \
- param(bool, enable_gvt, false)
+ param(bool, enable_gvt, false) \
+ param(unsigned int, ring_mask, (unsigned int)-1)
#define MEMBER(T, member, ...) T member;
struct i915_params {
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index caef01b1da23..f833280f2ef6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -993,10 +993,16 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
u32 media_fuse;
u16 vdbox_mask;
u16 vebox_mask;
+ u32 orig_engine_mask = info->engine_mask;
if (INTEL_GEN(dev_priv) < 11)
return;
+ info->engine_mask &= i915_modparams.ring_mask;
+ if (info->engine_mask != orig_engine_mask)
+ DRM_WARN("loading with reduced engine mask 0x%x\n",
+info->engine_mask);
+
media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
--
2.22.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Transcoder Port Sync preparation refactoring/renaming
This series renames some functions to match the drm function definitions and also refactors some functions out of intel_atomic_commit_tail() as a prep for adding newer hooks required for transcoder port sync enable series The renaming is done as suggested by Daniel Vetter. There is no functional change Manasi Navare (2): drm/i915/display: Rename update_crtcs() to commit_modeset_enables() drm/i915/display: Move the commit_tail() disable sequence to commit_modeset_disables() hook drivers/gpu/drm/i915/display/intel_display.c | 104 --- drivers/gpu/drm/i915/i915_drv.h | 3 +- 2 files changed, 67 insertions(+), 40 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/display: Move the commit_tail() disable sequence to commit_modeset_disables() hook
Create a new hook commit_modeset_disables() consistent with the naming
in drm atomic helpers and similar to the commit_modeset_enables() hook.
This helps better organize the disable sequence in atomic_commit_tail()
and move that to this disable hook.
No functional change
v3:
* Rebase (Manasi)
v2:
* Create a helper for old_crtc_state disables (Lucas)
Suggested-by: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 94 +---
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 61 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 23c8c7f5c47a..7f0ab0101569 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13758,6 +13758,61 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
+static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
+ struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state
*new_crtc_state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ intel_crtc_disable_planes(state, crtc);
+
+ /*
+* We need to disable pipe CRC before disabling the pipe,
+* or we race against vblank off.
+*/
+ intel_crtc_disable_pipe_crc(crtc);
+
+ dev_priv->display.crtc_disable(old_crtc_state, state);
+ crtc->active = false;
+ intel_fbc_disable(crtc);
+ intel_disable_shared_dpll(old_crtc_state);
+
+ /*
+* Underruns don't always raise interrupts,
+* so check manually.
+*/
+ intel_check_cpu_fifo_underruns(dev_priv);
+ intel_check_pch_fifo_underruns(dev_priv);
+
+ /* FIXME unify this for all platforms */
+ if (!new_crtc_state->base.active &&
+ !HAS_GMCH(dev_priv) &&
+ dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state,
+new_crtc_state);
+}
+
+static void intel_commit_modeset_disables(struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ if (!needs_modeset(new_crtc_state))
+ continue;
+
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
+}
+
static void intel_commit_modeset_enables(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
@@ -13938,42 +13993,10 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
put_domains[crtc->pipe] =
modeset_get_crtc_power_domains(new_crtc_state);
}
-
- if (!needs_modeset(new_crtc_state))
- continue;
-
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
-
- if (old_crtc_state->base.active) {
- intel_crtc_disable_planes(state, crtc);
-
- /*
-* We need to disable pipe CRC before disabling the
pipe,
-* or we race against vblank off.
-*/
- intel_crtc_disable_pipe_crc(crtc);
-
- dev_priv->display.crtc_disable(old_crtc_state, state);
- crtc->active = false;
- intel_fbc_disable(crtc);
- intel_disable_shared_dpll(old_crtc_state);
-
- /*
-* Underruns don't always raise
-* interrupts, so check manually.
-*/
- intel_check_cpu_fifo_underruns(dev_priv);
- intel_check_pch_fifo_underruns(dev_priv);
-
- /* FIXME unify this for all platforms */
- if (!new_crtc_state->base.active &&
- !HAS_GMCH(dev_priv) &&
- dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
-
new_crtc_state);
-
[Intel-gfx] [PATCH 1/2] drm/i915/display: Rename update_crtcs() to commit_modeset_enables()
This patch has no functional changes. This just renames the update_crtcs()
hooks to commit_modeset_enables() to match the drm_atomic helper naming
conventions.
v2:
* Rebase on drm-tip
Suggested-by: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9d8313850416..23c8c7f5c47a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13758,7 +13758,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
-static void intel_update_crtcs(struct intel_atomic_state *state)
+static void intel_commit_modeset_enables(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
@@ -13773,7 +13773,7 @@ static void intel_update_crtcs(struct
intel_atomic_state *state)
}
}
-static void skl_update_crtcs(struct intel_atomic_state *state)
+static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -14014,7 +14014,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_encoders_update_prepare(state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.update_crtcs(state);
+ dev_priv->display.commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -15926,9 +15926,9 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
}
if (INTEL_GEN(dev_priv) >= 9)
- dev_priv->display.update_crtcs = skl_update_crtcs;
+ dev_priv->display.commit_modeset_enables =
skl_commit_modeset_enables;
else
- dev_priv->display.update_crtcs = intel_update_crtcs;
+ dev_priv->display.commit_modeset_enables =
intel_commit_modeset_enables;
}
static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b42651a387d9..75a42e8df67e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -288,7 +288,7 @@ struct drm_i915_display_funcs {
struct intel_atomic_state *old_state);
void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *old_state);
- void (*update_crtcs)(struct intel_atomic_state *state);
+ void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state);
--
2.19.1
___
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Re: [Intel-gfx] [PATCH v10 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp
>
> On 2019-08-27 at 20:03:21 +0530, Winkler, Tomas wrote:
> > > On gen12+ platforms, HDCP HW is associated to the transcoder.
> > > Hence on every modeset update associated transcoder into the
> > > intel_hdcp of the port.
> > >
> > > v2:
> > > s/trans/cpu_transcoder [Jani]
> > > v3:
> > > comment is added for fw_ddi init for gen12+ [Shashank]
> > > only hdcp capable transcoder is translated into fw_tc [Shashank]
> > >
> > > Signed-off-by: Ramalingam C
> > > Acked-by: Jani Nikula
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 7 +++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 47 ++-
> > > drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
> > > 5 files changed, 62 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 96514dcc7812..61277a87dbe7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -388,6 +388,13 @@ struct intel_hdcp {
> > > wait_queue_head_t cp_irq_queue;
> > > atomic_t cp_irq_count;
> > > int cp_irq_count_cached;
> > > +
> > > + /*
> > > + * HDCP register access for gen12+ need the transcoder associated.
> > > + * Transcoder attached to the connector could be changed at
> modeset.
> > > + * Hence caching the transcoder here.
> > > + */
> > > + enum transcoder cpu_transcoder;
> > > };
> > >
> > > struct intel_connector {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 23908da1cd5d..e8471689f785 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2248,6 +2248,9 @@ intel_dp_compute_config(struct intel_encoder
> > > *encoder,
> > >
> > > intel_psr_compute_config(intel_dp, pipe_config);
> > >
> > > + intel_hdcp_transcoder_config(intel_connector,
> > > + pipe_config->cpu_transcoder);
> > > +
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index 534832f435dc..3591b8f7fe30 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -1762,13 +1762,58 @@ enum mei_fw_ddi
> > > intel_get_mei_fw_ddi_index(enum port port)
> > > }
> > > }
> > >
> > > +static inline
> > > +enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> {
> > > + switch (cpu_transcoder) {
> > > + case TRANSCODER_A ... TRANSCODER_D:
> > > + return (enum mei_fw_tc)(cpu_transcoder | 0x10);
> > > + default: /* eDP, DSI TRANSCODERS are non HDCP capable */
> > > + return MEI_INVALID_TRANSCODER;
> > > + }
> > > +}
> > > +
> > > +void intel_hdcp_transcoder_config(struct intel_connector *connector,
> > > + enum transcoder cpu_transcoder) {
> > > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > + struct intel_hdcp *hdcp = >hdcp;
> > > +
> > > + if (!hdcp->shim)
> > > + return;
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 12) {
> > > + mutex_lock(>mutex);
> > > + hdcp->cpu_transcoder = cpu_transcoder;
> > > + hdcp->port_data.fw_tc =
> > > intel_get_mei_fw_tc(cpu_transcoder);
> > > + mutex_unlock(>mutex);
> > > + }
> > > +}
> > > +
> > > static inline int initialize_hdcp_port_data(struct intel_connector
> *connector,
> > > const struct intel_hdcp_shim
> *shim) {
> > > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > struct intel_hdcp *hdcp = >hdcp;
> > > struct hdcp_port_data *data = >port_data;
> > > + struct intel_crtc *crtc;
> > > +
> > > + if (INTEL_GEN(dev_priv) < 12) {
> > > + data->fw_ddi =
> > > + intel_get_mei_fw_ddi_index(connector->encoder-
> > > >port);
> > > + } else {
> > > + crtc = to_intel_crtc(connector->base.state->crtc);
> > > + if (crtc) {
> > > + hdcp->cpu_transcoder = crtc->config-
> >cpu_transcoder;
> > > + data->fw_tc = intel_get_mei_fw_tc(hdcp-
> > > >cpu_transcoder);
> > > + }
> > What is the 'else' action here, looks like there is no default value for
> > fw_tc?
> else block stands of gen12+ platforms.
I mean when if (crctc) is false
And with respect to fw_tc
> initialization, we are configuring it at every modeset through
> intel_hdcp_transcoder_config(), as transcoder might change at modeset.
> And in hdcp_init initializing is possible only if crtc is associated with
> connector already.
So this is a bug if crtc is not NULL here? Should we set issue an error
message?
>
> And it will be initilaized when mei_hdcp
[Intel-gfx] ✓ Fi.CI.BAT: success for DSB enablement. (rev3)
== Series Details == Series: DSB enablement. (rev3) URL : https://patchwork.freedesktop.org/series/63013/ State : success == Summary == CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14206 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/ Known issues Here are the changes found in Patchwork_14206 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_requests: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([fdo#102657]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-byt-j1900/igt@i915_selftest@live_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/fi-byt-j1900/igt@i915_selftest@live_requests.html Possible fixes * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][3] ([fdo#109483] / [fdo#109635 ]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Warnings * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#109483]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html - fi-kbl-7500u: [FAIL][7] ([fdo#111407]) -> [FAIL][8] ([fdo#111096]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (51 -> 43) -- Additional (2): fi-hsw-peppy fi-gdg-551 Missing(10): fi-kbl-soraka fi-ilk-m540 fi-tgl-u fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6794 -> Patchwork_14206 CI-20190529: 20190529 CI_DRM_6794: a1a45a21f6fef00f6150dc151c23555aa851bf74 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14206: 3f02cf4823cdf5cf42a742179b460719c83960b6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3f02cf4823cd drm/i915/dsb: Enable DSB for gen12. e72f429fc2b0 drm/i915/dsb: Enable gamma lut programming using DSB. 93b7b00afa8d drm/i915/dsb: Documentation for DSB. ce14930553ee drm/i915/dsb: function to trigger workload execution of DSB. 4072b9dacf94 drm/i915/dsb: functions to enable/disable DSB engine. 593376017970 drm/i915/dsb: Check DSB engine status. c22d5381cd39 drm/i915/dsb: Register definition of DSB registers. 3eb1547fb3a4 drm/i915/dsb: Indexed register write function for DSB. c0e83ac07f1b drm/i915/dsb: single register write function for DSB. 3b8233fa3574 drm/i915/dsb: DSB context creation. da32d51f5b17 drm/i915/dsb: feature flag added for display state buffer. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14206/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: use a separate context for gpu relocs (rev2)
== Series Details ==
Series: drm/i915: use a separate context for gpu relocs (rev2)
URL : https://patchwork.freedesktop.org/series/65729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14205
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14205/
Known issues
Here are the changes found in Patchwork_14205 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][1] ([fdo#109483] / [fdo#109635 ]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14205/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
Participating hosts (51 -> 40)
--
Additional (2): fi-hsw-peppy fi-gdg-551
Missing(13): fi-kbl-soraka fi-icl-u4 fi-tgl-u fi-ilk-m540 fi-cml-s
fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-apl-guc fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6794 -> Patchwork_14205
CI-20190529: 20190529
CI_DRM_6794: a1a45a21f6fef00f6150dc151c23555aa851bf74 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14205: a94e55233bae8acf7bdcdf844e35b9e82e403c92 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a94e55233bae drm/i915: use a separate context for gpu relocs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14205/
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: use a separate context for gpu relocs
Quoting Daniele Ceraolo Spurio (2019-08-27 19:58:05) > The CS pre-parser can pre-fetch commands across memory sync points and > starting from gen12 it is able to pre-fetch across BB_START and BB_END > boundaries as well, so when we emit gpu relocs the pre-parser might > fetch the target location of the reloc before the memory write lands. > > The parser can't pre-fetch across the ctx switch, so we use a separate > context to guarantee that the memory is synchronized before the parser > can get to it. > > Note that there is no risk of the CS doing a lite restore from the reloc > context to the user context, even if the two have the same hw_id, > because since gen11 the CS also checks the LRCA when deciding if it can > lite-restore. > > v2: limit new context to gen12+, release in eb_destroy, add a comment > in emit_fini_breadcrumb (Chris). > > Suggested-by: Chris Wilson > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris Wilson Looks solid and the big explanatory reminders are very welcome. (I will shift it to gen11_fini_breadcrumbs I think, so it's closer to the gen12 divide.) Subtle changes in behaviour are easily forgotten. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSB enablement. (rev3)
== Series Details == Series: DSB enablement. (rev3) URL : https://patchwork.freedesktop.org/series/63013/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/dsb: feature flag added for display state buffer. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev3)
== Series Details == Series: DSB enablement. (rev3) URL : https://patchwork.freedesktop.org/series/63013/ State : warning == Summary == $ dim checkpatch origin/drm-tip da32d51f5b17 drm/i915/dsb: feature flag added for display state buffer. 3b8233fa3574 drm/i915/dsb: DSB context creation. -:49: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #49: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 137 lines checked c0e83ac07f1b drm/i915/dsb: single register write function for DSB. 3eb1547fb3a4 drm/i915/dsb: Indexed register write function for DSB. c22d5381cd39 drm/i915/dsb: Register definition of DSB registers. 593376017970 drm/i915/dsb: Check DSB engine status. 4072b9dacf94 drm/i915/dsb: functions to enable/disable DSB engine. ce14930553ee drm/i915/dsb: function to trigger workload execution of DSB. 93b7b00afa8d drm/i915/dsb: Documentation for DSB. e72f429fc2b0 drm/i915/dsb: Enable gamma lut programming using DSB. 3f02cf4823cd drm/i915/dsb: Enable DSB for gen12. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 11/11] drm/i915/dsb: Enable DSB for gen12.
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1974e4c78a43..613210385fb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info
intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
--
2.22.0
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[Intel-gfx] [PATCH v3 01/11] drm/i915/dsb: feature flag added for display state buffer.
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b42651a387d9..d32cfdb78b74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1856,6 +1856,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 92e0c2e0954c..e206f298f48e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.22.0
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[Intel-gfx] [PATCH v3 00/11] DSB enablement.
Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. v3: As per review comments from Chris and Jani, - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) - Simplified and optimized code few places. (Chris) - Called dsb-api directly in callsites instead going via I915_WRITE. (Jani) Cc: Ville Syrjälä Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Daniel Vetter Cc: Imre Deak Cc: Michel Thierry Cc: Uma Shankar Cc: Shashank Sharma Cc: Swati Sharma Cc: Lucas De Marchi Signed-off-by: Animesh Manna Animesh Manna (11): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Register definition of DSB registers. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Documentation for DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. Documentation/gpu/i915.rst| 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c| 64 ++-- .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 326 ++ drivers/gpu/drm/i915/display/intel_dsb.h | 49 +++ drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 15 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 452 insertions(+), 24 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 08/11] drm/i915/dsb: function to trigger workload execution of DSB.
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2d6e78868f2d..bc1734072f34 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -214,3 +214,45 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
DSB_OPCODE_SHIFT) | DSB_BYTE_EN |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_DEBUG_KMS("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(>cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_DEBUG_KMS("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index c848747f52d9..f5d1f1bedc12 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -44,5 +44,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
--
2.22.0
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[Intel-gfx] [PATCH v3 04/11] drm/i915/dsb: Indexed register write function for DSB.
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
v1: Initial version.
v2: simplified code by using ALIGN(). (Chris)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 48
drivers/gpu/drm/i915/display/intel_dsb.h | 8
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index df288446caeb..520f2bbcc8ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -22,6 +22,7 @@
#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_OPCODE_POLL0xA
#define DSB_BYTE_EN(0xf << 20)
+#define DSB_REG_VALUE_MASK 0xf
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -96,6 +97,53 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow.\n");
+ return;
+ }
+
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ /* Update the size. */
+ dsb->ins_start_offset = dsb->free_pos;
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = dsb->crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 1b33ab118640..c848747f52d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -30,11 +30,19 @@ struct intel_dsb {
* and help in calculating cmd_buf_tail.
*/
int free_pos;
+
+ /*
+* ins_start_offset will help to store start address
+* of the dsb instuction of auto-increment register.
+*/
+ u32 ins_start_offset;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val);
#endif
--
2.22.0
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[Intel-gfx] [PATCH v3 10/11] drm/i915/dsb: Enable gamma lut programming using DSB.
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 64 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +
2 files changed, 43 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 71a0201437a9..e4090d8e4547 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -589,34 +589,38 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
const struct drm_color_lut *lut = blob->data;
int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
+ struct intel_dsb *dsb = dev_priv->dsb;
- I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
- PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe),
+ prec_index | PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < hw_lut_size; i++) {
/* We discard half the user entries in split gamma mode */
const struct drm_color_lut *entry =
[i * (lut_size - 1) / (hw_lut_size - 1)];
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
+ ilk_lut_10(entry));
}
/*
* Reset the index, otherwise it prevents the legacy palette to be
* written properly.
*/
- I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+ intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), 0);
}
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = dev_priv->dsb;
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,9 +628,12 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
}
@@ -788,12 +795,13 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = dev_priv->dsb;
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
}
static void
@@ -803,6 +811,7 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
+ struct intel_dsb *dsb = dev_priv->dsb;
enum pipe pipe = crtc->pipe;
u32 i;
@@ -813,15 +822,16 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* Superfine segment has 9 entries, corresponding to values
* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
*/
- I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb,
[Intel-gfx] [PATCH v3 03/11] drm/i915/dsb: single register write function for DSB.
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 36
drivers/gpu/drm/i915/display/intel_dsb.h | 9 ++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index a2845df90573..df288446caeb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,20 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_NOOP0x0
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_WAIT_FOR_US 0x2
+#define DSB_OPCODE_WAIT_FOR_LINES 0x3
+#define DSB_OPCODE_WAIT_FOR_VBLANK 0x4
+#define DSB_OPCODE_WAIT_FOR_SL_IN 0x5
+#define DSB_OPCODE_WAIT_FOR_SL_OUT 0x6
+#define DSB_OPCODE_GENERATE_INT0x7
+#define DSB_OPCODE_INDEXED_WRITE 0x9
+#define DSB_OPCODE_POLL0xA
+#define DSB_BYTE_EN(0xf << 20)
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -81,3 +95,25 @@ void intel_dsb_put(struct intel_dsb *dsb)
mutex_unlock(>drm.struct_mutex);
}
}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow.\n");
+ return;
+ }
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE <<
+ DSB_OPCODE_SHIFT) | DSB_BYTE_EN |
+ i915_mmio_reg_offset(reg);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 4a4091cadc1e..1b33ab118640 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -22,10 +24,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating cmd_buf_tail.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.22.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/11] drm/i915/dsb: functions to enable/disable DSB engine.
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index d36ee8244427..2d6e78868f2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -33,6 +33,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ return true;
+}
+
+static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
--
2.22.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 06/11] drm/i915/dsb: Check DSB engine status.
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 520f2bbcc8ae..d36ee8244427 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -24,6 +24,15 @@
#define DSB_BYTE_EN(0xf << 20)
#define DSB_REG_VALUE_MASK 0xf
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
--
2.22.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 09/11] drm/i915/dsb: Documentation for DSB.
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
drivers/gpu/drm/i915/display/intel_dsb.c | 68
2 files changed, 77 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 3415255ad3dc..38e31223a24c 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bc1734072f34..501ff7f5db8c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,23 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_NOOP0x0
@@ -73,6 +90,17 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate dsb context and return a dsb instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function will give handle of the DSB instance which
+ * user want to operate on.
+ *
+ * Return : address of Intel_dsb instance requested for.
+ * In failure case, the dsb instance will not have any command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -124,6 +152,14 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to destroy the dsb-context by doing unpin
+ * and release the vma object.
+ */
+
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc;
@@ -146,6 +182,19 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+/**
+ * intel_dsb_indexed_reg_write() -Write to the dsb context for auto
+ * increment register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for auto-increment register and intel_dsb_reg_write()
+ * is used for normal register. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
+
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
@@ -193,6 +242,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the dsb context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = dsb->crtc;
@@ -215,6 +276,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = dsb->crtc;
--
2.22.0
___
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[Intel-gfx] [PATCH v3 02/11] drm/i915/dsb: DSB context creation.
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
v1: initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 83 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 119 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 96514dcc7812..0ab3516b0044 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1026,6 +1026,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb[MAX_DSB_PER_PIPE];
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index ..a2845df90573
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "../i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ struct intel_dsb *dsb;
+ intel_wakeref_t wakeref;
+ int i;
+
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++)
+ if (!crtc->dsb[i].cmd_buf)
+ break;
+
+ WARN_ON(i >= MAX_DSB_PER_PIPE);
+
+ dsb = >dsb[i];
+ dsb->id = i;
+ dsb->crtc = crtc;
+ if (!HAS_DSB(i915))
+ return dsb;
+
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj))
+ goto err;
+
+ mutex_lock(>drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(>drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_KMS("Vma creation failed.\n");
+ i915_gem_object_put(obj);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_DEBUG_KMS("Command buffer creation failed.\n");
+ dsb->cmd_buf = NULL;
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc;
+ struct drm_i915_private *i915;
+ struct i915_vma *vma;
+
+ if (!dsb)
+ return;
+
+ crtc = dsb->crtc;
+ i915 = to_i915(crtc->base.dev);
+
+ if (dsb->cmd_buf) {
+ vma = dsb->vma;
+ mutex_lock(>drm.struct_mutex);
+ i915_gem_object_unpin_map(vma->obj);
+ i915_vma_unpin_and_release(, 0);
+ dsb->cmd_buf = NULL;
+ mutex_unlock(>drm.struct_mutex);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
new file mode 100644
index ..4a4091cadc1e
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+ INVALID_DSB = -1,
+ DSB1,
+ DSB2,
+ DSB3,
+ MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+ struct intel_crtc *crtc;
+ enum dsb_id id;
+ u32 *cmd_buf;
+ struct i915_vma *vma;
+};
+
+struct intel_dsb *
[Intel-gfx] [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers.
Added key register definitions of DSB.
dsb-ctrl register is required to enable dsb-engine.
head-ptr register hold the head of buffer address from where the
execution will start.
Programming tail-ptr register is a trigger point to start execution.
Cc: Uma Shankar
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..71c6c2380443 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11564,4 +11564,19 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
+#define DSB_BUFFER_REITERATE (1 << 29)
+#define DSB_WAIT_FOR_VBLANK (1 << 28)
+#define DSB_WAIT_FOR_LINE_IN_RANGE (1 << 27)
+#define DSB_HALT (1 << 16)
+#define DSB_NON_POSTED_ENABLE(1 << 8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.22.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: use a separate context for gpu relocs
The CS pre-parser can pre-fetch commands across memory sync points and
starting from gen12 it is able to pre-fetch across BB_START and BB_END
boundaries as well, so when we emit gpu relocs the pre-parser might
fetch the target location of the reloc before the memory write lands.
The parser can't pre-fetch across the ctx switch, so we use a separate
context to guarantee that the memory is synchronized before the parser
can get to it.
Note that there is no risk of the CS doing a lite restore from the reloc
context to the user context, even if the two have the same hw_id,
because since gen11 the CS also checks the LRCA when deciding if it can
lite-restore.
v2: limit new context to gen12+, release in eb_destroy, add a comment
in emit_fini_breadcrumb (Chris).
Suggested-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 30 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b5f6937369ea..427210e301ae 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -252,6 +252,7 @@ struct i915_execbuffer {
bool has_fence : 1;
bool needs_unfenced : 1;
+ struct intel_context *ce;
struct i915_request *rq;
u32 *rq_cmd;
unsigned int rq_size;
@@ -880,6 +881,9 @@ static void eb_destroy(const struct i915_execbuffer *eb)
{
GEM_BUG_ON(eb->reloc_cache.rq);
+ if (eb->reloc_cache.ce)
+ intel_context_put(eb->reloc_cache.ce);
+
if (eb->lut_size > 0)
kfree(eb->buckets);
}
@@ -903,6 +907,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
cache->node.allocated = false;
+ cache->ce = NULL;
cache->rq = NULL;
cache->rq_size = 0;
}
@@ -1168,7 +1173,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
if (err)
goto err_unmap;
- rq = i915_request_create(eb->context);
+ rq = intel_context_create_request(cache->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_unpin;
@@ -1239,6 +1244,29 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb,
if (!intel_engine_can_store_dword(eb->engine))
return ERR_PTR(-ENODEV);
+ if (!cache->ce) {
+ struct intel_context *ce;
+
+ /*
+* The CS pre-parser can pre-fetch commands across
+* memory sync points and starting gen12 it is able to
+* pre-fetch across BB_START and BB_END boundaries
+* (within the same context). We therefore use a
+* separate context gen12+ to guarantee that the reloc
+* writes land before the parser gets to the target
+* memory location.
+*/
+ if (cache->gen >= 12)
+ ce =
intel_context_create(eb->context->gem_context,
+ eb->engine);
+ else
+ ce = intel_context_get(eb->context);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ cache->ce = ce;
+ }
+
err = __reloc_gpu_alloc(eb, vma, len);
if (unlikely(err))
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d42584439f51..12ec2830ba27 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2903,6 +2903,24 @@ gen8_emit_fini_breadcrumb_footer(struct i915_request
*request,
return gen8_emit_wa_tail(request, cs);
}
+/*
+ * Note that the CS instruction pre-parser will not stall on the breadcrumb
+ * flush and will continue pre-fetching the instructions after it before the
+ * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at
+ * BB_START/END instructions, so, even though we might pre-fetch the pre-amble
+ * of the next request before the memory has been flushed, we're guaranteed
that
+ * we won't access the batch itself too early.
+ * However, on gen12+ the parser can pre-fetch across the BB_START/END
commands,
+ * so, if the current request is modifying an instruction in the next request
on
+ * the same intel_context, we might pre-fetch and then execute the pre-update
+ * instruction. To avoid this, the
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
== Series Details == Series: drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors URL : https://patchwork.freedesktop.org/series/65845/ State : success == Summary == CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14195_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/ Known issues Here are the changes found in Patchwork_14195_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-contexts-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb5/igt@gem_exec_sched...@preempt-contexts-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd.html * igt@kms_busy@basic-flip-b: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#111317]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-apl8/igt@kms_b...@basic-flip-b.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-apl4/igt@kms_b...@basic-flip-b.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-kbl: [PASS][5] -> [FAIL][6] ([fdo#103232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#104873]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-modeset-vs-hang: - shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-apl6/igt@kms_f...@flip-vs-modeset-vs-hang.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-apl6/igt@kms_f...@flip-vs-modeset-vs-hang.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-hsw4/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html * igt@prime_busy@after-bsd2: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb2/igt@prime_b...@after-bsd2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-iclb3/igt@prime_b...@after-bsd2.html Possible fixes * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][21] ([fdo#109661]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-snb2/igt@gem_...@unwedge-stress.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb1/igt@gem_exec_sched...@preempt-bsd.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Remove accidental serialization between gpu_fill
== Series Details == Series: drm/i915/selftests: Remove accidental serialization between gpu_fill URL : https://patchwork.freedesktop.org/series/65886/ State : success == Summary == CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14203 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14203/ Known issues Here are the changes found in Patchwork_14203 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2] ([fdo#108744]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14203/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][3] ([fdo#109483] / [fdo#109635 ]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14203/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Warnings * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#111096]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6794/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14203/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (51 -> 44) -- Additional (1): fi-hsw-peppy Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6794 -> Patchwork_14203 CI-20190529: 20190529 CI_DRM_6794: a1a45a21f6fef00f6150dc151c23555aa851bf74 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14203: 179797309d1c2a7cf87dee81864b47d398156e0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 179797309d1c drm/i915/selftests: Remove accidental serialization between gpu_fill == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14203/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port
On Tue, 2019-08-27 at 09:36 -0700, Lucas De Marchi wrote:
> On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
> > > -Original Message-
> > > From: Imre Deak
> > > Sent: Monday, 26 August, 2019 6:42 AM
> > > To: Souza, Jose ; De Marchi, Lucas
> > > ; Runyan, Arthur J <
> > > arthur.j.run...@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> > >
> > > Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable
> > > PSR in any
> > > eDP port
> > >
> > > On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
> > > > From: José Roberto de Souza
> > > >
> > > > From BDW+ the PSR registers moved from DDIA to transcoder, so
> > > > any port
> > > > with a eDP panel connected can have PSR, so lets remove this
> > > > limitation.
> > > >
> > > > Cc: Dhinakaran Pandiyan
> > > > Cc: Rodrigo Vivi
> > > > Signed-off-by: José Roberto de Souza
> > > > Signed-off-by: Lucas De Marchi
> > > > Reviewed-by: Anshuman Gupta
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
> > > > 1 file changed, 2 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 81e3619cd905..0172b82858d9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct
> > > > intel_dp
> > > *intel_dp,
> > > > /*
> > > > * HSW spec explicitly says PSR is tied to port A.
> > > > -* BDW+ platforms have a instance of PSR registers per
> > > > transcoder but
> > > > -* for now it only supports one instance of PSR, so
> > > > lets keep it
> > > > -* hardcoded to PORT_A
> > > > +* BDW+ platforms have a instance of PSR registers per
> > > > transcoder.
> > > > */
> > > > - if (dig_port->base.port != PORT_A) {
> > > > + if (IS_HASWELL(dev_priv) && dig_port->base.port !=
> > > > PORT_A) {
> > >
> > > Based on an earlier discussion with Art, before TGL PSR is not
> > > supposed
> > > to be used anywhere else than port A.
> > >
> > > Art could you confirm that?
> >
> > Correct.
> > PSR1 is limited to DDIA until Tigerlake. There are registers for
> > PSR on the other
> > transcoders/ports because of reuse, but hardware isn't fully hooked
> > up or validated.
> > PSR2 is still limited to DDIA on Tigerlake.
>
> thank you both for confirming. José, I think we need to drop this
> patch
> and rebase the rest so we don't do anything before Tiger Lake. I will
> work on it.
Thanks, maybe write a patch updating the comment above would be nice.
Otherwise I can do it latter.
>
> Lucas De Marchi
>
> > > > DRM_DEBUG_KMS("PSR condition failed: Port not
> > > supported\n");
> > > > return;
> > > > }
> > > > --
> > > > 2.23.0
> > > >
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
On Tue, Aug 27, 2019 at 01:34:15PM +0300, Jani Nikula wrote: > On Tue, 27 Aug 2019, "Nautiyal, Ankit K" wrote: > > From: Ankit Nautiyal > > > > Currently, the transcoder port sync feature is not available, due to > > which the 5K-tiled dual DP monitors experience corruption when > > 2560x2880 mode is applied for both of the tiled DP connectors. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97244 > > > > There is a patch series to enable transcode port sync feature for > > tiled display for ICL+, which is under review: > > https://patchwork.kernel.org/project/intel-gfx/list/?series=137339 > > > > For the older platforms, we need to remove the 2560x2880 mode to avoid > > a possibility of userspace choosing 2560x2880 mode for both tiled > > displays, resulting in corruption. > > > > This patch prunes 2560x2880 mode for one of the tiled DP connector. > > Since both the tiled DP connectors have different tile_h_loc and > > tile_v_loc, the tiled connector with tile_h_loc and tile_v_loc as '0', > > is chosen, for which the given resolution is removed. > > > > Signed-off-by: Ankit Nautiyal > > CC: Manasi Navare > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 11 +++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 5c45a3b..aa43a3b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -564,6 +564,17 @@ intel_dp_mode_valid(struct drm_connector *connector, > > if (mode->flags & DRM_MODE_FLAG_DBLCLK) > > return MODE_H_ILLEGAL; > > > > + /* > > +* For 5K tiled dual DP monitors, dual-DP sync is not yet supported. > > +* This results in display sync issues, when both tiled connectors run > > +* on 2560x2880 resolution. Therefore prune the 2560x2880 mode on one > > +* of the tiled connector, to avoid such a case. > > +*/ > > + if (connector->has_tile && > > + (connector->tile_h_loc == 0 && connector->tile_v_loc == 0) && > > + (mode->hdisplay == 2560 && mode->vdisplay == 2880)) > > + return MODE_PANEL; > > + > > This assumes all tiled cases with specific resolutions fail. You don't > know that. You only know this fails on a specific display. Instead of > coming up with various rules on tiles and resolutions that match the > display (but might *also* match any number of *other* displays!), you > need to actually identify and match that specific display instead. > Actually without the transcoder port sync feature, we do not expect any tiled display over two separate ports to work correctly, so if it is two connectors in state with tile props set then we should reject the tiled mode on both those connectors since that might cause the artifacts without proper sync between two ports which is supported only on ICL+ > There are two ways to add display specific quirks: based on EDID > (edid_quirk_list in drm_edid.c) and based on DPCD (dpcd_quirk_list in > drm_dp_helper.c). You identify the display, and then prune the modes > that require port sync to work, for *that* display. We have seen this issue on multiple 5K tiled displays IMH, so just adding a quirk for specific monitors will not suffice. But we would need to make sure that the mode gets rejected only if there are multiple SST connectors with tile prop or connector->has_tile set because MST tiled displays still work correctly. Ville, you had played a little bit with this 5K display I believe, do you think pruning the tiled mode if there are tiled SST connectors and platform < ICL is a good solution? Regards Manasi > > Blanket filters like this are a no-go. > > BR, > Jani. > > > > return MODE_OK; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use
On Mon, Aug 26, 2019 at 08:28:33PM +0300, Imre Deak wrote:
On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
This also already prepares for future when more than one PSR instance
will be allowed.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 140 +--
drivers/gpu/drm/i915/i915_reg.h | 13 +--
2 files changed, 59 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 28b62e587204..81e3619cd905 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
+static void psr_irq_control(struct drm_i915_private *dev_priv)
{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
+ enum transcoder trans = dev_priv->psr.transcoder;
This is called from intel_psr_debug_set() where psr.transcoder may be
uninited.
+ u32 val, mask;
-static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
-{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
+ mask = EDP_PSR_ERROR(trans);
+ if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+ mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
- if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
-
- I915_WRITE(EDP_PSR_IMR, ~mask);
+ /*
+* TODO: when handling multiple PSR instances a global spinlock will be
+* needed to synchronize the value of shared register
+*/
+ val = I915_READ(EDP_PSR_IMR);
+ val &= ~EDP_PSR_TRANS_MASK(trans);
+ val |= ~mask;
+ I915_WRITE(EDP_PSR_IMR, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
+ enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
ktime_t time_ns = ktime_get();
- u32 mask = 0;
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
+ if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ u32 val;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
I think we should still catch all interrupts, log the unexpected ones
and react only on the expected one in intel_psr_work().
could you expand more on this? there is only one PSR instance hence only
one possible transcoder coming from dev_priv->psr.transcoder. Looping here just
to
warn seems wasteful.
- int shift = edp_psr_shift(cpu_transcoder);
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+transcoder_name(cpu_transcoder));
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
-transcoder_name(cpu_transcoder));
+ dev_priv->psr.irq_aux_error = true;
- dev_priv->psr.irq_aux_error = true;
+ /*
+* If this interruption is not masked it will keep
+* interrupting so fast that it prevents the scheduled
+* work to run.
+* Also after a PSR error, we don't want to arm PSR
+* again so we don't care about unmask the interruption
+
Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port
On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
-Original Message-
From: Imre Deak
Sent: Monday, 26 August, 2019 6:42 AM
To: Souza, Jose ; De Marchi, Lucas
; Runyan, Arthur J
Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any
eDP port
On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> From BDW+ the PSR registers moved from DDIA to transcoder, so any port
> with a eDP panel connected can have PSR, so lets remove this
> limitation.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
> index 81e3619cd905..0172b82858d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp
*intel_dp,
>
>/*
> * HSW spec explicitly says PSR is tied to port A.
> - * BDW+ platforms have a instance of PSR registers per transcoder but
> - * for now it only supports one instance of PSR, so lets keep it
> - * hardcoded to PORT_A
> + * BDW+ platforms have a instance of PSR registers per transcoder.
> */
> - if (dig_port->base.port != PORT_A) {
> + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
Based on an earlier discussion with Art, before TGL PSR is not supposed
to be used anywhere else than port A.
Art could you confirm that?
Correct.
PSR1 is limited to DDIA until Tigerlake. There are registers for PSR on the
other
transcoders/ports because of reuse, but hardware isn't fully hooked up or
validated.
PSR2 is still limited to DDIA on Tigerlake.
thank you both for confirming. José, I think we need to drop this patch
and rebase the rest so we don't do anything before Tiger Lake. I will
work on it.
Lucas De Marchi
>DRM_DEBUG_KMS("PSR condition failed: Port not
supported\n");
>return;
>}
> --
> 2.23.0
>
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Re: [Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
On 8/27/2019 6:50 PM, Imre Deak wrote:
On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
On 8/13/2019 8:16 PM, Imre Deak wrote:
On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 69 ++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e2ef202aeeef..c9e92d48cdab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
-static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+ udelay(200);
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
Should be called dc3co_off power well.
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ if (!dev_priv->psr.sink_psr2_support)
+ return;
We could end up enabling DC3CO while PSR2 is disabled after disabling
a PSR2 capable output, which is against the spec.
I'm thinking now that we should have a single dc_off power well and a
new interface setting the max allowed DC state (DC3CO, DC5/6).
Hi Imre,
Could you please comment if below part of new API code set_max_dc_state() is
ok? with respect to our DC3CO design sync.
static void set_target_dc_state(struct drm_i915_private *dev_priv)
{
gen9_dc_off_power_well_disable(dev_priv, NULL);
}
void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
{
bool dc_off_enabled;
struct i915_power_domains *power_domains = _priv->power_domains;
/* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
TGL_DISP_DC_OFF);
dc_off_enabled can get stale this way until you acquire the lock.
Probably easier to lookup_power_well() and then check its state with the
lock held.
mutex_lock(_domains->lock);
if (dc_off_enabled) {
dev_priv->csr.max_dc_state = state;
} else {
dev_priv->csr.max_dc_state = state;
set_target_dc_state(dev_priv);
}
mutex_unlock(_domains->lock);
}
gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
register accordingly.
There can be only issue according to me here when "DC off" power well
is disable (this will happen when we want to set max_dc_state to dc5
in dc5_idle_thread). In that case we need to manually call
set_target_dc_state()->gen9_dc_off_power_well_disable().
In that case you could just call power_well->enable(), ->disable(), and
in the ->disable() hook you'd enable the DC state accorindg to
csr.max_dc_state?
Thanks for suggestion, will incorporate suggesting approach.
Thanks,
Anshuman
Thanks,
Anshuman Gupta.
(Right now I think there is also a missing re-enabling of DC3CO when
disabling DC5/6).
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+
[Intel-gfx] [CI 1/2] drm/i915/selftests: Remove accidental serialization between gpu_fill
Upon object creation for live_gem_contexts, we fill the object with
known scratch and flush it out of the CPU cache. Before performing the
GPU fill, we don't need to flush it again and so avoid serialising with
previous fills.
However, we do need some throttling on the internal interfaces if we do
not want to run out of memory!
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../drm/i915/gem/selftests/i915_gem_context.c | 83 ---
1 file changed, 72 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 37a177e37665..63116c4fa8ba 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -180,12 +180,6 @@ static int gpu_fill(struct intel_context *ce,
if (IS_ERR(vma))
return PTR_ERR(vma);
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err)
- return err;
-
err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
if (err)
return err;
@@ -343,6 +337,45 @@ static unsigned long max_dwords(struct drm_i915_gem_object
*obj)
return npages / DW_PER_PAGE;
}
+static void throttle_release(struct i915_request **q, int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++) {
+ if (IS_ERR_OR_NULL(q[i]))
+ continue;
+
+ i915_request_put(fetch_and_zero([i]));
+ }
+}
+
+static int throttle(struct intel_context *ce,
+ struct i915_request **q, int count)
+{
+ int i;
+
+ if (!IS_ERR_OR_NULL(q[0])) {
+ if (i915_request_wait(q[0],
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT) < 0)
+ return -EINTR;
+
+ i915_request_put(q[0]);
+ }
+
+ for (i = 0; i < count - 1; i++)
+ q[i] = q[i + 1];
+
+ q[i] = intel_context_create_request(ce);
+ if (IS_ERR(q[i]))
+ return PTR_ERR(q[i]);
+
+ i915_request_get(q[i]);
+ i915_request_add(q[i]);
+
+ return 0;
+}
+
static int igt_ctx_exec(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -362,6 +395,7 @@ static int igt_ctx_exec(void *arg)
for_each_engine(engine, i915, id) {
struct drm_i915_gem_object *obj = NULL;
unsigned long ncontexts, ndwords, dw;
+ struct i915_request *tq[5] = {};
struct igt_live_test t;
struct drm_file *file;
IGT_TIMEOUT(end_time);
@@ -409,13 +443,18 @@ static int igt_ctx_exec(void *arg)
}
err = gpu_fill(ce, obj, dw);
- intel_context_put(ce);
-
if (err) {
pr_err("Failed to fill dword %lu [%lu/%lu] with
gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
ndwords, dw, max_dwords(obj),
engine->name, ctx->hw_id,
yesno(!!ctx->vm), err);
+ intel_context_put(ce);
+ goto out_unlock;
+ }
+
+ err = throttle(ce, tq, ARRAY_SIZE(tq));
+ if (err) {
+ intel_context_put(ce);
goto out_unlock;
}
@@ -426,6 +465,8 @@ static int igt_ctx_exec(void *arg)
ndwords++;
ncontexts++;
+
+ intel_context_put(ce);
}
pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
@@ -444,6 +485,7 @@ static int igt_ctx_exec(void *arg)
}
out_unlock:
+ throttle_release(tq, ARRAY_SIZE(tq));
if (igt_live_test_end())
err = -EIO;
mutex_unlock(>drm.struct_mutex);
@@ -461,6 +503,7 @@ static int igt_ctx_exec(void *arg)
static int igt_shared_ctx_exec(void *arg)
{
struct drm_i915_private *i915 = arg;
+ struct i915_request *tq[5] = {};
struct i915_gem_context *parent;
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -535,14 +578,20 @@ static int igt_shared_ctx_exec(void *arg)
}
err = gpu_fill(ce, obj, dw);
- intel_context_put(ce);
- kernel_context_close(ctx);
-
if (err) {
pr_err("Failed to fill dword %lu [%lu/%lu] with
gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
ndwords, dw,
[Intel-gfx] [CI 2/2] drm/i915/selftests: Try to recycle context allocations
igt_ctx_exec allocates a new context for each iteration, keeping them
all allocated until the end. Instead, release the local ctx reference at
the end of each iteration, allowing ourselves to reap those if under
mempressure.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 63116c4fa8ba..da54a718c712 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -424,7 +424,7 @@ static int igt_ctx_exec(void *arg)
struct i915_gem_context *ctx;
struct intel_context *ce;
- ctx = live_context(i915, file);
+ ctx = kernel_context(i915);
if (IS_ERR(ctx)) {
err = PTR_ERR(ctx);
goto out_unlock;
@@ -438,6 +438,7 @@ static int igt_ctx_exec(void *arg)
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
intel_context_put(ce);
+ kernel_context_close(ctx);
goto out_unlock;
}
}
@@ -449,12 +450,14 @@ static int igt_ctx_exec(void *arg)
engine->name, ctx->hw_id,
yesno(!!ctx->vm), err);
intel_context_put(ce);
+ kernel_context_close(ctx);
goto out_unlock;
}
err = throttle(ce, tq, ARRAY_SIZE(tq));
if (err) {
intel_context_put(ce);
+ kernel_context_close(ctx);
goto out_unlock;
}
@@ -467,6 +470,7 @@ static int igt_ctx_exec(void *arg)
ncontexts++;
intel_context_put(ce);
+ kernel_context_close(ctx);
}
pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
--
2.23.0
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[Intel-gfx] [PATCH i-g-t] benchmarks: Use labs() for abs(long)
e.g. benchmarks/gem_wsim.c:2936:4: warning: absolute value function ‘abs’ given an argument of type ‘long int’ but has parameter of type ‘int’ which may cause truncation of value [-Wabsolute-value] Signed-off-by: Chris Wilson --- benchmarks/gem_syslatency.c | 2 +- benchmarks/gem_wsim.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c index 7671dc43e..d7cf0ed49 100644 --- a/benchmarks/gem_syslatency.c +++ b/benchmarks/gem_syslatency.c @@ -343,7 +343,7 @@ static unsigned long calibrate_nop(unsigned int target_us, sz = loops * sz / elapsed(_start, _end) * 1e3 * target_us; sz = ALIGN(sz, sizeof(uint32_t)); } while (elapsed(_0, _end) < 5 || -abs(sz - prev) > (sz * tolerance_pct / 100)); +labs(sz - prev) > (sz * tolerance_pct / 100)); close(fd); diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index a76fdbfe2..b8e22b3f6 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -2933,7 +2933,7 @@ static unsigned long calibrate_nop(unsigned int tolerance_pct) size = loops * size / elapsed(_start, _end) / 1e6 * usecs; size = ALIGN(size, sizeof(uint32_t)); } while (elapsed(_0, _end) < 5 || -abs(size - last_size) > (size * tolerance_pct / 100)); +labs(size - last_size) > (size * tolerance_pct / 100)); return size / sizeof(uint32_t); } -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/28] drm/i915/selftests: Try to recycle context allocations
On Mon, 26 Aug 2019 at 08:23, Chris Wilson wrote: > > igt_ctx_exec allocates a new context for each iteration, keeping them > all allocated until the end. Instead, release the local ctx reference at > the end of each iteration, allowing ourselves to reap those if under > mempressure. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/selftests: Remove accidental serialization between gpu_fill
Upon object creation for live_gem_contexts, we fill the object with
known scratch and flush it out of the CPU cache. Before performing the
GPU fill, we don't need to flush it again and so avoid serialising with
previous fills.
However, we do need some throttling on the internal interfaces if we do
not want to run out of memory!
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../drm/i915/gem/selftests/i915_gem_context.c | 83 ---
1 file changed, 72 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 37a177e37665..63116c4fa8ba 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -180,12 +180,6 @@ static int gpu_fill(struct intel_context *ce,
if (IS_ERR(vma))
return PTR_ERR(vma);
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_gtt_domain(obj, true);
- i915_gem_object_unlock(obj);
- if (err)
- return err;
-
err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
if (err)
return err;
@@ -343,6 +337,45 @@ static unsigned long max_dwords(struct drm_i915_gem_object
*obj)
return npages / DW_PER_PAGE;
}
+static void throttle_release(struct i915_request **q, int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++) {
+ if (IS_ERR_OR_NULL(q[i]))
+ continue;
+
+ i915_request_put(fetch_and_zero([i]));
+ }
+}
+
+static int throttle(struct intel_context *ce,
+ struct i915_request **q, int count)
+{
+ int i;
+
+ if (!IS_ERR_OR_NULL(q[0])) {
+ if (i915_request_wait(q[0],
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT) < 0)
+ return -EINTR;
+
+ i915_request_put(q[0]);
+ }
+
+ for (i = 0; i < count - 1; i++)
+ q[i] = q[i + 1];
+
+ q[i] = intel_context_create_request(ce);
+ if (IS_ERR(q[i]))
+ return PTR_ERR(q[i]);
+
+ i915_request_get(q[i]);
+ i915_request_add(q[i]);
+
+ return 0;
+}
+
static int igt_ctx_exec(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -362,6 +395,7 @@ static int igt_ctx_exec(void *arg)
for_each_engine(engine, i915, id) {
struct drm_i915_gem_object *obj = NULL;
unsigned long ncontexts, ndwords, dw;
+ struct i915_request *tq[5] = {};
struct igt_live_test t;
struct drm_file *file;
IGT_TIMEOUT(end_time);
@@ -409,13 +443,18 @@ static int igt_ctx_exec(void *arg)
}
err = gpu_fill(ce, obj, dw);
- intel_context_put(ce);
-
if (err) {
pr_err("Failed to fill dword %lu [%lu/%lu] with
gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
ndwords, dw, max_dwords(obj),
engine->name, ctx->hw_id,
yesno(!!ctx->vm), err);
+ intel_context_put(ce);
+ goto out_unlock;
+ }
+
+ err = throttle(ce, tq, ARRAY_SIZE(tq));
+ if (err) {
+ intel_context_put(ce);
goto out_unlock;
}
@@ -426,6 +465,8 @@ static int igt_ctx_exec(void *arg)
ndwords++;
ncontexts++;
+
+ intel_context_put(ce);
}
pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
@@ -444,6 +485,7 @@ static int igt_ctx_exec(void *arg)
}
out_unlock:
+ throttle_release(tq, ARRAY_SIZE(tq));
if (igt_live_test_end())
err = -EIO;
mutex_unlock(>drm.struct_mutex);
@@ -461,6 +503,7 @@ static int igt_ctx_exec(void *arg)
static int igt_shared_ctx_exec(void *arg)
{
struct drm_i915_private *i915 = arg;
+ struct i915_request *tq[5] = {};
struct i915_gem_context *parent;
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -535,14 +578,20 @@ static int igt_shared_ctx_exec(void *arg)
}
err = gpu_fill(ce, obj, dw);
- intel_context_put(ce);
- kernel_context_close(ctx);
-
if (err) {
pr_err("Failed to fill dword %lu [%lu/%lu] with
gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
ndwords, dw,
Re: [Intel-gfx] [PATCH 02/28] drm/i915/selftests: Remove accidental serialization between gpu_fill
On Mon, 26 Aug 2019 at 08:24, Chris Wilson wrote: > > Upon object creation for live_gem_contexts, we fill the object with > known scratch and flush it out of the CPU cache. Before performing the > GPU fill, we don't need to flush it again and so avoid serialising with > previous fills. > > However, we do need some throttling on the internal interfaces if we do > not want to run out of memory! > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make engine batch pool's safe for use with virtual engines
On 27/08/2019 14:59, Chris Wilson wrote: A virtual engine itself does not have a batch pool, but we can gleefully use any of its siblings instead. Signed-off-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Only activate i915_active debugobject once
Quoting Matthew Auld (2019-08-27 16:30:40) > On 27/08/2019 14:26, Chris Wilson wrote: > > The point of debug_object_activate is to mark we first, only the first, > > acquisition. > -eparse It was meant to be "the first, and only the first," -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Only activate i915_active debugobject once
On 27/08/2019 14:26, Chris Wilson wrote: The point of debug_object_activate is to mark we first, only the first, acquisition. -eparse The object then remains active until the last release. However, we marked up all successful first acquires even though we allowed concurrent parties to try and acquire the i915_active simultaneously (serialised by the i915_active.mutex). Testcase: igt/gem_mmap_gtt/fault-concurrent Signed-off-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_big: Sync against asynchronous relocations
If we are writing the relocations using the GPU they will not be written
into the batch immediately. Instead there will be a write-fence while
the relocation is being performed, giving us something to conveniently
wait upon.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_big.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_exec_big.c b/tests/i915/gem_exec_big.c
index 9da90ead6..c06ee9959 100644
--- a/tests/i915/gem_exec_big.c
+++ b/tests/i915/gem_exec_big.c
@@ -95,6 +95,7 @@ static void exec1(int fd, uint32_t handle, uint64_t
reloc_ofs, unsigned flags, c
gem_execbuf(fd, );
igt_warn_on(gem_reloc[0].presumed_offset == -1);
+ gem_set_domain(fd, gem_exec[0].handle, I915_GEM_DOMAIN_WC, 0);
if (use_64bit_relocs) {
uint64_t tmp;
@@ -102,14 +103,14 @@ static void exec1(int fd, uint32_t handle, uint64_t
reloc_ofs, unsigned flags, c
tmp = *(uint64_t *)(ptr+reloc_ofs);
else
gem_read(fd, handle, reloc_ofs, , sizeof(tmp));
- igt_assert_eq(tmp, gem_reloc[0].presumed_offset);
+ igt_assert_eq_u64(tmp, gem_reloc[0].presumed_offset);
} else {
uint32_t tmp;
if (ptr)
tmp = *(uint32_t *)(ptr+reloc_ofs);
else
gem_read(fd, handle, reloc_ofs, , sizeof(tmp));
- igt_assert_eq(tmp, gem_reloc[0].presumed_offset);
+ igt_assert_eq_u32(tmp, gem_reloc[0].presumed_offset);
}
}
@@ -173,6 +174,7 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
if (igt_warn_on(gem_reloc[n].presumed_offset == -1))
break;
}
+ gem_set_domain(fd, gem_exec[0].handle, I915_GEM_DOMAIN_WC, 0);
if (use_64bit_relocs) {
for (n = 0; n < nreloc; n++) {
@@ -181,7 +183,7 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
tmp = *(uint64_t *)(ptr+reloc_ofs(n, nreloc));
else
gem_read(fd, handle, reloc_ofs(n, nreloc),
, sizeof(tmp));
- igt_assert_eq(tmp, gem_reloc[n].presumed_offset);
+ igt_assert_eq_u64(tmp, gem_reloc[n].presumed_offset);
}
} else {
for (n = 0; n < nreloc; n++) {
@@ -190,7 +192,7 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
tmp = *(uint32_t *)(ptr+reloc_ofs(n, nreloc));
else
gem_read(fd, handle, reloc_ofs(n, nreloc),
, sizeof(tmp));
- igt_assert_eq(tmp, gem_reloc[n].presumed_offset);
+ igt_assert_eq_u32(tmp, gem_reloc[n].presumed_offset);
}
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make engine batch pool's safe for use with virtual engines
== Series Details == Series: drm/i915: Make engine batch pool's safe for use with virtual engines URL : https://patchwork.freedesktop.org/series/65875/ State : success == Summary == CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14202 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14202/ Known issues Here are the changes found in Patchwork_14202 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14202/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html Possible fixes * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][3] ([fdo#08]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14202/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][5] ([fdo#103167]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14202/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 Participating hosts (52 -> 44) -- Additional (1): fi-tgl-u Missing(9): fi-kbl-soraka fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6792 -> Patchwork_14202 CI-20190529: 20190529 CI_DRM_6792: 87f7792bc3891de3fab4fb64d66a85a66729e3d4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14202: f55390ca10c5121730dae71319a6a0ed0b86 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f55390ca10c5 drm/i915: Make engine batch pool's safe for use with virtual engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14202/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp
On 2019-08-27 at 20:03:21 +0530, Winkler, Tomas wrote:
> > On gen12+ platforms, HDCP HW is associated to the transcoder.
> > Hence on every modeset update associated transcoder into the intel_hdcp of
> > the port.
> >
> > v2:
> > s/trans/cpu_transcoder [Jani]
> > v3:
> > comment is added for fw_ddi init for gen12+ [Shashank]
> > only hdcp capable transcoder is translated into fw_tc [Shashank]
> >
> > Signed-off-by: Ramalingam C
> > Acked-by: Jani Nikula
> > ---
> > .../drm/i915/display/intel_display_types.h| 7 +++
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 47 ++-
> > drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
> > 5 files changed, 62 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 96514dcc7812..61277a87dbe7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -388,6 +388,13 @@ struct intel_hdcp {
> > wait_queue_head_t cp_irq_queue;
> > atomic_t cp_irq_count;
> > int cp_irq_count_cached;
> > +
> > + /*
> > +* HDCP register access for gen12+ need the transcoder associated.
> > +* Transcoder attached to the connector could be changed at modeset.
> > +* Hence caching the transcoder here.
> > +*/
> > + enum transcoder cpu_transcoder;
> > };
> >
> > struct intel_connector {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 23908da1cd5d..e8471689f785 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2248,6 +2248,9 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >
> > intel_psr_compute_config(intel_dp, pipe_config);
> >
> > + intel_hdcp_transcoder_config(intel_connector,
> > +pipe_config->cpu_transcoder);
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 534832f435dc..3591b8f7fe30 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1762,13 +1762,58 @@ enum mei_fw_ddi
> > intel_get_mei_fw_ddi_index(enum port port)
> > }
> > }
> >
> > +static inline
> > +enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder) {
> > + switch (cpu_transcoder) {
> > + case TRANSCODER_A ... TRANSCODER_D:
> > + return (enum mei_fw_tc)(cpu_transcoder | 0x10);
> > + default: /* eDP, DSI TRANSCODERS are non HDCP capable */
> > + return MEI_INVALID_TRANSCODER;
> > + }
> > +}
> > +
> > +void intel_hdcp_transcoder_config(struct intel_connector *connector,
> > + enum transcoder cpu_transcoder)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > + struct intel_hdcp *hdcp = >hdcp;
> > +
> > + if (!hdcp->shim)
> > + return;
> > +
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + mutex_lock(>mutex);
> > + hdcp->cpu_transcoder = cpu_transcoder;
> > + hdcp->port_data.fw_tc =
> > intel_get_mei_fw_tc(cpu_transcoder);
> > + mutex_unlock(>mutex);
> > + }
> > +}
> > +
> > static inline int initialize_hdcp_port_data(struct intel_connector
> > *connector,
> > const struct intel_hdcp_shim *shim)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = >hdcp;
> > struct hdcp_port_data *data = >port_data;
> > + struct intel_crtc *crtc;
> > +
> > + if (INTEL_GEN(dev_priv) < 12) {
> > + data->fw_ddi =
> > + intel_get_mei_fw_ddi_index(connector->encoder-
> > >port);
> > + } else {
> > + crtc = to_intel_crtc(connector->base.state->crtc);
> > + if (crtc) {
> > + hdcp->cpu_transcoder = crtc->config->cpu_transcoder;
> > + data->fw_tc = intel_get_mei_fw_tc(hdcp-
> > >cpu_transcoder);
> > + }
> What is the 'else' action here, looks like there is no default value for
> fw_tc?
else block stands of gen12+ platforms. And with respect to fw_tc
initialization, we are configuring it at every modeset through
intel_hdcp_transcoder_config(), as transcoder might change at modeset.
And in hdcp_init initializing is possible only if crtc is associated
with connector already.
And it will be initilaized when mei_hdcp apis are called, as modeset
is essential to invoke HDCP.
PORT is statically associated with connector, hence we are initializing
here forever.
-Ram
>
> > + /*
> > +* As per ME FW API expectation, for GEN 12+, fw_ddi is filled
> > +
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
On Tue, Aug 27, 2019 at 03:35:14PM +0100, Chris Wilson wrote: > Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51) > > We want to support this on Gen11 as well, where these registers > > are context saved and restored and we prime the register values of new > > contexts > > from recorded defaults. What could be the correct way to handle this, write > > to the > > default object or should ask GPU to re-record after modifying the > > registers. > > That depends on whether you want to apply to existing or only to new. > For OA / sseu, we modify the context images so that existing contexts > are updated to reflect the new defaults, and we update the defaults. > E.g. gen8_configure_all_contexts() Applying to the existing contexts as well should be the right thing to do. Thank you! I will look at the example. Prathap > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 4/6] misc/mei/hdcp: Fill transcoder index in port info
On 2019-08-27 at 20:07:04 +0530, Winkler, Tomas wrote:
>
> >
> > On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > > > For gen12+ platform we need to pass the transcoder info as part of
> > > > the port info into ME FW.
> > > >
> > > > This change fills the payload for ME FW from hdcp_port_data.
> > > >
> > > > Signed-off-by: Ramalingam C
> > > > Acked-by: Jani Nikula
> > > > Reviewed-by: Shashank Sharma
> > > > ---
> > > > drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
> > > > drivers/misc/mei/hdcp/mei_hdcp.h | 4 +++-
> > > > 2 files changed, 14 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> > > > b/drivers/misc/mei/hdcp/mei_hdcp.c
> > > > index 3638c77eba26..93027fd96c71 100644
> > > > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> > > > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> > > > @@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev,
> > > > struct hdcp_port_data *data,
> > > >
> > > > session_init_in.port.integrated_port_type = data->port_type;
> > > > session_init_in.port.physical_port = (u8)data->fw_ddi;
> > > > + session_init_in.port.attached_transcoder = (u8)data->fw_tc;
> > > > session_init_in.protocol = data->protocol;
> > > >
> > > > byte = mei_cldev_send(cldev, (u8 *)_init_in, @@ -127,6
> > > > +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device
> > > > +*dev,
> > > >
> > > > verify_rxcert_in.port.integrated_port_type = data->port_type;
> > > > verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
> > > > + verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> > > > memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
> > > > @@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev,
> > > > struct hdcp_port_data *data,
> > > >
> > > > send_hprime_in.port.integrated_port_type = data->port_type;
> > > > send_hprime_in.port.physical_port = (u8)data->fw_ddi;
> > > > + send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> > > >HDCP_2_2_H_PRIME_LEN);
> > > > @@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev,
> > > > struct hdcp_port_data *data,
> > > >
> > > > pairing_info_in.port.integrated_port_type = data->port_type;
> > > > pairing_info_in.port.physical_port = (u8)data->fw_ddi;
> > > > + pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> > > >HDCP_2_2_E_KH_KM_LEN);
> > > > @@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device
> > > > *dev,
> > > >
> > > > lc_init_in.port.integrated_port_type = data->port_type;
> > > > lc_init_in.port.physical_port = (u8)data->fw_ddi;
> > > > + lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > byte = mei_cldev_send(cldev, (u8 *)_init_in,
> > > > sizeof(lc_init_in));
> > > > if (byte < 0) {
> > > > @@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev,
> > > > struct hdcp_port_data *data,
> > > >
> > > > verify_lprime_in.port.integrated_port_type = data->port_type;
> > > > verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
> > > > + verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> > > >HDCP_2_2_L_PRIME_LEN);
> > > > @@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct
> > > > device *dev,
> > > >
> > > > get_skey_in.port.integrated_port_type = data->port_type;
> > > > get_skey_in.port.physical_port = (u8)data->fw_ddi;
> > > > + get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > byte = mei_cldev_send(cldev, (u8 *)_skey_in,
> > > > sizeof(get_skey_in));
> > > > if (byte < 0) {
> > > > @@ -488,6 +495,7 @@
> > mei_hdcp_repeater_check_flow_prepare_ack(struct
> > > > device *dev,
> > > >
> > > > verify_repeater_in.port.integrated_port_type = data->port_type;
> > > > verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
> > > > + verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> > > >HDCP_2_2_RXINFO_LEN);
> > > > @@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device
> > > > *dev,
> > > >
> > > > verify_mprime_in.port.integrated_port_type = data->port_type;
> > > > verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
> > > > + verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > > >
> > > > memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> > > >HDCP_2_2_MPRIME_LEN);
> > >
Re: [Intel-gfx] [PATCH v10 4/6] misc/mei/hdcp: Fill transcoder index in port info
>
> On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > > For gen12+ platform we need to pass the transcoder info as part of
> > > the port info into ME FW.
> > >
> > > This change fills the payload for ME FW from hdcp_port_data.
> > >
> > > Signed-off-by: Ramalingam C
> > > Acked-by: Jani Nikula
> > > Reviewed-by: Shashank Sharma
> > > ---
> > > drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
> > > drivers/misc/mei/hdcp/mei_hdcp.h | 4 +++-
> > > 2 files changed, 14 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> > > b/drivers/misc/mei/hdcp/mei_hdcp.c
> > > index 3638c77eba26..93027fd96c71 100644
> > > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> > > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> > > @@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev,
> > > struct hdcp_port_data *data,
> > >
> > > session_init_in.port.integrated_port_type = data->port_type;
> > > session_init_in.port.physical_port = (u8)data->fw_ddi;
> > > + session_init_in.port.attached_transcoder = (u8)data->fw_tc;
> > > session_init_in.protocol = data->protocol;
> > >
> > > byte = mei_cldev_send(cldev, (u8 *)_init_in, @@ -127,6
> > > +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device
> > > +*dev,
> > >
> > > verify_rxcert_in.port.integrated_port_type = data->port_type;
> > > verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
> > > + verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> > > memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
> > > @@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev,
> > > struct hdcp_port_data *data,
> > >
> > > send_hprime_in.port.integrated_port_type = data->port_type;
> > > send_hprime_in.port.physical_port = (u8)data->fw_ddi;
> > > + send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> > > HDCP_2_2_H_PRIME_LEN);
> > > @@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev,
> > > struct hdcp_port_data *data,
> > >
> > > pairing_info_in.port.integrated_port_type = data->port_type;
> > > pairing_info_in.port.physical_port = (u8)data->fw_ddi;
> > > + pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> > > HDCP_2_2_E_KH_KM_LEN);
> > > @@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device
> > > *dev,
> > >
> > > lc_init_in.port.integrated_port_type = data->port_type;
> > > lc_init_in.port.physical_port = (u8)data->fw_ddi;
> > > + lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
> > > if (byte < 0) {
> > > @@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev,
> > > struct hdcp_port_data *data,
> > >
> > > verify_lprime_in.port.integrated_port_type = data->port_type;
> > > verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
> > > + verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> > > HDCP_2_2_L_PRIME_LEN);
> > > @@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct
> > > device *dev,
> > >
> > > get_skey_in.port.integrated_port_type = data->port_type;
> > > get_skey_in.port.physical_port = (u8)data->fw_ddi;
> > > + get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > byte = mei_cldev_send(cldev, (u8 *)_skey_in, sizeof(get_skey_in));
> > > if (byte < 0) {
> > > @@ -488,6 +495,7 @@
> mei_hdcp_repeater_check_flow_prepare_ack(struct
> > > device *dev,
> > >
> > > verify_repeater_in.port.integrated_port_type = data->port_type;
> > > verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
> > > + verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> > > HDCP_2_2_RXINFO_LEN);
> > > @@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device
> > > *dev,
> > >
> > > verify_mprime_in.port.integrated_port_type = data->port_type;
> > > verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
> > > + verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
> > >
> > > memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> > > HDCP_2_2_MPRIME_LEN);
> > > @@ -619,6 +628,7 @@ static int mei_hdcp_enable_authentication(struct
> > > device *dev,
> > >
> > > enable_auth_in.port.integrated_port_type = data->port_type;
> > > enable_auth_in.port.physical_port = (u8)data->fw_ddi;
> > > + enable_auth_in.port.attached_transcoder = (u8)data->fw_tc;
> > > enable_auth_in.stream_type = data->streams[0].stream_type;
> > >
> > > byte = mei_cldev_send(cldev, (u8 *)_auth_in, @@ -673,6
> > > +683,7 @@ mei_hdcp_close_session(struct device *dev, struct
> > > +hdcp_port_data
> > > *data)
> > >
> > >
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51) > We want to support this on Gen11 as well, where these registers > are context saved and restored and we prime the register values of new > contexts > from recorded defaults. What could be the correct way to handle this, write > to the > default object or should ask GPU to re-record after modifying the > registers. That depends on whether you want to apply to existing or only to new. For OA / sseu, we modify the context images so that existing contexts are updated to reflect the new defaults, and we update the defaults. E.g. gen8_configure_all_contexts() -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp
> On gen12+ platforms, HDCP HW is associated to the transcoder.
> Hence on every modeset update associated transcoder into the intel_hdcp of
> the port.
>
> v2:
> s/trans/cpu_transcoder [Jani]
> v3:
> comment is added for fw_ddi init for gen12+ [Shashank]
> only hdcp capable transcoder is translated into fw_tc [Shashank]
>
> Signed-off-by: Ramalingam C
> Acked-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_types.h| 7 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
> drivers/gpu/drm/i915/display/intel_hdcp.c | 47 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
> 5 files changed, 62 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 96514dcc7812..61277a87dbe7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -388,6 +388,13 @@ struct intel_hdcp {
> wait_queue_head_t cp_irq_queue;
> atomic_t cp_irq_count;
> int cp_irq_count_cached;
> +
> + /*
> + * HDCP register access for gen12+ need the transcoder associated.
> + * Transcoder attached to the connector could be changed at modeset.
> + * Hence caching the transcoder here.
> + */
> + enum transcoder cpu_transcoder;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23908da1cd5d..e8471689f785 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2248,6 +2248,9 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>
> intel_psr_compute_config(intel_dp, pipe_config);
>
> + intel_hdcp_transcoder_config(intel_connector,
> + pipe_config->cpu_transcoder);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 534832f435dc..3591b8f7fe30 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1762,13 +1762,58 @@ enum mei_fw_ddi
> intel_get_mei_fw_ddi_index(enum port port)
> }
> }
>
> +static inline
> +enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder) {
> + switch (cpu_transcoder) {
> + case TRANSCODER_A ... TRANSCODER_D:
> + return (enum mei_fw_tc)(cpu_transcoder | 0x10);
> + default: /* eDP, DSI TRANSCODERS are non HDCP capable */
> + return MEI_INVALID_TRANSCODER;
> + }
> +}
> +
> +void intel_hdcp_transcoder_config(struct intel_connector *connector,
> + enum transcoder cpu_transcoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_hdcp *hdcp = >hdcp;
> +
> + if (!hdcp->shim)
> + return;
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + mutex_lock(>mutex);
> + hdcp->cpu_transcoder = cpu_transcoder;
> + hdcp->port_data.fw_tc =
> intel_get_mei_fw_tc(cpu_transcoder);
> + mutex_unlock(>mutex);
> + }
> +}
> +
> static inline int initialize_hdcp_port_data(struct intel_connector
> *connector,
> const struct intel_hdcp_shim *shim)
> {
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = >hdcp;
> struct hdcp_port_data *data = >port_data;
> + struct intel_crtc *crtc;
> +
> + if (INTEL_GEN(dev_priv) < 12) {
> + data->fw_ddi =
> + intel_get_mei_fw_ddi_index(connector->encoder-
> >port);
> + } else {
> + crtc = to_intel_crtc(connector->base.state->crtc);
> + if (crtc) {
> + hdcp->cpu_transcoder = crtc->config->cpu_transcoder;
> + data->fw_tc = intel_get_mei_fw_tc(hdcp-
> >cpu_transcoder);
> + }
What is the 'else' action here, looks like there is no default value for fw_tc?
> + /*
> + * As per ME FW API expectation, for GEN 12+, fw_ddi is filled
> + * with INVALID PORT.
> + */
> + data->fw_ddi = intel_get_mei_fw_ddi_index(PORT_NONE);
> + }
>
> - data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder-
> >port);
> data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
> data->protocol = (u8)shim->protocol;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
> b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 59a2b40405cc..41c1053d9e38 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -16,10 +16,13 @@ struct drm_i915_private; struct intel_connector; struct
> intel_hdcp_shim; enum port;
>
Re: [Intel-gfx] [PATCH v10 4/6] misc/mei/hdcp: Fill transcoder index in port info
On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > For gen12+ platform we need to pass the transcoder info as part of the port
> > info into ME FW.
> >
> > This change fills the payload for ME FW from hdcp_port_data.
> >
> > Signed-off-by: Ramalingam C
> > Acked-by: Jani Nikula
> > Reviewed-by: Shashank Sharma
> > ---
> > drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
> > drivers/misc/mei/hdcp/mei_hdcp.h | 4 +++-
> > 2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> > b/drivers/misc/mei/hdcp/mei_hdcp.c
> > index 3638c77eba26..93027fd96c71 100644
> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> > @@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > session_init_in.port.integrated_port_type = data->port_type;
> > session_init_in.port.physical_port = (u8)data->fw_ddi;
> > + session_init_in.port.attached_transcoder = (u8)data->fw_tc;
> > session_init_in.protocol = data->protocol;
> >
> > byte = mei_cldev_send(cldev, (u8 *)_init_in, @@ -127,6
> > +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
> >
> > verify_rxcert_in.port.integrated_port_type = data->port_type;
> > verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
> > + verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> > memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
> > @@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > send_hprime_in.port.integrated_port_type = data->port_type;
> > send_hprime_in.port.physical_port = (u8)data->fw_ddi;
> > + send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> >HDCP_2_2_H_PRIME_LEN);
> > @@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > pairing_info_in.port.integrated_port_type = data->port_type;
> > pairing_info_in.port.physical_port = (u8)data->fw_ddi;
> > + pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> >HDCP_2_2_E_KH_KM_LEN);
> > @@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
> >
> > lc_init_in.port.integrated_port_type = data->port_type;
> > lc_init_in.port.physical_port = (u8)data->fw_ddi;
> > + lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
> > if (byte < 0) {
> > @@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
> > hdcp_port_data *data,
> >
> > verify_lprime_in.port.integrated_port_type = data->port_type;
> > verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
> > + verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> >HDCP_2_2_L_PRIME_LEN);
> > @@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct device
> > *dev,
> >
> > get_skey_in.port.integrated_port_type = data->port_type;
> > get_skey_in.port.physical_port = (u8)data->fw_ddi;
> > + get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > byte = mei_cldev_send(cldev, (u8 *)_skey_in, sizeof(get_skey_in));
> > if (byte < 0) {
> > @@ -488,6 +495,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct
> > device *dev,
> >
> > verify_repeater_in.port.integrated_port_type = data->port_type;
> > verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
> > + verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> >HDCP_2_2_RXINFO_LEN);
> > @@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> >
> > verify_mprime_in.port.integrated_port_type = data->port_type;
> > verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
> > + verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
> >
> > memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> >HDCP_2_2_MPRIME_LEN);
> > @@ -619,6 +628,7 @@ static int mei_hdcp_enable_authentication(struct
> > device *dev,
> >
> > enable_auth_in.port.integrated_port_type = data->port_type;
> > enable_auth_in.port.physical_port = (u8)data->fw_ddi;
> > + enable_auth_in.port.attached_transcoder = (u8)data->fw_tc;
> > enable_auth_in.stream_type = data->streams[0].stream_type;
> >
> > byte = mei_cldev_send(cldev, (u8 *)_auth_in, @@ -673,6
> > +683,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data
> > *data)
> >
> > session_close_in.port.integrated_port_type = data->port_type;
> > session_close_in.port.physical_port = (u8)data->fw_ddi;
> > +
Re: [Intel-gfx] [PATCH RESEND 03/14] drm/amdgpu: Provide ddc symlink in dm connector's sysfs directory
On 2019-08-26 3:25 p.m., Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index cb7cfa9b34f2..e872a415b409 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -5144,11 +5144,12 @@ static int amdgpu_dm_connector_init(struct
> amdgpu_display_manager *dm,
>
> connector_type = to_drm_connector_type(link->connector_signal);
>
> - res = drm_connector_init(
> + res = drm_connector_init_with_ddc(
> dm->ddev,
> >base,
> _dm_connector_funcs,
> - connector_type);
> + connector_type,
> + >base);
>
> if (res) {
> DRM_ERROR("connector_init failed\n");
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 1/6] drm/dp_mst: Add PBN calculation for DSC modes
On 2019-08-26 2:05 p.m., David Francis wrote:
> With DSC, bpp can be fractional in multiples of 1/16.
>
> Change drm_dp_calc_pbn_mode to reflect this, adding a new
> parameter bool dsc. When this parameter is true, treat the
> bpp parameter as having units not of bits per pixel, but
> 1/16 of a bit per pixel
>
> v2: Don't add separate function for this
>
> Cc: amd-...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Reviewed-by: Manasi Navare
> Reviewed-by: Lyude Paul
Reviewed-by: Harry Wentland
Harry
> Signed-off-by: David Francis
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 2 +-
> drivers/gpu/drm/drm_dp_mst_topology.c| 16
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
> include/drm/drm_dp_mst_helper.h | 3 +--
> 6 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index a0ed0154a9f0..abafb5221b44 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -235,7 +235,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>
> /* TODO need to know link rate */
>
> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
> + pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
>
> slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
> ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 82add736e17d..3e7b7553cf4d 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3534,10 +3534,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> * @clock: dot clock for the mode
> * @bpp: bpp for the mode.
> + * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp)
> +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> {
> u64 kbps;
> s64 peak_kbps;
> @@ -3555,11 +3556,18 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
>* peak_kbps *= (1006/1000)
>* peak_kbps *= (64/54)
>* peak_kbps *= 8convert to bytes
> + *
> + * If the bpp is in units of 1/16, further divide by 16. Put this
> + * factor in the numerator rather than the denominator to avoid
> + * integer overflow
>*/
>
> numerator = 64 * 1006;
> denominator = 54 * 8 * 1000 * 1000;
>
> + if (dsc)
> + numerator /= 16;
> +
> kbps *= numerator;
> peak_kbps = drm_fixp_from_fraction(kbps, denominator);
>
> @@ -3570,19 +3578,19 @@ EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> static int test_calc_pbn_mode(void)
> {
> int ret;
> - ret = drm_dp_calc_pbn_mode(154000, 30);
> + ret = drm_dp_calc_pbn_mode(154000, 30, false);
> if (ret != 689) {
> DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
> expected PBN %d, actual PBN %d.\n",
> 154000, 30, 689, ret);
> return -EINVAL;
> }
> - ret = drm_dp_calc_pbn_mode(234000, 30);
> + ret = drm_dp_calc_pbn_mode(234000, 30, false);
> if (ret != 1047) {
> DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
> expected PBN %d, actual PBN %d.\n",
> 234000, 30, 1047, ret);
> return -EINVAL;
> }
> - ret = drm_dp_calc_pbn_mode(297000, 24);
> + ret = drm_dp_calc_pbn_mode(297000, 24, false);
> if (ret != 1063) {
> DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
> expected PBN %d, actual PBN %d.\n",
> 297000, 24, 1063, ret);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2c5ac3dd647f..4f17f61f4453 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -61,7 +61,7 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> crtc_state->pipe_bpp = bpp;
>
> crtc_state->pbn =
> drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> -crtc_state->pipe_bpp);
> +crtc_state->pipe_bpp,
> false);
>
> slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
> port,
Re: [Intel-gfx] [PATCH v10 3/6] drm: Extend I915 mei interface for transcoder info
On 2019-08-27 at 19:30:23 +0530, Winkler, Tomas wrote:
> >
> > I915 needs to send the index of the transcoder as per ME FW.
> >
> > To support this, define enum mei_fw_tc and add as a member into the struct
> > hdcp_port_data.
> >
> > v2:
> > Typo in commit msg is fixed [Shashank]
> >
> > Signed-off-by: Ramalingam C
> > Acked-by: Jani Nikula
> > ---
> > include/drm/i915_mei_hdcp_interface.h | 13 +
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/include/drm/i915_mei_hdcp_interface.h
> > b/include/drm/i915_mei_hdcp_interface.h
> > index a97acf1c9710..0de629bf2f62 100644
> > --- a/include/drm/i915_mei_hdcp_interface.h
> > +++ b/include/drm/i915_mei_hdcp_interface.h
> > @@ -54,9 +54,21 @@ enum mei_fw_ddi {
> > MEI_DDI_RANGE_END = MEI_DDI_A,
> > };
> >
> > +enum mei_fw_tc {
> > + MEI_INVALID_TRANSCODER = 0x00, /* Invalid transcoder type */
> > + MEI_TC_EDP, /* Transcoder for eDP */
> > + MEI_TC_DSI0,/* Transcoder for DSI0 */
> > + MEI_TC_DSI1,/* Transcoder for DSI1 */
> > + MEI_TC_A = 0x10,/* Transcoder TCA */
> > + MEI_TC_B, /* Transcoder TCB */
> > + MEI_TC_C, /* Transcoder TCC */
> > + MEI_TC_D/* Transcoder TCD */
> > +};
>
> You should use kdoc format here, please.
> https://www.kernel.org/doc/html/v5.2/doc-guide/kernel-doc.html
> Also TCA just means Transcoder A or TC has other meaning?
TCA stands for TRANSCODER A only. Sure I will use kdoc format.
-Ram
>
> > +
> > /**
> > * struct hdcp_port_data - intel specific HDCP port data
> > * @fw_ddi: ddi index as per ME FW
> > + * @fw_tc: transcoder index as per ME FW
> > * @port_type: HDCP port type as per ME FW classification
> > * @protocol: HDCP adaptation as per ME FW
> > * @k: No of streams transmitted on a port. Only on DP MST this is != 1 @@
> > -
> > 69,6 +81,7 @@ enum mei_fw_ddi {
> > */
> > struct hdcp_port_data {
> > enum mei_fw_ddi fw_ddi;
> > + enum mei_fw_tc fw_tc;
> > u8 port_type;
> > u8 protocol;
> > u16 k;
> > --
> > 2.20.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only activate i915_active debugobject once
== Series Details ==
Series: drm/i915: Only activate i915_active debugobject once
URL : https://patchwork.freedesktop.org/series/65874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14201
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14201/
Known issues
Here are the changes found in Patchwork_14201 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#109635 ])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14201/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][3] ([fdo#08]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14201/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (52 -> 44)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6792 -> Patchwork_14201
CI-20190529: 20190529
CI_DRM_6792: 87f7792bc3891de3fab4fb64d66a85a66729e3d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14201: 72ee475bc646fdf764e95c15fb5909d6b91b7bd3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
72ee475bc646 drm/i915: Only activate i915_active debugobject once
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14201/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 4/6] misc/mei/hdcp: Fill transcoder index in port info
> For gen12+ platform we need to pass the transcoder info as part of the port
> info into ME FW.
>
> This change fills the payload for ME FW from hdcp_port_data.
>
> Signed-off-by: Ramalingam C
> Acked-by: Jani Nikula
> Reviewed-by: Shashank Sharma
> ---
> drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
> drivers/misc/mei/hdcp/mei_hdcp.h | 4 +++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c
> b/drivers/misc/mei/hdcp/mei_hdcp.c
> index 3638c77eba26..93027fd96c71 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
> hdcp_port_data *data,
>
> session_init_in.port.integrated_port_type = data->port_type;
> session_init_in.port.physical_port = (u8)data->fw_ddi;
> + session_init_in.port.attached_transcoder = (u8)data->fw_tc;
> session_init_in.protocol = data->protocol;
>
> byte = mei_cldev_send(cldev, (u8 *)_init_in, @@ -127,6
> +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
>
> verify_rxcert_in.port.integrated_port_type = data->port_type;
> verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
> + verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
>
> verify_rxcert_in.cert_rx = rx_cert->cert_rx;
> memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
> @@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
> hdcp_port_data *data,
>
> send_hprime_in.port.integrated_port_type = data->port_type;
> send_hprime_in.port.physical_port = (u8)data->fw_ddi;
> + send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
>
> memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
> HDCP_2_2_H_PRIME_LEN);
> @@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
> hdcp_port_data *data,
>
> pairing_info_in.port.integrated_port_type = data->port_type;
> pairing_info_in.port.physical_port = (u8)data->fw_ddi;
> + pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
>
> memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
> HDCP_2_2_E_KH_KM_LEN);
> @@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
>
> lc_init_in.port.integrated_port_type = data->port_type;
> lc_init_in.port.physical_port = (u8)data->fw_ddi;
> + lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
>
> byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
> if (byte < 0) {
> @@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
> hdcp_port_data *data,
>
> verify_lprime_in.port.integrated_port_type = data->port_type;
> verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
> + verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
>
> memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
> HDCP_2_2_L_PRIME_LEN);
> @@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct device
> *dev,
>
> get_skey_in.port.integrated_port_type = data->port_type;
> get_skey_in.port.physical_port = (u8)data->fw_ddi;
> + get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
>
> byte = mei_cldev_send(cldev, (u8 *)_skey_in, sizeof(get_skey_in));
> if (byte < 0) {
> @@ -488,6 +495,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct
> device *dev,
>
> verify_repeater_in.port.integrated_port_type = data->port_type;
> verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
> + verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
>
> memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
> HDCP_2_2_RXINFO_LEN);
> @@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
>
> verify_mprime_in.port.integrated_port_type = data->port_type;
> verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
> + verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
>
> memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
> HDCP_2_2_MPRIME_LEN);
> @@ -619,6 +628,7 @@ static int mei_hdcp_enable_authentication(struct
> device *dev,
>
> enable_auth_in.port.integrated_port_type = data->port_type;
> enable_auth_in.port.physical_port = (u8)data->fw_ddi;
> + enable_auth_in.port.attached_transcoder = (u8)data->fw_tc;
> enable_auth_in.stream_type = data->streams[0].stream_type;
>
> byte = mei_cldev_send(cldev, (u8 *)_auth_in, @@ -673,6
> +683,7 @@ mei_hdcp_close_session(struct device *dev, struct hdcp_port_data
> *data)
>
> session_close_in.port.integrated_port_type = data->port_type;
> session_close_in.port.physical_port = (u8)data->fw_ddi;
> + session_close_in.port.attached_transcoder = (u8)data->fw_tc;
>
> byte = mei_cldev_send(cldev, (u8 *)_close_in,
>
Re: [Intel-gfx] [PATCH] drm/i915: Align power domain names with port names
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> There is a difference in BSpec's and the driver's designation of DDI
> ports. BSpec uses the following names:
> - before GEN11:
> BSpec/driver:
> port A/B/C/D etc
> - GEN11:
> BSpec/driver:
> port A-F
> - GEN12:
> BSpec:
> port A/B/C for combo PHY ports
> port TC1-6 for Type C PHY ports
> driver:
> port A-I.
> The driver's port D name matches BSpec's TC1 port name.
>
> So far power domains were named according to the BSpec designation,
> to
> make it easier to match the code against the specification. That
> however
> can be confusing when a power domain needs to be matched to a port on
> GEN12+. To resolve that use the driver's port A-I designation for
> power
> domain names too and rename the corresponding power wells so that
> they
> reflect the mapping from the driver's to BSpec's port name.
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Lucas De Marchi
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> .../drm/i915/display/intel_display_power.c| 361 +---
> --
> .../drm/i915/display/intel_display_power.h| 40 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> 4 files changed, 198 insertions(+), 216 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b51d1ceb8739..a3cba6efbf71 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6737,16 +6737,16 @@ intel_aux_power_domain(struct
> intel_digital_port *dig_port)
> dig_port->tc_mode == TC_PORT_TBT_ALT) {
> switch (dig_port->aux_ch) {
> case AUX_CH_C:
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> case AUX_CH_D:
> - return POWER_DOMAIN_AUX_TBT2;
> + return POWER_DOMAIN_AUX_D_TBT;
> case AUX_CH_E:
> - return POWER_DOMAIN_AUX_TBT3;
> + return POWER_DOMAIN_AUX_E_TBT;
> case AUX_CH_F:
> - return POWER_DOMAIN_AUX_TBT4;
> + return POWER_DOMAIN_AUX_F_TBT;
> default:
> MISSING_CASE(dig_port->aux_ch);
> - return POWER_DOMAIN_AUX_TBT1;
> + return POWER_DOMAIN_AUX_C_TBT;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12099760d99e..ce88a27229ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -24,11 +24,8 @@ bool intel_display_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
>enum i915_power_well_id
> power_well_id);
>
> const char *
> -intel_display_power_domain_str(struct drm_i915_private *i915,
> -enum intel_display_power_domain domain)
> +intel_display_power_domain_str(enum intel_display_power_domain
> domain)
> {
> - bool ddi_tc_ports = IS_GEN(i915, 12);
> -
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -71,23 +68,17 @@ intel_display_power_domain_str(struct
> drm_i915_private *i915,
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC1_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
> "PORT_DDI_D_LANES";
> + return "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC2_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
> "PORT_DDI_E_LANES";
> + return "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> - POWER_DOMAIN_PORT_DDI_TC3_LANES);
> - return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
> "PORT_DDI_F_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> - return "PORT_DDI_TC4_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> - return "PORT_DDI_TC5_LANES";
> - case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> - return "PORT_DDI_TC6_LANES";
> + return "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_G_LANES:
> + return "PORT_DDI_G_LANES";
> + case POWER_DOMAIN_PORT_DDI_H_LANES:
> + return "PORT_DDI_H_LANES";
> + case POWER_DOMAIN_PORT_DDI_I_LANES:
> + return
[Intel-gfx] [PATCH v9 1/6] drm/dp_mst: Add PBN calculation for DSC modes
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate function for this
Cc: amd-...@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Manasi Navare
Reviewed-by: Lyude Paul
Reviewed-by: Harry Wentland
Signed-off-by: David Francis
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c| 16
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
include/drm/drm_dp_mst_helper.h | 3 +--
6 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index a0ed0154a9f0..abafb5221b44 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -235,7 +235,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
/* TODO need to know link rate */
- pbn = drm_dp_calc_pbn_mode(clock, bpp);
+ pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 82add736e17d..3e7b7553cf4d 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3534,10 +3534,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
+ * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
{
u64 kbps;
s64 peak_kbps;
@@ -3555,11 +3556,18 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
* peak_kbps *= (1006/1000)
* peak_kbps *= (64/54)
* peak_kbps *= 8convert to bytes
+*
+* If the bpp is in units of 1/16, further divide by 16. Put this
+* factor in the numerator rather than the denominator to avoid
+* integer overflow
*/
numerator = 64 * 1006;
denominator = 54 * 8 * 1000 * 1000;
+ if (dsc)
+ numerator /= 16;
+
kbps *= numerator;
peak_kbps = drm_fixp_from_fraction(kbps, denominator);
@@ -3570,19 +3578,19 @@ EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
static int test_calc_pbn_mode(void)
{
int ret;
- ret = drm_dp_calc_pbn_mode(154000, 30);
+ ret = drm_dp_calc_pbn_mode(154000, 30, false);
if (ret != 689) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
expected PBN %d, actual PBN %d.\n",
154000, 30, 689, ret);
return -EINVAL;
}
- ret = drm_dp_calc_pbn_mode(234000, 30);
+ ret = drm_dp_calc_pbn_mode(234000, 30, false);
if (ret != 1047) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
expected PBN %d, actual PBN %d.\n",
234000, 30, 1047, ret);
return -EINVAL;
}
- ret = drm_dp_calc_pbn_mode(297000, 24);
+ ret = drm_dp_calc_pbn_mode(297000, 24, false);
if (ret != 1063) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d,
expected PBN %d, actual PBN %d.\n",
297000, 24, 1063, ret);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2c5ac3dd647f..4f17f61f4453 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -61,7 +61,7 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
crtc_state->pipe_bpp = bpp;
crtc_state->pbn =
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- crtc_state->pipe_bpp);
+ crtc_state->pipe_bpp,
false);
slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
port, crtc_state->pbn);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 5c36c75232e6..c68783c1f3fa 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
Re: [Intel-gfx] [PATCH RESEND 02/14] drm/radeon: Provide ddc symlink in connector sysfs directory
On Mon, Aug 26, 2019 at 3:26 PM Andrzej Pietrasiewicz
wrote:
>
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/radeon_connectors.c | 143 +++--
> 1 file changed, 107 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
> b/drivers/gpu/drm/radeon/radeon_connectors.c
> index c60d1a44d22a..62d37eddf99c 100644
> --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> @@ -1870,6 +1870,7 @@ radeon_add_atom_connector(struct drm_device *dev,
> struct radeon_connector_atom_dig *radeon_dig_connector;
> struct drm_encoder *encoder;
> struct radeon_encoder *radeon_encoder;
> + struct i2c_adapter *ddc = NULL;
> uint32_t subpixel_order = SubPixelNone;
> bool shared_ddc = false;
> bool is_dp_bridge = false;
> @@ -1947,17 +1948,21 @@ radeon_add_atom_connector(struct drm_device *dev,
> radeon_connector->con_priv = radeon_dig_connector;
> if (i2c_bus->valid) {
> radeon_connector->ddc_bus = radeon_i2c_lookup(rdev,
> i2c_bus);
> - if (radeon_connector->ddc_bus)
> + if (radeon_connector->ddc_bus) {
> has_aux = true;
> - else
> + ddc = _connector->ddc_bus->adapter;
> + } else {
> DRM_ERROR("DP: Failed to assign ddc bus!
> Check dmesg for i2c errors.\n");
> + }
> }
> switch (connector_type) {
> case DRM_MODE_CONNECTOR_VGA:
> case DRM_MODE_CONNECTOR_DVIA:
> default:
> - drm_connector_init(dev, _connector->base,
> - _dp_connector_funcs,
> connector_type);
> + drm_connector_init_with_ddc(dev,
> _connector->base,
> +
> _dp_connector_funcs,
> + connector_type,
> + ddc);
> drm_connector_helper_add(_connector->base,
>
> _dp_connector_helper_funcs);
> connector->interlace_allowed = true;
> @@ -1979,8 +1984,10 @@ radeon_add_atom_connector(struct drm_device *dev,
> case DRM_MODE_CONNECTOR_HDMIA:
> case DRM_MODE_CONNECTOR_HDMIB:
> case DRM_MODE_CONNECTOR_DisplayPort:
> - drm_connector_init(dev, _connector->base,
> - _dp_connector_funcs,
> connector_type);
> + drm_connector_init_with_ddc(dev,
> _connector->base,
> +
> _dp_connector_funcs,
> + connector_type,
> + ddc);
> drm_connector_helper_add(_connector->base,
>
> _dp_connector_helper_funcs);
>
> drm_object_attach_property(_connector->base.base,
> @@ -2027,8 +2034,10 @@ radeon_add_atom_connector(struct drm_device *dev,
> break;
> case DRM_MODE_CONNECTOR_LVDS:
> case DRM_MODE_CONNECTOR_eDP:
> - drm_connector_init(dev, _connector->base,
> -
> _lvds_bridge_connector_funcs, connector_type);
> + drm_connector_init_with_ddc(dev,
> _connector->base,
> +
> _lvds_bridge_connector_funcs,
> + connector_type,
> + ddc);
> drm_connector_helper_add(_connector->base,
>
> _dp_connector_helper_funcs);
>
> drm_object_attach_property(_connector->base.base,
> @@ -2042,13 +2051,18 @@ radeon_add_atom_connector(struct drm_device *dev,
> } else {
> switch (connector_type) {
> case DRM_MODE_CONNECTOR_VGA:
> - drm_connector_init(dev, _connector->base,
> _vga_connector_funcs, connector_type);
> - drm_connector_helper_add(_connector->base,
> _vga_connector_helper_funcs);
> if (i2c_bus->valid) {
> radeon_connector->ddc_bus =
> radeon_i2c_lookup(rdev, i2c_bus);
> if (!radeon_connector->ddc_bus)
> DRM_ERROR("VGA: Failed
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
On Mon, Aug 26, 2019 at 10:17:55AM +0100, Chris Wilson wrote: > Quoting Prathap Kumar Valsan (2019-08-26 00:35:27) > > To provide shared last-level-cache isolation to cpu workloads running > > concurrently with gpu workloads, the gpu allocation of cache lines needs > > to be restricted to certain ways. Currently GPU hardware supports four > > class-of-service(CLOS) levels and there is an associated way-mask for > > each CLOS. > > > > Hardware supports reading supported way-mask configuration for GPU using > > a bios pcode interface. The supported way-masks and the one currently > > active is communicated to userspace via a sysfs file--closctrl. Admin user > > can then select a new mask by writing the mask value to the file. > > What impact does this have on inflight work? Do you need to drain the > submission queue, change the global registers, force an invalidation and > then restart? Can it be done from inside the GPU so that it is > serialised with on-going submission? I believe this should not be impacting the inflight work. Because, way mask only influnece a new cache allocation on cache miss. Cache hits are not restricted by way-mask. So even the way-mask is changed, in-flight requests previously allocated cache lines from other ways will still be a cache hit until thrashed. We want to support this on Gen11 as well, where these registers are context saved and restored and we prime the register values of new contexts from recorded defaults. What could be the correct way to handle this, write to the default object or should ask GPU to re-record after modifying the registers. Thanks, Prathap > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add sysfs interface to control class-of-service
On Mon, Aug 26, 2019 at 09:39:48AM +0100, Chris Wilson wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain ways. Currently GPU hardware supports four
> > class-of-service(CLOS) levels and there is an associated way-mask for
> > each CLOS.
> >
> > Hardware supports reading supported way-mask configuration for GPU using
> > a bios pcode interface. The supported way-masks and the one currently
> > active is communicated to userspace via a sysfs file--closctrl. Admin user
> > can then select a new mask by writing the mask value to the file.
> >
> > Note of Caution: Restricting cache ways using this mechanism presents a
> > larger attack surface for side-channel attacks.
> >
> > Example usage:
> > The active way-mask is highlighted within square brackets.
> > > cat /sys/class/drm/card0/closctrl
> > [0x] 0xff00 0xc000 0x8000
> >
> > CLOS0 is currently active.
> >
> > > echo 0x8000 > /sys/class/drm/card0/closctrl
> > > cat /sys/class/drm/card0/closctrl
> > 0x 0xff00 0xc000 [0x8000]
> >
> > CLOS3 is currently active
> >
> > Signed-off-by: Prathap Kumar Valsan
> > ---
> > Changes in v2:
> > Declare closctrl_show and closctrl_store as static functions.
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 57 ---
> > drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 8
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/i915_sysfs.c| 67
> > 5 files changed, 129 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 728704bbbe18..dd13e61944fd 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -26,6 +26,7 @@
> > #include "intel_gt.h"
> > #include "intel_mocs.h"
> > #include "intel_lrc.h"
> > +#include "intel_sideband.h"
> >
> > /* structures required */
> > struct drm_i915_mocs_entry {
> > @@ -51,6 +52,7 @@ struct drm_i915_mocs_table {
> > #define LE_SCF(value) ((value) << 14)
> > #define LE_COS(value) ((value) << 15)
> > #define LE_SSE(value) ((value) << 17)
> > +#define LE_COS_MASKGENMASK(16, 15)
> >
> > /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word
> > */
> > #define L3_ESC(value) ((value) << 0)
> > @@ -408,10 +410,13 @@ void intel_mocs_init_engine(struct intel_engine_cs
> > *engine)
> > unused_value);
> > }
> >
> > -static void intel_mocs_init_global(struct intel_gt *gt)
> > +void intel_mocs_init_global(struct intel_gt *gt)
> > {
> > + struct drm_i915_private *i915 = gt->i915;
> > struct intel_uncore *uncore = gt->uncore;
> > struct drm_i915_mocs_table table;
> > + unsigned int active_clos;
> > + u32 value, unused_value;
> > unsigned int index;
> >
> > GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
> > @@ -422,20 +427,31 @@ static void intel_mocs_init_global(struct intel_gt
> > *gt)
> > if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> > return;
> >
> > - for (index = 0; index < table.size; index++)
> > + active_clos = atomic_read(>clos.active_clos);
> > +
> > + for (index = 0; index < table.size; index++) {
> > + value = table.table[index].control_value;
> > + value &= ~LE_COS_MASK;
> > + value |= FIELD_PREP(LE_COS_MASK, active_clos);
> > +
> > intel_uncore_write(uncore,
> >GEN12_GLOBAL_MOCS(index),
> > - table.table[index].control_value);
> > + value);
> > + }
> >
> > /*
> > * Ok, now set the unused entries to the invalid entry (index 0).
> > These
> > * entries are officially undefined and no contract for the
> > contents and
> > * settings is given for these entries.
> > */
> > + unused_value = table.table[0].control_value;
> > + unused_value &= ~LE_COS_MASK;
> > + unused_value |= FIELD_PREP(LE_COS_MASK, active_clos);
> > +
> > for (; index < table.n_entries; index++)
> > intel_uncore_write(uncore,
> >GEN12_GLOBAL_MOCS(index),
> > - table.table[0].control_value);
> > + unused_value);
> > }
> >
> > static int emit_mocs_control_table(struct i915_request *rq,
> > @@ -625,10 +641,41 @@ int intel_mocs_emit(struct i915_request *rq)
> > return 0;
> > }
> >
> > +static void intel_read_clos_way_mask(struct intel_gt *gt)
> > +{
> > + struct drm_i915_private
Re: [Intel-gfx] [PATCH v10 3/6] drm: Extend I915 mei interface for transcoder info
>
> I915 needs to send the index of the transcoder as per ME FW.
>
> To support this, define enum mei_fw_tc and add as a member into the struct
> hdcp_port_data.
>
> v2:
> Typo in commit msg is fixed [Shashank]
>
> Signed-off-by: Ramalingam C
> Acked-by: Jani Nikula
> ---
> include/drm/i915_mei_hdcp_interface.h | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/include/drm/i915_mei_hdcp_interface.h
> b/include/drm/i915_mei_hdcp_interface.h
> index a97acf1c9710..0de629bf2f62 100644
> --- a/include/drm/i915_mei_hdcp_interface.h
> +++ b/include/drm/i915_mei_hdcp_interface.h
> @@ -54,9 +54,21 @@ enum mei_fw_ddi {
> MEI_DDI_RANGE_END = MEI_DDI_A,
> };
>
> +enum mei_fw_tc {
> + MEI_INVALID_TRANSCODER = 0x00, /* Invalid transcoder type */
> + MEI_TC_EDP, /* Transcoder for eDP */
> + MEI_TC_DSI0,/* Transcoder for DSI0 */
> + MEI_TC_DSI1,/* Transcoder for DSI1 */
> + MEI_TC_A = 0x10,/* Transcoder TCA */
> + MEI_TC_B, /* Transcoder TCB */
> + MEI_TC_C, /* Transcoder TCC */
> + MEI_TC_D/* Transcoder TCD */
> +};
You should use kdoc format here, please.
https://www.kernel.org/doc/html/v5.2/doc-guide/kernel-doc.html
Also TCA just means Transcoder A or TC has other meaning?
> +
> /**
> * struct hdcp_port_data - intel specific HDCP port data
> * @fw_ddi: ddi index as per ME FW
> + * @fw_tc: transcoder index as per ME FW
> * @port_type: HDCP port type as per ME FW classification
> * @protocol: HDCP adaptation as per ME FW
> * @k: No of streams transmitted on a port. Only on DP MST this is != 1 @@ -
> 69,6 +81,7 @@ enum mei_fw_ddi {
> */
> struct hdcp_port_data {
> enum mei_fw_ddi fw_ddi;
> + enum mei_fw_tc fw_tc;
> u8 port_type;
> u8 protocol;
> u16 k;
> --
> 2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Make engine batch pool's safe for use with virtual engines
A virtual engine itself does not have a batch pool, but we can gleefully
use any of its siblings instead.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pool.c| 12 +++-
drivers/gpu/drm/i915/gt/intel_engine_pool.h| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c| 12
drivers/gpu/drm/i915/gt/intel_lrc.h| 4
6 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b5f6937369ea..7b1d8c4e5ef5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1145,7 +1145,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
u32 *cmd;
int err;
- pool = intel_engine_pool_get(>engine->pool, PAGE_SIZE);
+ pool = intel_engine_get_pool(eb->engine, PAGE_SIZE);
if (IS_ERR(pool))
return PTR_ERR(pool);
@@ -1961,7 +1961,7 @@ static struct i915_vma *eb_parse(struct i915_execbuffer
*eb, bool is_master)
struct i915_vma *vma;
int err;
- pool = intel_engine_pool_get(>engine->pool, eb->batch_len);
+ pool = intel_engine_get_pool(eb->engine, eb->batch_len);
if (IS_ERR(pool))
return ERR_CAST(pool);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 6415f9a17e2d..5bd8de124d74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -32,7 +32,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context
*ce,
count = div_u64(vma->size, block_size);
size = (1 + 8 * count) * sizeof(u32);
size = round_up(size, PAGE_SIZE);
- pool = intel_engine_pool_get(>engine->pool, size);
+ pool = intel_engine_get_pool(ce->engine, size);
if (IS_ERR(pool)) {
err = PTR_ERR(pool);
goto out_pm;
@@ -216,7 +216,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct
intel_context *ce,
count = div_u64(dst->size, block_size);
size = (1 + 11 * count) * sizeof(u32);
size = round_up(size, PAGE_SIZE);
- pool = intel_engine_pool_get(>engine->pool, size);
+ pool = intel_engine_get_pool(ce->engine, size);
if (IS_ERR(pool)) {
err = PTR_ERR(pool);
goto out_pm;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.c
b/drivers/gpu/drm/i915/gt/intel_engine_pool.c
index 4cd54c569911..97d36cca8ded 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.c
@@ -107,9 +107,19 @@ node_create(struct intel_engine_pool *pool, size_t sz)
return node;
}
+static struct intel_engine_pool *lookup_pool(struct intel_engine_cs *engine)
+{
+ if (intel_engine_is_virtual(engine))
+ engine = intel_virtual_engine_get_sibling(engine, 0);
+
+ GEM_BUG_ON(!engine);
+ return >pool;
+}
+
struct intel_engine_pool_node *
-intel_engine_pool_get(struct intel_engine_pool *pool, size_t size)
+intel_engine_get_pool(struct intel_engine_cs *engine, size_t size)
{
+ struct intel_engine_pool *pool = lookup_pool(engine);
struct intel_engine_pool_node *node;
struct list_head *list;
unsigned long flags;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
index 8d069efd9457..7e2123b33594 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
@@ -12,7 +12,7 @@
#include "i915_request.h"
struct intel_engine_pool_node *
-intel_engine_pool_get(struct intel_engine_pool *pool, size_t size);
+intel_engine_get_pool(struct intel_engine_cs *engine, size_t size);
static inline int
intel_engine_pool_mark_active(struct intel_engine_pool_node *node,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d42584439f51..cfbdcca76ff0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3851,6 +3851,18 @@ int intel_virtual_engine_attach_bond(struct
intel_engine_cs *engine,
return 0;
}
+struct intel_engine_cs *
+intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
+unsigned int sibling)
+{
+ struct virtual_engine *ve = to_virtual_engine(engine);
+
+ if (sibling >= ve->num_siblings)
+ return NULL;
+
+ return ve->siblings[sibling];
+}
+
void intel_execlists_show_requests(struct intel_engine_cs *engine,
struct drm_printer *m,
void (*show_request)(struct drm_printer *m,
diff --git
Re: [Intel-gfx] [PATCH] drm/i915: Align power domain names with port names
On Tue, Aug 27, 2019 at 04:42:12PM +0300, Lisovskiy, Stanislav wrote: > On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote: > > There is a difference in BSpec's and the driver's designation of DDI > > ports. BSpec uses the following names: > > - before GEN11: > > BSpec/driver: > > port A/B/C/D etc > > - GEN11: > > BSpec/driver: > > port A-F > > - GEN12: > > BSpec: > > port A/B/C for combo PHY ports > > port TC1-6 for Type C PHY ports > > driver: > > port A-I. > > The driver's port D name matches BSpec's TC1 port name. > > > > So far power domains were named according to the BSpec designation, > > to > > make it easier to match the code against the specification. That > > however > > can be confusing when a power domain needs to be matched to a port on > > GEN12+. To resolve that use the driver's port A-I designation for > > power > > domain names too and rename the corresponding power wells so that > > they > > reflect the mapping from the driver's to BSpec's port name. > > > > Cc: Lucas De Marchi > > Cc: Ville Syrjälä > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 10 +- > > .../drm/i915/display/intel_display_power.c| 361 +--- > > -- > > .../drm/i915/display/intel_display_power.h| 40 +- > > drivers/gpu/drm/i915/i915_debugfs.c | 3 +- > > 4 files changed, 198 insertions(+), 216 deletions(-) > > > > For Tigerlake power domains we have this change: > > +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT)) > +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT)) > +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT)) > +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_G_TBT)) > +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_H_TBT)) > +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_I_TBT)) > > and TGL_PW_5_POWER_DOMAINS: > > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT5) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT6) |\ > > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \ > > For ICL_PW_3_POWER_DOMAINS: > > - BIT_ULL(POWER_DOMAIN_AUX_TBT1) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT2) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT3) |\ > - BIT_ULL(POWER_DOMAIN_AUX_TBT4) |\ > + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ > > However in intel_aux_power_domain: > > - return POWER_DOMAIN_AUX_TBT1; > + return POWER_DOMAIN_AUX_C_TBT; > case AUX_CH_D: > - return POWER_DOMAIN_AUX_TBT2; > + return POWER_DOMAIN_AUX_D_TBT; > case AUX_CH_E: > - return POWER_DOMAIN_AUX_TBT3; > + return POWER_DOMAIN_AUX_E_TBT; > case AUX_CH_F: > - return POWER_DOMAIN_AUX_TBT4; > + return POWER_DOMAIN_AUX_F_TBT; > default: > MISSING_CASE(dig_port->aux_ch); > - return POWER_DOMAIN_AUX_TBT1; > + return POWER_DOMAIN_AUX_C_TBT; > > While for Icelake power domains definition is still TBT1->AUX_C: > > -#define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_AUX_TBT1)) > -#define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_AUX_TBT2)) > -#define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_AUX_TBT3)) > -#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_AUX_TBT4)) > +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_C_TBT)) > +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_D_TBT)) > +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_E_TBT)) > +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS (\ > + BIT_ULL(POWER_DOMAIN_AUX_F_TBT)) > > So does POWER_DOMAIN_AUX_TBT1 correspond now to
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Allow /2 CD2X divider on gen11+
On Mon, Aug 26, 2019 at 03:55:39PM -0700, Matt Roper wrote:
> The bspec has just recently been updated with new cdclk values that
> require the use of a /2 CD2X divider rather than a /1 divider. Once we
> add the divider selection logic to ICL+ cdclk programming, we have
> pretty much the same logic we were already using on CNL, so it's simpler
> to drop icl_set_cdclk() completely and reuse cnl_set_cdclk() on gen11+
> platforms as well.
>
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 90 +-
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> 2 files changed, 36 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 939088c7d814..a56ccd0930e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1659,10 +1659,23 @@ static void cnl_set_cdclk(struct drm_i915_private
> *dev_priv,
> cnl_cdclk_pll_enable(dev_priv, vco);
>
> val = divider | skl_cdclk_decimal(cdclk);
> - if (pipe == INVALID_PIPE)
> - val |= BXT_CDCLK_CD2X_PIPE_NONE;
> - else
> - val |= BXT_CDCLK_CD2X_PIPE(pipe);
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + if (pipe == INVALID_PIPE)
> + val |= ICL_CDCLK_CD2X_PIPE_NONE;
> + else
> + val |= BXT_CDCLK_CD2X_PIPE(pipe);
Hmm. So the mess made here with icl is now fixed. Cool. Sad they
didn't fix it on icl as well.
However I have a feeling this may end up confusing people, so maybe we
should just add TGL_CDCLK_CD2X_PIPE()?
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> + if (pipe == INVALID_PIPE)
> + val |= ICL_CDCLK_CD2X_PIPE_NONE;
> + else
> + val |= ICL_CDCLK_CD2X_PIPE(pipe);
> + } else {
> + if (pipe == INVALID_PIPE)
> + val |= BXT_CDCLK_CD2X_PIPE_NONE;
> + else
> + val |= BXT_CDCLK_CD2X_PIPE(pipe);
> + }
> I915_WRITE(CDCLK_CTL, val);
>
> if (pipe != INVALID_PIPE)
> @@ -1813,51 +1826,6 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
> return dev_priv->cdclk.hw.ref * ratio;
> }
>
> -static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_state *cdclk_state,
> - enum pipe pipe)
> -{
> - unsigned int cdclk = cdclk_state->cdclk;
> - unsigned int vco = cdclk_state->vco;
> - int ret;
> -
> - ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> - if (ret) {
> - DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> - ret);
> - return;
> - }
> -
> - if (dev_priv->cdclk.hw.vco != 0 &&
> - dev_priv->cdclk.hw.vco != vco)
> - cnl_cdclk_pll_disable(dev_priv);
> -
> - if (dev_priv->cdclk.hw.vco != vco)
> - cnl_cdclk_pll_enable(dev_priv, vco);
> -
> - /*
> - * On ICL CD2X_DIV can only be 1, so we'll never end up changing the
> - * divider here synchronized to a pipe while CDCLK is on, nor will we
> - * need the corresponding vblank wait.
> - */
> - I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> - skl_cdclk_decimal(cdclk));
> -
> - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_state->voltage_level);
> -
> - intel_update_cdclk(dev_priv);
> -
> - /*
> - * Can't read out the voltage level :(
> - * Let's just assume everything is as expected.
> - */
> - dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> -}
> -
> static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int
> cdclk)
> {
> if (IS_ELKHARTLAKE(dev_priv)) {
> @@ -1881,6 +1849,7 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
> struct intel_cdclk_state *cdclk_state)
> {
> u32 val;
> + int div;
>
> cdclk_state->bypass = 5;
>
> @@ -1914,10 +1883,21 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
>
> cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
>
> - val = I915_READ(CDCLK_CTL);
> - WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> + val = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> + switch (val) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + div = 2;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + div = 4;
> + break;
> +
Re: [Intel-gfx] [PATCH] drm/i915: Align power domain names with port names
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote: > There is a difference in BSpec's and the driver's designation of DDI > ports. BSpec uses the following names: > - before GEN11: > BSpec/driver: > port A/B/C/D etc > - GEN11: > BSpec/driver: > port A-F > - GEN12: > BSpec: > port A/B/C for combo PHY ports > port TC1-6 for Type C PHY ports > driver: > port A-I. > The driver's port D name matches BSpec's TC1 port name. > > So far power domains were named according to the BSpec designation, > to > make it easier to match the code against the specification. That > however > can be confusing when a power domain needs to be matched to a port on > GEN12+. To resolve that use the driver's port A-I designation for > power > domain names too and rename the corresponding power wells so that > they > reflect the mapping from the driver's to BSpec's port name. > > Cc: Lucas De Marchi > Cc: Ville Syrjälä > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_display.c | 10 +- > .../drm/i915/display/intel_display_power.c| 361 +--- > -- > .../drm/i915/display/intel_display_power.h| 40 +- > drivers/gpu/drm/i915/i915_debugfs.c | 3 +- > 4 files changed, 198 insertions(+), 216 deletions(-) For Tigerlake power domains we have this change: +#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_D_TBT)) +#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_E_TBT)) +#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_F_TBT)) +#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_G_TBT)) +#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_H_TBT)) +#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_I_TBT)) and TGL_PW_5_POWER_DOMAINS: - BIT_ULL(POWER_DOMAIN_AUX_TBT1) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT2) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT3) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT4) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT5) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT6) |\ + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \ For ICL_PW_3_POWER_DOMAINS: - BIT_ULL(POWER_DOMAIN_AUX_TBT1) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT2) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT3) |\ - BIT_ULL(POWER_DOMAIN_AUX_TBT4) |\ + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ However in intel_aux_power_domain: - return POWER_DOMAIN_AUX_TBT1; + return POWER_DOMAIN_AUX_C_TBT; case AUX_CH_D: - return POWER_DOMAIN_AUX_TBT2; + return POWER_DOMAIN_AUX_D_TBT; case AUX_CH_E: - return POWER_DOMAIN_AUX_TBT3; + return POWER_DOMAIN_AUX_E_TBT; case AUX_CH_F: - return POWER_DOMAIN_AUX_TBT4; + return POWER_DOMAIN_AUX_F_TBT; default: MISSING_CASE(dig_port->aux_ch); - return POWER_DOMAIN_AUX_TBT1; + return POWER_DOMAIN_AUX_C_TBT; While for Icelake power domains definition is still TBT1->AUX_C: -#define ICL_AUX_TBT1_IO_POWER_DOMAINS (\ - BIT_ULL(POWER_DOMAIN_AUX_TBT1)) -#define ICL_AUX_TBT2_IO_POWER_DOMAINS (\ - BIT_ULL(POWER_DOMAIN_AUX_TBT2)) -#define ICL_AUX_TBT3_IO_POWER_DOMAINS (\ - BIT_ULL(POWER_DOMAIN_AUX_TBT3)) -#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\ - BIT_ULL(POWER_DOMAIN_AUX_TBT4)) +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C_TBT)) +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_D_TBT)) +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_E_TBT)) +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_F_TBT)) So does POWER_DOMAIN_AUX_TBT1 correspond now to POWER_DOMAIN_AUX_C_TBT for ICL and POWER_DOMAIN_AUX_D_TBT for TGL? Should we then change intel_aux_power_domain so that for Icl it returns POWER_DOMAIN_AUX_C_TBT and POWER_DOMAIN_AUX_D_TBT for
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Flush the post-sync breadcrumb write harder
== Series Details == Series: drm/i915/execlists: Flush the post-sync breadcrumb write harder URL : https://patchwork.freedesktop.org/series/65871/ State : success == Summary == CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14200 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/ Known issues Here are the changes found in Patchwork_14200 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#110627]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][7] ([fdo#08]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][9] ([fdo#103167]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#109483]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6792/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (52 -> 43) -- Missing(9): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6792 -> Patchwork_14200 CI-20190529: 20190529 CI_DRM_6792: 87f7792bc3891de3fab4fb64d66a85a66729e3d4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14200: c4d5dbd2cff36d506ce5f84da812b77434e94cfb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c4d5dbd2cff3 drm/i915/execlists: Flush the post-sync breadcrumb write harder == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14200/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for New cdclk values for gen11+
== Series Details == Series: New cdclk values for gen11+ URL : https://patchwork.freedesktop.org/series/65838/ State : success == Summary == CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14194_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14194_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-hang-bsd1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb1/igt@gem_exec_sched...@preempt-hang-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-iclb5/igt@gem_exec_sched...@preempt-hang-bsd1.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-apl8/igt@gem_workarou...@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-apl8/igt@gem_workarou...@suspend-resume-context.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-apl1/igt@kms_big...@yf-tiled-32bpp-rotate-90.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-apl6/igt@kms_big...@yf-tiled-32bpp-rotate-90.html * igt@kms_flip@flip-vs-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-kbl7/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-kbl1/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103167]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103191]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-skl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#102365]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-snb5/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-snb2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@tools_test@tools_test: - shard-glk: [PASS][23] -> [SKIP][24] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-glk4/igt@tools_test@tools_test.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14194/shard-glk2/igt@tools_test@tools_test.html Possible
Re: [Intel-gfx] [PATCH v10 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
Only files are that are modified in this year should be updated. For example. include/drm/i915_mei_hdcp_interface.h - * Copyright © 2017-2018 Intel Corporation + * Copyright © 2017-2019 Intel Corporation > -Original Message- > From: C, Ramalingam > Sent: Tuesday, August 27, 2019 16:23 > To: Winkler, Tomas > Cc: intel-gfx ; dri-devel de...@lists.freedesktop.org>; Sharma, Shashank > ; Daniel Vetter ; Nikula, Jani > > Subject: Re: [PATCH v10 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ > > On 2019-08-27 at 18:32:13 +0530, Winkler, Tomas wrote: > > > > > Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block > > > movement from DDI into transcoder. > > > > In some files needs to bump the copyright to 2019. > Tomas, > > I am not aware when a copyright year needs to be bumped, as copyright year > for many I915 files are not latest. > > Any guidelines here would help me to understand. > > Thanks, > -Ram. > > > > > > > > v10: > > > Review comments from shashank addressed > > > > > > Ramalingam C (6): > > > drm/i915: mei_hdcp: I915 sends ddi index as per ME FW > > > drm: Move port definition back to i915 header > > > drm: Extend I915 mei interface for transcoder info > > > misc/mei/hdcp: Fill transcoder index in port info > > > drm/i915/hdcp: update current transcoder into intel_hdcp > > > drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ > > > > > > drivers/gpu/drm/i915/display/intel_bios.h | 1 + > > > drivers/gpu/drm/i915/display/intel_display.h | 18 ++ > > > .../drm/i915/display/intel_display_types.h| 7 + > > > drivers/gpu/drm/i915/display/intel_dp.c | 3 + > > > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 212 +- > > > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 + > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +- > > > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + > > > drivers/gpu/drm/i915/display/intel_hotplug.h | 1 + > > > drivers/gpu/drm/i915/display/intel_sdvo.h | 1 + > > > drivers/gpu/drm/i915/i915_reg.h | 124 +- > > > drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++-- > > > drivers/misc/mei/hdcp/mei_hdcp.h | 16 +- > > > include/drm/i915_drm.h| 18 -- > > > include/drm/i915_mei_hdcp_interface.h | 29 ++- > > > 16 files changed, 372 insertions(+), 122 deletions(-) > > > > > > -- > > > 2.20.1 > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Only activate i915_active debugobject once
The point of debug_object_activate is to mark we first, only the first,
acquisition. The object then remains active until the last release.
However, we marked up all successful first acquires even though we
allowed concurrent parties to try and acquire the i915_active
simultaneously (serialised by the i915_active.mutex).
Testcase: igt/gem_mmap_gtt/fault-concurrent
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_active.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 48e16ad93bbd..d9d89bde8256 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -92,11 +92,14 @@ static void debug_active_init(struct i915_active *ref)
static void debug_active_activate(struct i915_active *ref)
{
- debug_object_activate(ref, _debug_desc);
+ lockdep_assert_held(>mutex);
+ if (!atomic_read(>count))
+ debug_object_activate(ref, _debug_desc);
}
static void debug_active_deactivate(struct i915_active *ref)
{
+ lockdep_assert_held(>mutex);
debug_object_deactivate(ref, _debug_desc);
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
On 2019-08-27 at 18:32:13 +0530, Winkler, Tomas wrote: > > > Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement > > from DDI into transcoder. > > In some files needs to bump the copyright to 2019. Tomas, I am not aware when a copyright year needs to be bumped, as copyright year for many I915 files are not latest. Any guidelines here would help me to understand. Thanks, -Ram. > > > > > v10: > > Review comments from shashank addressed > > > > Ramalingam C (6): > > drm/i915: mei_hdcp: I915 sends ddi index as per ME FW > > drm: Move port definition back to i915 header > > drm: Extend I915 mei interface for transcoder info > > misc/mei/hdcp: Fill transcoder index in port info > > drm/i915/hdcp: update current transcoder into intel_hdcp > > drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ > > > > drivers/gpu/drm/i915/display/intel_bios.h | 1 + > > drivers/gpu/drm/i915/display/intel_display.h | 18 ++ > > .../drm/i915/display/intel_display_types.h| 7 + > > drivers/gpu/drm/i915/display/intel_dp.c | 3 + > > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > > drivers/gpu/drm/i915/display/intel_hdcp.c | 212 +- > > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 + > > drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +- > > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + > > drivers/gpu/drm/i915/display/intel_hotplug.h | 1 + > > drivers/gpu/drm/i915/display/intel_sdvo.h | 1 + > > drivers/gpu/drm/i915/i915_reg.h | 124 +- > > drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++-- > > drivers/misc/mei/hdcp/mei_hdcp.h | 16 +- > > include/drm/i915_drm.h| 18 -- > > include/drm/i915_mei_hdcp_interface.h | 29 ++- > > 16 files changed, 372 insertions(+), 122 deletions(-) > > > > -- > > 2.20.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
>
>
> On 8/13/2019 8:16 PM, Imre Deak wrote:
> > On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
> > > "DC3CO Off" power well inherits its power domains from
> > > "DC Off" power well, these power domains will disallow
> > > DC3CO when any external displays are connected and at
> > > time of modeset and aux programming.
> > > Renaming "DC Off" power well to "DC5 Off" power well.
> > >
> > > v2: commit log improvement.
> > > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > > to a appropriate place haswell_crtc_enable(). [Imre]
> > > Changed the DC3CO power well enabled call back logic as
> > > recommended in review comments. [Imre]
> > > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > > v5: using udelay() instead of waiting for DC3CO exit status.
> > >
> > > Cc: Jani Nikula
> > > Cc: Imre Deak
> > > Cc: Animesh Manna
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: Anshuman Gupta
> > > ---
> > > .../drm/i915/display/intel_display_power.c| 69 ++-
> > > 1 file changed, 67 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index e2ef202aeeef..c9e92d48cdab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct
> > > drm_i915_private *dev_priv, u32 state)
> > > dev_priv->csr.dc_state = val & mask;
> > > }
> > > -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > > +{
> > > + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > +}
> > > +
> > > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > > +{
> > > + u32 val;
> > > +
> > > + val = I915_READ(DC_STATE_EN);
> > > + val &= ~DC_STATE_DC3CO_STATUS;
> > > + I915_WRITE(DC_STATE_EN, val);
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > + /*
> > > + * Delay of 200us DC3CO Exit time B.Spec 49196
> > > + */
> > > + udelay(200);
> > > +}
> > > +
> > > +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > {
> > > assert_can_enable_dc9(dev_priv);
> > > @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct
> > > drm_i915_private *dev_priv,
> > > gen9_enable_dc5(dev_priv);
> > > }
> > > +static void tgl_dc3co_power_well_enable(struct drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well *power_well)
> >
> > Should be called dc3co_off power well.
> >
> > > +{
> > > + tgl_disallow_dc3co(dev_priv);
> > > +}
> > > +
> > > +static void tgl_dc3co_power_well_disable(struct drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well *power_well)
> > > +{
> > > + if (!dev_priv->psr.sink_psr2_support)
> > > + return;
> >
> > We could end up enabling DC3CO while PSR2 is disabled after disabling
> > a PSR2 capable output, which is against the spec.
> >
> > I'm thinking now that we should have a single dc_off power well and a
> > new interface setting the max allowed DC state (DC3CO, DC5/6).
> Hi Imre,
>
> Could you please comment if below part of new API code set_max_dc_state() is
> ok? with respect to our DC3CO design sync.
>
> static void set_target_dc_state(struct drm_i915_private *dev_priv)
> {
> gen9_dc_off_power_well_disable(dev_priv, NULL);
> }
>
> void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
> {
> bool dc_off_enabled;
> struct i915_power_domains *power_domains = _priv->power_domains;
> /* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
> dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
> TGL_DISP_DC_OFF);
dc_off_enabled can get stale this way until you acquire the lock.
Probably easier to lookup_power_well() and then check its state with the
lock held.
>
> mutex_lock(_domains->lock);
> if (dc_off_enabled) {
> dev_priv->csr.max_dc_state = state;
> } else {
> dev_priv->csr.max_dc_state = state;
> set_target_dc_state(dev_priv);
> }
> mutex_unlock(_domains->lock);
> }
> gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
> register accordingly.
>
> There can be only issue according to me here when "DC off" power well
> is disable (this will happen when we want to set max_dc_state to dc5
> in dc5_idle_thread). In that case we need to manually call
> set_target_dc_state()->gen9_dc_off_power_well_disable().
In that case you could just
Re: [Intel-gfx] [PATCH v10 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
> Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement > from DDI into transcoder. In some files needs to bump the copyright to 2019. > > v10: > Review comments from shashank addressed > > Ramalingam C (6): > drm/i915: mei_hdcp: I915 sends ddi index as per ME FW > drm: Move port definition back to i915 header > drm: Extend I915 mei interface for transcoder info > misc/mei/hdcp: Fill transcoder index in port info > drm/i915/hdcp: update current transcoder into intel_hdcp > drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ > > drivers/gpu/drm/i915/display/intel_bios.h | 1 + > drivers/gpu/drm/i915/display/intel_display.h | 18 ++ > .../drm/i915/display/intel_display_types.h| 7 + > drivers/gpu/drm/i915/display/intel_dp.c | 3 + > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > drivers/gpu/drm/i915/display/intel_hdcp.c | 212 +- > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 + > drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +- > drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + > drivers/gpu/drm/i915/display/intel_hotplug.h | 1 + > drivers/gpu/drm/i915/display/intel_sdvo.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 124 +- > drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++-- > drivers/misc/mei/hdcp/mei_hdcp.h | 16 +- > include/drm/i915_drm.h| 18 -- > include/drm/i915_mei_hdcp_interface.h | 29 ++- > 16 files changed, 372 insertions(+), 122 deletions(-) > > -- > 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
On 8/13/2019 8:16 PM, Imre Deak wrote:
On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 69 ++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e2ef202aeeef..c9e92d48cdab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
-static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+ udelay(200);
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
Should be called dc3co_off power well.
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ if (!dev_priv->psr.sink_psr2_support)
+ return;
We could end up enabling DC3CO while PSR2 is disabled after disabling
a PSR2 capable output, which is against the spec.
I'm thinking now that we should have a single dc_off power well and a
new interface setting the max allowed DC state (DC3CO, DC5/6).
Hi Imre,
Could you please comment if below part of new API code
set_max_dc_state() is ok? with respect to our DC3CO design sync.
static void set_target_dc_state(struct drm_i915_private *dev_priv)
{
gen9_dc_off_power_well_disable(dev_priv, NULL);
}
void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
{
bool dc_off_enabled;
struct i915_power_domains *power_domains =
_priv->power_domains;
/* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
TGL_DISP_DC_OFF);
mutex_lock(_domains->lock);
if (dc_off_enabled) {
dev_priv->csr.max_dc_state = state;
} else {
dev_priv->csr.max_dc_state = state;
set_target_dc_state(dev_priv);
}
mutex_unlock(_domains->lock);
}
gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
register accordingly. There can be only issue according to me here when
"DC off" power well is disable (this will happen when we want to set
max_dc_state to dc5 in dc5_idle_thread). In that case we need to
manually call set_target_dc_state()->gen9_dc_off_power_well_disable().
Thanks,
Anshuman Gupta.
(Right now I think there is also a missing re-enabling of DC3CO when
disabling DC5/6).
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ /*
+* Checking alone DC_STATE_EN is not enough as DC5 power well also
+* allow/disallow DC3CO to make sure both are not enabled at same time
+*/
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) &
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: stall on render flush before writing seqno
== Series Details ==
Series: drm/i915/execlists: stall on render flush before writing seqno
URL : https://patchwork.freedesktop.org/series/65869/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14199
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/
Known issues
Here are the changes found in Patchwork_14199 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#08])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][7] -> [DMESG-WARN][8] ([fdo#106387]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@i915_selftest@live_reset:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-dsi/igt@i915_selftest@live_reset.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-icl-dsi/igt@i915_selftest@live_reset.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][11] ([fdo#110595]) -> [DMESG-WARN][12]
([fdo#110595] / [fdo#111214])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-u2: [INCOMPLETE][13] ([fdo#107713] / [fdo#108840]) ->
[DMESG-WARN][14] ([fdo#110595])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/fi-icl-u2/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (52 -> 44)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6791 -> Patchwork_14199
CI-20190529: 20190529
CI_DRM_6791: 911cf01f441a754e8ee511d4968f711c54e20ed8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14199: 4e569e09404eb7660c687c368be7ea7dea352458 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4e569e09404e drm/i915/execlists: stall on render flush before writing seqno
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14199/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev8)
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev8)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14198
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/
Known issues
Here are the changes found in Patchwork_14198 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live_reset:
- {fi-icl-dsi}: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-dsi/igt@i915_selftest@live_reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/fi-icl-dsi/igt@i915_selftest@live_reset.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][7] ([fdo#110595]) -> [DMESG-WARN][8]
([fdo#110595] / [fdo#111214])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-u2: [INCOMPLETE][9] ([fdo#107713] / [fdo#108840]) ->
[DMESG-WARN][10] ([fdo#110595])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/fi-icl-u2/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Participating hosts (52 -> 44)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6791 -> Patchwork_14198
CI-20190529: 20190529
CI_DRM_6791: 911cf01f441a754e8ee511d4968f711c54e20ed8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14198: 0101914752f70aa1cf5bd030103f38bdfcfd6a91 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0101914752f7 drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
06d9c7f7117c drm/i915/hdcp: update current transcoder into intel_hdcp
41afdc6b33b2 misc/mei/hdcp: Fill transcoder index in port info
20b0b00b2eea drm: Extend I915 mei interface for transcoder info
2a2e8c70055d drm: Move port definition back to i915 header
78ef4b4ab207 drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14198/
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Markup impossible error pointers
== Series Details ==
Series: drm/i915/selftests: Markup impossible error pointers
URL : https://patchwork.freedesktop.org/series/65862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14197
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14197/
Known issues
Here are the changes found in Patchwork_14197 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14197/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
Possible fixes
* igt@i915_selftest@live_reset:
- {fi-icl-dsi}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-dsi/igt@i915_selftest@live_reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14197/fi-icl-dsi/igt@i915_selftest@live_reset.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713] / [fdo#108840]) ->
[DMESG-WARN][6] ([fdo#110595])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6791/fi-icl-u2/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14197/fi-icl-u2/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (52 -> 44)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6791 -> Patchwork_14197
CI-20190529: 20190529
CI_DRM_6791: 911cf01f441a754e8ee511d4968f711c54e20ed8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14197: 993dabeb9a5c805787f22ccaea953234002a8c0a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
993dabeb9a5c drm/i915/selftests: Markup impossible error pointers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14197/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/8] drm/i915/tgl: Guard and warn if more than one eDP panel is present
== Series Details == Series: series starting with [CI,1/8] drm/i915/tgl: Guard and warn if more than one eDP panel is present URL : https://patchwork.freedesktop.org/series/65835/ State : success == Summary == CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14193_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14193_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@i915_suspend@fence-restore-untiled: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl8/igt@i915_susp...@fence-restore-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-skl2/igt@i915_susp...@fence-restore-untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-hsw7/igt@kms_frontbuffer_track...@fbc-stridechange.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-hsw6/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103167]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103191]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-skl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14193/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) [23]:
[Intel-gfx] [PATCH] drm/i915/execlists: Flush the post-sync breadcrumb write harder
Quite rarely we see that the CS completion event fires before the breadcrumb is coherent, which presumably is a result of the CS_STALL not waiting for the post-sync operation. Try following in a DC_FLUSH into the following pipecontrol to see if that makes any difference. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 80a3f1dbb456..48046d445733 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2971,6 +2971,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_DC_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL, 0); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: stall on render flush before writing seqno
Quoting Chris Wilson (2019-08-27 12:54:13)
> Quite rarely we see that the CS completion event fires before the
> breadcrumb is coherent. Try rearranging the breadcrumb write sequence
> such that the CS_STALL is on the post-sync write pipecontrol.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 17 -
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 80a3f1dbb456..669e8bd9f830 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2961,18 +2961,17 @@ static u32 *gen8_emit_fini_breadcrumb(struct
> i915_request *request, u32 *cs)
>
> static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32
> *cs)
> {
> - cs = gen8_emit_ggtt_write_rcs(cs,
> - request->fence.seqno,
> - request->timeline->hwsp_offset,
> - PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> - PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> - PIPE_CONTROL_DC_FLUSH_ENABLE);
> -
> /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl
> */
> cs = gen8_emit_pipe_control(cs,
> - PIPE_CONTROL_FLUSH_ENABLE |
> - PIPE_CONTROL_CS_STALL,
> + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> + PIPE_CONTROL_DC_FLUSH_ENABLE,
> 0);
> + cs = gen8_emit_ggtt_write_rcs(cs,
> + request->fence.seqno,
> + request->timeline->hwsp_offset,
> + PIPE_CONTROL_FLUSH_ENABLE |
Or perhaps we need PIPE_CONTROL_DC_FLUSH_ENABLE here.
I think that might make more sense (replace DC_FLUSH with whatever might
flush the post-sync write).
-Chris
___
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[Intel-gfx] [PATCH] drm/i915/execlists: stall on render flush before writing seqno
Quite rarely we see that the CS completion event fires before the
breadcrumb is coherent. Try rearranging the breadcrumb write sequence
such that the CS_STALL is on the post-sync write pipecontrol.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 80a3f1dbb456..669e8bd9f830 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2961,18 +2961,17 @@ static u32 *gen8_emit_fini_breadcrumb(struct
i915_request *request, u32 *cs)
static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32
*cs)
{
- cs = gen8_emit_ggtt_write_rcs(cs,
- request->fence.seqno,
- request->timeline->hwsp_offset,
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_DC_FLUSH_ENABLE);
-
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
cs = gen8_emit_pipe_control(cs,
- PIPE_CONTROL_FLUSH_ENABLE |
- PIPE_CONTROL_CS_STALL,
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_DC_FLUSH_ENABLE,
0);
+ cs = gen8_emit_ggtt_write_rcs(cs,
+ request->fence.seqno,
+ request->timeline->hwsp_offset,
+ PIPE_CONTROL_FLUSH_ENABLE |
+ PIPE_CONTROL_CS_STALL);
return gen8_emit_fini_breadcrumb_footer(request, cs);
}
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
== Series Details == Series: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support URL : https://patchwork.freedesktop.org/series/65858/ State : success == Summary == CI Bug Log - changes from CI_DRM_6790 -> Patchwork_14196 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14196/ Known issues Here are the changes found in Patchwork_14196 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live_gtt: - fi-glk-dsi: [INCOMPLETE][1] ([fdo#103359] / [k.org#198133]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6790/fi-glk-dsi/igt@i915_selftest@live_gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14196/fi-glk-dsi/igt@i915_selftest@live_gtt.html [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (49 -> 42) -- Additional (1): fi-kbl-7500u Missing(8): fi-kbl-soraka fi-cml-u2 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6790 -> Patchwork_14196 CI-20190529: 20190529 CI_DRM_6790: be6f240038f2ed178452504af00b0e940045542e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14196: 5d004c02a7cca1ff75591913da6fac493afa96f3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5d004c02a7cc drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14196/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
>From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_data.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
v4:
Few optimizations in the coding [Shashank]
v5:
Fixed alignment in macro definition in i915_reg.h [Shashank]
unused variables "reg" is removed.
v6:
Configuring the transcoder at compute_config.
transcoder is used instead of pipe in macros.
Rebased.
v7:
transcoder is cached at intel_hdcp
hdcp_port_data is configured with transcoder index asper ME FW.
v8:
s/trans/cpu_transcoder
s/tc/cpu_transcoder
v9:
rep_ctl is prepared for TCD too.
return moved into deault of rep_ctl prepare function [Shashank]
Signed-off-by: Ramalingam C
Reviewed-by: Shashank Sharma
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 152 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 124 --
3 files changed, 221 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 3591b8f7fe30..3de88a21d0ed 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -18,6 +18,7 @@
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -105,24 +106,20 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(PORT_HDCP_STATUS(port));
- return reg & HDCP_STATUS_ENC;
+ return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
+ HDCP_STATUS_ENC;
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(HDCP2_STATUS_DDI(port));
- return reg & LINK_ENCRYPTION_STATUS;
+ return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS;
}
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
@@ -253,9 +250,29 @@ static int intel_write_sha_text(struct drm_i915_private
*dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- enum port port = intel_dig_port->base.port;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case TRANSCODER_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case TRANSCODER_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ case TRANSCODER_D:
+ return HDCP_TRANSD_REP_PRESENT |
+ HDCP_TRANSD_SHA1_M0;
+ default:
+ DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder);
+ return -EINVAL;
+ }
+ }
+
switch (port) {
case PORT_A:
return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
@@ -268,18 +285,20 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port
*intel_dig_port)
case PORT_E:
return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
default:
- break;
+ DRM_ERROR("Unknown port %d\n", port);
+ return -EINVAL;
}
- DRM_ERROR("Unknown port %d\n", port);
- return -EINVAL;
}
static
-int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+int intel_hdcp_validate_v_prime(struct intel_connector *connector,
[Intel-gfx] [PATCH v10 1/6] drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
Hence expose the enum mei_fw_ddi to I915 through
i915_mei_interface.h.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +-
drivers/misc/mei/hdcp/mei_hdcp.c | 34 ---
drivers/misc/mei/hdcp/mei_hdcp.h | 12
include/drm/i915_mei_hdcp_interface.h | 16 +--
4 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6ec5ceeab601..534832f435dc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1749,13 +1749,26 @@ static const struct component_ops
i915_hdcp_component_ops = {
.unbind = i915_hdcp_component_unbind,
};
+static inline
+enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port)
+{
+ switch (port) {
+ case PORT_A:
+ return MEI_DDI_A;
+ case PORT_B ... PORT_F:
+ return (enum mei_fw_ddi)port;
+ default:
+ return MEI_DDI_INVALID_PORT;
+ }
+}
+
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
struct intel_hdcp *hdcp = >hdcp;
struct hdcp_port_data *data = >port_data;
- data->port = connector->encoder->port;
+ data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port);
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index c681f6fab342..3638c77eba26 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -27,18 +27,6 @@
#include "mei_hdcp.h"
-static inline u8 mei_get_ddi_index(enum port port)
-{
- switch (port) {
- case PORT_A:
- return MEI_DDI_A;
- case PORT_B ... PORT_F:
- return (u8)port;
- default:
- return MEI_DDI_INVALID_PORT;
- }
-}
-
/**
* mei_hdcp_initiate_session() - Initiate a Wired HDCP2.2 Tx Session in ME FW
* @dev: device corresponding to the mei_cl_device
@@ -69,7 +57,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
hdcp_port_data *data,
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
session_init_in.port.integrated_port_type = data->port_type;
- session_init_in.port.physical_port = mei_get_ddi_index(data->port);
+ session_init_in.port.physical_port = (u8)data->fw_ddi;
session_init_in.protocol = data->protocol;
byte = mei_cldev_send(cldev, (u8 *)_init_in,
@@ -138,7 +126,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
verify_rxcert_in.port.integrated_port_type = data->port_type;
- verify_rxcert_in.port.physical_port = mei_get_ddi_index(data->port);
+ verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
verify_rxcert_in.cert_rx = rx_cert->cert_rx;
memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
@@ -208,7 +196,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
hdcp_port_data *data,
send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
send_hprime_in.port.integrated_port_type = data->port_type;
- send_hprime_in.port.physical_port = mei_get_ddi_index(data->port);
+ send_hprime_in.port.physical_port = (u8)data->fw_ddi;
memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
HDCP_2_2_H_PRIME_LEN);
@@ -265,7 +253,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
hdcp_port_data *data,
WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
pairing_info_in.port.integrated_port_type = data->port_type;
- pairing_info_in.port.physical_port = mei_get_ddi_index(data->port);
+ pairing_info_in.port.physical_port = (u8)data->fw_ddi;
memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
HDCP_2_2_E_KH_KM_LEN);
@@ -323,7 +311,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
lc_init_in.port.integrated_port_type = data->port_type;
- lc_init_in.port.physical_port = mei_get_ddi_index(data->port);
+ lc_init_in.port.physical_port = (u8)data->fw_ddi;
byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
if (byte < 0) {
@@ -378,7 +366,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
hdcp_port_data *data,
WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
[Intel-gfx] [PATCH v10 3/6] drm: Extend I915 mei interface for transcoder info
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_tc and add as a member into
the struct hdcp_port_data.
v2:
Typo in commit msg is fixed [Shashank]
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
include/drm/i915_mei_hdcp_interface.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/i915_mei_hdcp_interface.h
b/include/drm/i915_mei_hdcp_interface.h
index a97acf1c9710..0de629bf2f62 100644
--- a/include/drm/i915_mei_hdcp_interface.h
+++ b/include/drm/i915_mei_hdcp_interface.h
@@ -54,9 +54,21 @@ enum mei_fw_ddi {
MEI_DDI_RANGE_END = MEI_DDI_A,
};
+enum mei_fw_tc {
+ MEI_INVALID_TRANSCODER = 0x00, /* Invalid transcoder type */
+ MEI_TC_EDP, /* Transcoder for eDP */
+ MEI_TC_DSI0,/* Transcoder for DSI0 */
+ MEI_TC_DSI1,/* Transcoder for DSI1 */
+ MEI_TC_A = 0x10,/* Transcoder TCA */
+ MEI_TC_B, /* Transcoder TCB */
+ MEI_TC_C, /* Transcoder TCC */
+ MEI_TC_D/* Transcoder TCD */
+};
+
/**
* struct hdcp_port_data - intel specific HDCP port data
* @fw_ddi: ddi index as per ME FW
+ * @fw_tc: transcoder index as per ME FW
* @port_type: HDCP port type as per ME FW classification
* @protocol: HDCP adaptation as per ME FW
* @k: No of streams transmitted on a port. Only on DP MST this is != 1
@@ -69,6 +81,7 @@ enum mei_fw_ddi {
*/
struct hdcp_port_data {
enum mei_fw_ddi fw_ddi;
+ enum mei_fw_tc fw_tc;
u8 port_type;
u8 protocol;
u16 k;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 4/6] misc/mei/hdcp: Fill transcoder index in port info
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME FW from hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
Reviewed-by: Shashank Sharma
---
drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
drivers/misc/mei/hdcp/mei_hdcp.h | 4 +++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 3638c77eba26..93027fd96c71 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -58,6 +58,7 @@ mei_hdcp_initiate_session(struct device *dev, struct
hdcp_port_data *data,
session_init_in.port.integrated_port_type = data->port_type;
session_init_in.port.physical_port = (u8)data->fw_ddi;
+ session_init_in.port.attached_transcoder = (u8)data->fw_tc;
session_init_in.protocol = data->protocol;
byte = mei_cldev_send(cldev, (u8 *)_init_in,
@@ -127,6 +128,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
verify_rxcert_in.port.integrated_port_type = data->port_type;
verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
+ verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
verify_rxcert_in.cert_rx = rx_cert->cert_rx;
memcpy(verify_rxcert_in.r_rx, _cert->r_rx, HDCP_2_2_RRX_LEN);
@@ -197,6 +199,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct
hdcp_port_data *data,
send_hprime_in.port.integrated_port_type = data->port_type;
send_hprime_in.port.physical_port = (u8)data->fw_ddi;
+ send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
HDCP_2_2_H_PRIME_LEN);
@@ -254,6 +257,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct
hdcp_port_data *data,
pairing_info_in.port.integrated_port_type = data->port_type;
pairing_info_in.port.physical_port = (u8)data->fw_ddi;
+ pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
HDCP_2_2_E_KH_KM_LEN);
@@ -312,6 +316,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
lc_init_in.port.integrated_port_type = data->port_type;
lc_init_in.port.physical_port = (u8)data->fw_ddi;
+ lc_init_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)_init_in, sizeof(lc_init_in));
if (byte < 0) {
@@ -367,6 +372,7 @@ mei_hdcp_verify_lprime(struct device *dev, struct
hdcp_port_data *data,
verify_lprime_in.port.integrated_port_type = data->port_type;
verify_lprime_in.port.physical_port = (u8)data->fw_ddi;
+ verify_lprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
HDCP_2_2_L_PRIME_LEN);
@@ -424,6 +430,7 @@ static int mei_hdcp_get_session_key(struct device *dev,
get_skey_in.port.integrated_port_type = data->port_type;
get_skey_in.port.physical_port = (u8)data->fw_ddi;
+ get_skey_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)_skey_in, sizeof(get_skey_in));
if (byte < 0) {
@@ -488,6 +495,7 @@ mei_hdcp_repeater_check_flow_prepare_ack(struct device *dev,
verify_repeater_in.port.integrated_port_type = data->port_type;
verify_repeater_in.port.physical_port = (u8)data->fw_ddi;
+ verify_repeater_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
HDCP_2_2_RXINFO_LEN);
@@ -558,6 +566,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in.port.integrated_port_type = data->port_type;
verify_mprime_in.port.physical_port = (u8)data->fw_ddi;
+ verify_mprime_in.port.attached_transcoder = (u8)data->fw_tc;
memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
HDCP_2_2_MPRIME_LEN);
@@ -619,6 +628,7 @@ static int mei_hdcp_enable_authentication(struct device
*dev,
enable_auth_in.port.integrated_port_type = data->port_type;
enable_auth_in.port.physical_port = (u8)data->fw_ddi;
+ enable_auth_in.port.attached_transcoder = (u8)data->fw_tc;
enable_auth_in.stream_type = data->streams[0].stream_type;
byte = mei_cldev_send(cldev, (u8 *)_auth_in,
@@ -673,6 +683,7 @@ mei_hdcp_close_session(struct device *dev, struct
hdcp_port_data *data)
session_close_in.port.integrated_port_type = data->port_type;
session_close_in.port.physical_port = (u8)data->fw_ddi;
+ session_close_in.port.attached_transcoder = (u8)data->fw_tc;
byte = mei_cldev_send(cldev, (u8 *)_close_in,
sizeof(session_close_in));
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h b/drivers/misc/mei/hdcp/mei_hdcp.h
[Intel-gfx] [PATCH v10 5/6] drm/i915/hdcp: update current transcoder into intel_hdcp
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
v3:
comment is added for fw_ddi init for gen12+ [Shashank]
only hdcp capable transcoder is translated into fw_tc [Shashank]
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
.../drm/i915/display/intel_display_types.h| 7 +++
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 47 ++-
drivers/gpu/drm/i915/display/intel_hdcp.h | 3 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++
5 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 96514dcc7812..61277a87dbe7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -388,6 +388,13 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ /*
+* HDCP register access for gen12+ need the transcoder associated.
+* Transcoder attached to the connector could be changed at modeset.
+* Hence caching the transcoder here.
+*/
+ enum transcoder cpu_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 23908da1cd5d..e8471689f785 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2248,6 +2248,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
+ intel_hdcp_transcoder_config(intel_connector,
+pipe_config->cpu_transcoder);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 534832f435dc..3591b8f7fe30 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1762,13 +1762,58 @@ enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port
port)
}
}
+static inline
+enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
+{
+ switch (cpu_transcoder) {
+ case TRANSCODER_A ... TRANSCODER_D:
+ return (enum mei_fw_tc)(cpu_transcoder | 0x10);
+ default: /* eDP, DSI TRANSCODERS are non HDCP capable */
+ return MEI_INVALID_TRANSCODER;
+ }
+}
+
+void intel_hdcp_transcoder_config(struct intel_connector *connector,
+ enum transcoder cpu_transcoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = >hdcp;
+
+ if (!hdcp->shim)
+ return;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ mutex_lock(>mutex);
+ hdcp->cpu_transcoder = cpu_transcoder;
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ mutex_unlock(>mutex);
+ }
+}
+
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
struct hdcp_port_data *data = >port_data;
+ struct intel_crtc *crtc;
+
+ if (INTEL_GEN(dev_priv) < 12) {
+ data->fw_ddi =
+ intel_get_mei_fw_ddi_index(connector->encoder->port);
+ } else {
+ crtc = to_intel_crtc(connector->base.state->crtc);
+ if (crtc) {
+ hdcp->cpu_transcoder = crtc->config->cpu_transcoder;
+ data->fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ }
+ /*
+* As per ME FW API expectation, for GEN 12+, fw_ddi is filled
+* with INVALID PORT.
+*/
+ data->fw_ddi = intel_get_mei_fw_ddi_index(PORT_NONE);
+ }
- data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port);
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 59a2b40405cc..41c1053d9e38 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -16,10 +16,13 @@ struct drm_i915_private;
struct intel_connector;
struct intel_hdcp_shim;
enum port;
+enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
+void
[Intel-gfx] [PATCH v10 2/6] drm: Move port definition back to i915 header
We dont need the definition of the enum port outside I915, anymore.
Hence move enum port definition into I915 driver itself.
v2:
intel_display.h is included in intel_hdcp.h
v3:
enum port is declared in headers.
v4:
commit msg is rephrased.
Signed-off-by: Ramalingam C
Reviewed-by: Jani Nikula
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display/intel_display.h | 18 ++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.h| 1 +
drivers/gpu/drm/i915/display/intel_hdmi.h| 1 +
drivers/gpu/drm/i915/display/intel_hotplug.h | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.h| 1 +
include/drm/i915_drm.h | 18 --
8 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
b/drivers/gpu/drm/i915/display/intel_bios.h
index 4969189e620f..4c6e56a3940a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,7 @@
#include
struct drm_i915_private;
+enum port;
enum intel_backlight_type {
INTEL_BACKLIGHT_PMIC,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index e57e6969051d..40610d51327e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -182,6 +182,24 @@ enum plane_id {
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
+enum port {
+ PORT_NONE = -1,
+
+ PORT_A = 0,
+ PORT_B,
+ PORT_C,
+ PORT_D,
+ PORT_E,
+ PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
+
+ I915_MAX_PORTS
+};
+
+#define port_name(p) ((p) + 'A')
+
/*
* Ports identifier referenced from other drivers.
* Expected to remain stable over time
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..e01d1f89409d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -13,6 +13,7 @@
#include "i915_reg.h"
enum pipe;
+enum port;
struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 13555b054930..59a2b40405cc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -15,6 +15,7 @@ struct drm_connector_state;
struct drm_i915_private;
struct intel_connector;
struct intel_hdcp_shim;
+enum port;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 106c2e0bc3c9..cf1ea5427639 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -23,6 +23,7 @@ struct intel_crtc_state;
struct intel_hdmi;
struct drm_connector_state;
union hdmi_infoframe;
+enum port;
void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h
b/drivers/gpu/drm/i915/display/intel_hotplug.h
index b0cd447b7fbc..087b5f57b321 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -13,6 +13,7 @@
struct drm_i915_private;
struct intel_connector;
struct intel_encoder;
+enum port;
void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h
b/drivers/gpu/drm/i915/display/intel_sdvo.h
index c9e05bcdd141..a66f224aa17d 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.h
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
@@ -14,6 +14,7 @@
struct drm_i915_private;
enum pipe;
+enum port;
bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t sdvo_reg, enum pipe *pipe);
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 23274cf92712..6722005884db 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -100,22 +100,4 @@ extern struct resource intel_graphics_stolen_res;
#define INTEL_GEN11_BSM_DW10xc4
#define INTEL_BSM_MASK (-(1u << 20))
-enum port {
- PORT_NONE = -1,
-
- PORT_A = 0,
- PORT_B,
- PORT_C,
- PORT_D,
- PORT_E,
- PORT_F,
- PORT_G,
- PORT_H,
- PORT_I,
-
- I915_MAX_PORTS
-};
-
-#define port_name(p) ((p) + 'A')
-
#endif /* _I915_DRM_H_ */
--
2.20.1
___
Intel-gfx mailing list
[Intel-gfx] [PATCH v10 0/6] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+
Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement from DDI into transcoder. v10: Review comments from shashank addressed Ramalingam C (6): drm/i915: mei_hdcp: I915 sends ddi index as per ME FW drm: Move port definition back to i915 header drm: Extend I915 mei interface for transcoder info misc/mei/hdcp: Fill transcoder index in port info drm/i915/hdcp: update current transcoder into intel_hdcp drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ drivers/gpu/drm/i915/display/intel_bios.h | 1 + drivers/gpu/drm/i915/display/intel_display.h | 18 ++ .../drm/i915/display/intel_display_types.h| 7 + drivers/gpu/drm/i915/display/intel_dp.c | 3 + drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_hdcp.c | 212 +- drivers/gpu/drm/i915/display/intel_hdcp.h | 4 + drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + drivers/gpu/drm/i915/display/intel_hotplug.h | 1 + drivers/gpu/drm/i915/display/intel_sdvo.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 124 +- drivers/misc/mei/hdcp/mei_hdcp.c | 45 ++-- drivers/misc/mei/hdcp/mei_hdcp.h | 16 +- include/drm/i915_drm.h| 18 -- include/drm/i915_mei_hdcp_interface.h | 29 ++- 16 files changed, 372 insertions(+), 122 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
On Tue, 27 Aug 2019, "Nautiyal, Ankit K" wrote: > From: Ankit Nautiyal > > Currently, the transcoder port sync feature is not available, due to > which the 5K-tiled dual DP monitors experience corruption when > 2560x2880 mode is applied for both of the tiled DP connectors. > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97244 > > There is a patch series to enable transcode port sync feature for > tiled display for ICL+, which is under review: > https://patchwork.kernel.org/project/intel-gfx/list/?series=137339 > > For the older platforms, we need to remove the 2560x2880 mode to avoid > a possibility of userspace choosing 2560x2880 mode for both tiled > displays, resulting in corruption. > > This patch prunes 2560x2880 mode for one of the tiled DP connector. > Since both the tiled DP connectors have different tile_h_loc and > tile_v_loc, the tiled connector with tile_h_loc and tile_v_loc as '0', > is chosen, for which the given resolution is removed. > > Signed-off-by: Ankit Nautiyal > CC: Manasi Navare > --- > drivers/gpu/drm/i915/display/intel_dp.c | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 5c45a3b..aa43a3b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -564,6 +564,17 @@ intel_dp_mode_valid(struct drm_connector *connector, > if (mode->flags & DRM_MODE_FLAG_DBLCLK) > return MODE_H_ILLEGAL; > > + /* > + * For 5K tiled dual DP monitors, dual-DP sync is not yet supported. > + * This results in display sync issues, when both tiled connectors run > + * on 2560x2880 resolution. Therefore prune the 2560x2880 mode on one > + * of the tiled connector, to avoid such a case. > + */ > + if (connector->has_tile && > + (connector->tile_h_loc == 0 && connector->tile_v_loc == 0) && > + (mode->hdisplay == 2560 && mode->vdisplay == 2880)) > + return MODE_PANEL; > + This assumes all tiled cases with specific resolutions fail. You don't know that. You only know this fails on a specific display. Instead of coming up with various rules on tiles and resolutions that match the display (but might *also* match any number of *other* displays!), you need to actually identify and match that specific display instead. There are two ways to add display specific quirks: based on EDID (edid_quirk_list in drm_edid.c) and based on DPCD (dpcd_quirk_list in drm_dp_helper.c). You identify the display, and then prune the modes that require port sync to work, for *that* display. Blanket filters like this are a no-go. BR, Jani. > return MODE_OK; > } -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_data.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
v4:
Few optimizations in the coding [Shashank]
v5:
Fixed alignment in macro definition in i915_reg.h [Shashank]
unused variables "reg" is removed.
v6:
Configuring the transcoder at compute_config.
transcoder is used instead of pipe in macros.
Rebased.
v7:
transcoder is cached at intel_hdcp
hdcp_port_data is configured with transcoder index asper ME FW.
v8:
s/trans/cpu_transcoder
s/tc/cpu_transcoder
Signed-off-by: Ramalingam C
Reviewed-by: Shashank Sharma [v5]
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 148 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 124 --
3 files changed, 219 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1e5548833e8f..e2084403db27 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -18,6 +18,7 @@
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -105,24 +106,20 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(PORT_HDCP_STATUS(port));
- return reg & HDCP_STATUS_ENC;
+ return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
+ HDCP_STATUS_ENC;
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline
+bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
- u32 reg;
-
- reg = I915_READ(HDCP2_STATUS_DDI(port));
- return reg & LINK_ENCRYPTION_STATUS;
+ return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS;
}
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
@@ -253,9 +250,28 @@ static int intel_write_sha_text(struct drm_i915_private
*dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, enum port port)
{
- enum port port = intel_dig_port->base.port;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case TRANSCODER_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case TRANSCODER_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ /* FIXME: Add a case for PIPE_D */
+ default:
+ DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder);
+ break;
+ }
+ return -EINVAL;
It doesn't make sense to have this return statement along sitting here,
it should be up in with the default case; in place of break.
+ }
+
switch (port) {
case PORT_A:
return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
@@ -268,18 +284,21 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port
*intel_dig_port)
case PORT_E:
return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
default:
+ DRM_ERROR("Unknown port %d\n", port);
break;
}
- DRM_ERROR("Unknown port %d\n", port);
return -EINVAL;
}
static
-int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+int intel_hdcp_validate_v_prime(struct
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Markup impossible error pointers
On 27/08/2019 10:49, Chris Wilson wrote: If we create a new live_context() we should have a mapping for each engine. Document that assumption with an assertion. Reported-by: Dan Carpenter Signed-off-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
== Series Details == Series: drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors URL : https://patchwork.freedesktop.org/series/65845/ State : success == Summary == CI Bug Log - changes from CI_DRM_6787 -> Patchwork_14195 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/ Known issues Here are the changes found in Patchwork_14195 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6787/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 Participating hosts (31 -> 43) -- Additional (17): fi-hsw-4770r fi-cml-u2 fi-icl-u4 fi-skl-gvtdvm fi-hsw-peppy fi-glk-dsi fi-icl-u2 fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-kbl-guc fi-whl-u fi-cfl-8109u fi-skl-iommu fi-bsw-kefka fi-skl-lmem fi-icl-guc Missing(5): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-icl-u3 fi-icl-y Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6787 -> Patchwork_14195 CI-20190529: 20190529 CI_DRM_6787: 63ed0eb50431f1428ab0ced810f8e438945405fd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5150: a4e8217bcdfef9bb523f26a9084bbf615a6e8abb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14195: 0a60b1119e920d54254ab2985eefa717f6bcae09 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0a60b1119e92 drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14195/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
