[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details ==
Series: series starting with [1/2] drm/connector: Share with non-atomic drivers
the function to get the single encoder
URL : https://patchwork.freedesktop.org/series/66547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14365
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/
Known issues
Here are the changes found in Patchwork_14365 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][3] ([fdo#103927] / [fdo#111381]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [DMESG-WARN][5] ([fdo#105128] / [fdo#107139]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [INCOMPLETE][11] ([fdo#111514]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6874 -> Patchwork_14365
CI-20190529: 20190529
CI_DRM_6874: f9ee689ff55489da8db3cd5ddad533967c07561f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14365: cb40462fdc864dcd4a7a0461a32dad8a9a4924fa @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cb40462fdc86 drm/connector: Allow max possible encoders to attach to a connector
bbd3d29d2b47 drm/connector: Share with non-atomic drivers the function to get
the single encoder
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14365/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details == Series: series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66547/ State : warning == Summary == $ dim checkpatch origin/drm-tip bbd3d29d2b47 drm/connector: Share with non-atomic drivers the function to get the single encoder cb40462fdc86 drm/connector: Allow max possible encoders to attach to a connector -:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'connector' - possible side-effects? #491: FILE: include/drm/drm_connector.h:1612: +#define drm_connector_for_each_possible_encoder(connector, encoder) \ + drm_for_each_encoder_mask(encoder, (connector)->dev, \ + (connector)->possible_encoders) total: 0 errors, 0 warnings, 1 checks, 388 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Use GT parked for estimating RC6 while asleep (rev3)
== Series Details ==
Series: drm/i915/pmu: Use GT parked for estimating RC6 while asleep (rev3)
URL : https://patchwork.freedesktop.org/series/56583/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14364
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/
Known issues
Here are the changes found in Patchwork_14364 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
* igt@vgem_basic@unload:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-icl-u3/igt@vgem_ba...@unload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-icl-u3/igt@vgem_ba...@unload.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [DMESG-WARN][9] ([fdo#105128] / [fdo#107139]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [INCOMPLETE][15] ([fdo#111514]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6874/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14364/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6874 -> Patchwork_14364
CI-20190529: 20190529
CI_DRM_6874: f9ee689ff55489da8db3cd5ddad533967c07561f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14364: 004d0ffa224bd6a4c23026177ca012a1a9b89545 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
004d0ffa224b
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Skip busyness sampling when and where not needed
== Series Details == Series: drm/i915/pmu: Skip busyness sampling when and where not needed URL : https://patchwork.freedesktop.org/series/66541/ State : success == Summary == CI Bug Log - changes from CI_DRM_6872_full -> Patchwork_14363_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14363_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +19 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb7/igt@gem_exec_sched...@in-order-bsd2.html * igt@gem_exec_schedule@preempt-self-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb6/igt@gem_exec_sched...@preempt-self-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb4/igt@gem_exec_sched...@preempt-self-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl1/igt@kms_fbcon_...@psr-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-skl1/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html Possible fixes * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][19] ([fdo#111325]) -> [PASS][20] +9 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [SKIP][21] ([fdo#109276]) -> [PASS][22] +19 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_pwrite@big-cpu-forwards: - shard-iclb: [INCOMPLETE][23] ([fdo#107713] / [fdo#109100]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb4/igt@gem_pwr...@big-cpu-forwards.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/shard-iclb5/igt@gem_pwr...@big-cpu-forwards.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][25]
[Intel-gfx] [PATCH v6 7/7] drm/i915/dp: Attach HDR metadata property to DP connector
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index abbf1d5c54c4..4084b06fcbfc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6539,6 +6539,11 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
intel_attach_colorspace_property(connector);
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
+ drm_object_attach_property(>base,
+
connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
+
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/7] drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp function.
If the output colorspace requires vsc sdp or output format is YCbCr 4:2:0,
it uses MSA with VSC SDP.
As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of
Color Encoding Format and Content Color Gamut] while sending
BT.2020 Colorimetry signals we should program MSA MISC1 fields which
indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
v2: Remove useless parentheses
v3: Addressed review comments from Ville
- In order to checking output format and output colorspace on
intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state struct
value.
- Remove a pointless variable.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++--
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 29 ++-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
4 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 98d69febd8e3..8dc030650801 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1737,11 +1737,12 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
/*
* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
* of Color Encoding Format and Content Color Gamut] while sending
-* YCBCR 420 signals we should program MSA MISC1 fields which
-* indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
+* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
*/
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ if (intel_dp_needs_vsc_sdp(crtc_state))
temp |= TRANS_MSA_USE_VSC_SDP;
+
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..4108570907d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -971,6 +971,9 @@ struct intel_crtc_state {
/* Output format RGB/YCBCR etc */
enum intel_output_format output_format;
+ /* Output colorspace sRGB/BT.2020 etc */
+ u32 output_colorspace;
+
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a2a0214f771a..3a8aef1c6036 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2187,6 +2187,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = true;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ pipe_config->output_colorspace = intel_conn_state->base.colorspace;
+
if (lspcon->active)
lspcon_ycbcr420_config(_connector->base, pipe_config);
else
@@ -4448,6 +4450,31 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
return 0;
}
+bool
+intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state)
+{
+ /*
+* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+* of Color Encoding Format and Content Color Gamut], in order to
+* sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return true;
+
+ switch (crtc_state->output_colorspace) {
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
static void
intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
@@ -4576,7 +4603,7 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+ if (!intel_dp_needs_vsc_sdp(crtc_state))
return;
intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
diff --git
[Intel-gfx] [CI RESEND] drm/i915: convert device info num_pipes to pipe_mask
Replace device info number of pipes with a bit mask of available
pipes. This will prove handy in the future. There's still a bunch of
future work to do to actually allow a non-consecutive mask of pipes, but
it's a start. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 24
drivers/gpu/drm/i915/intel_device_info.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 84fb0245cf62..bf600888b3f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2188,9 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define GT_FREQUENCY_MULTIPLIER 50
#define GEN9_FREQ_SCALER 3
-#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
+#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
-#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
static inline bool intel_vtd_active(void)
{
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..698116276441 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -147,7 +147,7 @@
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_overlay = 1, \
.display.cursor_needs_physical = 1, \
.display.overlay_needs_physical = 1, \
@@ -165,7 +165,7 @@
#define I845_FEATURES \
GEN(2), \
- .num_pipes = 1, \
+ .pipe_mask = BIT(PIPE_A), \
.display.has_overlay = 1, \
.display.overlay_needs_physical = 1, \
.display.has_gmch = 1, \
@@ -203,7 +203,7 @@ static const struct intel_device_info intel_i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.engine_mask = BIT(RCS0), \
@@ -287,7 +287,7 @@ static const struct intel_device_info intel_pineview_m_info
= {
#define GEN4_FEATURES \
GEN(4), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
@@ -337,7 +337,7 @@ static const struct intel_device_info intel_gm45_info = {
#define GEN5_FEATURES \
GEN(5), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_snoop = true, \
@@ -363,7 +363,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
#define GEN6_FEATURES \
GEN(6), \
- .num_pipes = 2, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -411,7 +411,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .num_pipes = 3, \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -462,7 +462,7 @@ static const struct intel_device_info
intel_ivybridge_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .num_pipes = 0, /* legal, last one wins */
+ .pipe_mask = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -470,7 +470,7 @@ static const struct intel_device_info intel_valleyview_info
= {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .num_pipes = 2,
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_rps = true,
@@ -560,7 +560,7 @@ static const struct intel_device_info
intel_broadwell_gt3_info = {
static const struct intel_device_info intel_cherryview_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .num_pipes = 3,
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
.display.has_hotplug = 1,
.is_lp = 1,
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -631,7 +631,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.is_lp = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .num_pipes = 3, \
+
[Intel-gfx] [PATCH v6 1/7] drm/i915/dp: Extend program of VSC Header and DB for Colorimetry Format
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it adds an argument
of drm_connector_state type.
Setup VSC header and data block in function intel_dp_setup_vsc_sdp for
pixel encoding / colorimetry format as per dp 1.4a spec, section 2.2.5.7.1,
table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120: VSC SDP Payload for DB16 through DB18.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 -
drivers/gpu/drm/i915/display/intel_dp.c | 68
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
4 files changed, 60 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..98d69febd8e3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3623,7 +3623,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
+ intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index f4ddde171655..409544e0e2f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -526,8 +526,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
enum link_m_n_set m_n);
-void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d09133a958e1..a2a0214f771a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4449,8 +4449,9 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
}
static void
-intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct dp_sdp vsc_sdp = {};
@@ -4471,13 +4472,55 @@ intel_pixel_encoding_setup_vsc(struct intel_dp
*intel_dp,
*/
vsc_sdp.sdp_header.HB3 = 0x13;
- /*
-* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
-* DB16[3:0] DP 1.4a spec, Table 2-120
-*/
- vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ /* RGB: DB16[7:4] = 0h */
+ break;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc_sdp.db[16] |= 0x1;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc_sdp.db[16] |= 0x2;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc_sdp.db[16] |= 0x3;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc_sdp.db[16] |= 0x4;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc_sdp.db[16] |= 0x5;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc_sdp.db[16] |= 0x6;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc_sdp.db[16] |= 0x7;
+ break;
+ case
[Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
static HDR metadata. The HDR Metadata will be provided by userspace
compositors, based on blending policies and passed to the driver through
a blob property.
Because each of GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet, it adds and uses different register
size.
Setup Infoframe SDP header and data block in function
intel_dp_setup_hdr_metadata_infoframe_sdp for HDR Static Metadata as per
dp 1.4 spec and CTA-861-F spec.
As per DP 1.4 spec, 2.2.2.5 SDP Formats. It enables Dynamic Range and
Mastering Infoframe for HDR content, which is defined in CTA-861-F spec.
According to DP 1.4 spec and CEA-861-F spec Table 5, in order to transmit
static HDR metadata, we have to use Non-audio INFOFRAME SDP v1.3.
++---+
| [ Packet Type Value ] | [ Packet Type ] |
++---+
| 80h + Non-audio INFOFRAME Type | CEA-861-F Non-audio INFOFRAME |
++---+
| [Transmission Timing] |
++
| As per CEA-861-F for INFOFRAME, including CEA-861.3 within |
| which Dynamic Range and Mastering INFOFRAME are defined|
++
v2: Add a missed blank line after function declaration.
v3: Remove not handled return values from
intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma]
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 89
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
3 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8dc030650801..306f6f9f0204 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3625,6 +3625,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7fe22b37474d..abbf1d5c54c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4599,6 +4599,83 @@ intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
crtc_state, DP_SDP_VSC, _sdp, sizeof(vsc_sdp));
}
+static void
+intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
+ struct dp_sdp infoframe_sdp = {};
+ struct hdmi_drm_infoframe drm_infoframe = {};
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+ int ret;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(_infoframe, conn_state);
+ if (ret) {
+ DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+ return;
+ }
+
+ len = hdmi_drm_infoframe_pack_only(_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Packet ID, 00h for non-Audio INFOFRAME */
+ infoframe_sdp.sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87,
+*/
+ infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
+ /*
+* Least Significant Eight Bits of (Data Byte
[Intel-gfx] [PATCH v6 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b1da2b06263a..2b0ffc0afb74 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9188a0b53538..2dbaa49f5c74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,6 +11688,7 @@ enum skl_power_gate {
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
#endif /* _I915_REG_H_ */
--
2.22.0
___
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Re: [Intel-gfx] [PATCH v7 04/11] drm: revocation check at drm subsystem
> -Original Message- > From: Wentland, Harry > Sent: Wednesday, September 11, 2019 8:16 PM > To: Ramalingam C ; intel- > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; > daniel.vet...@intel.com > Cc: gwan-gyeong@intel.com; Kumar, Ranjeet > ; Deucher, Alexander > ; Lakha, Bhawanpreet > > Subject: Re: [PATCH v7 04/11] drm: revocation check at drm subsystem > > Adding a couple AMD guys. > > I know this is already merged but I have a few questions after some internal > discussions. > > On 2019-05-07 12:27 p.m., Ramalingam C wrote: > > On every hdcp revocation check request SRM is read from fw file > > /lib/firmware/display_hdcp_srm.bin > > > > According to section 5 of the HDCP 2.3 spec [1] a device compliant with HDCP > 2.0 and higher must be capable of storing and updating the SRM in non- > volatile memory. Section 5.2 describes how this SRM needs to be updated > when a new version is served alongside protected content. > > Isn't /lib/firmware intended for static firmware making updates to the folder > problematic for anyone but the system's package maintainer? I've heard /lib > might even be treated as read-only in certain environments. > This would mean it'd be impossible to support HDCP 2.x on those systems. > > Wouldn't it be easier to provide a sysfs entry for SRM that allows userspace > (e.g. system startup/shutdown scripts) to (a) retrieve the SRM from the > HDCP implementation for non-volatile storage and (b) to pass the SRM to the > HDCP implementation for revocation checking? Also, IIRC, for level 1 support, I think the srm parsing has to happen on something other than the CPU, so I'm not sure where need to do any parsing in software, at least for HDCP 2.x. Alex > > [1] > https://www.digital- > cp.com/sites/default/files/HDCP%20on%20HDMI%20Specification%20Rev2_ > 3.pdf > > Thanks, > Harry > > > SRM table is parsed and stored at drm_hdcp.c, with functions exported > > for the services for revocation check from drivers (which implements > > the HDCP authentication) > > > > This patch handles the HDCP1.4 and 2.2 versions of SRM table. > > > > v2: > > moved the uAPI to request_firmware_direct() [Daniel] > > v3: > > kdoc added. [Daniel] > > srm_header unified and bit field definitions are removed. [Daniel] > > locking improved. [Daniel] > > vrl length violation is fixed. [Daniel] > > v4: > > s/__swab16/be16_to_cpu [Daniel] > > be24_to_cpu is done through a global func [Daniel] > > Unused variables are removed. [Daniel] > > unchecked return values are dropped from static funcs [Daniel] > > > > Signed-off-by: Ramalingam C > > Acked-by: Satyeshwar Singh > > Reviewed-by: Daniel Vetter > > --- > > Documentation/gpu/drm-kms-helpers.rst | 6 + > > drivers/gpu/drm/Makefile | 2 +- > > drivers/gpu/drm/drm_hdcp.c| 333 > ++ > > drivers/gpu/drm/drm_internal.h| 4 + > > drivers/gpu/drm/drm_sysfs.c | 2 + > > include/drm/drm_hdcp.h| 24 ++ > > 6 files changed, 370 insertions(+), 1 deletion(-) create mode 100644 > > drivers/gpu/drm/drm_hdcp.c > > > > diff --git a/Documentation/gpu/drm-kms-helpers.rst > > b/Documentation/gpu/drm-kms-helpers.rst > > index 14102ae035dc..0fe726a6ee67 100644 > > --- a/Documentation/gpu/drm-kms-helpers.rst > > +++ b/Documentation/gpu/drm-kms-helpers.rst > > @@ -181,6 +181,12 @@ Panel Helper Reference .. kernel-doc:: > > drivers/gpu/drm/drm_panel_orientation_quirks.c > > :export: > > > > +HDCP Helper Functions Reference > > +=== > > + > > +.. kernel-doc:: drivers/gpu/drm/drm_hdcp.c > > + :export: > > + > > Display Port Helper Functions Reference > > === > > > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index > > 72f5036d9bfa..dd02e9dec810 100644 > > --- a/drivers/gpu/drm/Makefile > > +++ b/drivers/gpu/drm/Makefile > > @@ -17,7 +17,7 @@ drm-y :=drm_auth.o drm_cache.o \ > > drm_plane.o drm_color_mgmt.o drm_print.o \ > > drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \ > > drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \ > > - drm_atomic_uapi.o > > + drm_atomic_uapi.o drm_hdcp.o > > > > drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o > > drm_context.o drm_dma.o drm_scatter.o drm_lock.o > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o diff --git > > a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c new file > > mode 100644 index ..5e5409505c31 > > --- /dev/null > > +++ b/drivers/gpu/drm/drm_hdcp.c > > @@ -0,0 +1,333 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2019 Intel Corporation. > > + * > > + * Authors: > > + * Ramalingam C */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > >
[Intel-gfx] [PATCH v6 03/10] drm/i915/dsb: single register write function for DSB.
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 7c1b1574788c..e2c383352145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,13 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -66,5 +73,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(>vma, 0);
mutex_unlock(>drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 27eb68eb5392..31b87dcfe160 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -21,10 +23,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating tail of command buffer.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.22.0
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[Intel-gfx] [PATCH v6 5/7] drm/i915: Add new GMP register size for GEN11
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Uma's review comments.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c500fc9154c8..287999b31217 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -189,13 +189,19 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
-static int hsw_dip_data_size(unsigned int type)
+static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
+unsigned int type)
{
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_VSC_DATA_SIZE;
case DP_SDP_PPS:
return VIDEO_DIP_PPS_DATA_SIZE;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ if (INTEL_GEN(dev_priv) >= 11)
+ return VIDEO_DIP_GMP_DATA_SIZE;
+ else
+ return VIDEO_DIP_DATA_SIZE;
default:
return VIDEO_DIP_DATA_SIZE;
}
@@ -514,7 +520,7 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
int i;
u32 val = I915_READ(ctl_reg);
- data_size = hsw_dip_data_size(type);
+ data_size = hsw_dip_data_size(dev_priv, type);
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..ff7f32b59363 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4677,6 +4677,7 @@ enum {
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each
byte
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
+#define VIDEO_DIP_GMP_DATA_SIZE 36
#define VIDEO_DIP_VSC_DATA_SIZE 36
#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
--
2.23.0
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[Intel-gfx] [PATCH v6 4/7] drm/i915/dp: Attach colorspace property
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT2020 on a
sink device.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3a8aef1c6036..7fe22b37474d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6448,6 +6448,8 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
else if (INTEL_GEN(dev_priv) >= 5)
drm_connector_attach_max_bpc_property(connector, 6, 12);
+ intel_attach_colorspace_property(connector);
+
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
--
2.23.0
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[Intel-gfx] [PATCH 4/4] drm/i915/tgl: Fix driver crash when update_active_dpll is called
From: "Taylor, Clinton A"
TGL PLL function table doesn't include and update_active_pll function.
The driver attempts to make a call to this function and crashes during
PLL changes.
Signed-off-by: Taylor, Clinton A
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 98288edf88f0..84e734d44828 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3479,6 +3479,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dpll_info = tgl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
+ .update_active_dpll = icl_update_active_dpll,
.dump_hw_state = icl_dump_hw_state,
};
--
2.23.0
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Re: [Intel-gfx] [CI RESEND] drm/i915: add INTEL_NUM_PIPES() and use it
On Wed, 11 Sep 2019, Jani Nikula wrote:
> Abstract away direct access to ->num_pipes to allow further
> refactoring. No functional changes.
>
> Cc: Chris Wilson
> Cc: José Roberto de Souza
> Cc: Ville Syrjälä
> Reviewed-by: José Roberto de Souza
> Acked-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Pushed, thanks for the review, now on to the next patch...
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++--
> drivers/gpu/drm/i915/display/intel_display.h | 4 ++--
> drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h| 4 +++-
> drivers/gpu/drm/i915/intel_pm.c| 6 +++---
> 6 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3b5275ab66cf..0ac5f507a09a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7190,7 +7190,7 @@ static int ironlake_check_fdi_lanes(struct drm_device
> *dev, enum pipe pipe,
> }
> }
>
> - if (INTEL_INFO(dev_priv)->num_pipes == 2)
> + if (INTEL_NUM_PIPES(dev_priv) == 2)
> return 0;
>
> /* Ivybridge 3 pipe is really complicated */
> @@ -9574,7 +9574,7 @@ static void ironlake_compute_dpll(struct intel_crtc
> *crtc,
>* clear if it''s a win or loss power wise. No point in doing
>* this on ILK at all since it has a fixed DPLL<->pipe mapping.
>*/
> - if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
> + if (INTEL_NUM_PIPES(dev_priv) == 3 &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
> dpll |= DPLL_SDVO_HIGH_SPEED;
>
> @@ -13899,7 +13899,7 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
>
> if
> (skl_ddb_allocation_overlaps(_crtc_state->wm.skl.ddb,
> entries,
> -
> INTEL_INFO(dev_priv)->num_pipes, i))
> +
> INTEL_NUM_PIPES(dev_priv), i))
> continue;
>
> updated |= cmask;
> @@ -16256,8 +16256,8 @@ int intel_modeset_init(struct drm_device *dev)
> }
>
> DRM_DEBUG_KMS("%d display pipe%s available.\n",
> - INTEL_INFO(dev_priv)->num_pipes,
> - INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
> + INTEL_NUM_PIPES(dev_priv),
> + INTEL_NUM_PIPES(dev_priv) > 1 ? "s" : "");
>
> for_each_pipe(dev_priv, pipe) {
> ret = intel_crtc_init(dev_priv, pipe);
> @@ -17348,7 +17348,7 @@ intel_display_print_error_state(struct
> drm_i915_error_state_buf *m,
> if (!error)
> return;
>
> - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
> + err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> err_printf(m, "PWR_WELL_CTL2: %08x\n",
> error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 33fd523c4622..f4ddde171655 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -307,10 +307,10 @@ enum phy_fia {
> };
>
> #define for_each_pipe(__dev_priv, __p) \
> - for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
> + for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
>
> #define for_each_pipe_masked(__dev_priv, __p, __mask) \
> - for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
> + for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
> for_each_if((__mask) & BIT(__p))
>
> #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
> diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> index b19800b58442..0b67f7887cd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> @@ -114,7 +114,7 @@ lpe_audio_platdev_create(struct drm_i915_private
> *dev_priv)
> pinfo.size_data = sizeof(*pdata);
> pinfo.dma_mask = DMA_BIT_MASK(32);
>
> - pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
> + pdata->num_pipes = INTEL_NUM_PIPES(dev_priv);
> pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
> pdata->port[0].pipe = -1;
> pdata->port[1].pipe = -1;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b1a942fc43c8..0dfcb40f3162 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
== Series Details == Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk URL : https://patchwork.freedesktop.org/series/66537/ State : success == Summary == CI Bug Log - changes from CI_DRM_6871_full -> Patchwork_14361_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14361_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl8/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@unwedge-stress: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl1/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl5/igt@gem_...@unwedge-stress.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713] / [fdo#109507]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb6/igt@kms_f...@flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb3/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109276]) +19 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@prime_v...@fence-wait-bsd2.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb6/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][19] ([fdo#110854]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb5/igt@gem_exec_balan...@smoke.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb1/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][21] ([fdo#111325]) -> [PASS][22] +9 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
== Series Details == Series: drm/i915: Fix DRM_I915_DEBUG IOMMU stuff URL : https://patchwork.freedesktop.org/series/66539/ State : success == Summary == CI Bug Log - changes from CI_DRM_6872_full -> Patchwork_14362_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14362_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb3/igt@gem_exec_sched...@in-order-bsd2.html * igt@gem_exec_schedule@preempt-self-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb6/igt@gem_exec_sched...@preempt-self-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb4/igt@gem_exec_sched...@preempt-self-bsd.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#104873]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([fdo#106107]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl1/igt@kms_fbcon_...@psr-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-skl8/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb8/igt@kms_frontbuffer_track...@fbc-modesetfrombusy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb4/igt@kms_frontbuffer_track...@fbc-modesetfrombusy.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#108341]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb8/igt@kms_psr@no_drrs.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-skl7/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-skl1/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html Possible fixes * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24] +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/shard-iclb7/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_pwrite@big-cpu-forwards: - shard-iclb: [INCOMPLETE][25] ([fdo#107713] / [fdo#109100]) -> [PASS][26] [25]:
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave and Daniel, Here goes drm-intel-next-fixes-2019-09-11: Few fixes on GGTT and PPGTT around pin, locks, fence and vgpu. This also includes GVT fixes with two recent fixes: one for recent guest hang regression and another for guest reset fix. Thanks, Rodrigo. The following changes since commit 578d2342ec702e5fb8a77983fabb3754ae3e9660: Merge tag 'drm-next-5.4-2019-08-23' of git://people.freedesktop.org/~agd5f/linux into drm-next (2019-08-27 17:22:15 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2019-09-11 for you to fetch changes up to 6e5c5272ca00809aae20817efb6f25881268b50b: drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap (2019-09-06 09:53:15 -0700) Few fixes on GGTT and PPGTT around pin, locks, fence and vgpu. This also includes GVT fixes with two recent fixes: one for recent guest hang regression and another for guest reset fix. Chris Wilson (3): drm/i915: Hold irq-off for the entire fake lock period drm/i915: Flush the existing fence before GGTT read/write drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap Rodrigo Vivi (1): Merge tag 'gvt-next-fixes-2019-09-06' of https://github.com/intel/gvt-linux into drm-intel-next-fixes Weinan Li (1): drm/i915/gvt: update RING_START reg of vGPU when the context is submitted to i915 Xiaolin Zhang (2): drm/i915/gvt: update vgpu workload head pointer correctly drm/i915: to make vgpu ppgtt notificaiton as atomic operation drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 28 --- drivers/gpu/drm/i915/gt/intel_reset.c | 9 --- drivers/gpu/drm/i915/gt/intel_timeline.c | 10 --- drivers/gpu/drm/i915/gvt/scheduler.c | 45 ++- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 23 +++- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 + drivers/gpu/drm/i915/i915_request.c | 9 --- drivers/gpu/drm/i915/i915_vgpu.c | 1 + 10 files changed, 92 insertions(+), 48 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
On Wed, 2019-09-11 at 21:10 +0300, Ville Syrjälä wrote:
> On Wed, Sep 11, 2019 at 10:56:02AM -0700, José Roberto de Souza
> wrote:
> > This 3 non-atomic drivers all have the same function getting the
> > only encoder available in the connector, also atomic drivers have
> > this fallback. So moving it a common place and sharing between
> > atomic
> > and non-atomic drivers.
> >
> > While at it I also removed the mention of
> > drm_atomic_helper_best_encoder() that was renamed in
> > commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
> > drm_atomic_helper_best_encoder").
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Cc: Daniel Vetter
> > Cc: Laurent Pinchart
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: intel-gfx@lists.freedesktop.org
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/ast/ast_mode.c | 12
> > drivers/gpu/drm/drm_atomic_helper.c | 15 ++-
> > drivers/gpu/drm/drm_connector.c | 11 +++
> > drivers/gpu/drm/drm_crtc_helper.c| 8 +++-
> > drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> > drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
> > drivers/gpu/drm/udl/udl_connector.c | 8
> > include/drm/drm_modeset_helper_vtables.h | 6 +++---
> > 8 files changed, 25 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/ast/ast_mode.c
> > b/drivers/gpu/drm/ast/ast_mode.c
> > index d349c721501c..eef95e1af06b 100644
> > --- a/drivers/gpu/drm/ast/ast_mode.c
> > +++ b/drivers/gpu/drm/ast/ast_mode.c
> > @@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct
> > drm_encoder *encoder)
> > kfree(encoder);
> > }
> >
> > -
> > -static struct drm_encoder *ast_best_single_encoder(struct
> > drm_connector *connector)
> > -{
> > - int enc_id = connector->encoder_ids[0];
> > - /* pick the encoder ids */
> > - if (enc_id)
> > - return drm_encoder_find(connector->dev, NULL, enc_id);
> > - return NULL;
> > -}
> > -
> > -
> > static const struct drm_encoder_funcs ast_enc_funcs = {
> > .destroy = ast_encoder_destroy,
> > };
> > @@ -847,7 +836,6 @@ static void ast_connector_destroy(struct
> > drm_connector *connector)
> > static const struct drm_connector_helper_funcs
> > ast_connector_helper_funcs = {
> > .mode_valid = ast_mode_valid,
> > .get_modes = ast_get_modes,
> > - .best_encoder = ast_best_single_encoder,
> > };
> >
> > static const struct drm_connector_funcs ast_connector_funcs = {
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index 4706439fb490..9d7e4da6c292 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct
> > drm_atomic_state *state,
> > }
> > }
> >
> > -/*
> > - * For connectors that support multiple encoders, either the
> > - * .atomic_best_encoder() or .best_encoder() operation must be
> > implemented.
> > - */
> > -static struct drm_encoder *
> > -pick_single_encoder_for_connector(struct drm_connector *connector)
> > -{
> > - WARN_ON(connector->encoder_ids[1]);
> > - return drm_encoder_find(connector->dev, NULL, connector-
> > >encoder_ids[0]);
> > -}
> > -
> > static int handle_conflicting_encoders(struct drm_atomic_state
> > *state,
> >bool
> > disable_conflicting_encoders)
> > {
> > @@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
> > drm_atomic_state *state,
> > else if (funcs->best_encoder)
> > new_encoder = funcs->best_encoder(connector);
> > else
> > - new_encoder =
> > pick_single_encoder_for_connector(connector);
> > + new_encoder =
> > drm_connector_get_single_encoder(connector);
> >
> > if (new_encoder) {
> > if (encoder_mask &
> > drm_encoder_mask(new_encoder)) {
> > @@ -359,7 +348,7 @@ update_connector_routing(struct
> > drm_atomic_state *state,
> > else if (funcs->best_encoder)
> > new_encoder = funcs->best_encoder(connector);
> > else
> > - new_encoder =
> > pick_single_encoder_for_connector(connector);
> > + new_encoder =
> > drm_connector_get_single_encoder(connector);
> >
> > if (!new_encoder) {
> > DRM_DEBUG_ATOMIC("No suitable encoder found for
> > [CONNECTOR:%d:%s]\n",
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c
> > index 4c766624b20d..3e2a632cf861 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -2334,3 +2334,14 @@ struct drm_tile_group
> > *drm_mode_create_tile_group(struct drm_device *dev,
> > return tg;
> > }
> > EXPORT_SYMBOL(drm_mode_create_tile_group);
> > +
> > +/*
> > + * For connectors that support multiple encoders, either the
> > + * .atomic_best_encoder() or .best_encoder()
[Intel-gfx] [PATCH v6 3/7] drm: Add DisplayPort colorspace property
Becasue between HDMI and DP have different colorspaces, it renames
drm_mode_create_colorspace_property() function to
drm_mode_create_hdmi_colorspace_property() function for HDMI connector.
And it adds drm_mode_create_dp_colorspace_property() function for creating
of DP colorspace property.
In order to apply changed and added drm api, i915 driver has channged.
v3: Addressed review comments from Ville
- Add new colorimetry options for DP 1.4a spec.
- Separate set of colorimetry enum values for DP.
v4: Add additional comments to struct drm_prop_enum_list.
Polishing an enum string of struct drm_prop_enum_list
v5: Change definitions of DRM_MODE_COLORIMETRYs to follow HDMI prefix and
DP abbreviations.
Add missed variables on dp_colorspaces.
Fix typo. [Uma]
v6: Addressed review comments from Ilia and Ville
- Split drm_mode_create_colorspace_property() to DP and HDMI connector.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 110 +++---
.../gpu/drm/i915/display/intel_connector.c| 21 +++-
include/drm/drm_connector.h | 11 +-
3 files changed, 121 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4c766624b20d..48f4058c6d96 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -882,6 +882,47 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
};
+/*
+ * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
Encoding/Colorimetry
+ * Format Table 2-120
+ */
+static const struct drm_prop_enum_list dp_colorspaces[] = {
+ /* For Default case, driver will set the colorspace */
+ { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
+ /* Colorimetry based on sRGB (IEC 61966-2-1) */
+ { DRM_MODE_COLORIMETRY_CEA_RGB, "CEA_RGB" },
+ { DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED, "RGB_Wide_Gamut_Fixed_Point" },
+ /* Colorimetry based on scRGB (IEC 61966-2-2) */
+ { DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT, "RGB_Wide_Gamut_Floating_Point"
},
+ /* Colorimetry based on IEC 61966-2-5 */
+ { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
+ /* Colorimetry based on SMPTE RP 431-2 */
+ { DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
+ { DRM_MODE_COLORIMETRY_RGB_CUSTOM_COLOR_PROFILE,
"RGB_Custom_Color_Profile" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+ { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
+ { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+ /*
+* Colorimetry based on Digital Imaging and Communications in Medicine
+* (DICOM) Part 14: Grayscale Standard Display Function
+*/
+ { DRM_MODE_COLORIMETRY_Y_ONLY_DICOM_P14_GRAYSCALE,
"Y_ONLY_DICOM_Part_14_Grayscale" },
+ { DRM_MODE_COLORIMETRY_RAW_CUSTOM_COLOR_PROFILE,
"Raw_Custom_Color_Profile" },
+};
+
/**
* DOC: standard connector properties
*
@@ -1674,7 +1715,6 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
* DOC: standard connector properties
*
* Colorspace:
- * drm_mode_create_colorspace_property - create colorspace property
* This property helps select a suitable colorspace based on the sink
* capability. Modern sink devices support wider gamut like BT2020.
* This helps switch to BT2020 mode if the BT2020 encoded video stream
@@ -1694,32 +1734,68 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
* - This property is just to inform sink what colorspace
*source is trying to drive.
*
+ * Becasue between HDMI and DP have different colorspaces,
+ * drm_mode_create_hdmi_colorspace_property() is used for HDMI connector and
+ * drm_mode_create_dp_colorspace_property() is used for DP connector.
+ */
+
+/**
+ * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
+ * @connector: connector to create the Colorspace property on.
+ *
* Called by a driver the first time it's needed, must be attached to desired
- * connectors.
+ * HDMI connectors.
+ *
+ * Returns:
+ * Zero on success, negative errono on failure.
*/
-int
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Disable read-only support
== Series Details == Series: drm/i915/tgl: Disable read-only support URL : https://patchwork.freedesktop.org/series/66535/ State : success == Summary == CI Bug Log - changes from CI_DRM_6870_full -> Patchwork_14360_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14360_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb3/igt@gem_exec_sched...@wide-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html * igt@i915_hangman@error-state-capture-vecs0: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-apl8/igt@i915_hang...@error-state-capture-vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-apl7/igt@i915_hang...@error-state-capture-vecs0.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-skl8/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-skl7/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html * igt@prime_busy@hang-bsd2: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276]) +18 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb4/igt@prime_b...@hang-bsd2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb8/igt@prime_b...@hang-bsd2.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [SKIP][19] ([fdo#109276]) -> [PASS][20] +10 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb6/igt@gem_exec_sched...@out-order-bsd2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][21] ([fdo#111325]) -> [PASS][22] +9 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/shard-glk1/igt@gem_tiled_swapp...@non-threaded.html [24]:
[Intel-gfx] [PATCH v6 02/10] drm/i915/dsb: DSB context creation.
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
v4: for simplification and based on current usage added single dsb
object in intel_crtc. (Shashank)
v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 70 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 30
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 105 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..49c902b00484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1033,6 +1033,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index ..7c1b1574788c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ struct intel_dsb *dsb = >dsb;
+ intel_wakeref_t wakeref;
+
+ if ((!HAS_DSB(i915)) || dsb->cmd_buf)
+ return dsb;
+
+ dsb->id = DSB1;
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj))
+ goto err;
+
+ mutex_lock(>drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(>drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ i915_vma_unpin_and_release(, 0);
+ dsb->cmd_buf = NULL;
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!dsb)
+ return;
+
+ if (dsb->cmd_buf) {
+ mutex_lock(>drm.struct_mutex);
+ i915_gem_object_unpin_map(dsb->vma->obj);
+ i915_vma_unpin_and_release(>vma, 0);
+ mutex_unlock(>drm.struct_mutex);
+ dsb->cmd_buf = NULL;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
new file mode 100644
index ..27eb68eb5392
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_DSB_H
+#define _INTEL_DSB_H
+
+struct intel_crtc;
+struct i915_vma;
+
+enum dsb_id {
+ INVALID_DSB = -1,
+ DSB1,
+ DSB2,
+ DSB3,
+ MAX_DSB_PER_PIPE
+};
+
+struct intel_dsb {
+ enum dsb_id id;
+ u32 *cmd_buf;
+
[Intel-gfx] [PATCH v6 01/10] drm/i915/dsb: feature flag added for display state buffer.
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2ea11123e933..6c6af007f29d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1863,6 +1863,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 92e0c2e0954c..e206f298f48e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.22.0
___
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[Intel-gfx] [PATCH v6 04/10] drm/i915/dsb: Indexed register write function for DSB.
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code comment. (Shashank)
v4: cosmetic changes done. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 65
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index e2c383352145..9e2927f869b9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -15,6 +15,7 @@
#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_BYTE_EN0xF
#define DSB_BYTE_EN_SHIFT 20
+#define DSB_REG_VALUE_MASK 0xf
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -77,6 +78,70 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
+ }
+
+ /*
+* For example the buffer will look like below for 3 dwords for auto
+* increment register:
+* ++
+* | size = 3 | offset &| value1 | value2 | value3 | zero |
+* | | opcode |||||
+* ++
+* + + +++++
+* 0 4 812 16 20 24
+* Byte
+*
+* As every instruction is 8 byte aligned the index of dsb instruction
+* will start always from even number while dealing with u32 array. If
+* we are writing odd no of dwords, Zeros will be added in the end for
+* padding.
+*/
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ dsb->ins_start_offset = dsb->free_pos;
+
+ /* Update the size. */
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 31b87dcfe160..9b2522f20bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -29,11 +29,19 @@ struct intel_dsb {
* and help in calculating tail of command buffer.
*/
int free_pos;
+
+ /*
+* ins_start_offset will help to store start address
+* of the dsb instuction of auto-increment register.
+*/
+ u32 ins_start_offset;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val);
#endif
--
2.22.0
___
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[Intel-gfx] [PATCH v6 0/7] drm/i915/dp: Support for DP HDR outputs
Support for HDR10 video was introduced in DisplayPort 1.4. On GLK+ platform, in order to use DisplayPort HDR10, we need to support BT.2020 colorimetry and HDR Static metadata. It implements the CTA-861-G standard for transport of static HDR metadata. It enables writing of HDR metadata infoframe SDP to the panel. The HDR Metadata will be provided by userspace compositors, based on blending policies and passed to the driver through a blob property. And It refactors, renames and extends a function which handled vsc sdp header and data block setup for supporting colorimetry format. And It attaches the colorspace connector property and HDR metadata property to a DisplayPort connector. These patches tested on below test environment. Test Environment: - Tested System: GLK and Gen11 platform. - Monitor: Dell UP2718Q 4K HDR Monitor. - In order to test DP HDR10, test environment uses patched Kodi-gbm, patched Media driver and HDR10 video. You can find these on below. [patched Kodi-gbm] - repo: https://github.com/Kwiboo/xbmc/tree/drmprime-hdr [download 4K HDR video file] - link: https://4kmedia.org/lg-new-york-hdr-uhd-4k-demo/ [Media Driver for GLK] - repo https://gitlab.freedesktop.org/emersion/intel-vaapi-driver master branch [Media Driver for ICL] - repo: https://github.com/harishkrupo/media-driver/tree/p010_composite v2: - Add a missed blank line after function declaration. - Remove useless parentheses. - Minor style fix. v3: - Remove not handled return values from intel_dp_setup_hdr_metadata_infoframe_sdp(). [Uma] - Add handling of different register size for HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN platforms [Uma] - Add new colorimetry options for DP 1.4a spec. [Ville] - Separate set of colorimetry enum values for DP. [Ville] - In order to checking output format and output colorspace on intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state stucture.[Ville] - Remove a pointless variable. [Ville] v4: - Add additional comments to struct drm_prop_enum_list. - Polishing an enum string of struct drm_prop_enum_list. v5: - Change definitions of DRM_MODE_COLORIMETRYs to follow HDMI prefix and DP abbreviations. - Add missed variables on dp_colorspaces. - Fix typo. [Uma] v6: - Addressed review comments from Ilia and Ville Split drm_mode_create_colorspace_property() to DP and HDMI connector. Becasue between HDMI and DP have different colorspaces, it renames drm_mode_create_colorspace_property() function to drm_mode_create_hdmi_colorspace_property() function for HDMI connector. And it adds drm_mode_create_dp_colorspace_property() function for creating of DP colorspace property. In order to apply changed and added drm api, i915 driver has channged. Gwan-gyeong Mun (7): drm/i915/dp: Extend program of VSC Header and DB for Colorimetry Format drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA drm: Add DisplayPort colorspace property drm/i915/dp: Attach colorspace property drm/i915: Add new GMP register size for GEN11 drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static Metadata drm/i915/dp: Attach HDR metadata property to DP connector drivers/gpu/drm/drm_connector.c | 110 -- .../gpu/drm/i915/display/intel_connector.c| 21 +- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +- drivers/gpu/drm/i915/display/intel_display.h | 2 - .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/display/intel_dp.c | 193 -- drivers/gpu/drm/i915/display/intel_dp.h | 7 + drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +- drivers/gpu/drm/i915/i915_reg.h | 1 + include/drm/drm_connector.h | 11 +- 10 files changed, 326 insertions(+), 42 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] i915 firmware updates - PR for CML guc,huc; TGL DMC and Gen9-Gen11 HuC Updates
Josh,Kyle,Ben Can these i915 updates be merged from cml_tgldmc_huc_updates to linux-firmware The following changes since commit 44d4fca9922a252a0bd81f6307bcc072a78da54a: Merge https://github.com/pmachata/linux-firmware (2018-09-13 11:45:40 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware cml_tgldmc_huc_updates for you to fetch changes up to e848f4708bcea2fa829cfbfd7e7a1b3a83b91d3e: drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-11 15:46:03 -0700) Anusha Srivatsa (8): drm/i915/firmware: Add v2.04 of DMC for TGL drm/i915/firmware: Add v33 of GuC for CML drm/i915/firmware: Add v2.0.0 of HuC for Skylake drm/i915/firmware: Add v4.0.0 of HuC for Kabylake drm/i915/firmware: Add v2.0.0 of HuC for Broxton drm/i915/firmware: Add v4.0.0 of HuC for Geminilake drm/i915/firmware: Add v4.0.0 of HuC for Cometlake drm/i915/firmware: Add v9.0.0 of HuC for Icelake WHENCE | 26 ++ i915/bxt_huc_2.0.0.bin | Bin 0 -> 149824 bytes i915/cml_guc_33.0.0.bin | Bin 0 -> 182912 bytes i915/cml_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/glk_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/icl_huc_9.0.0.bin | Bin 0 -> 498880 bytes i915/kbl_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/skl_huc_2.0.0.bin | Bin 0 -> 136320 bytes i915/tgl_dmc_ver2_04.bin | Bin 0 -> 18436 bytes 9 files changed, 26 insertions(+) create mode 100644 i915/bxt_huc_2.0.0.bin create mode 100644 i915/cml_guc_33.0.0.bin create mode 100644 i915/cml_huc_4.0.0.bin create mode 100644 i915/glk_huc_4.0.0.bin create mode 100644 i915/icl_huc_9.0.0.bin create mode 100644 i915/kbl_huc_4.0.0.bin create mode 100644 i915/skl_huc_2.0.0.bin create mode 100644 i915/tgl_dmc_ver2_04.bin Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Finish modular FIA support on registers
If platform supports and has modular FIA is enabled, the registers
bits also change, example: reading TC3 registers with modular FIA
enabled, driver should read from FIA2 but with TC1 bits offsets.
It is described in BSpec 50231 for DFLEXDPSP, other registers don't
have the BSpec description but testing in real hardware have proven
that it had moved for all other registers too.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +
drivers/gpu/drm/i915/display/intel_tc.c | 52
drivers/gpu/drm/i915/display/intel_tc.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 45 -
5 files changed, 61 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..16aaf20a80e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15369,6 +15369,8 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
+ intel_tc_init(dev_priv);
+
if (INTEL_GEN(dev_priv) >= 12) {
/* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 3a7302e360cc..fc5d0e73cf21 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -23,19 +23,21 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
-static bool has_modular_fia(struct drm_i915_private *i915)
+void intel_tc_init(struct drm_i915_private *i915)
{
+ u32 val;
+
if (!INTEL_INFO(i915)->display.has_modular_fia)
- return false;
+ return;
- return intel_uncore_read(>uncore,
-PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+ val = intel_uncore_read(>uncore, PORT_TX_DFLEXDPSP(FIA1));
+ i915->has_modular_fia = val & MODULAR_FIA_MASK;
}
static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
enum tc_port tc_port)
{
- if (!has_modular_fia(i915))
+ if (!i915->has_modular_fia)
return FIA1;
/*
@@ -51,14 +53,15 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = >uncore;
u32 lane_mask;
+ bool mod_fia = i915->has_modular_fia;
lane_mask = intel_uncore_read(uncore,
PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0x);
- return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
- DP_LANE_ASSIGNMENT_SHIFT(tc_port);
+ return (lane_mask & DP_LANE_ASSIGNMENT_MASK(mod_fia, tc_port)) >>
+ DP_LANE_ASSIGNMENT_SHIFT(mod_fia, tc_port);
}
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
@@ -66,6 +69,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct
intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = >uncore;
+ bool mod_fia = i915->has_modular_fia;
u32 pin_mask;
pin_mask = intel_uncore_read(uncore,
@@ -73,8 +77,8 @@ u32 intel_tc_port_get_pin_assignment_mask(struct
intel_digital_port *dig_port)
WARN_ON(pin_mask == 0x);
- return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc_port)) >>
- DP_PIN_ASSIGNMENT_SHIFT(tc_port);
+ return (pin_mask & DP_PIN_ASSIGNMENT_MASK(mod_fia, tc_port)) >>
+ DP_PIN_ASSIGNMENT_SHIFT(mod_fia, tc_port);
}
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
@@ -114,25 +118,28 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
struct intel_uncore *uncore = >uncore;
+ bool mod_fia = i915->has_modular_fia;
u32 val;
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
val = intel_uncore_read(uncore,
PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
- val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(mod_fia, tc_port);
switch (required_lanes) {
case 1:
- val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+ val |= lane_reversal ?
+
[Intel-gfx] [CI] drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use
As we remove the struct_mutex protection from around the vma pinning,
counters need to be atomic and aware that there may be multiple threads
simultaneously active.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++-
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a09a9b62afbe..8883bb8e5ca2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1790,6 +1790,8 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
gen6_ppgtt_free_pd(ppgtt);
free_scratch(vm);
+
+ mutex_destroy(>pin_mutex);
kfree(ppgtt->base.pd);
}
@@ -1895,7 +1897,7 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt
*ppgtt, int size)
int gen6_ppgtt_pin(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- int err;
+ int err = 0;
GEM_BUG_ON(ppgtt->base.vm.closed);
@@ -1905,24 +1907,26 @@ int gen6_ppgtt_pin(struct i915_ppgtt *base)
* (When vma->pin_count becomes atomic, I expect we will naturally
* need a larger, unpacked, type and kill this redundancy.)
*/
- if (ppgtt->pin_count++)
+ if (atomic_add_unless(>pin_count, 1, 0))
return 0;
+ if (mutex_lock_interruptible(>pin_mutex))
+ return -EINTR;
+
/*
* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
* size. We allocate at the top of the GTT to avoid fragmentation.
*/
- err = i915_vma_pin(ppgtt->vma,
- 0, GEN6_PD_ALIGN,
- PIN_GLOBAL | PIN_HIGH);
- if (err)
- goto unpin;
-
- return 0;
+ if (!atomic_read(>pin_count)) {
+ err = i915_vma_pin(ppgtt->vma,
+ 0, GEN6_PD_ALIGN,
+ PIN_GLOBAL | PIN_HIGH);
+ }
+ if (!err)
+ atomic_inc(>pin_count);
+ mutex_unlock(>pin_mutex);
-unpin:
- ppgtt->pin_count = 0;
return err;
}
@@ -1930,22 +1934,19 @@ void gen6_ppgtt_unpin(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- GEM_BUG_ON(!ppgtt->pin_count);
- if (--ppgtt->pin_count)
- return;
-
- i915_vma_unpin(ppgtt->vma);
+ GEM_BUG_ON(!atomic_read(>pin_count));
+ atomic_dec(>pin_count);
}
void gen6_ppgtt_unpin_all(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- if (!ppgtt->pin_count)
+ if (!atomic_read(>pin_count))
return;
- ppgtt->pin_count = 0;
i915_vma_unpin(ppgtt->vma);
+ atomic_set(>pin_count, 0);
}
static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
@@ -1958,6 +1959,8 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
+ mutex_init(>pin_mutex);
+
ppgtt_init(>base, >gt);
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 201788126a89..8fd2234ba0bf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -437,7 +437,9 @@ struct gen6_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
- unsigned int pin_count;
+ atomic_t pin_count;
+ struct mutex pin_mutex;
+
bool scan_for_unused_pt;
};
--
2.23.0
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[Intel-gfx] [PATCH v6 10/10] drm/i915/dsb: Documentation for DSB.
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
drivers/gpu/drm/i915/display/intel_dsb.c | 68
2 files changed, 77 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index e249ea7b0ec7..465779670fd4 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index eea86afb0583..909fdb9935e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,23 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
@@ -66,6 +83,17 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb
*dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate dsb context and return a dsb instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function will give handle of the DSB instance which
+ * user want to operate on.
+ *
+ * Return : address of Intel_dsb instance requested for.
+ * In failure case, the dsb instance will not have any command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -109,6 +137,14 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to destroy the dsb-context by doing unpin
+ * and release the vma object.
+ */
+
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -127,6 +163,19 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+/**
+ * intel_dsb_indexed_reg_write() -Write to the dsb context for auto
+ * increment register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for auto-increment register and intel_dsb_reg_write()
+ * is used for normal register. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
+
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
@@ -191,6 +240,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the dsb context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -213,6 +274,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
--
2.22.0
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[Intel-gfx] [PATCH] drm/i915/dmc: Update ICL DMC version to v1.09
We have a new version of DMC for ICL - v1.09. This version adds the Half Refresh Rate capability into DMC. Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 546577e39b4e..09870a31b4f0 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -44,8 +44,8 @@ #define TGL_CSR_MAX_FW_SIZE0x6000 MODULE_FIRMWARE(TGL_CSR_PATH); -#define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin" -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) +#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin" +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) #define ICL_CSR_MAX_FW_SIZE0x6000 MODULE_FIRMWARE(ICL_CSR_PATH); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915/tgl: Add missing ddi clock select during DP init sequence
From: "Taylor, Clinton A" Step 4.b was complete missed because it is only required to TC and TBT. Bspec: 49190 Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3e6394139964..81792a04e0aa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3224,11 +3224,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_edp_panel_on(intel_dp); /* -* 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by: +* 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by: * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and * haswell_crtc_enable()->intel_enable_shared_dpll() */ + /* 4.b */ + intel_ddi_clk_select(encoder, crtc_state); + /* 5. */ if (!intel_phy_is_tc(dev_priv, phy) || dig_port->tc_mode != TC_PORT_TBT_ALT) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 00/10] DSB enablement.
Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. v3: As per review comments from Chris and Jani, - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) - Simplified and optimized code few places. (Chris) - Called dsb-api directly in callsites instead going via I915_WRITE. (Jani) v4: Addressed review commnets from Shashank. v5: Addressed review commnets from Shashank and Jani. v6: Addressed review commnets from Shashank. Cc: Ville Syrjälä Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Daniel Vetter Cc: Imre Deak Cc: Michel Thierry Cc: Uma Shankar Cc: Shashank Sharma Cc: Swati Sharma Cc: Lucas De Marchi Signed-off-by: Animesh Manna Animesh Manna (10): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. drm/i915/dsb: Documentation for DSB. Documentation/gpu/i915.rst| 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c| 57 +-- .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 324 ++ drivers/gpu/drm/i915/display/intel_dsb.h | 48 +++ drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 436 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix spelling mistake "resseting" -> "resetting"
== Series Details == Series: drm/i915/gvt: fix spelling mistake "resseting" -> "resetting" URL : https://patchwork.freedesktop.org/series/66529/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14358_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6868_full and Patchwork_14358_full: ### New Piglit tests (7) ### * spec@arb_gpu_shader5@texturegather@vs-rgb-0-int-cubearray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgb-1-int-cubearray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgb-2-int-cubearray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgb-2-int-2darray-const: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-0-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-1-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-2-int-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14358_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb6/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl3/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-apl5/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions: - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-hsw8/igt@kms_cursor_leg...@cursorb-vs-flipb-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-hsw7/igt@kms_cursor_leg...@cursorb-vs-flipb-atomic-transitions.html * igt@kms_flip@basic-flip-vs-dpms: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl4/igt@kms_f...@basic-flip-vs-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-apl1/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#111609]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-glk3/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-glk8/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html *
Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: Update GuC and HuC firmware naming convention
You're not touching GuC at all in this patch, so the subject is incorrect. You should also mention in the subject that you're updating the required FW version. with the title fixed: Reviewed-by: Daniele Ceraolo Spurio Daniele On 9/10/19 3:42 PM, Anusha Srivatsa wrote: Make both GuC and HuC to use "." as the separator. Hardcode the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC. The current convention being: _uc_..patch.bin Update the versions of HuC being loaded of the platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL v4.0.0 ICL - v9.0.0 CML - v4.0.0 v2: Remove the separator parameter altogether from __MAKE_UC_FW_PATH.(Daniele) - Squash all firmware update patches (Daniele) v3: s/huc/HuC - Correct the order of platforms - Change REVID of cml to 5(Michal) - Code space changes in huc_def (Daniele) Suggested-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 296a82603be0..ea9a807abd4f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * Must be ordered based on platform + revid, from newer to older. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ - fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ - fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01, 8, 2893)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398)) - -#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ + fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ + fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) + +#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \ "i915/" \ __stringify(prefix_) name_ \ - __stringify(major_) separator_ \ - __stringify(minor_) separator_ \ + __stringify(major_) "." \ + __stringify(minor_) "." \ __stringify(patch_) ".bin" #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \ - __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_) + __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_) #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ - __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_) + __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_) /* All blobs need to be declared via MODULE_FIRMWARE() */ #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915/tgl: TC helper function to return pin mapping
From: "Taylor, Clinton A"
Add a helper function to return pin map for use during dkl phy
DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
The user of this function will come in future TC patches.
Signed-off-by: Taylor, Clinton A
---
drivers/gpu/drm/i915/display/intel_tc.c | 16
drivers/gpu/drm/i915/display/intel_tc.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +
3 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 85743a43bee2..3a7302e360cc 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -61,6 +61,22 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
DP_LANE_ASSIGNMENT_SHIFT(tc_port);
}
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = >uncore;
+ u32 pin_mask;
+
+ pin_mask = intel_uncore_read(uncore,
+PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
+
+ WARN_ON(pin_mask == 0x);
+
+ return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc_port)) >>
+ DP_PIN_ASSIGNMENT_SHIFT(tc_port);
+}
+
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
b/drivers/gpu/drm/i915/display/intel_tc.h
index 783d75531435..463f1b3c836f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -13,6 +13,7 @@ struct intel_digital_port;
bool intel_tc_port_connected(struct intel_digital_port *dig_port);
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..16d5548adb84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11683,4 +11683,9 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
+#define DP_PIN_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 4)
+#define DP_PIN_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 4))
+#define DP_PIN_ASSIGNMENT(tc_port, x)((x) << ((tc_port) * 4))
+
#endif /* _I915_REG_H_ */
--
2.23.0
___
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Re: [Intel-gfx] [RFC] drm/i915/guc: Enable guc logging on guc log relay write
On 9/10/19 5:48 PM, Daniele Ceraolo Spurio wrote:
On 9/10/19 3:46 PM, Robert M. Fosha wrote:
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 38 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 27 +--
3 files changed, 56 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 36332064de9c..9a98270d05b6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -361,6 +361,7 @@ void intel_guc_log_init_early(struct
intel_guc_log *log)
{
mutex_init(>relay.lock);
INIT_WORK(>relay.flush_work, capture_logs_work);
+ log->relay_started = false;
}
static int guc_log_relay_create(struct intel_guc_log *log)
@@ -585,15 +586,6 @@ int intel_guc_log_relay_open(struct
intel_guc_log *log)
mutex_unlock(>relay.lock);
- guc_log_enable_flush_events(log);
-
- /*
- * When GuC is logging without us relaying to userspace, we're
ignoring
- * the flush notification. This means that we need to
unconditionally
- * flush on relay enabling, since GuC only notifies us once.
- */
- queue_work(system_highpri_wq, >relay.flush_work);
-
return 0;
out_relay:
@@ -604,12 +596,38 @@ int intel_guc_log_relay_open(struct
intel_guc_log *log)
return ret;
}
+int intel_guc_log_relay_start(struct intel_guc_log *log)
+{
+ int ret = 0;
+
+ if (log->relay_started) {
+ ret = -EEXIST;
+ } else {
style: for this kind of checks, we usually just return early instead
of using an if-else, i.e.:
if (log->relay_started)
return -EEXIST;
[...] /* code */
return 0;
+ guc_log_enable_flush_events(log);
+
+ /*
+ * When GuC is logging without us relaying to userspace, we're
+ * ignoring the flush notification. This means that we need to
+ * unconditionally * flush on relay enabling, since GuC only
stray "*"
+ * notifies us once.
+ */
+ queue_work(system_highpri_wq, >relay.flush_work);
+
+ log->relay_started = false;
s/false/true/
+ }
+
+ return ret;
+}
+
void intel_guc_log_relay_flush(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
+ if (!log->relay_started)
+ return;
+
/*
* Before initiating the forceful flush, wait for any
pending/ongoing
* flush to complete otherwise forceful flush may not actually
happen.
@@ -638,6 +656,8 @@ void intel_guc_log_relay_close(struct
intel_guc_log *log)
guc_log_unmap(log);
guc_log_relay_destroy(log);
mutex_unlock(>relay.lock);
+
+ log->relay_started = false;
For symmetry, it might be worth adding a guc_log_relay_stop:
Should it be intel_guc_log_relay_stop to be consistent with naming of
other functions?
static void guc_log_relay_stop(...)
{
if (!log->relay_started)
return;
guc_log_disable_flush_events(log);
intel_synchronize_irq(i915);
flush_work(>relay.flush_work);
log->relay_started = false;
}
and call it from intel_guc_log_relay_close().
Also, it should be impossible to race the start/flush with the stop
because the relay_write can't race the relay_close, but it might be
worth a comment in case we decide to have guc_log_relay_stop()
callable from the debugfs in the future.
How about this comment just above the relay_stop function:
/*
* Stops the relay log. Called from intel_guc_log_relay_close(), so no
* possibility of race with start/flush since relay_write cannot race
* relay_close.
*/
}
void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
index 6f764879acb1..ecf7a49416b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
@@ -44,6 +44,7 @@ struct intel_guc;
struct intel_guc_log {
u32 level;
+ bool relay_started;
this should move inside the relay structure below. Just "started" will
be enough as a name at that point because the structure is already
called relay.
struct i915_vma *vma;
struct {
void *buf_addr;
@@ -67,6 +68,7 @@ void intel_guc_log_destroy(struct intel_guc_log *log);
int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);
bool
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
HI, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Chris > Wilson > Sent: keskiviikko 11. syyskuuta 2019 18.09 > To: Roper, Matthew D ; Ville Syrjala > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking > during > cdclk sanitation > > Quoting Matt Roper (2019-09-11 16:00:44) > > I'm confused why pre-merge CI flagged the results as a success if TGL > > was hitting this? > > We've only just (Fri) got CI's Tigerlake surviving boot, so a second failure > during boot > would have been missed. For the summary report, Tigerlake is currently > suppressed > as it is not yet proven itself as being a stable result. (Which is a bit of a > nuisance as > you have to remind yourself to actually check the details.) -Chris Exactly. > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
On Wed, Sep 11, 2019 at 10:56:02AM -0700, José Roberto de Souza wrote:
> This 3 non-atomic drivers all have the same function getting the
> only encoder available in the connector, also atomic drivers have
> this fallback. So moving it a common place and sharing between atomic
> and non-atomic drivers.
>
> While at it I also removed the mention of
> drm_atomic_helper_best_encoder() that was renamed in
> commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
> drm_atomic_helper_best_encoder").
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Laurent Pinchart
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/ast/ast_mode.c | 12
> drivers/gpu/drm/drm_atomic_helper.c | 15 ++-
> drivers/gpu/drm/drm_connector.c | 11 +++
> drivers/gpu/drm/drm_crtc_helper.c| 8 +++-
> drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
> drivers/gpu/drm/udl/udl_connector.c | 8
> include/drm/drm_modeset_helper_vtables.h | 6 +++---
> 8 files changed, 25 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index d349c721501c..eef95e1af06b 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct drm_encoder
> *encoder)
> kfree(encoder);
> }
>
> -
> -static struct drm_encoder *ast_best_single_encoder(struct drm_connector
> *connector)
> -{
> - int enc_id = connector->encoder_ids[0];
> - /* pick the encoder ids */
> - if (enc_id)
> - return drm_encoder_find(connector->dev, NULL, enc_id);
> - return NULL;
> -}
> -
> -
> static const struct drm_encoder_funcs ast_enc_funcs = {
> .destroy = ast_encoder_destroy,
> };
> @@ -847,7 +836,6 @@ static void ast_connector_destroy(struct drm_connector
> *connector)
> static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
> .mode_valid = ast_mode_valid,
> .get_modes = ast_get_modes,
> - .best_encoder = ast_best_single_encoder,
> };
>
> static const struct drm_connector_funcs ast_connector_funcs = {
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4706439fb490..9d7e4da6c292 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state
> *state,
> }
> }
>
> -/*
> - * For connectors that support multiple encoders, either the
> - * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> - */
> -static struct drm_encoder *
> -pick_single_encoder_for_connector(struct drm_connector *connector)
> -{
> - WARN_ON(connector->encoder_ids[1]);
> - return drm_encoder_find(connector->dev, NULL,
> connector->encoder_ids[0]);
> -}
> -
> static int handle_conflicting_encoders(struct drm_atomic_state *state,
> bool disable_conflicting_encoders)
> {
> @@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
> drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder =
> pick_single_encoder_for_connector(connector);
> + new_encoder =
> drm_connector_get_single_encoder(connector);
>
> if (new_encoder) {
> if (encoder_mask & drm_encoder_mask(new_encoder)) {
> @@ -359,7 +348,7 @@ update_connector_routing(struct drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder = pick_single_encoder_for_connector(connector);
> + new_encoder = drm_connector_get_single_encoder(connector);
>
> if (!new_encoder) {
> DRM_DEBUG_ATOMIC("No suitable encoder found for
> [CONNECTOR:%d:%s]\n",
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 4c766624b20d..3e2a632cf861 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -2334,3 +2334,14 @@ struct drm_tile_group
> *drm_mode_create_tile_group(struct drm_device *dev,
> return tg;
> }
> EXPORT_SYMBOL(drm_mode_create_tile_group);
> +
> +/*
> + * For connectors that support multiple encoders, either the
> + * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> + */
> +struct drm_encoder *
> +drm_connector_get_single_encoder(struct drm_connector *connector)
> +{
> + WARN_ON(connector->encoder_ids[1]);
> + return drm_encoder_find(connector->dev, NULL,
> connector->encoder_ids[0]);
> +}
I believe we
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Squeeze iommu status into debugfs/i915_capabilities
== Series Details == Series: drm/i915: Squeeze iommu status into debugfs/i915_capabilities URL : https://patchwork.freedesktop.org/series/66530/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14359_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14359_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-iclb7/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl6/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-skl1/igt@gem_exec_susp...@basic-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@debugfs-read: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#107807]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl2/igt@i915_pm_...@debugfs-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-skl5/igt@i915_pm_...@debugfs-read.html * igt@kms_draw_crc@draw-method-rgb565-render-ytiled: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103184] / [fdo#103232]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_draw_...@draw-method-rgb565-render-ytiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-iclb5/igt@kms_draw_...@draw-method-rgb565-render-ytiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-glk4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#109507]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-skl8/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +6 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [24]:
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt
> Roper
> Sent: keskiviikko 11. syyskuuta 2019 18.01
> To: Ville Syrjala
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking
> during
> cdclk sanitation
>
> On Wed, Sep 11, 2019 at 04:31:27PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We're forgetting to mask off all three pipe select bits from the
> > CDCLK_CTL value on icl+ which may lead to the extra bit being left in.
> > That will cause us to consider the current hardware cdclk state as
> > invalid, and we proceed to sanitize it even though the hardware may
> > have active pipes and whatnot.
> >
> > Fix up the mask so we get rid of all three pipe select bits and thus
> > hopefully no longer sanitize cdclk when it's already correctly
> > programmed.
> >
> > Cc: Matt Roper
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
> > Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Matt Roper
>
> I'm confused why pre-merge CI flagged the results as a success if TGL was
> hitting
> this?
It died also on CI: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14345/?
Martin, Tomi can you explain?
>
>
> Matt
>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 42
> > --
> > 1 file changed, 23 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 6b75d2a91cd9..f59a6f775177 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> > dev_priv->cdclk.hw.vco = vco;
> > }
> >
> > +static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv,
> > +enum pipe pipe) {
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + if (pipe == INVALID_PIPE)
> > + return TGL_CDCLK_CD2X_PIPE_NONE;
> > + else
> > + return TGL_CDCLK_CD2X_PIPE(pipe);
> > + } else if (INTEL_GEN(dev_priv) >= 11) {
> > + if (pipe == INVALID_PIPE)
> > + return ICL_CDCLK_CD2X_PIPE_NONE;
> > + else
> > + return ICL_CDCLK_CD2X_PIPE(pipe);
> > + } else {
> > + if (pipe == INVALID_PIPE)
> > + return BXT_CDCLK_CD2X_PIPE_NONE;
> > + else
> > + return BXT_CDCLK_CD2X_PIPE(pipe);
> > + }
> > +}
> > +
> > static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > const struct intel_cdclk_state *cdclk_state,
> > enum pipe pipe)
> > @@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> > bxt_de_pll_enable(dev_priv, vco);
> > }
> >
> > - val = divider | skl_cdclk_decimal(cdclk);
> > -
> > - if (INTEL_GEN(dev_priv) >= 12) {
> > - if (pipe == INVALID_PIPE)
> > - val |= TGL_CDCLK_CD2X_PIPE_NONE;
> > - else
> > - val |= TGL_CDCLK_CD2X_PIPE(pipe);
> > - } else if (INTEL_GEN(dev_priv) >= 11) {
> > - if (pipe == INVALID_PIPE)
> > - val |= ICL_CDCLK_CD2X_PIPE_NONE;
> > - else
> > - val |= ICL_CDCLK_CD2X_PIPE(pipe);
> > - } else {
> > - if (pipe == INVALID_PIPE)
> > - val |= BXT_CDCLK_CD2X_PIPE_NONE;
> > - else
> > - val |= BXT_CDCLK_CD2X_PIPE(pipe);
> > - }
> > + val = divider | skl_cdclk_decimal(cdclk) |
> > + bxt_cdclk_cd2x_pipe(dev_priv, pipe);
> >
> > /*
> > * Disable SSA Precharge when CD clock frequency < 500 MHz, @@
> > -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> > * dividers both synching to an active pipe, or asynchronously
> > * (PIPE_NONE).
> > */
> > - cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> > + cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
> >
> > /* Make sure this is a legal cdclk value for the platform */
> > cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
> > --
> > 2.21.0
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
On Wed, Sep 11, 2019 at 08:01:55PM +, Souza, Jose wrote:
> On Wed, 2019-09-11 at 21:10 +0300, Ville Syrjälä wrote:
> > On Wed, Sep 11, 2019 at 10:56:02AM -0700, José Roberto de Souza
> > wrote:
> > > This 3 non-atomic drivers all have the same function getting the
> > > only encoder available in the connector, also atomic drivers have
> > > this fallback. So moving it a common place and sharing between
> > > atomic
> > > and non-atomic drivers.
> > >
> > > While at it I also removed the mention of
> > > drm_atomic_helper_best_encoder() that was renamed in
> > > commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
> > > drm_atomic_helper_best_encoder").
> > >
> > > Suggested-by: Ville Syrjälä
> > > Cc: Ville Syrjälä
> > > Cc: Daniel Vetter
> > > Cc: Laurent Pinchart
> > > Cc: dri-de...@lists.freedesktop.org
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/ast/ast_mode.c | 12
> > > drivers/gpu/drm/drm_atomic_helper.c | 15 ++-
> > > drivers/gpu/drm/drm_connector.c | 11 +++
> > > drivers/gpu/drm/drm_crtc_helper.c| 8 +++-
> > > drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> > > drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
> > > drivers/gpu/drm/udl/udl_connector.c | 8
> > > include/drm/drm_modeset_helper_vtables.h | 6 +++---
> > > 8 files changed, 25 insertions(+), 48 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/ast/ast_mode.c
> > > b/drivers/gpu/drm/ast/ast_mode.c
> > > index d349c721501c..eef95e1af06b 100644
> > > --- a/drivers/gpu/drm/ast/ast_mode.c
> > > +++ b/drivers/gpu/drm/ast/ast_mode.c
> > > @@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct
> > > drm_encoder *encoder)
> > > kfree(encoder);
> > > }
> > >
> > > -
> > > -static struct drm_encoder *ast_best_single_encoder(struct
> > > drm_connector *connector)
> > > -{
> > > - int enc_id = connector->encoder_ids[0];
> > > - /* pick the encoder ids */
> > > - if (enc_id)
> > > - return drm_encoder_find(connector->dev, NULL, enc_id);
> > > - return NULL;
> > > -}
> > > -
> > > -
> > > static const struct drm_encoder_funcs ast_enc_funcs = {
> > > .destroy = ast_encoder_destroy,
> > > };
> > > @@ -847,7 +836,6 @@ static void ast_connector_destroy(struct
> > > drm_connector *connector)
> > > static const struct drm_connector_helper_funcs
> > > ast_connector_helper_funcs = {
> > > .mode_valid = ast_mode_valid,
> > > .get_modes = ast_get_modes,
> > > - .best_encoder = ast_best_single_encoder,
> > > };
> > >
> > > static const struct drm_connector_funcs ast_connector_funcs = {
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c
> > > index 4706439fb490..9d7e4da6c292 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct
> > > drm_atomic_state *state,
> > > }
> > > }
> > >
> > > -/*
> > > - * For connectors that support multiple encoders, either the
> > > - * .atomic_best_encoder() or .best_encoder() operation must be
> > > implemented.
> > > - */
> > > -static struct drm_encoder *
> > > -pick_single_encoder_for_connector(struct drm_connector *connector)
> > > -{
> > > - WARN_ON(connector->encoder_ids[1]);
> > > - return drm_encoder_find(connector->dev, NULL, connector-
> > > >encoder_ids[0]);
> > > -}
> > > -
> > > static int handle_conflicting_encoders(struct drm_atomic_state
> > > *state,
> > > bool
> > > disable_conflicting_encoders)
> > > {
> > > @@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
> > > drm_atomic_state *state,
> > > else if (funcs->best_encoder)
> > > new_encoder = funcs->best_encoder(connector);
> > > else
> > > - new_encoder =
> > > pick_single_encoder_for_connector(connector);
> > > + new_encoder =
> > > drm_connector_get_single_encoder(connector);
> > >
> > > if (new_encoder) {
> > > if (encoder_mask &
> > > drm_encoder_mask(new_encoder)) {
> > > @@ -359,7 +348,7 @@ update_connector_routing(struct
> > > drm_atomic_state *state,
> > > else if (funcs->best_encoder)
> > > new_encoder = funcs->best_encoder(connector);
> > > else
> > > - new_encoder =
> > > pick_single_encoder_for_connector(connector);
> > > + new_encoder =
> > > drm_connector_get_single_encoder(connector);
> > >
> > > if (!new_encoder) {
> > > DRM_DEBUG_ATOMIC("No suitable encoder found for
> > > [CONNECTOR:%d:%s]\n",
> > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > b/drivers/gpu/drm/drm_connector.c
> > > index 4c766624b20d..3e2a632cf861 100644
> > > --- a/drivers/gpu/drm/drm_connector.c
> > > +++ b/drivers/gpu/drm/drm_connector.c
> > > @@ -2334,3 +2334,14 @@ struct drm_tile_group
> > >
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement Wa_1409142259
On 9/9/19 4:14 PM, Radhakrishna Sripada wrote:
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
v2: Move WA to ctx WA's(Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..95ef2f1dfdbb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ /* Wa_1409142259 */
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X(1 << 15)
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[Intel-gfx] [PATCH v6 09/10] drm/i915/dsb: Enable DSB for gen12.
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b3cc8560696b..1fd2a364891a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info
intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
--
2.22.0
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[Intel-gfx] [PATCH v6 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in future
based on need.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
v3:
- modified the code as per single dsb instance per crtc. (Shashank)
- Added dsb get/put call in platform specific load_lut hook. (Jani)
- removed dsb pointer from dev_priv. (Jani)
v4: simplified code by dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 57 +-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308dc136c..b6b9f0e5166b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,9 +625,12 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
}
@@ -787,22 +791,22 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
}
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
u32 i;
@@ -813,15 +817,16 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* Superfine segment has 9 entries, corresponding to values
* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
*/
- I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = [i];
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
+ ilk_lut_12p4_ldw(entry));
+ intel_dsb_indexed_reg_write(dsb,
[Intel-gfx] [PATCH] drm/i915: Disable FBC if BIOS reserved memory (stolen) is unavailable
The FBC requires a couple of contiguous buffers, which we allocate from stolen memory. If stolen memory is unavailable, we cannot allocate those buffers and so cannot support FBC. Mark it so. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index dc34b23e2320..3111ecaeabd0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1320,6 +1320,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) fbc->enabled = false; fbc->active = false; + if (!drm_mm_initialized(_priv->mm.stolen)) + mkwrite_device_info(dev_priv)->display.has_fbc = false; + if (need_fbc_vtd_wa(dev_priv)) mkwrite_device_info(dev_priv)->display.has_fbc = false; -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/connector: Allow max possible encoders to attach to a connector
From: Dhinakaran Pandiyan
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized(32).
To more effiently do that lets switch from an array of encoder ids to
bitmask.
v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Alex Deucher
Cc: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 ---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
drivers/gpu/drm/drm_client_modeset.c | 3 +-
drivers/gpu/drm/drm_connector.c | 40 +++
drivers/gpu/drm/drm_probe_helper.c| 3 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++--
drivers/gpu/drm/radeon/radeon_connectors.c| 27 +
include/drm/drm_connector.h | 18 -
11 files changed, 55 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index ece55c8fa673..d8729285f731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct drm_connector
*connector,
struct drm_encoder *encoder;
const struct drm_connector_helper_funcs *connector_funcs =
connector->helper_private;
bool connected;
- int i;
best_encoder = connector_funcs->best_encoder(connector);
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if ((encoder == best_encoder) && (status ==
connector_status_connected))
connected = true;
else
@@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct drm_connector
*connector,
int encoder_type)
{
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type == encoder_type)
return encoder;
}
@@ -347,10 +345,9 @@ static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector *connector)
{
struct drm_encoder *encoder;
- int i;
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct drm_connector
*connector, bool force)
/* find analog encoder */
if (amdgpu_connector->dac_load_detect) {
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
continue;
@@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
{
struct amdgpu_connector *amdgpu_connector =
to_amdgpu_connector(connector);
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (amdgpu_connector->use_digital == true) {
if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
return encoder;
@@ -1134,7 +1129,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
/* then check use digitial */
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1271,9 +1266,8 @@ u16
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
amdgpu_encoder =
[Intel-gfx] [CI] drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use
As we remove the struct_mutex protection from around the vma pinning,
counters need to be atomic and aware that there may be multiple threads
simultaneously active.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++-
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a09a9b62afbe..8883bb8e5ca2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1790,6 +1790,8 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
gen6_ppgtt_free_pd(ppgtt);
free_scratch(vm);
+
+ mutex_destroy(>pin_mutex);
kfree(ppgtt->base.pd);
}
@@ -1895,7 +1897,7 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt
*ppgtt, int size)
int gen6_ppgtt_pin(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- int err;
+ int err = 0;
GEM_BUG_ON(ppgtt->base.vm.closed);
@@ -1905,24 +1907,26 @@ int gen6_ppgtt_pin(struct i915_ppgtt *base)
* (When vma->pin_count becomes atomic, I expect we will naturally
* need a larger, unpacked, type and kill this redundancy.)
*/
- if (ppgtt->pin_count++)
+ if (atomic_add_unless(>pin_count, 1, 0))
return 0;
+ if (mutex_lock_interruptible(>pin_mutex))
+ return -EINTR;
+
/*
* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
* size. We allocate at the top of the GTT to avoid fragmentation.
*/
- err = i915_vma_pin(ppgtt->vma,
- 0, GEN6_PD_ALIGN,
- PIN_GLOBAL | PIN_HIGH);
- if (err)
- goto unpin;
-
- return 0;
+ if (!atomic_read(>pin_count)) {
+ err = i915_vma_pin(ppgtt->vma,
+ 0, GEN6_PD_ALIGN,
+ PIN_GLOBAL | PIN_HIGH);
+ }
+ if (!err)
+ atomic_inc(>pin_count);
+ mutex_unlock(>pin_mutex);
-unpin:
- ppgtt->pin_count = 0;
return err;
}
@@ -1930,22 +1934,19 @@ void gen6_ppgtt_unpin(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- GEM_BUG_ON(!ppgtt->pin_count);
- if (--ppgtt->pin_count)
- return;
-
- i915_vma_unpin(ppgtt->vma);
+ GEM_BUG_ON(!atomic_read(>pin_count));
+ atomic_dec(>pin_count);
}
void gen6_ppgtt_unpin_all(struct i915_ppgtt *base)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
- if (!ppgtt->pin_count)
+ if (!atomic_read(>pin_count))
return;
- ppgtt->pin_count = 0;
i915_vma_unpin(ppgtt->vma);
+ atomic_set(>pin_count, 0);
}
static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
@@ -1958,6 +1959,8 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
+ mutex_init(>pin_mutex);
+
ppgtt_init(>base, >gt);
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 201788126a89..8fd2234ba0bf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -437,7 +437,9 @@ struct gen6_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
- unsigned int pin_count;
+ atomic_t pin_count;
+ struct mutex pin_mutex;
+
bool scan_for_unused_pt;
};
--
2.23.0
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[Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
This 3 non-atomic drivers all have the same function getting the
only encoder available in the connector, also atomic drivers have
this fallback. So moving it a common place and sharing between atomic
and non-atomic drivers.
While at it I also removed the mention of
drm_atomic_helper_best_encoder() that was renamed in
commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
drm_atomic_helper_best_encoder").
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Laurent Pinchart
Cc: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/ast/ast_mode.c | 12
drivers/gpu/drm/drm_atomic_helper.c | 15 ++-
drivers/gpu/drm/drm_connector.c | 11 +++
drivers/gpu/drm/drm_crtc_helper.c| 8 +++-
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
drivers/gpu/drm/udl/udl_connector.c | 8
include/drm/drm_modeset_helper_vtables.h | 6 +++---
8 files changed, 25 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index d349c721501c..eef95e1af06b 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct drm_encoder
*encoder)
kfree(encoder);
}
-
-static struct drm_encoder *ast_best_single_encoder(struct drm_connector
*connector)
-{
- int enc_id = connector->encoder_ids[0];
- /* pick the encoder ids */
- if (enc_id)
- return drm_encoder_find(connector->dev, NULL, enc_id);
- return NULL;
-}
-
-
static const struct drm_encoder_funcs ast_enc_funcs = {
.destroy = ast_encoder_destroy,
};
@@ -847,7 +836,6 @@ static void ast_connector_destroy(struct drm_connector
*connector)
static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
.mode_valid = ast_mode_valid,
.get_modes = ast_get_modes,
- .best_encoder = ast_best_single_encoder,
};
static const struct drm_connector_funcs ast_connector_funcs = {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 4706439fb490..9d7e4da6c292 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state
*state,
}
}
-/*
- * For connectors that support multiple encoders, either the
- * .atomic_best_encoder() or .best_encoder() operation must be implemented.
- */
-static struct drm_encoder *
-pick_single_encoder_for_connector(struct drm_connector *connector)
-{
- WARN_ON(connector->encoder_ids[1]);
- return drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[0]);
-}
-
static int handle_conflicting_encoders(struct drm_atomic_state *state,
bool disable_conflicting_encoders)
{
@@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
drm_atomic_state *state,
else if (funcs->best_encoder)
new_encoder = funcs->best_encoder(connector);
else
- new_encoder =
pick_single_encoder_for_connector(connector);
+ new_encoder =
drm_connector_get_single_encoder(connector);
if (new_encoder) {
if (encoder_mask & drm_encoder_mask(new_encoder)) {
@@ -359,7 +348,7 @@ update_connector_routing(struct drm_atomic_state *state,
else if (funcs->best_encoder)
new_encoder = funcs->best_encoder(connector);
else
- new_encoder = pick_single_encoder_for_connector(connector);
+ new_encoder = drm_connector_get_single_encoder(connector);
if (!new_encoder) {
DRM_DEBUG_ATOMIC("No suitable encoder found for
[CONNECTOR:%d:%s]\n",
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4c766624b20d..3e2a632cf861 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2334,3 +2334,14 @@ struct drm_tile_group *drm_mode_create_tile_group(struct
drm_device *dev,
return tg;
}
EXPORT_SYMBOL(drm_mode_create_tile_group);
+
+/*
+ * For connectors that support multiple encoders, either the
+ * .atomic_best_encoder() or .best_encoder() operation must be implemented.
+ */
+struct drm_encoder *
+drm_connector_get_single_encoder(struct drm_connector *connector)
+{
+ WARN_ON(connector->encoder_ids[1]);
+ return drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[0]);
+}
diff --git a/drivers/gpu/drm/drm_crtc_helper.c
b/drivers/gpu/drm/drm_crtc_helper.c
index a51824a7e7c1..a1f3c388e398 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -48,6 +48,8 @@
#include
#include
+#include "drm_crtc_internal.h"
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Don't mix srcu tag and negative error codes
== Series Details == Series: drm/i915: Don't mix srcu tag and negative error codes URL : https://patchwork.freedesktop.org/series/66524/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14357_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14357_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14357_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14357_full: ### IGT changes ### Possible regressions * igt@gem_vm_create@isolation: - shard-apl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl2/igt@gem_vm_cre...@isolation.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-apl5/igt@gem_vm_cre...@isolation.html Known issues Here are the changes found in Patchwork_14357_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@fifo-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb4/igt@gem_exec_sched...@fifo-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb7/igt@gem_exec_sched...@fifo-bsd2.html * igt@gem_exec_schedule@preempt-other-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb6/igt@gem_exec_sched...@preempt-other-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb4/igt@gem_exec_sched...@preempt-other-bsd.html * igt@kms_atomic_transition@plane-all-transition-fencing: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_atomic_transit...@plane-all-transition-fencing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb7/igt@kms_atomic_transit...@plane-all-transition-fencing.html * igt@kms_flip@flip-vs-fences-interruptible: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl4/igt@kms_f...@flip-vs-fences-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-apl3/igt@kms_f...@flip-vs-fences-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14357/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-kbl7/igt@kms_setm...@basic.html [22]:
[Intel-gfx] [PATCH v6 05/10] drm/i915/dsb: Check DSB engine status.
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 9e2927f869b9..b1da2b06263a 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,15 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xf
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..9188a0b53538 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11683,4 +11683,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2b0ffc0afb74..eea86afb0583 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -212,3 +212,45 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(>cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 9b2522f20bfb..7389c8c5b665 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -43,5 +43,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dbaa49f5c74..c77b5066d8dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11687,6 +11687,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
intel_gt_pm_wait_for_idle
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 19
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 22 ++---
drivers/gpu/drm/i915/i915_pmu.c | 120 +++
drivers/gpu/drm/i915/i915_pmu.h | 4 +-
5 files changed, 90 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 3bd764104d41..45a72cb698db 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -141,6 +141,21 @@ bool i915_gem_load_power_context(struct drm_i915_private
*i915)
return switch_to_kernel_context_sync(>gt);
}
+static void user_forcewake(struct intel_gt *gt, bool suspend)
+{
+ int count = atomic_read(>user_wakeref);
+
+ if (likely(!count))
+ return;
+
+ intel_gt_pm_get(gt);
+ if (suspend)
+ atomic_sub(count, >wakeref.count);
+ else
+ atomic_add(count, >wakeref.count);
+ intel_gt_pm_put(gt);
+}
+
void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("\n");
@@ -148,6 +163,8 @@ void i915_gem_suspend(struct drm_i915_private *i915)
intel_wakeref_auto(>ggtt.userfault_wakeref, 0);
flush_workqueue(i915->wq);
+ user_forcewake(>gt, true);
+
mutex_lock(>drm.struct_mutex);
/*
@@ -259,6 +276,8 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (!i915_gem_load_power_context(i915))
goto err_wedged;
+ user_forcewake(>gt, false);
+
out_unlock:
intel_uncore_forcewake_put(>uncore, FORCEWAKE_ALL);
mutex_unlock(>drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dc295c196d11..3039cef64b11 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -50,6 +50,7 @@ struct intel_gt {
} timelines;
struct intel_wakeref wakeref;
+ atomic_t user_wakeref;
struct list_head closed_vma;
spinlock_t closed_lock; /* guards the list of closed_vma */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 708855e051b5..f00c0dc4f57e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3988,13 +3988,12 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- file->private_data =
- (void *)(uintptr_t)intel_runtime_pm_get(>runtime_pm);
- intel_uncore_forcewake_user_get(>uncore);
+ atomic_inc(>user_wakeref);
+ intel_gt_pm_get(gt);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
return 0;
}
@@ -4002,13 +4001,12 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = >gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- intel_uncore_forcewake_user_put(>uncore);
- intel_runtime_pm_put(>runtime_pm,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_put(>uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>user_wakeref);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 8e251e719390..a3d3d3e39c15 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -116,19 +116,51 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
return enable;
}
+static u64 __get_rc6(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ u64 val;
+
+ val = intel_rc6_residency_ns(i915,
+IS_VALLEYVIEW(i915) ?
+VLV_GT_RENDER_RC6 :
+GEN6_GT_GFX_RC6);
+
+ if (HAS_RC6p(i915))
+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+
+ if (HAS_RC6pp(i915))
+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Skip busyness sampling when and where not needed
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14363
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/
Known issues
Here are the changes found in Patchwork_14363 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724] /
[fdo#111214])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([fdo#111514])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
* igt@kms_addfb_basic@invalid-set-prop-any:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@kms_addfb_ba...@invalid-set-prop-any.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@kms_addfb_ba...@invalid-set-prop-any.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6872 -> Patchwork_14363
CI-20190529: 20190529
CI_DRM_6872: b27acd37b7dedf49557d6e41a3ee046c3f5d99ba @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14363: 48733870bba853158fe3f7c529866078838f6198 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
48733870bba8 drm/i915/pmu: Skip busyness sampling when and where not needed
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14363/
___
Intel-gfx mailing list
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pmu: Skip busyness sampling when and where not needed
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48733870bba8 drm/i915/pmu: Skip busyness sampling when and where not needed
-:7: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit d0aa694b9239 ("drm/i915/pmu:
Always sample an active ringbuffer")'
#7:
Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer")
total: 1 errors, 0 warnings, 0 checks, 10 lines checked
___
Intel-gfx mailing list
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Re: [Intel-gfx] [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote: > On Tue, 10 Sep 2019, Manasi Navare wrote: > > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote: > >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote: > >> > On Sun, 08 Sep 2019, Manasi Navare wrote: > >> > > This patch series addresses all review comments and now the enable and > >> > > disable paths follow the method of obtaining slave states from master > >> > > and updating master-slaves in correct order during master modeset. > >> > > >> > Main high level question: what does it take to enable this on gen9+? > >> > >> As per the Bspec project platforms, the first platform that supports this > >> is > >> ICL > > > > Hi Jani, > > > > Apparently the Bspec caused some confusion, after double checking with the > > HW teams here, this feature is enabled starting BDW for the SST connectors > > and only the MST support is new to Gen 11+. > > > > So i guess I can change the patches to add support starting BDW and > > this should also fix the 5K tiled display issue that Ankit has been > > working on > > Thanks! I don't mind getting the patches merged for ICL+ at first, and > updating to cover older gens in follow-up. So you are suggesting that i keep the patches as is and have them get merged first and then i could change the GEN checks to add support for BDW+? Regards Manasi > > BR, > Jani. > > > > > > Manasi > > > >> > >> Regards > >> Manasi > >> > >> > > >> > BR, > >> > Jani. > >> > > >> > > >> > -- > >> > Jani Nikula, Intel Open Source Graphics Center > >> ___ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
== Series Details ==
Series: drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
URL : https://patchwork.freedesktop.org/series/66539/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14362
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/
Known issues
Here are the changes found in Patchwork_14362 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/fi-icl-u3/igt@prime_v...@basic-busy-default.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6872/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6872 -> Patchwork_14362
CI-20190529: 20190529
CI_DRM_6872: b27acd37b7dedf49557d6e41a3ee046c3f5d99ba @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14362: 59352cdaf9bc65842eaf5894d61e5047f1e2b345 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
59352cdaf9bc drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14362/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Skip busyness sampling when and where not needed
Quoting Tvrtko Ursulin (2019-09-11 17:07:30)
> From: Tvrtko Ursulin
>
> Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer")
> the cost of sampling the engine state on execlists platforms became a
> little bit higher when both engine busyness and one of the wait states are
> being monitored. (Previously the busyness sampling on legacy platforms was
> done via seqno comparison so there was no cost of mmio read.)
>
> We can avoid that by skipping busyness sampling when engine supports
> software busy stats and so avoid the cost of potential mmio read and
> sample accumulation.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 8e251e719390..623ad32303a1 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -194,6 +194,10 @@ engines_sample(struct intel_gt *gt, unsigned int
> period_ns)
> if (val & RING_WAIT_SEMAPHORE)
> add_sample(>sample[I915_SAMPLE_SEMA], period_ns);
>
> + /* No need to sample when busy stats are supported. */
> + if (intel_engine_supports_stats(engine))
> + goto skip;
> +
Reviewed-by: Chris Wilson
I was worried we were double accounting, but later on we
have
if (intel_engine_supports_stats())
val = ktime_to_ns(intel_engine_get_busy_time());
else
val = engine->pmu.sample[sample].cur;
so indeed, this is just wasted effort.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add INTEL_NUM_PIPES() and use it
== Series Details == Series: drm/i915: add INTEL_NUM_PIPES() and use it URL : https://patchwork.freedesktop.org/series/66520/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14355_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14355_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@fifo-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb6/igt@gem_exec_sched...@fifo-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb1/igt@gem_exec_sched...@fifo-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-apl3/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#109507]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl1/igt@kms_f...@flip-vs-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-skl9/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb3/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14355/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-kbl: [PASS][25] -> [FAIL][26] ([fdo#99912]) [25]:
[Intel-gfx] [PATCH] drm/i915/pmu: Skip busyness sampling when and where not needed
From: Tvrtko Ursulin
Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer")
the cost of sampling the engine state on execlists platforms became a
little bit higher when both engine busyness and one of the wait states are
being monitored. (Previously the busyness sampling on legacy platforms was
done via seqno comparison so there was no cost of mmio read.)
We can avoid that by skipping busyness sampling when engine supports
software busy stats and so avoid the cost of potential mmio read and
sample accumulation.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 8e251e719390..623ad32303a1 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -194,6 +194,10 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
if (val & RING_WAIT_SEMAPHORE)
add_sample(>sample[I915_SAMPLE_SEMA], period_ns);
+ /* No need to sample when busy stats are supported. */
+ if (intel_engine_supports_stats(engine))
+ goto skip;
+
/*
* While waiting on a semaphore or event, MI_MODE reports the
* ring as idle. However, previously using the seqno, and with
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
== Series Details == Series: drm/i915: Fix DRM_I915_DEBUG IOMMU stuff URL : https://patchwork.freedesktop.org/series/66539/ State : warning == Summary == $ dim checkpatch origin/drm-tip 59352cdaf9bc drm/i915: Fix DRM_I915_DEBUG IOMMU stuff -:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #20: /home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466: undefined reference to `free_cpu_cached_iovas' -:20: WARNING:USE_RELATIVE_PATH: use relative pathname instead of absolute in changelog text #20: /home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466: undefined reference to `free_cpu_cached_iovas' total: 0 errors, 2 warnings, 0 checks, 7 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for
tgl/bxt/glk
URL : https://patchwork.freedesktop.org/series/66537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6871 -> Patchwork_14361
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14361:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-threads:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-tgl-u/igt@gem_close_r...@basic-threads.html
Known issues
Here are the changes found in Patchwork_14361 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1
similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [PASS][4] -> [INCOMPLETE][5] ([fdo#107718])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][6] ([fdo#107713] / [fdo#109100]) ->
[PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [DMESG-WARN][8] ([fdo#107724]) -> [PASS][9] +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][10] ([fdo#111407]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][12] ([fdo#103167]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][14] ([fdo#103167]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6871/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14361/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 47)
--
Additional (1): fi-kbl-soraka
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6871 -> Patchwork_14361
CI-20190529: 20190529
CI_DRM_6871: f58f61f8f8a1137f3b4e2bf4af02d5f7694a0b2e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14361: 0e9dbe16b22854f6ff1450049b10a87581dfe2a7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0e9dbe16b228 drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
0edf73272516
Re: [Intel-gfx] [PATCH] drm/i915: Whitelist COMMON_SLICE_CHICKEN2
On Wednesday, September 11, 2019 1:00:51 AM PDT Chris Wilson wrote: > Quoting Chris Wilson (2019-09-11 08:42:22) > > Quoting Kenneth Graunke (2019-09-11 02:48:01) > > > This allows userspace to use "legacy" mode for push constants, where > > > they are committed at 3DPRIMITIVE or flush time, rather than being > > > committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11 > > > both use the "legacy" behavior - only Gen9 works in the "new" way. > > > > > > Conflating push constants with binding tables is painful for userspace, > > > we would like to be able to avoid doing so. > > > > > > Signed-off-by: Kenneth Graunke > > > Cc: sta...@vger.kernel.org > > Reviewed-by: Chris Wilson > > Pushed. Do you also want to do this for icl? > -Chris Thanks! I don't think it's necessary for ICL, the bit seems to be gone and it appears to perform the legacy behavior all the time. --Ken signature.asc Description: This is a digitally signed message part. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make i915_vma.flags atomic_t for mutex reduction
== Series Details == Series: drm/i915: Make i915_vma.flags atomic_t for mutex reduction URL : https://patchwork.freedesktop.org/series/66518/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14354_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14354_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb8/igt@gem_exec_sched...@wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl3/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-apl3/igt@i915_susp...@sysfs-reader.html * igt@kms_atomic_transition@plane-all-transition-fencing: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_atomic_transit...@plane-all-transition-fencing.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-iclb7/igt@kms_atomic_transit...@plane-all-transition-fencing.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#104873]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14354/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [24]:
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
On Wed, Sep 11, 2019 at 04:31:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reuse the same .modeset_calc_cdclk() function for all bxt+.
>
> The only difference in between the cnl/icl and the bxt variants
> is the call to cnl_compute_min_voltage_level(). We can do that call
> just fine on older platforms since they leave min_voltage_level[]
> zeroed. Let's rename the function to bxt_compute_min_voltage_level()
> just so it stays consistent with the rest of the naming scheme.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
> 1 file changed, 9 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f5a99eb77efa..b8b3814ba116 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> }
>
> /*
> + * Account for port clock min voltage level requirements.
> + * This only really does something on CNL+ but can be
> + * called on earlier platforms as well.
> + *
> * Note that this functions assumes that 0 is
> * the lowest voltage value, and higher values
> * correspond to increasingly higher voltages.
> @@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
> * future platforms this code will need to be
> * adjusted.
> */
> -static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
> +static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> - state->cdclk.logical.vco = vco;
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> -
> - if (!state->active_pipes) {
> - cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> - state->cdclk.actual.vco = vco;
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> - } else {
> - state->cdclk.actual = state->cdclk.logical;
> - }
> -
> - return 0;
> -}
> -
> -static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - int min_cdclk, cdclk, vco;
> -
> - min_cdclk = intel_compute_min_cdclk(state);
> - if (min_cdclk < 0)
> - return min_cdclk;
> -
> - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> state->cdclk.logical.voltage_level =
> max(dev_priv->display.calc_voltage_level(cdclk),
> - cnl_compute_min_voltage_level(state));
> + bxt_compute_min_voltage_level(state));
>
> if (!state->active_pipes) {
> cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> @@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> {
> if (IS_ELKHARTLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> dev_priv->cdclk.table = cnl_cdclk_table;
> } else if (IS_GEN9_LP(dev_priv)) {
> --
> 2.21.0
>
> ___
> Intel-gfx mailing
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Disable read-only support
Quoting Mika Kuoppala (2019-09-11 14:08:10)
> Chris Wilson writes:
>
> > The same read-only affliction as befell Icelake is affecting Tigerlake.
> > Disable the read-only support as cleary it was not fixed.
> >
> > Testcase: igt/i915_selftests/live_gem_context
> > References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for
> > gen11")
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
>
> Reviewed-by: Mika Kuoppala
Pushed, we can try again later, but for now this should remove one more
fail when Tigerlake comes back online. Provided it survives long enough
to run selftests.
-Chris
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
On Wed, 11 Sep 2019, Matt Roper wrote: > I'm confused why pre-merge CI flagged the results as a success if TGL > was hitting this? I didn't check the specifics, but the full set of IGT tests is only run on a limited number of platforms, and TGL is not yet one of them. You get the narrow range of tests on a wide range of platforms and the wide range of tests on a narrow range of platforms. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
Quoting Matt Roper (2019-09-11 16:00:44) > I'm confused why pre-merge CI flagged the results as a success if TGL > was hitting this? We've only just (Fri) got CI's Tigerlake surviving boot, so a second failure during boot would have been missed. For the summary report, Tigerlake is currently suppressed as it is not yet proven itself as being a stable result. (Which is a bit of a nuisance as you have to remind yourself to actually check the details.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel - A couple more fixes for v5.3, both cc: stable. drm-intel-fixes-2019-09-11: Final drm/i915 fixes for v5.3: - Fox DP MST high color depth regression - Fix GPU hangs on Vulkan compute workloads BR, Jani. The following changes since commit f74c2bb98776e2de508f4d607cd519873065118e: Linux 5.3-rc8 (2019-09-08 13:33:15 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-09-11 for you to fetch changes up to 2eb0964eec5f1d99f9eaf4963eee267acc72b615: drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ (2019-09-09 16:10:28 +0300) Final drm/i915 fixes for v5.3: - Fox DP MST high color depth regression - Fix GPU hangs on Vulkan compute workloads Chris Wilson (1): drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ Ville Syrjälä (1): drm/i915: Limit MST to <= 8bpc once again drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 - 2 files changed, 9 insertions(+), 6 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+
On Wed, Sep 11, 2019 at 04:31:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
> copy.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++
> 1 file changed, 2 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f59a6f775177..f5a99eb77efa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2227,39 +2227,6 @@ static int cnl_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> - state->cdclk.logical.vco = vco;
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> - max(cnl_calc_voltage_level(cdclk),
> - cnl_compute_min_voltage_level(state));
> -
> - if (!state->active_pipes) {
> - cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> - state->cdclk.actual.vco = vco;
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> - cnl_calc_voltage_level(cdclk);
> - } else {
> - state->cdclk.actual = state->cdclk.logical;
> - }
> -
> - return 0;
> -}
> -
> -static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - int min_cdclk, cdclk, vco;
> -
> - min_cdclk = intel_compute_min_cdclk(state);
> - if (min_cdclk < 0)
> - return min_cdclk;
> -
> - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> state->cdclk.logical.voltage_level =
> @@ -2499,12 +2466,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> {
> if (IS_ELKHARTLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_CANNONLAKE(dev_priv)) {
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
On Wed, Sep 11, 2019 at 04:31:27PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're forgetting to mask off all three pipe select bits from the
> CDCLK_CTL value on icl+ which may lead to the extra bit being
> left in. That will cause us to consider the current hardware
> cdclk state as invalid, and we proceed to sanitize it even
> though the hardware may have active pipes and whatnot.
>
> Fix up the mask so we get rid of all three pipe select bits
> and thus hopefully no longer sanitize cdclk when it's already
> correctly programmed.
>
> Cc: Matt Roper
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
> Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
I'm confused why pre-merge CI flagged the results as a success if TGL
was hitting this?
Matt
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 42 --
> 1 file changed, 23 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6b75d2a91cd9..f59a6f775177 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe
> pipe)
> +{
> + if (INTEL_GEN(dev_priv) >= 12) {
> + if (pipe == INVALID_PIPE)
> + return TGL_CDCLK_CD2X_PIPE_NONE;
> + else
> + return TGL_CDCLK_CD2X_PIPE(pipe);
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> + if (pipe == INVALID_PIPE)
> + return ICL_CDCLK_CD2X_PIPE_NONE;
> + else
> + return ICL_CDCLK_CD2X_PIPE(pipe);
> + } else {
> + if (pipe == INVALID_PIPE)
> + return BXT_CDCLK_CD2X_PIPE_NONE;
> + else
> + return BXT_CDCLK_CD2X_PIPE(pipe);
> + }
> +}
> +
> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_state *cdclk_state,
> enum pipe pipe)
> @@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> bxt_de_pll_enable(dev_priv, vco);
> }
>
> - val = divider | skl_cdclk_decimal(cdclk);
> -
> - if (INTEL_GEN(dev_priv) >= 12) {
> - if (pipe == INVALID_PIPE)
> - val |= TGL_CDCLK_CD2X_PIPE_NONE;
> - else
> - val |= TGL_CDCLK_CD2X_PIPE(pipe);
> - } else if (INTEL_GEN(dev_priv) >= 11) {
> - if (pipe == INVALID_PIPE)
> - val |= ICL_CDCLK_CD2X_PIPE_NONE;
> - else
> - val |= ICL_CDCLK_CD2X_PIPE(pipe);
> - } else {
> - if (pipe == INVALID_PIPE)
> - val |= BXT_CDCLK_CD2X_PIPE_NONE;
> - else
> - val |= BXT_CDCLK_CD2X_PIPE(pipe);
> - }
> + val = divider | skl_cdclk_decimal(cdclk) |
> + bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>
> /*
>* Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
>* dividers both synching to an active pipe, or asynchronously
>* (PIPE_NONE).
>*/
> - cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> + cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
>
> /* Make sure this is a legal cdclk value for the platform */
> cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] Power Management
On Wed, 11 Sep 2019, Robert Dinse wrote: > Can anyone tell me how to disable power management in the i915 > drivers? It appears enable_rc6 has been disabled? Why do you think you need it? See [1]. If you have issues, please file bugs at [2]. BR, Jani. [1] https://en.wikipedia.org/wiki/XY_problem [2] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI=DRM/Intel -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
> reference clock. So let's read out the ref clock before we
> try to compute the bypass clock.
>
> Cc: Matt Roper
> Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a93bad0a8..6b75d2a91cd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private
> *dev_priv,
> u32 divider;
> int div;
>
> + bxt_de_pll_readout(dev_priv, cdclk_state);
> +
> if (INTEL_GEN(dev_priv) >= 12)
> cdclk_state->bypass = cdclk_state->ref / 2;
> else if (INTEL_GEN(dev_priv) >= 11)
> @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private
> *dev_priv,
> else
> cdclk_state->bypass = cdclk_state->ref;
>
> - bxt_de_pll_readout(dev_priv, cdclk_state);
> if (cdclk_state->vco == 0) {
> cdclk_state->cdclk = cdclk_state->bypass;
> goto out;
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
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[Intel-gfx] Power Management
Can anyone tell me how to disable power management in the i915 drivers? It appears enable_rc6 has been disabled? -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Eskimo North Linux Friendly Internet Access, Shell Accounts, and Hosting. Knowledgeable human assistance, not telephone trees or script readers. See our web site: http://www.eskimo.com/ (206) 812-0051 or (800) 246-6874. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] dma-buf: change DMA-buf locking convention
Am 03.09.19 um 10:05 schrieb Daniel Vetter:
On Thu, Aug 29, 2019 at 04:29:14PM +0200, Christian König wrote:
This patch is a stripped down version of the locking changes
necessary to support dynamic DMA-buf handling.
For compatibility we cache the DMA-buf mapping as soon as
exporter/importer disagree on the dynamic handling.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 90 ---
include/linux/dma-buf.h | 51 +-
2 files changed, 133 insertions(+), 8 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 433d91d710e4..65052d52602b 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -525,6 +525,10 @@ struct dma_buf *dma_buf_export(const struct
dma_buf_export_info *exp_info)
return ERR_PTR(-EINVAL);
}
+ if (WARN_ON(exp_info->ops->cache_sgt_mapping &&
+ exp_info->ops->dynamic_mapping))
+ return ERR_PTR(-EINVAL);
+
if (!try_module_get(exp_info->owner))
return ERR_PTR(-ENOENT);
@@ -645,10 +649,11 @@ void dma_buf_put(struct dma_buf *dmabuf)
EXPORT_SYMBOL_GPL(dma_buf_put);
/**
- * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
+ * dma_buf_dynamic_attach - Add the device to dma_buf's attachments list;
optionally,
* calls attach() of dma_buf_ops to allow device-specific attach functionality
- * @dmabuf:[in]buffer to attach device to.
- * @dev: [in]device to be attached.
+ * @dmabuf:[in]buffer to attach device to.
+ * @dev: [in]device to be attached.
+ * @dynamic_mapping: [in]calling convention for map/unmap
*
* Returns struct dma_buf_attachment pointer for this attachment. Attachments
* must be cleaned up by calling dma_buf_detach().
@@ -662,8 +667,9 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
* accessible to @dev, and cannot be moved to a more suitable place. This is
* indicated with the error code -EBUSY.
*/
-struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
- struct device *dev)
+struct dma_buf_attachment *
+dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev,
+ bool dynamic_mapping)
{
struct dma_buf_attachment *attach;
int ret;
@@ -677,6 +683,7 @@ struct dma_buf_attachment *dma_buf_attach(struct dma_buf
*dmabuf,
attach->dev = dev;
attach->dmabuf = dmabuf;
+ attach->dynamic_mapping = dynamic_mapping;
mutex_lock(>lock);
@@ -685,16 +692,64 @@ struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
if (ret)
goto err_attach;
}
+ dma_resv_lock(dmabuf->resv, NULL);
list_add(>node, >attachments);
+ dma_resv_unlock(dmabuf->resv);
mutex_unlock(>lock);
+ /* When either the importer or the exporter can't handle dynamic
+* mappings we cache the mapping here to avoid issues with the
+* reservation object lock.
+*/
+ if (dma_buf_attachment_is_dynamic(attach) !=
+ dma_buf_is_dynamic(dmabuf)) {
+ struct sg_table *sgt;
+
+ if (dma_buf_is_dynamic(attach->dmabuf))
+ dma_resv_lock(attach->dmabuf->resv, NULL);
+
+ sgt = dmabuf->ops->map_dma_buf(attach, DMA_BIDIRECTIONAL);
Now we're back to enforcing DMA_BIDI, which works nicely around the
locking pain, but apparently upsets the arm-soc folks who want to control
this better.
Take another look at dma_buf_map_attachment(), we still try to get the
caching there for ARM.
What we do here is to bidirectionally map the buffer to avoid the
locking hydra when importer and exporter disagree on locking.
So the ARM folks can easily avoid that by switching to dynamic locking
for both.
Regards,
Christian.
That's why your previous version moved the caching into
map/unmap_sg, which resurrected the locking hydra.
I think we're going a bit in circles here, and I don't have a good idea
either :-/
-Daniel
+ if (!sgt)
+ sgt = ERR_PTR(-ENOMEM);
+ if (IS_ERR(sgt)) {
+ ret = PTR_ERR(sgt);
+ goto err_unlock;
+ }
+ if (dma_buf_is_dynamic(attach->dmabuf))
+ dma_resv_unlock(attach->dmabuf->resv);
+ attach->sgt = sgt;
+ attach->dir = DMA_BIDIRECTIONAL;
+ }
+
return attach;
err_attach:
kfree(attach);
mutex_unlock(>lock);
return ERR_PTR(ret);
+
+err_unlock:
+ if (dma_buf_is_dynamic(attach->dmabuf))
+ dma_resv_unlock(attach->dmabuf->resv);
+
+ dma_buf_detach(dmabuf, attach);
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(dma_buf_dynamic_attach);
+
+/**
+ * dma_buf_attach - Wrapper for
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Put glk_cdclk_table
== Series Details == Series: drm/i915/display: Put glk_cdclk_table URL : https://patchwork.freedesktop.org/series/66516/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14353_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14353_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@basic-hang-rcs0: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-hsw2/igt@gem_b...@basic-hang-rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-hsw1/igt@gem_b...@basic-hang-rcs0.html * igt@gem_ctx_switch@bcs0: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb2/igt@gem_ctx_swi...@bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-iclb7/igt@gem_ctx_swi...@bcs0.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-iclb5/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-b-tiling-x: - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-apl3/igt@kms_plane_low...@pipe-b-tiling-x.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-apl4/igt@kms_plane_low...@pipe-b-tiling-x.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-kbl7/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-kbl6/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#110728]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/shard-skl5/igt@p...@blocking.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14353/shard-skl8/igt@p...@blocking.html Possible fixes * igt@gem_ctx_isolation@vcs0-s3: - shard-skl: [INCOMPLETE][25] ([fdo#104108]) -> [PASS][26] [25]:
Re: [Intel-gfx] [PATCH] drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
On Wed, Sep 11, 2019 at 05:08:24PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 11, 2019 at 02:59:29PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-09-11 14:50:00)
> > > From: Ville Syrjälä
> > >
> > > We need to select IOMMU_SUPPORT as well, otherwise we can be left
> > > with:
> > > CONFIG_IOMMU_IOVA=m
> > > # CONFIG_IOMMU_SUPPORT is not set
> > > CONFIG_INTEL_IOMMU=y
> > >
> > > which complains:
> > > "WARNING: unmet direct dependencies detected for INTEL_IOMMU"
> > >
> > > and fails to link:
> > > ld: drivers/iommu/intel-iommu.o: in function `free_all_cpu_cached_iovas':
> > > /home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466:
> > > undefined reference to `free_cpu_cached_iovas'
> > > ...
> > >
> > > Or do we maybe want something like:
> > > select if IOMMU_SUPPORT
> > > instead?
> >
> > Hmm. My goal for DRM_I915_DEBUG was basically to dictate the
> > configuration options for CI. Now CI has entered a new era of git
> > itself, this could be reined back in I guess. But I still like having a
> > single option that enables a good set of debug options (that match what
> > CI does for convenience).
> >
> > > Cc: Chris Wilson
> > > Fixes: 02229acb3926 ("drm/i915: Force compilation with intel-iommu for CI
> > > validation")
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/Kconfig.debug | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/Kconfig.debug
> > > b/drivers/gpu/drm/i915/Kconfig.debug
> > > index c5c00cad6ba1..d940280df6b9 100644
> > > --- a/drivers/gpu/drm/i915/Kconfig.debug
> > > +++ b/drivers/gpu/drm/i915/Kconfig.debug
> > > @@ -22,6 +22,7 @@ config DRM_I915_DEBUG
> > > depends on DRM_I915
> > > select PCI_MSI
> > > select IOMMU_API
> > > + select IOMMU_SUPPORT
> >
> > Already in the updated
> > 41dfd5f67ae4 ("drm/i915: Force compilation with intel-iommu for CI
> > validation")
>
> That's not upstream though. So my build is still broken.
Bah. Never mind. It was more than two minutes since my last git fetch
so I was horribly out of date. Seems fine now.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Disable read-only support
== Series Details == Series: drm/i915/tgl: Disable read-only support URL : https://patchwork.freedesktop.org/series/66535/ State : success == Summary == CI Bug Log - changes from CI_DRM_6870 -> Patchwork_14360 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/ Known issues Here are the changes found in Patchwork_14360 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-short: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-icl-u3/igt@gem_mmap_...@basic-short.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-icl-u3/igt@gem_mmap_...@basic-short.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#08]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_reset: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([fdo#107709]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-bsw-kefka/igt@i915_selftest@live_reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-bsw-kefka/igt@i915_selftest@live_reset.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6870/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 Participating hosts (53 -> 45) -- Missing(8): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6870 -> Patchwork_14360 CI-20190529: 20190529 CI_DRM_6870: d478e765b0d1ceef82e602b69a92eeb344f741d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14360: 8f09708f48ffa421f03e54c19dfb56b499da5793 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8f09708f48ff drm/i915/tgl: Disable read-only support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14360/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
Quoting Ville Syrjälä (2019-09-11 15:08:24)
> > Already in the updated
> > 41dfd5f67ae4 ("drm/i915: Force compilation with intel-iommu for CI
> > validation")
>
> That's not upstream though. So my build is still broken.
It should be there. I checked in drm-tip. Could you double check if I've
somehow deluded myself?
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
On Wed, Sep 11, 2019 at 02:59:29PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-09-11 14:50:00)
> > From: Ville Syrjälä
> >
> > We need to select IOMMU_SUPPORT as well, otherwise we can be left
> > with:
> > CONFIG_IOMMU_IOVA=m
> > # CONFIG_IOMMU_SUPPORT is not set
> > CONFIG_INTEL_IOMMU=y
> >
> > which complains:
> > "WARNING: unmet direct dependencies detected for INTEL_IOMMU"
> >
> > and fails to link:
> > ld: drivers/iommu/intel-iommu.o: in function `free_all_cpu_cached_iovas':
> > /home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466:
> > undefined reference to `free_cpu_cached_iovas'
> > ...
> >
> > Or do we maybe want something like:
> > select if IOMMU_SUPPORT
> > instead?
>
> Hmm. My goal for DRM_I915_DEBUG was basically to dictate the
> configuration options for CI. Now CI has entered a new era of git
> itself, this could be reined back in I guess. But I still like having a
> single option that enables a good set of debug options (that match what
> CI does for convenience).
>
> > Cc: Chris Wilson
> > Fixes: 02229acb3926 ("drm/i915: Force compilation with intel-iommu for CI
> > validation")
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/Kconfig.debug | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/Kconfig.debug
> > b/drivers/gpu/drm/i915/Kconfig.debug
> > index c5c00cad6ba1..d940280df6b9 100644
> > --- a/drivers/gpu/drm/i915/Kconfig.debug
> > +++ b/drivers/gpu/drm/i915/Kconfig.debug
> > @@ -22,6 +22,7 @@ config DRM_I915_DEBUG
> > depends on DRM_I915
> > select PCI_MSI
> > select IOMMU_API
> > + select IOMMU_SUPPORT
>
> Already in the updated
> 41dfd5f67ae4 ("drm/i915: Force compilation with intel-iommu for CI
> validation")
That's not upstream though. So my build is still broken.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
Quoting Ville Syrjala (2019-09-11 14:50:00)
> From: Ville Syrjälä
>
> We need to select IOMMU_SUPPORT as well, otherwise we can be left
> with:
> CONFIG_IOMMU_IOVA=m
> # CONFIG_IOMMU_SUPPORT is not set
> CONFIG_INTEL_IOMMU=y
>
> which complains:
> "WARNING: unmet direct dependencies detected for INTEL_IOMMU"
>
> and fails to link:
> ld: drivers/iommu/intel-iommu.o: in function `free_all_cpu_cached_iovas':
> /home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466:
> undefined reference to `free_cpu_cached_iovas'
> ...
>
> Or do we maybe want something like:
> select if IOMMU_SUPPORT
> instead?
Hmm. My goal for DRM_I915_DEBUG was basically to dictate the
configuration options for CI. Now CI has entered a new era of git
itself, this could be reined back in I guess. But I still like having a
single option that enables a good set of debug options (that match what
CI does for convenience).
> Cc: Chris Wilson
> Fixes: 02229acb3926 ("drm/i915: Force compilation with intel-iommu for CI
> validation")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig.debug
> b/drivers/gpu/drm/i915/Kconfig.debug
> index c5c00cad6ba1..d940280df6b9 100644
> --- a/drivers/gpu/drm/i915/Kconfig.debug
> +++ b/drivers/gpu/drm/i915/Kconfig.debug
> @@ -22,6 +22,7 @@ config DRM_I915_DEBUG
> depends on DRM_I915
> select PCI_MSI
> select IOMMU_API
> + select IOMMU_SUPPORT
Already in the updated
41dfd5f67ae4 ("drm/i915: Force compilation with intel-iommu for CI validation")
-Chris
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[Intel-gfx] [PATCH] drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
From: Ville Syrjälä
We need to select IOMMU_SUPPORT as well, otherwise we can be left
with:
CONFIG_IOMMU_IOVA=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_INTEL_IOMMU=y
which complains:
"WARNING: unmet direct dependencies detected for INTEL_IOMMU"
and fails to link:
ld: drivers/iommu/intel-iommu.o: in function `free_all_cpu_cached_iovas':
/home/vsyrjala/src/linux/build_skl/../drivers/iommu/intel-iommu.c:4466:
undefined reference to `free_cpu_cached_iovas'
...
Or do we maybe want something like:
select if IOMMU_SUPPORT
instead?
Cc: Chris Wilson
Fixes: 02229acb3926 ("drm/i915: Force compilation with intel-iommu for CI
validation")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index c5c00cad6ba1..d940280df6b9 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -22,6 +22,7 @@ config DRM_I915_DEBUG
depends on DRM_I915
select PCI_MSI
select IOMMU_API
+ select IOMMU_SUPPORT
select IOMMU_IOVA
select NEED_DMA_MAP_STATE
select DMAR_TABLE
--
2.21.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Disable read-only support
== Series Details ==
Series: drm/i915/tgl: Disable read-only support
URL : https://patchwork.freedesktop.org/series/66535/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f09708f48ff drm/i915/tgl: Disable read-only support
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for gen11")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3936867dbc1e ("drm/i915: Disable
read only ppgtt support for gen11")'
#10:
References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for gen11")
total: 1 errors, 1 warnings, 0 checks, 11 lines checked
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[Intel-gfx] [PATCH i-g-t] i915/gem_exec_whisper: Disable preparser around self-modifications
Our "whisper" consists of writing the secret value given to us by our
predecessors into the next batch, i.e. we are modifying on the GPU the
chain of inflight batches. As the preparser on gen12 will read the batch
instructions ahead of time, we need to disable it around the
self-modifications.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
tests/i915/gem_exec_whisper.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index de7a14dad..43b716e7c 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -166,6 +166,11 @@ static void ctx_set_random_priority(int fd, uint32_t ctx)
gem_context_set_priority(fd, ctx, prio);
}
+static uint32_t preparser_disable(bool state)
+{
+ return 0x5 << 23 | 1 << 8 | state; /* custom MI_ARB_CHECK */
+}
+
static void whisper(int fd, unsigned engine, unsigned flags)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -259,6 +264,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
loc = 8;
if (gen >= 4)
loc += 4;
+ if (gen >= 12)
+ loc += 1;
reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
@@ -280,6 +287,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
}
i = 0;
+ if (gen >= 12)
+ batch[i++] = preparser_disable(true);
batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
if (gen >= 8) {
batch[++i] = store.offset + loc;
@@ -293,6 +302,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
}
batch[++i] = 0xc0ffee;
igt_assert(loc == sizeof(uint32_t) * i);
+ if (gen >= 12)
+ batch[++i] = preparser_disable(false);
batch[++i] = MI_BATCH_BUFFER_END;
if (flags & CONTEXTS) {
--
2.23.0
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[Intel-gfx] [PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
From: Ville Syrjälä
On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.
Cc: Matt Roper
Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 618a93bad0a8..6b75d2a91cd9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
u32 divider;
int div;
+ bxt_de_pll_readout(dev_priv, cdclk_state);
+
if (INTEL_GEN(dev_priv) >= 12)
cdclk_state->bypass = cdclk_state->ref / 2;
else if (INTEL_GEN(dev_priv) >= 11)
@@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
else
cdclk_state->bypass = cdclk_state->ref;
- bxt_de_pll_readout(dev_priv, cdclk_state);
if (cdclk_state->vco == 0) {
cdclk_state->cdclk = cdclk_state->bypass;
goto out;
--
2.21.0
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[Intel-gfx] [PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
From: Ville Syrjälä
Reuse the same .modeset_calc_cdclk() function for all bxt+.
The only difference in between the cnl/icl and the bxt variants
is the call to cnl_compute_min_voltage_level(). We can do that call
just fine on older platforms since they leave min_voltage_level[]
zeroed. Let's rename the function to bxt_compute_min_voltage_level()
just so it stays consistent with the rest of the naming scheme.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 9 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f5a99eb77efa..b8b3814ba116 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct
intel_atomic_state *state)
}
/*
+ * Account for port clock min voltage level requirements.
+ * This only really does something on CNL+ but can be
+ * called on earlier platforms as well.
+ *
* Note that this functions assumes that 0 is
* the lowest voltage value, and higher values
* correspond to increasingly higher voltages.
@@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct
intel_atomic_state *state)
* future platforms this code will need to be
* adjusted.
*/
-static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
+static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct
intel_atomic_state *state)
cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- state->cdclk.logical.vco = vco;
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
-
- if (!state->active_pipes) {
- cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
- state->cdclk.actual.vco = vco;
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
- } else {
- state->cdclk.actual = state->cdclk.logical;
- }
-
- return 0;
-}
-
-static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- int min_cdclk, cdclk, vco;
-
- min_cdclk = intel_compute_min_cdclk(state);
- if (min_cdclk < 0)
- return min_cdclk;
-
- cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
state->cdclk.logical.vco = vco;
state->cdclk.logical.cdclk = cdclk;
state->cdclk.logical.voltage_level =
max(dev_priv->display.calc_voltage_level(cdclk),
- cnl_compute_min_voltage_level(state));
+ bxt_compute_min_voltage_level(state));
if (!state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
{
if (IS_ELKHARTLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_CANNONLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
dev_priv->cdclk.table = cnl_cdclk_table;
} else if (IS_GEN9_LP(dev_priv)) {
--
2.21.0
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[Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation
From: Ville Syrjälä
We're forgetting to mask off all three pipe select bits from the
CDCLK_CTL value on icl+ which may lead to the extra bit being
left in. That will cause us to consider the current hardware
cdclk state as invalid, and we proceed to sanitize it even
though the hardware may have active pipes and whatnot.
Fix up the mask so we get rid of all three pipe select bits
and thus hopefully no longer sanitize cdclk when it's already
correctly programmed.
Cc: Matt Roper
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641
Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 42 --
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6b75d2a91cd9..f59a6f775177 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1464,6 +1464,26 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private
*dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe
pipe)
+{
+ if (INTEL_GEN(dev_priv) >= 12) {
+ if (pipe == INVALID_PIPE)
+ return TGL_CDCLK_CD2X_PIPE_NONE;
+ else
+ return TGL_CDCLK_CD2X_PIPE(pipe);
+ } else if (INTEL_GEN(dev_priv) >= 11) {
+ if (pipe == INVALID_PIPE)
+ return ICL_CDCLK_CD2X_PIPE_NONE;
+ else
+ return ICL_CDCLK_CD2X_PIPE(pipe);
+ } else {
+ if (pipe == INVALID_PIPE)
+ return BXT_CDCLK_CD2X_PIPE_NONE;
+ else
+ return BXT_CDCLK_CD2X_PIPE(pipe);
+ }
+}
+
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state,
enum pipe pipe)
@@ -1534,24 +1554,8 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
bxt_de_pll_enable(dev_priv, vco);
}
- val = divider | skl_cdclk_decimal(cdclk);
-
- if (INTEL_GEN(dev_priv) >= 12) {
- if (pipe == INVALID_PIPE)
- val |= TGL_CDCLK_CD2X_PIPE_NONE;
- else
- val |= TGL_CDCLK_CD2X_PIPE(pipe);
- } else if (INTEL_GEN(dev_priv) >= 11) {
- if (pipe == INVALID_PIPE)
- val |= ICL_CDCLK_CD2X_PIPE_NONE;
- else
- val |= ICL_CDCLK_CD2X_PIPE(pipe);
- } else {
- if (pipe == INVALID_PIPE)
- val |= BXT_CDCLK_CD2X_PIPE_NONE;
- else
- val |= BXT_CDCLK_CD2X_PIPE(pipe);
- }
+ val = divider | skl_cdclk_decimal(cdclk) |
+ bxt_cdclk_cd2x_pipe(dev_priv, pipe);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1620,7 +1624,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv)
* dividers both synching to an active pipe, or asynchronously
* (PIPE_NONE).
*/
- cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
+ cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
/* Make sure this is a legal cdclk value for the platform */
cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
--
2.21.0
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[Intel-gfx] [PATCH 3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+
From: Ville Syrjälä
The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
copy.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f59a6f775177..f5a99eb77efa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2227,39 +2227,6 @@ static int cnl_modeset_calc_cdclk(struct
intel_atomic_state *state)
cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- state->cdclk.logical.vco = vco;
- state->cdclk.logical.cdclk = cdclk;
- state->cdclk.logical.voltage_level =
- max(cnl_calc_voltage_level(cdclk),
- cnl_compute_min_voltage_level(state));
-
- if (!state->active_pipes) {
- cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
- state->cdclk.actual.vco = vco;
- state->cdclk.actual.cdclk = cdclk;
- state->cdclk.actual.voltage_level =
- cnl_calc_voltage_level(cdclk);
- } else {
- state->cdclk.actual = state->cdclk.logical;
- }
-
- return 0;
-}
-
-static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- int min_cdclk, cdclk, vco;
-
- min_cdclk = intel_compute_min_cdclk(state);
- if (min_cdclk < 0)
- return min_cdclk;
-
- cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
state->cdclk.logical.vco = vco;
state->cdclk.logical.cdclk = cdclk;
state->cdclk.logical.voltage_level =
@@ -2499,12 +2466,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
{
if (IS_ELKHARTLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+ dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
+ dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_CANNONLAKE(dev_priv)) {
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915: Fix memory type read in bandwidth calc
On Tue, Sep 10, 2019 at 07:56:51AM -0700, James Ausmus wrote: > The returned memory value does not align with BSpec - update to correct > this. Hrm. The values came directly from "IceLake PCODE/Punit Mailboxes MAS" .doc. The question is which documentation is more correct? > > BSpec: 54023 > > Cc: Ville Syrjälä > Signed-off-by: James Ausmus > --- > drivers/gpu/drm/i915/display/intel_bw.c | 14 +- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c > b/drivers/gpu/drm/i915/display/intel_bw.c > index 688858ebe4d0..af9b849c2c3e 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -39,15 +39,19 @@ static int icl_pcode_read_mem_global_info(struct > drm_i915_private *dev_priv, > case 0: > qi->dram_type = INTEL_DRAM_DDR4; > break; > - case 1: > - qi->dram_type = INTEL_DRAM_DDR3; > + case 3: > + qi->dram_type = INTEL_DRAM_LPDDR4; > break; > - case 2: > - qi->dram_type = INTEL_DRAM_LPDDR3; > + case 4: > + qi->dram_type = INTEL_DRAM_DDR3; > break; > - case 3: > + case 5: > qi->dram_type = INTEL_DRAM_LPDDR3; > break; > + case 1: > + case 2: > + /* Unimplemented */ > + /* fall through */ > default: > MISSING_CASE(val & 0xf); > break; > -- > 2.22.1 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] USB-C
On Mon, 09 Sep 2019, nnet wrote: > Searching on the kernel warnings and errors didn't bring it up, but in > browsing bugzilla I stumbled on this. > > Bug 111501 - [CFL] Kernel 5.3.0-rc6: i915 fails at typec_displayport > 5120x1440 > https://bugs.freedesktop.org/show_bug.cgi?id=111501 > > It's the same monitor and connection type. > > Is the related patchset intended for 5.3 then? > https://patchwork.freedesktop.org/series/66286/ > > Thanks > > On Mon, Sep 9, 2019, at 10:06 AM, nnet wrote: >> Hello, >> >> 5.2.13 is working fine (great) still with a Dell U4919DW connected via >> USB-C from a X1 Carbon Gen 6. >> >> 5.3-rc8 so far is not (blank screen) and errors: >> >> https://pastebin.com/tXFi6AfK >> >> Seems there has been some refactoring for just this kind of connection in >> 5.3? >> >> Is there perhaps and issue since for this scenario or are other >> components at fault perhaps (ACPI / mutter)? Please check if the patches on the bug help you, and follow-up on the bug. Thanks. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Disable read-only support
Chris Wilson writes:
> The same read-only affliction as befell Icelake is affecting Tigerlake.
> Disable the read-only support as cleary it was not fixed.
>
> Testcase: igt/i915_selftests/live_gem_context
> References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for
> gen11")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e4f66bfe74c2..a09a9b62afbe 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1486,8 +1486,10 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
> drm_i915_private *i915)
>*
>* Gen11 has HSDES#:1807136187 unresolved. Disable ro support
>* for now.
> + *
> + * Gen12 has inherited the same read-only fault issue from gen11.
>*/
> - ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11;
> + ppgtt->vm.has_read_only = !IS_GEN_RANGE(i915, 11, 12);
>
> /* There are only few exceptions for gen >=6. chv and bxt.
>* And we are not sure about the latter so play safe for now.
> --
> 2.23.0
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[Intel-gfx] [PATCH] drm/i915/tgl: Disable read-only support
The same read-only affliction as befell Icelake is affecting Tigerlake.
Disable the read-only support as cleary it was not fixed.
Testcase: igt/i915_selftests/live_gem_context
References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for gen11")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e4f66bfe74c2..a09a9b62afbe 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1486,8 +1486,10 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
*
* Gen11 has HSDES#:1807136187 unresolved. Disable ro support
* for now.
+*
+* Gen12 has inherited the same read-only fault issue from gen11.
*/
- ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11;
+ ppgtt->vm.has_read_only = !IS_GEN_RANGE(i915, 11, 12);
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
--
2.23.0
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Re: [Intel-gfx] [PATCH] drm/i915/display: Put glk_cdclk_table
Quoting Ville Syrjälä (2019-09-11 11:36:53)
> On Wed, Sep 11, 2019 at 08:47:27AM +0100, Chris Wilson wrote:
> > Commit 736da8112fee ("drm/i915: Use literal representation of cdclk
> > tables") pushed the cdclk logic into tables, adding glk_cdclk_table but
> > not using yet:
> >
> > drivers/gpu/drm/i915/display/intel_cdclk.c:1173:38: error:
> > ‘glk_cdclk_table’ defined but not used [-Werror=unused-const-variable=]
> >
> > Fixes: 736da8112fee ("drm/i915: Use literal representation of cdclk tables")
> > Signed-off-by: Chris Wilson
> > Cc: Ville Syrjälä
> > Cc: Matt Roper
> > Cc: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 618a93bad0a8..13779b6029f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2511,7 +2511,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> > *dev_priv)
> > dev_priv->display.set_cdclk = bxt_set_cdclk;
> > dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> > dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
> > - dev_priv->cdclk.table = bxt_cdclk_table;
> > + if (IS_GEMINILAKE(dev_priv))
> > + dev_priv->cdclk.table = glk_cdclk_table;
> > + else
> > + dev_priv->cdclk.table = bxt_cdclk_table;
>
> Whoops.
>
> Reviewed-by: Ville Syrjälä
Pushed to silence the compiler. I'll let Matt check if this was all that
was truly required :)
-Chris
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Re: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well
On 2019-09-11 at 11:21:42 +0300, Imre Deak wrote:
> On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> > Hi Imre,
> > Thanks for reviewing the pacthes i will rework the patches.
> > There are few comments from my side which will help to rework.
> > > > Add max_dc_state and tgl_set_target_dc_state() API
> > > > in order to enable DC3CO state with existing DC states.
> > > > max_dc_state will enable/disable the desired DC state in
> > > > DC_STATE_EN reg when "DC Off" power well gets disable/enable.
> > > >
> > > > v2: commit log improvement.
> > > > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > > > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > > > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > > > to a appropriate place haswell_crtc_enable(). [Imre]
> > > > Changed the DC3CO power well enabled call back logic as
> > > > recommended in review comments. [Imre]
> > > > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > > > v5: using udelay() instead of waiting for DC3CO exit status.
> > > > v6: Fixed minor unwanted change.
> > > > v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
> > > >
> > > > Cc: Jani Nikula
> > > > Cc: Imre Deak
> > > > Cc: Animesh Manna
> > > > Signed-off-by: Anshuman Gupta
> > > > ---
> > > > .../drm/i915/display/intel_display_power.c| 111 ++
> > > > .../drm/i915/display/intel_display_power.h| 3 +
> > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > 3 files changed, 95 insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 496fa1b53ffb..83b10f61ee42 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct
> > > > drm_i915_private *dev_priv, u32 state)
> > > > dev_priv->csr.dc_state = val & mask;
> > > > }
> > > >
> > > > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > >
> > > Should be tgl_enable_dc3co(), to match the rest of DC state helpers.
> > >
> > > > +{
> > > > + if (!dev_priv->psr.sink_psr2_support)
> > > > + return;
> > >
> > > PSR knows when to enable DC3co, so no need to double-check that here.
> > >
> > > > +
> > > > + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> > >
> > > This check is out-of-place wrt. the same checks for other DC states.
> > >
> > > > + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > > +}
> > > > +
> > > > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > > > +{
> > > > + u32 val;
> > > > +
> > > > + val = I915_READ(DC_STATE_EN);
> > > > + val &= ~DC_STATE_DC3CO_STATUS;
> > > > + I915_WRITE(DC_STATE_EN, val);
> > > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > + /*
> > > > +* Delay of 200us DC3CO Exit time B.Spec 49196
> > > > +*/
> > > > + udelay(200);
> > > > +}
> > > > +
> > > > static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > > {
> > > > assert_can_enable_dc9(dev_priv);
> > > > @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct
> > > > drm_i915_private *dev_priv)
> > > > static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> > > > *dev_priv,
> > > >struct i915_power_well
> > > > *power_well)
> > > > {
> > > > - return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> > > > == 0;
> > > > + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> > > > + (I915_READ(DC_STATE_EN) &
> > > > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> > > > }
> > > >
> > > > static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> > > > @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct
> > > > drm_i915_private *dev_priv)
> > > > {
> > > > struct intel_cdclk_state cdclk_state = {};
> > > >
> > > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > + if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
> > > > + tgl_disallow_dc3co(dev_priv);
> > > > + } else {
> > >
> > > With an early return you can avoid the extra diff and make reviewing
> > > easier.
> > >
> > > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > >
> > > > - dev_priv->display.get_cdclk(dev_priv, _state);
> > > > - /* Can't read out voltage_level so can't use
> > > > intel_cdclk_changed() */
> > > > - WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw,
> > > > _state));
> > > > +
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Squeeze iommu status into debugfs/i915_capabilities
== Series Details == Series: drm/i915: Squeeze iommu status into debugfs/i915_capabilities URL : https://patchwork.freedesktop.org/series/66530/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14359 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/ Known issues Here are the changes found in Patchwork_14359 that come from known issues: ### IGT changes ### Issues hit * igt@kms_addfb_basic@addfb25-y-tiled: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u3/igt@kms_addfb_ba...@addfb25-y-tiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/fi-icl-u3/igt@kms_addfb_ba...@addfb25-y-tiled.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [PASS][3] -> [FAIL][4] ([fdo#103167]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@prime_vgem@basic-gtt: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u3/igt@prime_v...@basic-gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/fi-icl-u3/igt@prime_v...@basic-gtt.html Warnings * igt@i915_pm_rpm@module-reload: - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713] / [fdo#108840]) -> [DMESG-WARN][8] ([fdo#110595]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u2/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/fi-icl-u2/igt@i915_pm_...@module-reload.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595 Participating hosts (53 -> 46) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6868 -> Patchwork_14359 CI-20190529: 20190529 CI_DRM_6868: fb9bbe42526c1a8467c99f8137ed6b94c749681f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14359: aeb118dbe7755b8963de83ce6b778c2db2d1468b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aeb118dbe775 drm/i915: Squeeze iommu status into debugfs/i915_capabilities == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14359/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Squeeze iommu status into debugfs/i915_capabilities
Quoting Martin Peres (2019-09-11 13:19:06) > > > On 11/09/2019 14:46, Chris Wilson wrote: > > There's no easy way of checking whether iommu is enabled for the GPU > > (you can grep dmesg if you know the device, or you can grep > > i915_gpu_info if that's available). We do have a central > > i915_capabilities with the intent of listing such pertinent information, > > so add the iommu status. > > > > Suggested-by: Martin Peres > > Signed-off-by: Chris Wilson > > Cc: Martin Peres > > Cc: Tomi Sarvela > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 7 +++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > b/drivers/gpu/drm/i915/i915_debugfs.c > > index 708855e051b5..e5835337f022 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -61,11 +61,18 @@ static int i915_capabilities(struct seq_file *m, void > > *data) > > struct drm_i915_private *dev_priv = node_to_i915(m->private); > > const struct intel_device_info *info = INTEL_INFO(dev_priv); > > struct drm_printer p = drm_seq_file_printer(m); > > + const char *msg; > > > > seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); > > seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); > > seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); > > > > + msg = "n/a"; > > Here, "n/a" really means "kernel not compiled with IOMMU support". > Should we find a wording better explaining this to users? Or are we > going to tell users to check their dmesg for IOMMU messages and if there > are none, it means either the kernel has not been compiled with support > for it, or an option needs to be enabled in the bios, or the platform > lacks support? Users? This is debugfs, we should not be having users! :) So whatever is convenient, just a string is slightly nicer for humans than having -1, 0, 1. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: fix spelling mistake "resseting" -> "resetting"
== Series Details == Series: drm/i915/gvt: fix spelling mistake "resseting" -> "resetting" URL : https://patchwork.freedesktop.org/series/66529/ State : success == Summary == CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14358 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/ Known issues Here are the changes found in Patchwork_14358 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-read-write-distinct: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([fdo#111514]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@prime_vgem@basic-gtt: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u3/igt@prime_v...@basic-gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/fi-icl-u3/igt@prime_v...@basic-gtt.html Warnings * igt@i915_pm_rpm@module-reload: - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713] / [fdo#108840]) -> [DMESG-WARN][8] ([fdo#110595]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6868/fi-icl-u2/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/fi-icl-u2/igt@i915_pm_...@module-reload.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595 [fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514 Participating hosts (53 -> 46) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6868 -> Patchwork_14358 CI-20190529: 20190529 CI_DRM_6868: fb9bbe42526c1a8467c99f8137ed6b94c749681f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5178: efb4539494d94f03374874d3b61bd04ef3802aaa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14358: 58c43117342b119d610d98c62c352bba4899b877 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 58c43117342b drm/i915/gvt: fix spelling mistake "resseting" -> "resetting" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14358/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Squeeze iommu status into debugfs/i915_capabilities
On 11/09/2019 14:46, Chris Wilson wrote: > There's no easy way of checking whether iommu is enabled for the GPU > (you can grep dmesg if you know the device, or you can grep > i915_gpu_info if that's available). We do have a central > i915_capabilities with the intent of listing such pertinent information, > so add the iommu status. > > Suggested-by: Martin Peres > Signed-off-by: Chris Wilson > Cc: Martin Peres > Cc: Tomi Sarvela > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_debugfs.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index 708855e051b5..e5835337f022 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -61,11 +61,18 @@ static int i915_capabilities(struct seq_file *m, void > *data) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > const struct intel_device_info *info = INTEL_INFO(dev_priv); > struct drm_printer p = drm_seq_file_printer(m); > + const char *msg; > > seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); > seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); > seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); > > + msg = "n/a"; Here, "n/a" really means "kernel not compiled with IOMMU support". Should we find a wording better explaining this to users? Or are we going to tell users to check their dmesg for IOMMU messages and if there are none, it means either the kernel has not been compiled with support for it, or an option needs to be enabled in the bios, or the platform lacks support? Anyway, thanks! Acked-by: Martin Peres > +#ifdef CONFIG_INTEL_IOMMU > + msg = enableddisabled(intel_iommu_gfx_mapped); > +#endif > + seq_printf(m, "iommu: %s\n", msg); > + > intel_device_info_dump_flags(info, ); > intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), ); > intel_driver_caps_print(_priv->caps, ); > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] FW: [PATCH 1/5] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
Quoting Balestrieri, Francesco (2019-09-11 13:03:25) > On 04/09/2019, 13.33, "Intel-gfx on behalf of Daniel Vetter" > wrote: > > On Mon, Aug 26, 2019 at 2:21 PM Abdiel Janulgue > > - ret = create_mmap_offset(obj); > > - if (ret == 0) > > - *offset = drm_vma_node_offset_addr(>base.vma_node); > > + mmo = kzalloc(sizeof(*mmo), GFP_KERNEL); > > I got thrown off a bunch of times here reading the code, but I think I > got this right now. > > Why exactly do we want multiple vma offsets? Yes this makes it a > drop-in replacement for the old cpu mmap ioctl, which was a bit > dubious design. But if we go all new here, I really wonder about why > this is necessary. No other discrete driver needs this, they all fix > the mmap mode for the lifetime of an object, because flushing stuff is > as expensive as just reallocating (or at least close enough). > > I think us going once again our separate route here needs a lot more > justification than just "we've accidentally ended up with uapi like > this 10 years ago". That's exactly the whole point, to replace the uapi we accidentally ended up with 10 years ago with the api that doesn't cause valgrind to complain, is easily extensible and supports all legacy usecases which should be a very good position to be in to support unknown future usecases as well. Letting userspace control their mmapings is very powerful, and we definitely do not want to be limiting their flexibility. That no other driver even seems to allow multiple mmaps, and so has not developed a desire to manage multiple vma per object does not seem to be a reason to limit ourselves. The infrastructure all supports it; the only thing that is at odds is the desire to force the lowest common denominator as the defacto standard. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/userptr: Beware recursive lock_page()
On 11/09/2019 12:38, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-09-11 12:31:32) On 09/09/2019 14:52, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-07-26 14:38:40) On 17/07/2019 21:09, Tvrtko Ursulin wrote: On 17/07/2019 15:06, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-07-17 14:46:15) On 17/07/2019 14:35, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-07-17 14:23:55) On 17/07/2019 14:17, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-07-17 14:09:00) On 16/07/2019 16:37, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-07-16 16:25:22) On 16/07/2019 13:49, Chris Wilson wrote: Following a try_to_unmap() we may want to remove the userptr and so call put_pages(). However, try_to_unmap() acquires the page lock and so we must avoid recursively locking the pages ourselves -- which means that we cannot safely acquire the lock around set_page_dirty(). Since we can't be sure of the lock, we have to risk skip dirtying the page, or else risk calling set_page_dirty() without a lock and so risk fs corruption. So if trylock randomly fail we get data corruption in whatever data set application is working on, which is what the original patch was trying to avoid? Are we able to detect the backing store type so at least we don't risk skipping set_page_dirty with anonymous/shmemfs? page->mapping??? Would page->mapping work? What is it telling us? It basically tells us if there is a fs around; anything that is the most basic of malloc (even tmpfs/shmemfs has page->mapping). Normal malloc so anonymous pages? Or you meant everything _apart_ from the most basic malloc? Aye missed the not. We still have the issue that if there is a mapping we should be taking the lock, and we may have both a mapping and be inside try_to_unmap(). Is this a problem? On a path with mappings we trylock and so solve the set_dirty_locked and recursive deadlock issues, and with no mappings with always dirty the page and avoid data corruption. The problem as I see it is !page->mapping are likely an insignificant minority of userptr; as I think even memfd are essentially shmemfs (or hugetlbfs) and so have mappings. Better then nothing, no? If easy to do.. Actually, I erring on the opposite side. Peeking at mm/ internals does not bode confidence and feels indefensible. I'd much rather throw my hands up and say "this is the best we can do with the API provided, please tell us what we should have done." To which the answer is probably to not have used gup in the first place :| """ /* * set_page_dirty() is racy if the caller has no reference against * page->mapping->host, and if the page is unlocked. This is because another * CPU could truncate the page off the mapping and then free the mapping. * * Usually, the page _is_ locked, or the caller is a user-space process which * holds a reference on the inode by having an open file. * * In other cases, the page should be locked before running set_page_dirty(). */ int set_page_dirty_lock(struct page *page) """ Could we hold a reference to page->mapping->host while having pages and then would be okay to call plain set_page_dirty? We would then be hitting the warnings in ext4 for unlocked pages again. Ah true.. Essentially the argument is whether or not that warn is valid, to which I think requires inner knowledge of vfs + ext4. To hold a reference on the host would require us tracking page->mapping (reasonable since we already hooked into mmu and so will get an invalidate + fresh gup on any changes), plus iterating over all to acquire the extra reference if applicable -- and I have no idea what the side-effects of that would be. Could well be positive side-effects. Just feels like wandering even further off the beaten path without a map. Good news hmm is just around the corner (which will probably prohibit this use-case) :| ... can we reach out to someone more knowledgeable in mm matters to recommend us what to do? Regards, Tvrtko Just a reminder to not let this slip. We run into userptr bugs in CI quite regularly. Remind away. Revert or trylock, there doesn't seem to be a good answer. Rock and a hard place. Data corruption for userptr users (with either trylock or no lock) or a deadlock (with the lock). I honestly can't decide what is worse. Tiny preference to deadlock rather than silent corruption. Misguided? Don't know really.. The deadlock is pretty easy to hit as soon as the system is under mempressure and it tries to free pages as we do the userptr gup... (Hah, easy in theory, but not in CI.) I know what's the answer! Push the policy to userspace! :D echo 1 > /sys/class/drm/card0/userptr_corrupt_or_deadlock Am I joking or not? Wish I knew! :) Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
