== Series Details ==
Series: drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
URL : https://patchwork.freedesktop.org/series/67850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7056_full -> Patchwork_14749_full
== Series Details ==
Series: Small fixes before fixing MST
URL : https://patchwork.freedesktop.org/series/67883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7060 -> Patchwork_14763
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Small fixes before fixing MST
URL : https://patchwork.freedesktop.org/series/67883/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: simplify setting of ddi_io_power_domain
Okay!
Commit: drm/i915: cleanup unused
== Series Details ==
Series: Small fixes before fixing MST
URL : https://patchwork.freedesktop.org/series/67883/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0fdcd1fc0932 drm/i915: simplify setting of ddi_io_power_domain
e302891b93c2 drm/i915: cleanup unused returns on DP-MST
== Series Details ==
Series: drm/i915/ehl: Port C's hotplug interrupt is associated with TC1 bits
URL : https://patchwork.freedesktop.org/series/67881/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7060 -> Patchwork_14762
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7055_full -> Patchwork_14748_full
I'm trying to understand why TGL is failing on link training when MST is
enabled. I couldn't find it yet, but here some trivial patches trying to
improve our code.
Lucas De Marchi (7):
drm/i915: simplify setting of ddi_io_power_domain
drm/i915: cleanup unused returns on DP-MST
drm/i915: fix
Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check")
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index
Instead of the ever growing switch, just compute the ddi io power domain
based on the port number.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++--
1 file changed, 3 insertions(+), 40 deletions(-)
diff --git
Those init functions mark their success in the intel_dig_port
struct, the return values are not really used.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +--
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +-
2 files changed, 6 insertions(+), 7
The new line is already added by pipe_config_mismatch(), so the callers
shouldn't add it.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
connections except DDI A. Tiger Lake (gen 12) supports on all external
connections.
Move the check to happen inside intel_dp_mst_encoder_init() and add
specific platform checks.
Signed-off-by: Lucas De Marchi
---
This way it's easier to figure out what didn't match when we have
multiple pipes enabled.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 33 +++-
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git
s/?/:/ so it's get correctly colored by dmesg.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
On some platforms that have the MCC PCH, Port C's hotplug interrupt
bits are mapped to TC1 bits.
Suggested-by: Matt Roper
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 8
2 files changed, 7 insertions(+),
Hi all,
After merging the drm-misc tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
drivers/gpu/drm/drm_dp_mst_topology.c: In function
'drm_atomic_get_mst_topology_state':
drivers/gpu/drm/drm_dp_mst_topology.c:4187:21: warning: unused variable 'dev'
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm (rev4)
URL : https://patchwork.freedesktop.org/series/67874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14761
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm (rev4)
URL : https://patchwork.freedesktop.org/series/67874/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8bb740107b70 drm/i915/perf: Replace global
== Series Details ==
Series: drm/dp: Remove the unused drm_device to get rid of build warning
URL : https://patchwork.freedesktop.org/series/67879/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14760
== Series Details ==
Series: drm/dp: Remove the unused drm_device to get rid of build warning
URL : https://patchwork.freedesktop.org/series/67879/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/dp: Remove the unused drm_device to get rid of build
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check that registers are
preserved between virtual engines
URL : https://patchwork.freedesktop.org/series/67843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7051_full -> Patchwork_14747_full
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm (rev3)
URL : https://patchwork.freedesktop.org/series/67874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14759
On 10/10/2019 22:50, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-10-10 17:07:11)
Yeah, that's a fine interface actually.
One last thought for the interface, should we return the previous
config-id?
That limits the config-id space to long (min s32) so that we can report
the negative
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm
URL : https://patchwork.freedesktop.org/series/67874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14758
We no longer use the connection mutex and hence no need to
define drm_device *dev, it causes a unused variable build warning
Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check")
Cc: Sean Paul
Cc: Lyude Paul
Cc: Daniel Vetter
Signed-off-by: Manasi Navare
---
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm (rev3)
URL : https://patchwork.freedesktop.org/series/67874/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e3e8e6f3790d drm/i915/perf: Replace global
I messed up on this patch, please ignore this one.
Will send the fixed version soon.
On Thu, 2019-10-10 at 12:32 -0700, José Roberto de Souza wrote:
> On GLK those registers are reserved and on another gens it have
> another meaning, so renaming it to BXT only.
>
> BSpec: 7548
> Signed-off-by:
Quoting Sebastian Andrzej Siewior (2019-10-10 19:26:10)
> On 2019-10-10 19:11:27 [+0100], Chris Wilson wrote:
> > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i
> > >
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm
URL : https://patchwork.freedesktop.org/series/67874/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4aa72c4ef98d drm/i915/perf: Replace global wakeref
== Series Details ==
Series: series starting with [1/4] drm/i915/display: Handle fused off display
correctly
URL : https://patchwork.freedesktop.org/series/67872/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14757
Quoting Lionel Landwerlin (2019-10-10 17:07:11)
> Yeah, that's a fine interface actually.
One last thought for the interface, should we return the previous
config-id?
That limits the config-id space to long (min s32) so that we can report
the negative error code (or exclude the top 4095 values).
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between
As we now have a specific engine to use OA on, exchange the top-level
runtime-pm wakeref with the engine-pm. This still results in the same
top-level runtime-pm, but with more nuances to keep the engine and its
gt awake.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 8
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a context. Thus if we
allow a later request
From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: drm/i915/execlists: Mark up expected state during reset
URL : https://patchwork.freedesktop.org/series/67830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7050_full -> Patchwork_14745_full
HDCP could be fused off, so not all GEN9+ platforms will support it.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
On GLK those registers are reserved and on another gens it have
another meaning, so renaming it to BXT only.
BSpec: 7548
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +---
drivers/gpu/drm/i915/i915_reg.h| 10 +-
2 files
If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above.
On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
it has another function, probably on GEN 9 when bit 31 is set all
the 3 pipes disable bit are set, so we can unify
Those features could be fused off on GEN9 non-low power and newer
GENs.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
== Series Details ==
Series: series starting with [v7,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/67806/
State : failure
== Summary ==
Applying: drm/i915/display/icl: Save Master
== Series Details ==
Series: drm/i915: Don't disable interrupts independently of the lock (rev2)
URL : https://patchwork.freedesktop.org/series/59289/
State : failure
== Summary ==
Applying: drm/i915: Don't disable interrupts independently of the lock
error: sha1 information is lacking or
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7057 -> Patchwork_14754
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
On 2019-10-10 19:11:27 [+0100], Chris Wilson wrote:
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/drm/i915/i915_request.c
> > @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i
> > active->retire(active, rq);
> > }
> >
> > -
Quoting Sebastian Andrzej Siewior (2019-10-10 17:06:40)
> The locks (active.lock and rq->lock) need to be taken with disabled
> interrupts. This is done in i915_request_retire() by disabling the
> interrupts independently of the locks itself.
> While local_irq_disable()+spin_lock() equals
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/perf: store the associated
engine of a stream
URL : https://patchwork.freedesktop.org/series/67857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14753
On Wed, Oct 09, 2019 at 10:37:21PM +, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
== Series Details ==
Series: series starting with [1/5] drm/i915: Shrink eDRAM ways/sets arrays
URL : https://patchwork.freedesktop.org/series/67853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14752
== Series Details ==
Series: RFC drm/i915: Allow userspace to specify ringsize on construction
URL : https://patchwork.freedesktop.org/series/67852/
State : failure
== Summary ==
Applying: RFC drm/i915: Allow userspace to specify ringsize on construction
Using index info to reconstruct a base
== Series Details ==
Series: drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
URL : https://patchwork.freedesktop.org/series/67850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14749
== Series Details ==
Series: Enable bigjoiner support, second approach. (rev3)
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
Applying: HAX to make DSC work on the icelake test system
Applying: drm/i915: Fix for_each_intel_plane_mask definition
Using index
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047_full -> Patchwork_14742_full
On 10/10/2019 00:19, Chris Wilson wrote:
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in
On 10/10/2019 18:44, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-10-10 16:22:25)
On 10/10/2019 00:19, Chris Wilson wrote:
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT. Also, it is not
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by:
Quoting Lionel Landwerlin (2019-10-10 16:22:25)
> On 10/10/2019 00:19, Chris Wilson wrote:
> > From: Lionel Landwerlin
> >
> > Introduce a new perf_ioctl command to change the OA configuration of the
> > active stream. This allows the OA stream to be reconfigured between
> > batch buffers, giving
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7055 -> Patchwork_14748
On 10/10/2019 00:19, Chris Wilson wrote:
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson
Quoting Lionel Landwerlin (2019-10-10 15:57:32)
> On 10/10/2019 10:27, Chris Wilson wrote:
> > From: Lionel Landwerlin
> >
> > We'll use this information later to verify that a client trying to
> > reconfigure the stream does so on the right engine. For now, we want to
> > pull the knowledge of
On 10/10/2019 10:27, Chris Wilson wrote:
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful
On 10/10/2019 10:27, Chris Wilson wrote:
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel
From: Ville Syrjälä
The .read_2_2() hooks is never called for any of the message
types with a zero timeout. So it's all just dead weight which
we can chuck.
text data bss dec hex filename
- 34701360 0 3506188f5 intel_hdmi.o
+ 34633
From: Ville Syrjälä
The only reason for the timeout2 value in the array is the
HDCP_2_2_AKE_SEND_HPRIME message. But that one still needs
special casing inside the loop, and so just ends up making
the code harder to read. Let's just remove this leaky
timeout2 abstraction and special case that
From: Ville Syrjälä
All the timeout values fit in u16, so let's shrink the structure
a bit.
This ends up actually increasing the .text size a bit due to
some changes in instructions (constant imul+small jmps replaced
with mov+bigger jmpqs). Seems pretty arbitrary to me so I'll
just pretend I
From: Ville Syrjälä
Make the ways/sets arrays static cosnt u8 to shrink things a bit.
text data bss dec hex filename
- 23935629 128 246926074 i915_drv.o
+ 23818629 128 245755fff i915_drv.o
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
The array is there only for timeout, "data" doesn't mean anything
so let's rename the thing to be more descriptive.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> >> We want to split drm_crtc_state into the user visible state
> >> and actual hardware state. To prepare for
Hi Dave and Daniel,
This pull request includes the ones we missed for -rc1
drm-intel-next-fixes-2019-09-26 & drm-intel-next-fixes-2019-09-19
plus few fixes for execlists requests and CML display.
Here goes drm-intel-fixes-2019-10-10:
- Fix CML display by adding a missing ID.
- Drop redundant
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 83 +++--
include/uapi/drm/i915_drm.h | 12 +++
2 files
Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
>> We want to split drm_crtc_state into the user visible state
>> and actual hardware state. To prepare for this, we need some
>> ground rules what should be in each state:
>>
>> In
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>>
Quoting Chris Wilson (2019-10-10 14:48:49)
> Check the user's flags on the struct file before deciding whether or not
> to stall before submitting a request. This allows us to reasonably
> cheaply honour O_NONBLOCK without checking at more critical phases
> during request submission.
One might
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen
Signed-off-by: Chris Wilson
Cc:
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block
URL : https://patchwork.freedesktop.org/series/67811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14741_full
Summary
---
On Wed, Oct 09, 2019 at 06:46:38PM -0400, Lyude Paul wrote:
> oh, completely forgot about this one
>
> Reviewed-by: Lyude Paul
Thanks for your review, applied to drm-misc-next.
-Daniel
>
> On Thu, 2019-10-10 at 00:41 +0200, Daniel Vetter wrote:
> > Private atomic objects have grown their own
On Thu, 10 Oct 2019, Hans de Goede wrote:
> Hi Jani,
>
> During plumbers I had some discussions with Daniel about supporting
> OLED screens. Userspace may need to know that a panel is OLED for 2
> reasons:
>
> 1) To avoid screen burn-in
> 2) OLED screens do not have a classic backlight, so in
Quoting Chris Wilson (2019-10-10 14:15:21)
> +static int __live_gpr_clear(struct i915_gem_context *fixme,
> + struct intel_engine_cs *engine,
> + struct i915_vma *scratch)
> +{
> + struct intel_context *ce;
> + struct i915_request
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by:
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check that registers are
preserved between virtual engines
URL : https://patchwork.freedesktop.org/series/67843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7051 -> Patchwork_14747
Op 10-10-2019 om 14:39 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
Use this in all the places where we try to acquire planes
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67810/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14740_full
Quoting Tvrtko Ursulin (2019-10-10 13:31:04)
>
> On 10/10/2019 12:02, Chris Wilson wrote:
> > Make sure that we copy across the registers from one engine to the next,
> > as we hop around a virtual engine.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > Skip the test on
Hi Jani,
During plumbers I had some discussions with Daniel about supporting
OLED screens. Userspace may need to know that a panel is OLED for 2
reasons:
1) To avoid screen burn-in
2) OLED screens do not have a classic backlight, so in some cases
some sort of brightness/contrast emulation
Chris Wilson writes:
> Move the BUG_ON around slightly and add some explanations for each to
> try and capture the expected state more carefully. We want to compare
> the expected active state of our bookkeeping as compared to the tracked
> HW state.
>
> References:
Op 08-10-2019 om 21:40 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
>> When the clock is higher than the dotclock, try with 2 pipes enabled.
>> If we can enable 2, then we will go into big joiner mode, and steal
>> the adjacent crtc.
>>
>> This only
On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> >> Use this in all the places where we try to acquire planes after the planes
> >> atomic_check().
> >>
> >>
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