Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: remove unneeded clflush calls

[Lucas De Marchi]

On Tue, Sep 21, 2021 at 04:06:00PM +0300, Ville Syrjälä wrote:

On Mon, Sep 20, 2021 at 10:47:08PM -0700, Lucas De Marchi wrote:

On Wed, Sep 15, 2021 at 12:29:12PM -0700, John Harrison wrote:
>On 9/15/2021 12:24, Belgaumkar, Vinay wrote:
>>On 9/14/2021 12:51 PM, Lucas De Marchi wrote:
>>>The clflush calls here aren't doing anything since we are not writting
>>>something and flushing the cache lines to be visible to GuC. Here the
>>>intention seems to be to make sure whatever GuC has written is visible
>>>to the CPU before we read them. However a clflush from the CPU side is
>>>the wrong instruction to use.
>Is there a right instruction to use? Either we need to verify that no

how can there be a right instruction? If the GuC needs to flush, then
the GuC needs to do it, nothing to be done by the CPU.

Flushing the CPU cache line here is doing nothing to guarantee that what
was written by GuC hit the memory and we are reading it. Not sure why it
was actually added, but since it was added by Vinay and he reviewed this
patch, I'm assuming he also agrees


clflush == writeback + invalidate. The invalidate is the important part
when the CPU has to read something written by something else that's not
cache coherent.


Although the invalidate would be the important part, how would that work
if there is still a flush? Wouldn't we be overriding whatever
was written by the other side? Or are we using the fact that we
shouldn't be writting to this cacheline so we know it's not dirty?



Now, I have no idea if the guc has its own (CPU invisible) caches or not.
If it does then it will need to trigger a writeback. But regardless, if
the guc bypasses the CPU caches the CPU will need to invalidate before
it reads anything in case it has stale data sitting in its cache.


Indeed, thanks... but another case would be if caches are coherent
through snoop.  Do you know what is the cache architecture with GuC
and CPU?

Another question comes to mind, but first some context: I'm looking
at this in order to support other archs besides x86... the only
platforms in which this would be relevant would be on the discrete ones
(I'm currently running an arm64 guest on qemu and using pci
passthrough). I see that for dgfx intel_guc_allocate_vma() uses
i915_gem_object_create_lmem() instead of i915_gem_object_create_shmem().
Would that make a difference?

thanks
Lucas De Marchi

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)
URL   : https://patchwork.freedesktop.org/series/94733/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629_full -> Patchwork_21139_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21139_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-snb5/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2410])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_eio@unwedge-stress:
- shard-snb:  NOTRUN -> [FAIL][4] ([i915#3354])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-snb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2876])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb5/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb:  NOTRUN -> [SKIP][13] ([fdo#109271]) +218 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-apl1/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#3297]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb5/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#2856]) +2 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb2/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#2856])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-iclb8/igt@gen9_exec_pa...@secure-batches.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#1937])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-apl7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html

  * igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][20] ([i915#2681])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb5/igt@i915_pm_rc6_reside...@rc6-fence.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/shard-tglb5/igt@i915_pm_...@modeset-non-lpsp.html

  * igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#109288])
   [22]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Rework CFB stride/size calculations (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: Rework CFB stride/size calculations (rev7)
URL   : https://patchwork.freedesktop.org/series/92163/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21141


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21141/index.html

Known issues


  Here are the changes found in Patchwork_21141 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][1] ([i915#2291] / [i915#541]) -> 
[PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21141/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 33)
--

  Missing(9): fi-kbl-soraka fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-kbl-x1275 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21141

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21141: 7427679d6af0e6d4a93c2f0ef47f32065d39b172 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7427679d6af0 drm/i915/fbc: Allow higher compression limits on FBC1
842bd07b4804 drm/i915/fbc: Implement Wa_16011863758 for icl+
80899c3dca21 drm/i915/fbc: Align FBC segments to 512B on glk+
6796f449a672 drm/i915/fbc: Rework cfb stride/size calculations

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21141/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: Rework CFB stride/size calculations (rev7)
URL   : https://patchwork.freedesktop.org/series/92163/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' 
- different lock contexts for basic block

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove warning from the rps worker (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Remove warning from the rps worker (rev3)
URL   : https://patchwork.freedesktop.org/series/94650/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21140


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21140/index.html

Known issues


  Here are the changes found in Patchwork_21140 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-kbl-soraka:  [PASS][1] -> [INCOMPLETE][2] ([i915#794])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21140/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][3] ([i915#2291] / [i915#541]) -> 
[PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21140/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794


Participating hosts (42 -> 34)
--

  Missing(8): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 
fi-kbl-x1275 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21140

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21140: ab9f33f1f6119518b032bb3f4e5da2b699aa6f20 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ab9f33f1f611 drm/i915: Remove warning from the rps worker

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21140/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Introduce Intel PXP (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce Intel PXP (rev10)
URL   : https://patchwork.freedesktop.org/series/90503/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629_full -> Patchwork_21138_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21138_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-snb7/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_eio@unwedge-stress:
- shard-snb:  NOTRUN -> [FAIL][2] ([i915#3354])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-snb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-glk9/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb:  NOTRUN -> [SKIP][11] ([fdo#109271]) +281 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#3297]) +1 similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb8/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3323])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-apl2/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#2856]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb1/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#2856])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-iclb1/igt@gen9_exec_pa...@secure-batches.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#454])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb8/igt@i915_pm...@dc6-psr.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-iclb4/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1937])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-apl6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html

  * igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][19] ([i915#2681])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb8/igt@i915_pm_rc6_reside...@rc6-fence.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb8/igt@i915_pm_...@modeset-non-lpsp.html

  * igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109288])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/shard-tglb2/igt@i915_pm_s...@full-enable.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#1769])
   [22]: 

[Intel-gfx] [PATCH v3 1/4] drm/i915/fbc: Rework cfb stride/size calculations

[Ville Syrjala]

From: Ville Syrjälä 

The code to calculate the cfb stride/size is a bit of mess.
The cfb size is getting calculated based purely on the plane
stride and plane height. That doesn't account for extra
alignment we want for the cfb stride. The gen9 override
stride OTOH is just calculated based on the plane width, and
it does try to make things more aligned but any extra alignment
added there is not considered in the cfb size calculations.
So not at all convinced this is working as intended. Additionally
the compression limit handling is split between the cfb allocation
code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just
confusing.

Let's streamline the whole thing:
- Start with the plane stride, convert that into cfb stride (cfb is
  always 4 bytes per pixel). All the calculations will assume 1:1
  compression limit since that will give us the max values, and we
  don't yet know how much stolen memory we will be able to allocate
- Align the cfb stride to 512 bytes on modern platforms. This guarantees
  the 4 line segment will be 512 byte aligned regardles of the final
  compression limit we choose later. The 512 byte alignment for the
  segment is required by at least some of the platforms, and just doing
  it always seems like the easiest option
- Figure out if we need to use the override stride or not. For X-tiled
  it's never needed since the plane stride is already 512 byte aligned,
  for Y-tiled it will be needed if the plane stride is not a multiple
  of 512 bytes, and for linear it's apparently always needed because the
  hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
  the PLANE_STRIDE*64 that it use with linear.
- The cfb size will be calculated based on the aligned cfb stride to
  guarantee we actually reserved enough stolen memory and the FBC hw
  won't end up scribbling over whatever else is allocated in stolen
- The compression limit handling we just do fully in the cfb allocation
  code to make things less confusing

v2: Write the min cfb segment stride calculation in a more
explicit way to make it clear what is going on
v3: Remeber to update fbc->limit when changing to 16bpp

Reviewed-by: Uma Shankar  #v2
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 180 +++
 drivers/gpu/drm/i915/i915_drv.h  |   4 +-
 2 files changed, 123 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index b1c1a23c36be..e3934424040b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -62,19 +62,76 @@ static void intel_fbc_get_plane_source_size(const struct 
intel_fbc_state_cache *
*height = cache->plane.src_h;
 }
 
-static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
-   const struct intel_fbc_state_cache 
*cache)
+/* plane stride in pixels */
+static unsigned int intel_fbc_plane_stride(const struct intel_plane_state 
*plane_state)
 {
-   int lines;
+   const struct drm_framebuffer *fb = plane_state->hw.fb;
+   unsigned int stride;
+
+   stride = plane_state->view.color_plane[0].stride;
+   if (!drm_rotation_90_or_270(plane_state->hw.rotation))
+   stride /= fb->format->cpp[0];
+
+   return stride;
+}
+
+/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
+static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache 
*cache)
+{
+   unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
+
+   return cache->fb.stride * cpp;
+}
+
+/* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
+static unsigned int skl_fbc_min_cfb_stride(const struct intel_fbc_state_cache 
*cache)
+{
+   unsigned int limit = 4; /* 1:4 compression limit is the worst case */
+   unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
+   unsigned int height = 4; /* FBC segment is 4 lines */
+   unsigned int stride;
+
+   /* minimum segment stride we can use */
+   stride = cache->plane.src_w * cpp * height / limit;
+
+   /*
+* At least some of the platforms require each 4 line segment to
+* be 512 byte aligned. Just do it always for simplicity.
+*/
+   stride = ALIGN(stride, 512);
+
+   /* convert back to single line equivalent with 1:1 compression limit */
+   return stride * limit / height;
+}
+
+/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
+static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
+const struct intel_fbc_state_cache 
*cache)
+{
+   unsigned int stride = _intel_fbc_cfb_stride(cache);
+
+   /*
+* At least some of the platforms require each 4 line segment to
+* be 512 byte aligned. Aligning each line to 512 bytes guarantees
+* that regardless of the 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/uncore: fwtable read handlers are now used on all forcewake platforms

[Patchwork]

== Series Details ==

Series: drm/i915/uncore: fwtable read handlers are now used on all forcewake 
platforms
URL   : https://patchwork.freedesktop.org/series/94975/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629_full -> Patchwork_21137_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21137_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@file:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-snb7/igt@gem_ctx_persiste...@file.html

  * igt@gem_eio@unwedge-stress:
- shard-skl:  [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#3063])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-skl2/igt@gem_...@unwedge-stress.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-skl8/igt@gem_...@unwedge-stress.html
- shard-snb:  NOTRUN -> [FAIL][4] ([i915#3354])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-snb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-apl:  [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-apl3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +3 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271]) +231 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_sync@basic-all:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118] / 
[i915#95])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-glk6/igt@gem_s...@basic-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-glk2/igt@gem_s...@basic-all.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-tglb3/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-apl1/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-tglb2/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-iclb3/igt@gen9_exec_pa...@secure-batches.html

  * igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][22] ([i915#2681])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/shard-tglb3/igt@i915_pm_rc6_reside...@rc6-fence.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [23]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)
URL   : https://patchwork.freedesktop.org/series/94733/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21139


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/index.html

Known issues


  Here are the changes found in Patchwork_21139 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u:   [PASS][1] -> [FAIL][2] ([i915#3449])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][3] ([i915#2291] / [i915#541]) -> 
[PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3449]: https://gitlab.freedesktop.org/drm/intel/issues/3449
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 34)
--

  Missing(8): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 
fi-kbl-x1275 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21139

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21139: 388b23930275754702d2e5fbe26bd88e66e97254 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

388b23930275 drm/i915/dsi: do not register gmbus if it was reserved for MIPI 
display

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21139/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: unregister gmbus if LFP display was MIPI panel (rev4)
URL   : https://patchwork.freedesktop.org/series/94733/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
388b23930275 drm/i915/dsi: do not register gmbus if it was reserved for MIPI 
display
-:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#41: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:122:
+static bool intel_gmbus_ddc_reserve_for_mipi_dsi(struct drm_i915_private 
*dev_priv,
+unsigned int pin)

-:46: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#46: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:127:
+   if ((pin == GMBUS_PIN_2_BXT && 
dev_priv->vbt.dsi.config->dual_link) ||
+pin == GMBUS_PIN_1_BXT) {

total: 0 errors, 0 warnings, 2 checks, 29 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce Intel PXP (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce Intel PXP (rev10)
URL   : https://patchwork.freedesktop.org/series/90503/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21138


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/index.html

Known issues


  Here are the changes found in Patchwork_21138 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][1] -> [FAIL][2] ([i915#1888])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][5] ([i915#2291] / [i915#541]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 34)
--

  Missing(8): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 
fi-kbl-x1275 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21138

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21138: 4728e4ee5b2daab9744d047be8443fee7efe7ef8 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4728e4ee5b2d drm/i915/pxp: enable PXP for integrated Gen12
0ff702586cf9 drm/i915/pxp: add PXP documentation
3c1965c6e3ef drm/i915/pxp: add pxp debugfs
6faffa9df265 drm/i915/pxp: black pixels on pxp disabled
e58d9b52e0f0 drm/i915/pxp: Add plane decryption support
54fbc154318a drm/i915/pxp: Enable PXP power management
c4ff99595b46 drm/i915/pxp: start the arb session on demand
f6b4768e1fa2 drm/i915/pxp: interfaces for using protected objects
2b49864b5bed drm/i915/pxp: Implement PXP irq handler
1975d3f5fda6 drm/i915/pxp: Implement arb session teardown
d401356a6ad5 drm/i915/pxp: Create the arbitrary session after boot
d242815536ca drm/i915/pxp: set KCR reg init
8a35249b2073 drm/i915/pxp: Implement funcs to create the TEE channel
1b5cc61a686b drm/i915/pxp: allocate a vcs context for pxp usage
9f5fd3d81cf3 drm/i915/pxp: define PXP device flag and kconfig
a6f0b119f74f mei: pxp: export pavp client to me client bus
05e1ec3f284d drm/i915/pxp: Define PXP component interface

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21138/index.html

Re: [Intel-gfx] [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission

[Matthew Brost]

On Wed, Sep 22, 2021 at 01:15:46PM -0700, John Harrison wrote:
> On 9/22/2021 09:25, Matthew Brost wrote:
> > On Mon, Sep 20, 2021 at 02:48:52PM -0700, John Harrison wrote:
> > > On 8/20/2021 15:44, Matthew Brost wrote:
> > > > Implement multi-lrc submission via a single workqueue entry and single
> > > > H2G. The workqueue entry contains an updated tail value for each
> > > > request, of all the contexts in the multi-lrc submission, and updates
> > > > these values simultaneously. As such, the tasklet and bypass path have
> > > > been updated to coalesce requests into a single submission.
> > > > 
> > > > Signed-off-by: Matthew Brost 
> > > > ---
> > > >drivers/gpu/drm/i915/gt/uc/intel_guc.c|  21 ++
> > > >drivers/gpu/drm/i915/gt/uc/intel_guc.h|   8 +
> > > >drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  24 +-
> > > >drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   6 +-
> > > >.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 312 
> > > > +++---
> > > >drivers/gpu/drm/i915/i915_request.h   |   8 +
> > > >6 files changed, 317 insertions(+), 62 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > index fbfcae727d7f..879aef662b2e 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > @@ -748,3 +748,24 @@ void intel_guc_load_status(struct intel_guc *guc, 
> > > > struct drm_printer *p)
> > > > }
> > > > }
> > > >}
> > > > +
> > > > +void intel_guc_write_barrier(struct intel_guc *guc)
> > > > +{
> > > > +   struct intel_gt *gt = guc_to_gt(guc);
> > > > +
> > > > +   if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
> > > > +   GEM_BUG_ON(guc->send_regs.fw_domains);
> > > Granted, this patch is just moving code from one file to another not
> > > changing it. However, I think it would be worth adding a blank line in 
> > > here.
> > > Otherwise the 'this register' comment below can be confusingly read as
> > > referring to the send_regs.fw_domain entry above.
> > > 
> > > And maybe add a comment why it is a bug for the send_regs value to be set?
> > > I'm not seeing any obvious connection between it and the reset of this 
> > > code.
> > > 
> > Can add a blank line. I think the GEM_BUG_ON relates to being able to
> > use intel_uncore_write_fw vs intel_uncore_write. Can add comment.
> > 
> > > > +   /*
> > > > +* This register is used by the i915 and GuC for MMIO 
> > > > based
> > > > +* communication. Once we are in this code CTBs are the 
> > > > only
> > > > +* method the i915 uses to communicate with the GuC so 
> > > > it is
> > > > +* safe to write to this register (a value of 0 is NOP 
> > > > for MMIO
> > > > +* communication). If we ever start mixing CTBs and 
> > > > MMIOs a new
> > > > +* register will have to be chosen.
> > > > +*/
> > > > +   intel_uncore_write_fw(gt->uncore, 
> > > > GEN11_SOFT_SCRATCH(0), 0);
> > > > +   } else {
> > > > +   /* wmb() sufficient for a barrier if in smem */
> > > > +   wmb();
> > > > +   }
> > > > +}
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > > index 3f95b1b4f15c..0ead2406d03c 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > > @@ -37,6 +37,12 @@ struct intel_guc {
> > > > /* Global engine used to submit requests to GuC */
> > > > struct i915_sched_engine *sched_engine;
> > > > struct i915_request *stalled_request;
> > > > +   enum {
> > > > +   STALL_NONE,
> > > > +   STALL_REGISTER_CONTEXT,
> > > > +   STALL_MOVE_LRC_TAIL,
> > > > +   STALL_ADD_REQUEST,
> > > > +   } submission_stall_reason;
> > > > /* intel_guc_recv interrupt related state */
> > > > spinlock_t irq_lock;
> > > > @@ -332,4 +338,6 @@ void intel_guc_submission_cancel_requests(struct 
> > > > intel_guc *guc);
> > > >void intel_guc_load_status(struct intel_guc *guc, struct drm_printer 
> > > > *p);
> > > > +void intel_guc_write_barrier(struct intel_guc *guc);
> > > > +
> > > >#endif
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
> > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > > index 20c710a74498..10d1878d2826 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > > @@ -377,28 +377,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct 
> > > > *ct)
> > > > return ++ct->requests.last_fence;
> > > >}
> > > > -static void write_barrier(struct intel_guc_ct *ct)
> > > > -{
> > > > -   struct intel_guc *guc = ct_to_guc(ct);
> > > 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Introduce Intel PXP (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce Intel PXP (rev10)
URL   : https://patchwork.freedesktop.org/series/90503/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./include/uapi/drm/i915_drm.h:1904: warning: This comment starts with '/**', 
but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Introduce Intel PXP (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce Intel PXP (rev10)
URL   : https://patchwork.freedesktop.org/series/90503/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' 
- different lock contexts for basic block

[Intel-gfx] [v4] drm/i915/dsi: do not register gmbus if it was reserved for MIPI display

[Lee Shawn C]

Gmbus driver would setup all Intel i2c GMBuses. But DDC bus
may configured as gpio and reserved for MIPI driver to control
panel power on/off sequence.

Using i2c tool to communicate to peripherals via i2c interface
reversed for gmbus(DDC). There will be some high/low pulse
appear on DDC SCL and SDA (might be host sent out i2c slave
address). MIPI panel would be impacted due to unexpected signal
then caused abnormal display or shut down issue.

v2: gmbus driver should not add i2c adapter for DDC interface
if LFP display was configured to support MIPI panel.
v3: fix sparse warning
v4: before gmbus driver add/delete/access i2c adapter would
call intel_gmbus_is_valid_pin() to know target adapter
is available or not. Avoid to access unexisting adapter.
Driver should check DSI status and pin's availability in
intel_gmbus_is_valid_pin().

Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
---
 drivers/gpu/drm/i915/display/intel_gmbus.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index ceb1bf8a8c3c..852e499e2e8c 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -118,11 +118,29 @@ static const struct gmbus_pin *get_gmbus_pin(struct 
drm_i915_private *dev_priv,
return _pins[pin];
 }
 
+static bool intel_gmbus_ddc_reserve_for_mipi_dsi(struct drm_i915_private 
*dev_priv,
+unsigned int pin)
+{
+   if (intel_bios_is_dsi_present(dev_priv, NULL)) {
+   if (DISPLAY_VER(dev_priv) >= 11) {
+   if ((pin == GMBUS_PIN_2_BXT && 
dev_priv->vbt.dsi.config->dual_link) ||
+pin == GMBUS_PIN_1_BXT) {
+   return true;
+   }
+   }
+   }
+
+   return false;
+}
+
 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  unsigned int pin)
 {
unsigned int size;
 
+   if (intel_gmbus_ddc_reserve_for_mipi_dsi(dev_priv, pin))
+   return false;
+
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
size = ARRAY_SIZE(gmbus_pins_dg1);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-- 
2.17.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce Intel PXP (rev10)
URL   : https://patchwork.freedesktop.org/series/90503/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
05e1ec3f284d drm/i915/pxp: Define PXP component interface
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 49 lines checked
a6f0b119f74f mei: pxp: export pavp client to me client bus
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#36: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 276 lines checked
9f5fd3d81cf3 drm/i915/pxp: define PXP device flag and kconfig
-:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#49: FILE: drivers/gpu/drm/i915/i915_drv.h:1686:
+#define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+   INTEL_INFO(dev_priv)->has_pxp) && \
+   VDBOX_MASK(_priv->gt))

total: 0 errors, 0 warnings, 1 checks, 33 lines checked
1b5cc61a686b drm/i915/pxp: allocate a vcs context for pxp usage
-:100: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#100: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 172 lines checked
8a35249b2073 drm/i915/pxp: Implement funcs to create the TEE channel
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#79: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 145 lines checked
d242815536ca drm/i915/pxp: set KCR reg init
d401356a6ad5 drm/i915/pxp: Create the arbitrary session after boot
-:107: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#107: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 344 lines checked
1975d3f5fda6 drm/i915/pxp: Implement arb session teardown
-:117: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#117: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 283 lines checked
2b49864b5bed drm/i915/pxp: Implement PXP irq handler
-:213: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#213: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 424 lines checked
f6b4768e1fa2 drm/i915/pxp: interfaces for using protected objects
c4ff99595b46 drm/i915/pxp: start the arb session on demand
54fbc154318a drm/i915/pxp: Enable PXP power management
-:122: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#122: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 239 lines checked
e58d9b52e0f0 drm/i915/pxp: Add plane decryption support
6faffa9df265 drm/i915/pxp: black pixels on pxp disabled
-:169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible 
side-effects?
#169: FILE: drivers/gpu/drm/i915/i915_reg.h:11412:
+#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \
+   
_PLANE_CSC_RY_GY_1(pipe) +  (index) * 4, \
+   
_PLANE_CSC_RY_GY_2(pipe) + (index) * 4)

-:169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible 
side-effects?
#169: FILE: drivers/gpu/drm/i915/i915_reg.h:11412:
+#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \
+   
_PLANE_CSC_RY_GY_1(pipe) +  (index) * 4, \
+   
_PLANE_CSC_RY_GY_2(pipe) + (index) * 4)

-:170: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#170: FILE: drivers/gpu/drm/i915/i915_reg.h:11413:
+   
_PLANE_CSC_RY_GY_1(pipe) +  (index) * 4, \

-:183: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible 
side-effects?
#183: FILE: drivers/gpu/drm/i915/i915_reg.h:11426:
+#define PLANE_CSC_PREOFF(pipe, plane, index)   _MMIO_PLANE(plane, 
_PLANE_CSC_PREOFF_HI_1(pipe) + \
+   (index) * 4, 
_PLANE_CSC_PREOFF_HI_2(pipe) + \
+   (index) * 4)

-:183: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible 
side-effects?
#183: FILE: drivers/gpu/drm/i915/i915_reg.h:11426:
+#define PLANE_CSC_PREOFF(pipe, plane, index)   _MMIO_PLANE(plane, 
_PLANE_CSC_PREOFF_HI_1(pipe) + \
+   (index) * 4, 
_PLANE_CSC_PREOFF_HI_2(pipe) + \
+   (index) * 4)

-:184: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#184: FILE: drivers/gpu/drm/i915/i915_reg.h:11427:
+   (index) * 4, 
_PLANE_CSC_PREOFF_HI_2(pipe) + \

-:197: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)

[Vudum, Lakshminarayana]

Failure is related to https://gitlab.freedesktop.org/drm/intel/-/issues/3797. I 
have re-reported the results after updating the CI bug log filters.

Lakshmi.

From: Thomas Hellström 
Sent: Wednesday, September 22, 2021 11:07 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and 
restore of LMEM. (rev9)



On 9/22/21 11:05 AM, Patchwork wrote:
Patch Details
Series:

drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)

URL:

https://patchwork.freedesktop.org/series/94278/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html

CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_21124_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21124_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_21124_full:

IGT changes
Possible regressions

  *   igt@gem_exec_schedule@u-submit-golden-slice@rcs0:

 *   shard-tglb: 
PASS
 -> 
INCOMPLETE



Lakshmi, this failure is unrelated.

The igt@gem_exec_schedule@u-submit-golden-slice plus some other subtests have 
been broken since igt commit

a9987a8d tests/i915/gem_exec_schedule: Convert to intel_ctx_t (v3)

Although the tests typically says SUCCESS, it's because they typically are 
interrupted by the watchdog and move on.

Thanks,

Thomas

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915/display/dmc: Set 
DC_STATE_DEBUG_MASK_CORES after firmware load
URL   : https://patchwork.freedesktop.org/series/94967/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629_full -> Patchwork_21136_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21136_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2] ([i915#198])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-skl10/igt@gem_ctx_isolation@preservation...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-skl1/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#1373])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb3/igt@gem_ctx_isolation@preservation...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_persistence@file:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-snb2/igt@gem_ctx_persiste...@file.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb:  NOTRUN -> [SKIP][12] ([fdo#109271]) +76 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][13] ([i915#2658])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-apl2/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#3297]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-tglb6/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-kbl7/igt@gem_userptr_bl...@dmabuf-sync.html
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-apl8/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@huge-split:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#3376])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb3/igt@gem_userptr_bl...@huge-split.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-iclb8/igt@gem_userptr_bl...@huge-split.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271]) +22 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-kbl7/igt@gem_userptr_bl...@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) +2 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-tglb5/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-iclb4/igt@gen9_exec_pa...@secure-batches.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#1937])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/shard-apl7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html

  * 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uncore: fwtable read handlers are now used on all forcewake platforms

[Patchwork]

== Series Details ==

Series: drm/i915/uncore: fwtable read handlers are now used on all forcewake 
platforms
URL   : https://patchwork.freedesktop.org/series/94975/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21137


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/index.html

Known issues


  Here are the changes found in Patchwork_21137 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [PASS][1] -> [FAIL][2] ([i915#1888])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][5] ([i915#2291] / [i915#541]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 35)
--

  Missing(7): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21137

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21137: c04aba0807daf89649b82f0659dfd657d582a5c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c04aba0807da drm/i915/uncore: fwtable read handlers are now used on all 
forcewake platforms

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21137/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix bug in user proto-context creation that leaked contexts

[Patchwork]

== Series Details ==

Series: drm/i915: Fix bug in user proto-context creation that leaked contexts
URL   : https://patchwork.freedesktop.org/series/94962/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10629_full -> Patchwork_21135_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21135_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21135_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21135_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html

  
Known issues


  Here are the changes found in Patchwork_21135_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-cleanup:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-snb5/igt@gem_ctx_persiste...@engines-cleanup.html

  * igt@gem_eio@unwedge-stress:
- shard-snb:  NOTRUN -> [FAIL][4] ([i915#3354])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-snb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl:  NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html
- shard-apl:  [PASS][6] -> [FAIL][7] ([i915#2842] / [i915#3468])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271]) +213 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-apl7/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#3297]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-tglb2/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-kbl7/igt@gem_userptr_bl...@dmabuf-sync.html
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-apl8/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#2856]) +2 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-tglb6/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/shard-iclb3/igt@gen9_exec_pa...@secure-batches.html

  * 

[Intel-gfx] [PATCH] drm/i915/uncore: fwtable read handlers are now used on all forcewake platforms

[Matt Roper]

With the recent refactor of the uncore mmio handling, all
forcewake-based platforms (i.e., graphics version 6 and beyond) now use
the 'fwtable' read handlers.  Let's pull the assignment out of the
per-platform if/else ladder to make this more obvious.

Suggested-by: Tvrtko Ursulin 
Suggested-by: Lucas De Marchi 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_uncore.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index c8e7c71f0896..678a99de07fe 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2088,49 +2088,42 @@ static int uncore_forcewake_init(struct intel_uncore 
*uncore)
return ret;
forcewake_early_sanitize(uncore, 0);
 
+   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
+
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) >= 12) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) == 11) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (IS_CHERRYVIEW(i915)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) == 8) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (IS_VALLEYVIEW(i915)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
} else if (IS_GRAPHICS_VER(i915, 6, 7)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
-   ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
}
 
uncore->pmic_bus_access_nb.notifier_call = 
i915_pmic_bus_access_notifier;
-- 
2.33.0

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL   : https://patchwork.freedesktop.org/series/94278/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21124_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- {shard-rkl}:NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-rkl-6/igt@kms_multipipe_mode...@basic-max-pipe-crc-check.html

  
Known issues


  Here are the changes found in Patchwork_21124_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][2] ([i915#3002])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4] ([i915#146] / [i915#198])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_ctx_isolation@preservation...@vecs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl10/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_ctx_persistence@engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb2/igt@gem_ctx_persiste...@engines-mixed.html

  * igt@gem_eio@in-flight-1us:
- shard-skl:  [PASS][6] -> [TIMEOUT][7] ([i915#3063])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_...@in-flight-1us.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl9/igt@gem_...@in-flight-1us.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#2481] 
/ [i915#3070])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb4/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb3/igt@gem_...@unwedge-stress.html
- shard-snb:  NOTRUN -> [FAIL][10] ([i915#3354])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109283])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_par...@no-blt.html

  * igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#3797])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb3/igt@gem_exec_schedule@u-submit-golden-sl...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_schedule@u-submit-golden-sl...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2190])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][22] 

Re: [Intel-gfx] [PATCH v11 08/17] drm/i915/pxp: Implement arb session teardown

[Harish Chegondi]

On Tue, Sep 21, 2021 at 05:15:22PM -0700, Alan Previn wrote:
> From: "Huang, Sean Z" 
> 
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. Additionally, we want to emit a
> teardown operation to make sure we're clean on boot and resume
> 
> v2: emit in the ring, use high prio request (Chris)
> v3: better defines, stalling flush, cleaned up and renamed submission
> funcs (Chris)
> 
> Signed-off-by: Huang, Sean Z 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Chris Wilson 
> Reviewed-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/Makefile|   1 +
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  22 ++-
>  drivers/gpu/drm/i915/pxp/intel_pxp.c |   7 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 141 +++
>  drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h |  15 ++
>  drivers/gpu/drm/i915/pxp/intel_pxp_session.c |  29 
>  drivers/gpu/drm/i915/pxp/intel_pxp_session.h |   1 +
>  7 files changed, 212 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>  create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 334efd835cd8..ac4585f98e43 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -283,6 +283,7 @@ i915-y += i915_perf.o
>  # Protected execution platform (PXP) support
>  i915-$(CONFIG_DRM_I915_PXP) += \
>   pxp/intel_pxp.o \
> + pxp/intel_pxp_cmd.o \
>   pxp/intel_pxp_session.o \
>   pxp/intel_pxp_tee.o
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 1c3af0fc0456..f8253012d166 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -28,10 +28,13 @@
>  #define INSTR_26_TO_24_MASK  0x700
>  #define   INSTR_26_TO_24_SHIFT   24
>  
> +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> +
>  /*
>   * Memory interface instructions used by the kernel
>   */
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_INSTR(opcode, flags) \
> + (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
>  /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
>  #define  MI_GLOBAL_GTT(1<<22)
>  
> @@ -57,6 +60,7 @@
>  #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
>  #define   MI_SUSPEND_FLUSH_EN(1<<0)
>  #define MI_SET_APPID MI_INSTR(0x0e, 0)
> +#define   MI_SET_APPID_SESSION_ID(x) ((x) << 0)
>  #define MI_OVERLAY_FLIP  MI_INSTR(0x11, 0)
>  #define   MI_OVERLAY_CONTINUE(0x0<<21)
>  #define   MI_OVERLAY_ON  (0x1<<21)
> @@ -146,6 +150,7 @@
>  #define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
>  #define   MI_SRM_LRM_GLOBAL_GTT  (1<<22)
>  #define MI_FLUSH_DW  MI_INSTR(0x26, 1) /* for GEN6 */
> +#define   MI_FLUSH_DW_PROTECTED_MEM_EN   (1 << 22)
>  #define   MI_FLUSH_DW_STORE_INDEX(1<<21)
>  #define   MI_INVALIDATE_TLB  (1<<18)
>  #define   MI_FLUSH_DW_OP_STOREDW (1<<14)
> @@ -272,6 +277,19 @@
>  #define   MI_MATH_REG_ZF 0x32
>  #define   MI_MATH_REG_CF 0x33
>  
> +/*
> + * Media instructions used by the kernel
> + */
> +#define MEDIA_INSTR(pipe, op, sub_op, flags) \
> + (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
> + (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
> +
> +#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
> +#define  MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG  REG_BIT(8)
> +#define  MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG  REG_BIT(9)
> +
> +#define CRYPTO_KEY_EXCHANGE  MEDIA_INSTR(2, 6, 9, 0)
> +
>  /*
>   * Commands used only by the command parser
>   */
> @@ -328,8 +346,6 @@
>  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
>   ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
>  
> -#define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
> -
>  #define COLOR_BLT ((0x2<<29)|(0x40<<22))
>  #define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
>  
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 54ad5e3d0df2..a589d40e08a8 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -109,9 +109,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
>  
>  void intel_pxp_init_hw(struct intel_pxp *pxp)
>  {
> + int ret;
> +
>   kcr_pxp_enable(pxp_to_gt(pxp));
>  
> - intel_pxp_create_arb_session(pxp);
> + /* always emit a full termination to clean the state */
> + ret = intel_pxp_terminate_arb_session_and_global(pxp);
> + if (!ret)
> + intel_pxp_create_arb_session(pxp);
>  }
>  
>  void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c 
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915/display/dmc: Set 
DC_STATE_DEBUG_MASK_CORES after firmware load
URL   : https://patchwork.freedesktop.org/series/94967/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21136


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21136:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_heartbeat:
- {fi-ehl-2}: [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/fi-ehl-2/igt@i915_selftest@live@gt_heartbeat.html

  
Known issues


  Here are the changes found in Patchwork_21136 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][5] ([i915#2291] / [i915#541]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 35)
--

  Missing(7): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21136

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21136: f58ed69579ae3a19f7ddbbbaf0ba19dbc67ecfe7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f58ed69579ae drm/i915/display: Only keep PSR enabled if there is active planes
99491a0cc1f9 drm/i915/display: Match PSR2 selective fetch sequences with 
specification
5b64a2f4c3ca drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware 
load

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21136/index.html

Re: [Intel-gfx] [PATCH RESEND] drm/i915: Flush buffer pools on driver remove

[Matt Roper]

On Fri, Sep 03, 2021 at 04:23:20PM +0200, Janusz Krzysztofik wrote:
> In preparation for clean driver release, attempts to drain work queues
> and release freed objects are taken at driver remove time.  However, GT
> buffer pools are now not flushed before the driver release phase.
> Since unused objects may stay there for up to one second, some may
> survive until driver release is attempted.  That can potentially
> explain sporadic then hardly reproducible issues observed at driver
> release time, like non-zero shrink counter or outstanding address space

So just to make sure I'm understanding the description here:
 - We currently do an explicit flush of the buffer pools within the call
   path of drm_driver.release(); this removes all buffers, regardless of
   their age.
 - However there may be other code that runs *earlier* within the
   drm_driver.release() call chain that expects buffer pools have
   already been flushed and are already empty.
 - Since buffer pools auto-flush old buffers once per second in a worker
   thread, there's a small window where if we remove the driver while
   there are still buffers with an age of less than one second, the
   assumptions of the other release code may be violated.

So by moving the flush to driver remove (which executes earlier via the
pci_driver.remove() flow) you're ensuring that all buffers are flushed
before _any_ code in drm_driver.release() executes.

I found the wording of the commit message here somewhat confusing since
it's talking about flushes we do in driver release, but mentions
problems that arise during driver release due to lack of flushing.  You
might want to reword the commit message somewhat to help clarify.
Otherwise, the code change itself looks reasonable to me.

BTW, I do notice that drm_driver.release() in general is technically
deprecated at this point (with a suggestion in the drm_drv.h comments to
switch to using drmm_add_action(), drmm_kmalloc(), etc. to manage the
cleanup of resources).  At some point in the future me may want to
rework the i915 cleanup in general according to that guidance.


Matt

> areas.
> 
> Flush buffer pools on GT remove as a fix.  On driver release, don't
> flush the pools again, just assert that the flush was called and
> nothing added more in between.
> 
> Signed-off-by: Janusz Krzysztofik 
> Cc: Chris Wilson 
> ---
> Resending with Cc: dri-de...@lists.freedesktop.org as requested, and a
> typo in commit description fixed.
> 
> Thanks,
> Janusz
> 
>  drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
>  drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 2 --
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 62d40c986642..8f322a4ecd87 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -737,6 +737,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
>   intel_uc_driver_remove(>uc);
>  
>   intel_engines_release(gt);
> +
> + intel_gt_flush_buffer_pool(gt);
>  }
>  
>  void intel_gt_driver_unregister(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
> index aa0a59c5b614..acc49c56a9f3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
> @@ -245,8 +245,6 @@ void intel_gt_fini_buffer_pool(struct intel_gt *gt)
>   struct intel_gt_buffer_pool *pool = >buffer_pool;
>   int n;
>  
> - intel_gt_flush_buffer_pool(gt);
> -
>   for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
>   GEM_BUG_ON(!list_empty(>cache_list[n]));
>  }
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915/display/dmc: Set 
DC_STATE_DEBUG_MASK_CORES after firmware load
URL   : https://patchwork.freedesktop.org/series/94967/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5b64a2f4c3ca drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware 
load
99491a0cc1f9 drm/i915/display: Match PSR2 selective fetch sequences with 
specification
f58ed69579ae drm/i915/display: Only keep PSR enabled if there is active planes
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#16: 
commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before 
planes").

total: 0 errors, 1 warnings, 0 checks, 321 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix bug in user proto-context creation that leaked contexts

[Patchwork]

== Series Details ==

Series: drm/i915: Fix bug in user proto-context creation that leaked contexts
URL   : https://patchwork.freedesktop.org/series/94962/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10629 -> Patchwork_21135


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/index.html

Known issues


  Here are the changes found in Patchwork_21135 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2:  [PASS][1] -> [FAIL][2] ([i915#1888])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@gt_timelines:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4034])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][5] ([i915#3928])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/fi-rkl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r:   [DMESG-FAIL][6] ([i915#2291] / [i915#541]) -> 
[PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10629/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (42 -> 34)
--

  Missing(8): fi-kbl-soraka fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10629 -> Patchwork_21135

  CI-20190529: 20190529
  CI_DRM_10629: ce6974ec90355ddef78e6bc2221cb2296e5ba349 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21135: fa5831f0711b5ca53a2f4ee399726ac19da12204 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fa5831f0711b drm/i915: Fix bug in user proto-context creation that leaked 
contexts

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21135/index.html

Re: [Intel-gfx] [PATCH 14/19] drm/i915/oprom: Basic sanitization

[Lucas De Marchi]

On Mon, Sep 20, 2021 at 08:04:32AM +, Gupta, Anshuman wrote:




-Original Message-
From: Nikula, Jani 
Sent: Monday, September 20, 2021 1:12 PM
To: De Marchi, Lucas 
Cc: Auld, Matthew ; intel-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org; Gupta, Anshuman

Subject: Re: [Intel-gfx] [PATCH 14/19] drm/i915/oprom: Basic sanitization

On Fri, 17 Sep 2021, Lucas De Marchi  wrote:
> On Mon, May 17, 2021 at 02:57:33PM +0300, Jani Nikula wrote:
>>On Mon, 12 Apr 2021, Matthew Auld  wrote:
>>> From: Anshuman Gupta 
>>>
>>> Sanitize OPROM header, CPD signature and OPROM PCI version.
>>> OPROM_HEADER, EXPANSION_ROM_HEADER and OPROM_MEU_BLOB
structures and
>>> PCI struct offsets are provided by GSC counterparts.
>>> These are yet to be Documented in B.Spec.
>>> After successful sanitization, extract VBT from opregion image.
>>
>>So I don't understand what the point is with two consecutive patches
>>where the latter rewrites a lot of the former.
>
> I actually wonder what's the point of this. Getting it from spi is
> already the fallback and looks much more complex. Yes, it's pretty
> detailed and document the format pretty well, but it still looks more
> complex than the initial code. Do you see additional benefit in this
> one?

Getting opregion image from spi is needed to get the intel_opregion and its 
mailboxes on discrete card.


The commit message doesn't really explain much. Anshuman?

I will get rework of the patches and float it again.



from this patch the only thing I see it's doing is to get the VBT from
inside opregion... it moves the read part to helper methods and
apparently it supports multiple images...?

The question here is not why we are reading from spi, but rather what
this is doing that the previous commit wasn't already.

Lucas De Marchi

[Intel-gfx] [PATCH CI 3/3] drm/i915/display: Only keep PSR enabled if there is active planes

[José Roberto de Souza]

PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.

Similar behavior was fixed during the pipe disable sequence by
commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before 
planes").

intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.

Reviewed-by: Gwan-gyeong Mun 
Cc: Ville Syrjälä 
Cc: Gwan-gyeong Mun 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |   2 -
 drivers/gpu/drm/i915/display/intel_display.c  |  14 +-
 .../drm/i915/display/intel_display_types.h|   3 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |   6 +-
 drivers/gpu/drm/i915/display/intel_dp.h   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 140 ++
 drivers/gpu/drm/i915/display/intel_psr.h  |  11 +-
 7 files changed, 98 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bba0ab99836b1..a4667741d3548 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3034,7 +3034,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state 
*state,
intel_dp_stop_link_train(intel_dp, crtc_state);
 
intel_edp_backlight_on(crtc_state, conn_state);
-   intel_psr_enable(intel_dp, crtc_state, conn_state);
 
if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
@@ -3255,7 +3254,6 @@ static void intel_ddi_update_pipe_dp(struct 
intel_atomic_state *state,
 
intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-   intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_drrs_update(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 66e63f3429172..9985a1c5be96f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8095,10 +8095,12 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, 
bp_gamma);
 
-   PIPE_CONF_CHECK_BOOL(has_psr);
-   PIPE_CONF_CHECK_BOOL(has_psr2);
-   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-   PIPE_CONF_CHECK_I(dc3co_exitline);
+   if (current_config->active_planes) {
+   PIPE_CONF_CHECK_BOOL(has_psr);
+   PIPE_CONF_CHECK_BOOL(has_psr2);
+   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+   PIPE_CONF_CHECK_I(dc3co_exitline);
+   }
}
 
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -8155,7 +8157,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
}
 
-   if (fastset && (current_config->has_psr || pipe_config->has_psr))
+   if (current_config->has_psr || pipe_config->has_psr)
PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,

~intel_hdmi_infoframe_enable(DP_SDP_VSC));
else
@@ -10209,6 +10211,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
intel_encoders_update_prepare(state);
 
intel_dbuf_pre_plane_update(state);
+   intel_psr_pre_plane_update(state);
 
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip)
@@ -10272,6 +10275,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
}
 
intel_dbuf_post_plane_update(state);
+   intel_psr_post_plane_update(state);
 
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
intel_post_plane_update(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e9e806d90eec4..c900bfbb7cc52 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1056,12 +1056,14 @@ struct intel_crtc_state {
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
 
+   /* PSR is supported but might not be enabled due the lack of enabled 
planes */
bool has_psr;
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
u32 

[Intel-gfx] [PATCH CI 2/3] drm/i915/display: Match PSR2 selective fetch sequences with specification

[José Roberto de Souza]

We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank

With this changes the last remainig underrun found in Alderlake-P is
fixed.

Bspec: 55229
Tested-by: Gwan-gyeong Mun 
Reviewed-by: Gwan-gyeong Mun 
Cc: Gwan-gyeong Mun 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_cursor.c   |  4 ++-
 drivers/gpu/drm/i915/display/intel_display.c  | 12 +++
 drivers/gpu/drm/i915/display/intel_psr.c  | 33 ++-
 drivers/gpu/drm/i915/display/intel_psr.h  |  2 ++
 .../drm/i915/display/skl_universal_plane.c|  4 +--
 5 files changed, 36 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c 
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c7618fef01439..901ad3a4c8c3b 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -536,8 +536,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
if (DISPLAY_VER(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
 
-   if (!intel_crtc_needs_modeset(crtc_state))
+   if (plane_state)
intel_psr2_program_plane_sel_fetch(plane, crtc_state, 
plane_state, 0);
+   else
+   intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
 
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 23b1e0ccc72de..66e63f3429172 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6816,11 +6816,9 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
 
}
 
-   if (!mode_changed) {
-   ret = intel_psr2_sel_fetch_update(state, crtc);
-   if (ret)
-   return ret;
-   }
+   ret = intel_psr2_sel_fetch_update(state, crtc);
+   if (ret)
+   return ret;
 
return 0;
 }
@@ -9713,10 +9711,10 @@ static void commit_pipe_pre_planes(struct 
intel_atomic_state *state,
 
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
-   intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
 
+   intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
+
if (dev_priv->display.atomic_update_watermarks)
dev_priv->display.atomic_update_watermarks(state, crtc);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index c1894b056d6c1..868e5205dd09e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -561,15 +561,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_SU_SDP_SCANLINE;
 
if (intel_dp->psr.psr2_sel_fetch_enabled) {
+   u32 tmp;
+
/* Wa_1408330847 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 DIS_RAM_BYPASS_PSR2_MAN_TRACK);
 
-   intel_de_write(dev_priv,
-  PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
-  PSR2_MAN_TRK_CTL_ENABLE);
+   tmp = intel_de_read(dev_priv, 
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
+   drm_WARN_ON(_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
intel_de_write(dev_priv,
   PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
@@ -1450,6 +1451,18 @@ static void psr_force_hw_tracking_exit(struct intel_dp 
*intel_dp)
intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
 }
 
+void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
+   const struct intel_crtc_state 
*crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+   enum pipe pipe = plane->pipe;
+
+   if (!crtc_state->enable_psr2_sel_fetch)
+   return;
+
+   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+}
+
 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state 
*crtc_state,
const struct intel_plane_state 
*plane_state,
@@ -1464,11 +1477,11 @@ void intel_psr2_program_plane_sel_fetch(struct 
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
 
-   val = plane_state ? 

[Intel-gfx] [PATCH CI 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load

[José Roberto de Souza]

Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
platforms that supports DMC, not only for geminilake and broxton.

While at is also taking the oportunity to simply the code.

BSpec: 7402
BSpec: 49436
Reviewed-by: Imre Deak 
Cc: Imre Deak 
Cc: Gwan-gyeong Mun 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index b0268552b2863..2dc9d632969db 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
 
 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 {
-   u32 val, mask;
-
-   mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
-
-   if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-   mask |= DC_STATE_DEBUG_MASK_CORES;
-
/* The below bit doesn't need to be cleared ever afterwards */
-   val = intel_de_read(dev_priv, DC_STATE_DEBUG);
-   if ((val & mask) != mask) {
-   val |= mask;
-   intel_de_write(dev_priv, DC_STATE_DEBUG, val);
-   intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
-   }
+   intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
+DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
+   intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 }
 
 /**
-- 
2.33.0

Re: [Intel-gfx] [PATCH] drm/i915: fix blank screen booting crashes

[Lucas De Marchi]

On Tue, Sep 21, 2021 at 06:40:41PM -0700, Matthew Brost wrote:

On Tue, Sep 21, 2021 at 04:29:31PM -0700, Lucas De Marchi wrote:

On Tue, Sep 21, 2021 at 03:55:15PM -0700, Matthew Brost wrote:
> On Tue, Sep 21, 2021 at 11:46:37AM -0700, Lucas De Marchi wrote:
> > On Tue, Sep 21, 2021 at 10:43:32AM -0700, Matthew Brost wrote:
> > > From: Hugh Dickins 
> > >
> > > 5.15-rc1 crashes with blank screen when booting up on two ThinkPads
> > > using i915.  Bisections converge convincingly, but arrive at different
> > > and surprising "culprits", none of them the actual culprit.
> > >
> > > netconsole (with init_netconsole() hacked to call i915_init() when
> > > logging has started, instead of by module_init()) tells the story:
> > >
> > > kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
> > > with RSI: 814d408b pointing to sw_fence_dummy_notify().
> > > I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
> > > function needs to be 4-byte aligned.
> > >
> > > v2:
> > > (Jani Nikula)
> > >  - Change BUG_ON to WARN_ON
> > > v3:
> > > (Jani / Tvrtko)
> > >  - Short circuit __i915_sw_fence_init on WARN_ON
> > >
> > > Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
> > > Signed-off-by: Hugh Dickins 
> > > Signed-off-by: Matthew Brost 
> > > Reviewed-by: Matthew Brost 
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_context.c |  4 ++--
> > > drivers/gpu/drm/i915/i915_sw_fence.c| 17 ++---
> > > 2 files changed, 12 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
> > > index ff637147b1a9..e7f78bc7ebfc 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > > @@ -362,8 +362,8 @@ static int __intel_context_active(struct i915_active 
*active)
> > >  return 0;
> > > }
> > >
> >
> > > -static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
> > > - enum i915_sw_fence_notify state)
> > > +static int __i915_sw_fence_call
> > > +sw_fence_dummy_notify(struct i915_sw_fence *sf, enum 
i915_sw_fence_notify state)
> > > {
> > >  return NOTIFY_DONE;
> > > }
> > > diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
> > > index c589a681da77..08cea73264e7 100644
> > > --- a/drivers/gpu/drm/i915/i915_sw_fence.c
> > > +++ b/drivers/gpu/drm/i915/i915_sw_fence.c
> > > @@ -13,9 +13,9 @@
> > > #include "i915_selftest.h"
> > >
> > > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
> > > -#define I915_SW_FENCE_BUG_ON(expr) BUG_ON(expr)
> > > +#define I915_SW_FENCE_WARN_ON(expr) WARN_ON(expr)
> > > #else
> > > -#define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
> > > +#define I915_SW_FENCE_WARN_ON(expr) BUILD_BUG_ON_INVALID(expr)
> > > #endif
> > >
> > > static DEFINE_SPINLOCK(i915_sw_fence_lock);
> > > @@ -129,7 +129,10 @@ static int __i915_sw_fence_notify(struct 
i915_sw_fence *fence,
> > >  i915_sw_fence_notify_t fn;
> > >
> > >  fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
> > > -return fn(fence, state);
> > > +if (likely(fn))
> > > +return fn(fence, state);
> > > +else
> > > +return 0;
> >
> > since the knowledge for these being NULL (or with the wrong alignment)
> > are in the init/reinit functions,  wouldn't it be better to just add a
> > fence_nop() and assign it there instead this likely() here?
> >
>
> Maybe? I prefer the way it is.
>
> > > }
> > >
> > > #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
> > > @@ -242,9 +245,9 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
> > >const char *name,
> > >struct lock_class_key *key)
> > > {
> > > -BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
> > > -
> > >  __init_waitqueue_head(>wait, name, key);
> > > +if (WARN_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK))
> > > +return;
> >
> > like:
> >   if (WARN_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK))
> >   fence->flags = (unsigned long)sw_fence_dummy_notify;
> >   else
> >   fence->flags = (unsigned long)fn;
> >
> >
> > f you return here instead of calling i915_sw_fence_reinit(), aren't you
> > just going to use uninitialized memory later? At least in the selftests,
> > which allocate it with kmalloc()... I didn't check others.
> >
>
> I don't think so, maybe the fence won't work but it won't blow up
> either.
>
> >
> > For the bug fix we could just add the __aligned(4) and leave the rest to a
> > separate patch.
> >
>
> The bug was sw_fence_dummy_notify in gt/intel_context.c was not 4 byte
> align which triggered a BUG_ON during boot which blank screened a
> laptop. Jani / Tvrtko suggested that we make the BUG_ON to WARN_ONs so
> if someone makes this mistake in the future kernel should boot albiet
> with a WARNING.

yes, I understood. But afaics with WARN_ON you 

[Intel-gfx] [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined

[Harry Wentland]

[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.

In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 
'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined 
[-Werror,-Wmacro-redefined]
^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous 
definition is here
^
1 error generated.

[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 53 ++--
 1 file changed, 48 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..74b8de616dcd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -860,28 +860,71 @@ struct psr_caps {
 };
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
 #define DP_MAIN_LINK_CHANNEL_CODING_CAP0x006
+#endif
+#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
+#endif
+#ifndef DP_FEC_CAPABILITY_1
 #define DP_FEC_CAPABILITY_10x091
+#endif
+#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0A3
+#endif
+#ifndef DP_DSC_CONFIGURATION
 #define DP_DSC_CONFIGURATION   0x161
+#endif
+#ifndef DP_PHY_SQUARE_PATTERN
 #define DP_PHY_SQUARE_PATTERN  0x249
+#endif
+#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
 #define DP_128b_132b_SUPPORTED_LINK_RATES  0x2215
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL  0x2216
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0  0X2230
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256  0X2250
+#endif
+#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
 #define DP_DSC_SUPPORT_AND_DECODER_COUNT   0x2260
+#endif
+#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0   0x2270
-# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT1
-# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
-# define DP_DSC_DECODER_COUNT_SHIFT5
+#endif
+#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
+#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK  (1 << 0)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK  (0b111 << 1)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+#endif
+#ifndef DP_DSC_DECODER_COUNT_MASK
+#define DP_DSC_DECODER_COUNT_MASK  (0b111 << 5)
+#endif
+#ifndef DP_DSC_DECODER_COUNT_SHIFT
+#define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
 #define DP_MAIN_LINK_CHANNEL_CODING_SET0x108
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER   0xF0006
+#endif
+#ifndef DP_PHY_REPEATER_128b_132b_RATES
 #define DP_PHY_REPEATER_128b_132b_RATES0xF0007
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER10xF0022
+#endif
+#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
 #define DP_INTRA_HOP_AUX_REPLY_INDICATION  (1 << 3)
+#endif
 /* TODO - Use DRM header to replace above once available */
 
 union dp_main_line_channel_coding_cap {
-- 
2.33.0

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Rework CFB stride/size calculations (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: Rework CFB stride/size calculations (rev6)
URL   : https://patchwork.freedesktop.org/series/92163/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627_full -> Patchwork_21134_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21134_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +4 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#2481] 
/ [i915#3070])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-iclb6/igt@gem_...@unwedge-stress.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-iclb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-glk6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  NOTRUN -> [FAIL][6] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-tglb7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-tglb1/igt@gem_exec_par...@no-blt.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-snb5/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#768])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-iclb5/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-apl7/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-tglb3/igt@gem_userptr_bl...@unsync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume:
- shard-kbl:  NOTRUN -> [DMESG-WARN][18] ([i915#180]) +1 similar 
issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-kbl1/igt@gem_workarou...@suspend-resume.html

  * igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2856]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-iclb5/igt@gen9_exec_pa...@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / 
[i915#716])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl9/igt@gen9_exec_pa...@allowed-single.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-skl1/igt@gen9_exec_pa...@allowed-single.html

  * igt@gen9_exec_parse@secure-batches:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#2856])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/shard-tglb5/igt@gen9_exec_pa...@secure-batches.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> [SKIP][23] ([fdo#109271] / 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bug in user proto-context creation that leaked contexts

[Patchwork]

== Series Details ==

Series: drm/i915: Fix bug in user proto-context creation that leaked contexts
URL   : https://patchwork.freedesktop.org/series/94962/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fa5831f0711b drm/i915: Fix bug in user proto-context creation that leaked 
contexts
-:30: WARNING:BRACES: braces {} are not necessary for single statement blocks
#30: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:901:
+   if (!e) {
+   return ERR_PTR(-ENOMEM);
+   }

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix blank screen booting crashes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: fix blank screen booting crashes (rev5)
URL   : https://patchwork.freedesktop.org/series/94822/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627_full -> Patchwork_21132_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21132_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2410])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063] 
/ [i915#3648])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb2/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-tglb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-kbl3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-tglb6/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-tglb3/igt@gem_exec_par...@no-blt.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-kbl2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-snb5/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-apl3/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-tglb5/igt@gem_userptr_bl...@unsync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-kbl:  NOTRUN -> [DMESG-WARN][18] ([i915#180])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-kbl6/igt@gem_workarou...@suspend-resume-context.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][19] -> [INCOMPLETE][20] ([i915#155] / 
[i915#794])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][21] -> [DMESG-WARN][22] ([i915#1436] / 
[i915#716])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl9/igt@gen9_exec_pa...@allowed-single.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/shard-skl9/igt@gen9_exec_pa...@allowed-single.html

  * igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#2856])
   [23]: 

Re: [Intel-gfx] [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission

[John Harrison]

On 9/22/2021 09:25, Matthew Brost wrote:

On Mon, Sep 20, 2021 at 02:48:52PM -0700, John Harrison wrote:

On 8/20/2021 15:44, Matthew Brost wrote:

Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet and bypass path have
been updated to coalesce requests into a single submission.

Signed-off-by: Matthew Brost 
---
   drivers/gpu/drm/i915/gt/uc/intel_guc.c|  21 ++
   drivers/gpu/drm/i915/gt/uc/intel_guc.h|   8 +
   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  24 +-
   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   6 +-
   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 312 +++---
   drivers/gpu/drm/i915/i915_request.h   |   8 +
   6 files changed, 317 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index fbfcae727d7f..879aef662b2e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -748,3 +748,24 @@ void intel_guc_load_status(struct intel_guc *guc, struct 
drm_printer *p)
}
}
   }
+
+void intel_guc_write_barrier(struct intel_guc *guc)
+{
+   struct intel_gt *gt = guc_to_gt(guc);
+
+   if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
+   GEM_BUG_ON(guc->send_regs.fw_domains);

Granted, this patch is just moving code from one file to another not
changing it. However, I think it would be worth adding a blank line in here.
Otherwise the 'this register' comment below can be confusingly read as
referring to the send_regs.fw_domain entry above.

And maybe add a comment why it is a bug for the send_regs value to be set?
I'm not seeing any obvious connection between it and the reset of this code.


Can add a blank line. I think the GEM_BUG_ON relates to being able to
use intel_uncore_write_fw vs intel_uncore_write. Can add comment.


+   /*
+* This register is used by the i915 and GuC for MMIO based
+* communication. Once we are in this code CTBs are the only
+* method the i915 uses to communicate with the GuC so it is
+* safe to write to this register (a value of 0 is NOP for MMIO
+* communication). If we ever start mixing CTBs and MMIOs a new
+* register will have to be chosen.
+*/
+   intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
+   } else {
+   /* wmb() sufficient for a barrier if in smem */
+   wmb();
+   }
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 3f95b1b4f15c..0ead2406d03c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -37,6 +37,12 @@ struct intel_guc {
/* Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
struct i915_request *stalled_request;
+   enum {
+   STALL_NONE,
+   STALL_REGISTER_CONTEXT,
+   STALL_MOVE_LRC_TAIL,
+   STALL_ADD_REQUEST,
+   } submission_stall_reason;
/* intel_guc_recv interrupt related state */
spinlock_t irq_lock;
@@ -332,4 +338,6 @@ void intel_guc_submission_cancel_requests(struct intel_guc 
*guc);
   void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
+void intel_guc_write_barrier(struct intel_guc *guc);
+
   #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 20c710a74498..10d1878d2826 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -377,28 +377,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
return ++ct->requests.last_fence;
   }
-static void write_barrier(struct intel_guc_ct *ct)
-{
-   struct intel_guc *guc = ct_to_guc(ct);
-   struct intel_gt *gt = guc_to_gt(guc);
-
-   if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
-   GEM_BUG_ON(guc->send_regs.fw_domains);
-   /*
-* This register is used by the i915 and GuC for MMIO based
-* communication. Once we are in this code CTBs are the only
-* method the i915 uses to communicate with the GuC so it is
-* safe to write to this register (a value of 0 is NOP for MMIO
-* communication). If we ever start mixing CTBs and MMIOs a new
-* register will have to be chosen.
-*/
-   intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
-   } else {
-   /* wmb() sufficient for a barrier if in smem */
-   wmb();
-   }
-}
-
   static int ct_write(struct 

[Intel-gfx] [PATCH] drm/i915: Fix bug in user proto-context creation that leaked contexts

[Matthew Brost]

Set number of engines before attempting to create contexts so the
function free_engines can clean up properly. Also check return of
alloc_engines for NULL.

v2:
 (Tvrtko)
  - Send as stand alone patch
 (John Harrison)
  - Check for alloc_engines returning NULL

Cc: Jason Ekstrand 
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create 
parameters (v5)")
Signed-off-by: Matthew Brost 
Cc: 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..9627c7aac6a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -898,6 +898,11 @@ static struct i915_gem_engines *user_engines(struct 
i915_gem_context *ctx,
unsigned int n;
 
e = alloc_engines(num_engines);
+   if (!e) {
+   return ERR_PTR(-ENOMEM);
+   }
+   e->num_engines = num_engines;
+
for (n = 0; n < num_engines; n++) {
struct intel_context *ce;
int ret;
@@ -931,7 +936,6 @@ static struct i915_gem_engines *user_engines(struct 
i915_gem_context *ctx,
goto free_engines;
}
}
-   e->num_engines = num_engines;
 
return e;
 
-- 
2.32.0

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Drop stealing of bits from i915_sw_fence function pointer (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer 
(rev3)
URL   : https://patchwork.freedesktop.org/series/94924/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10627_full -> Patchwork_21131_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21131_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21131_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21131_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_whisper@basic-queues-all:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-iclb7/igt@gem_exec_whis...@basic-queues-all.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-iclb2/igt@gem_exec_whis...@basic-queues-all.html

  
Known issues


  Here are the changes found in Patchwork_21131_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063] 
/ [i915#3648])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb2/igt@gem_...@unwedge-stress.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-tglb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl:  [PASS][8] -> [SKIP][9] ([fdo#109271])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-apl3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][10] ([i915#2842]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-tglb2/igt@gem_exec_fair@basic-p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-tglb7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-snb7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-iclb8/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-apl3/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][18] -> [INCOMPLETE][19] ([i915#155] / 
[i915#794])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/shard-iclb8/igt@gen9_exec_pa...@allowed-all.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Rework CFB stride/size calculations (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: Rework CFB stride/size calculations (rev6)
URL   : https://patchwork.freedesktop.org/series/92163/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627 -> Patchwork_21134


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/index.html

Known issues


  Here are the changes found in Patchwork_21134 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][3] ([fdo#109315])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][4] ([fdo#109271]) +23 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][6] ([i915#3718])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-cfl-8109u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cfl-8109u:   NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][18] ([i915#3301])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21134/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u:   [INCOMPLETE][19] ([i915#155]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
   [20]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: Rework CFB stride/size calculations (rev6)
URL   : https://patchwork.freedesktop.org/series/92163/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' 
- different lock contexts for basic block

[Intel-gfx] ✓ Fi.CI.IGT: success for Per client GPU stats (rev4)

[Patchwork]

== Series Details ==

Series: Per client GPU stats (rev4)
URL   : https://patchwork.freedesktop.org/series/92574/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627_full -> Patchwork_21130_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_21130_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [FAIL][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#3174])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl9/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl8/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl2/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl1/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl4/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl10/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl10/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl10/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl7/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl1/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl1/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl6/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl1/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl2/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl6/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl6/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl5/boot.html
   [44]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/shard-skl2/boot.html
   [45]: 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Rework cfb stride/size calculations

[Shankar, Uma]

> -Original Message-
> From: Ville Syrjala 
> Sent: Tuesday, September 21, 2021 8:55 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma 
> Subject: [PATCH v2 1/4] drm/i915/fbc: Rework cfb stride/size calculations
> 
> From: Ville Syrjälä 
> 
> The code to calculate the cfb stride/size is a bit of mess.
> The cfb size is getting calculated based purely on the plane stride and plane 
> height.
> That doesn't account for extra alignment we want for the cfb stride. The gen9
> override stride OTOH is just calculated based on the plane width, and it does 
> try to
> make things more aligned but any extra alignment added there is not 
> considered in
> the cfb size calculations.
> So not at all convinced this is working as intended. Additionally the 
> compression limit
> handling is split between the cfb allocation code and g4x_dpfc_ctl_limit() 
> (for the
> 16bpp case), which is just confusing.
> 
> Let's streamline the whole thing:
> - Start with the plane stride, convert that into cfb stride (cfb is
>   always 4 bytes per pixel). All the calculations will assume 1:1
>   compression limit since that will give us the max values, and we
>   don't yet know how much stolen memory we will be able to allocate
> - Align the cfb stride to 512 bytes on modern platforms. This guarantees
>   the 4 line segment will be 512 byte aligned regardles of the final
>   compression limit we choose later. The 512 byte alignment for the
>   segment is required by at least some of the platforms, and just doing
>   it always seems like the easiest option
> - Figure out if we need to use the override stride or not. For X-tiled
>   it's never needed since the plane stride is already 512 byte aligned,
>   for Y-tiled it will be needed if the plane stride is not a multiple
>   of 512 bytes, and for linear it's apparently always needed because the
>   hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
>   the PLANE_STRIDE*64 that it use with linear.
> - The cfb size will be calculated based on the aligned cfb stride to
>   guarantee we actually reserved enough stolen memory and the FBC hw
>   won't end up scribbling over whatever else is allocated in stolen
> - The compression limit handling we just do fully in the cfb allocation
>   code to make things less confusing
> 
> v2: Write the min cfb segment stride calculation in a more
> explicit way to make it clear what is going on

Looks Good to me.
Reviewed-by: Uma Shankar 

> Cc: Uma Shankar 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 163 +++
>  drivers/gpu/drm/i915/i915_drv.h  |   4 +-
>  2 files changed, 112 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b1c1a23c36be..f51871f39eb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -62,19 +62,76 @@ static void intel_fbc_get_plane_source_size(const struct
> intel_fbc_state_cache *
>   *height = cache->plane.src_h;
>  }
> 
> -static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> - const struct intel_fbc_state_cache 
> *cache)
> +/* plane stride in pixels */
> +static unsigned int intel_fbc_plane_stride(const struct
> +intel_plane_state *plane_state)
>  {
> - int lines;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + unsigned int stride;
> +
> + stride = plane_state->view.color_plane[0].stride;
> + if (!drm_rotation_90_or_270(plane_state->hw.rotation))
> + stride /= fb->format->cpp[0];
> +
> + return stride;
> +}
> +
> +/* plane stride based cfb stride in bytes, assuming 1:1 compression
> +limit */ static unsigned int _intel_fbc_cfb_stride(const struct
> +intel_fbc_state_cache *cache) {
> + unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
> +
> + return cache->fb.stride * cpp;
> +}
> +
> +/* minimum acceptable cfb stride in bytes, assuming 1:1 compression
> +limit */ static unsigned int skl_fbc_min_cfb_stride(const struct
> +intel_fbc_state_cache *cache) {
> + unsigned int limit = 4; /* 1:4 compression limit is the worst case */
> + unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
> + unsigned int height = 4; /* FBC segment is 4 lines */
> + unsigned int stride;
> +
> + /* minimum segment stride we can use */
> + stride = cache->plane.src_w * cpp * height / limit;
> +
> + /*
> +  * At least some of the platforms require each 4 line segment to
> +  * be 512 byte aligned. Just do it always for simplicity.
> +  */
> + stride = ALIGN(stride, 512);
> +
> + /* convert back to single line equivalent with 1:1 compression limit */
> + return stride * limit / height;
> +}
> +
> +/* properly aligned cfb stride in bytes, assuming 1:1 compression limit
> +*/ static unsigned int 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix blank screen booting crashes (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: fix blank screen booting crashes (rev5)
URL   : https://patchwork.freedesktop.org/series/94822/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627 -> Patchwork_21132


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/index.html

Known issues


  Here are the changes found in Patchwork_21132 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][3] ([fdo#109315])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][4] ([fdo#109271]) +23 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][6] ([i915#3718])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  NOTRUN -> [FAIL][7] ([i915#1888])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][10] ([i915#1155])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-cfl-8109u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][13] ([i915#4103]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-rkl-11600:   [PASS][15] -> [SKIP][16] ([i915#1849] / [i915#3180])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-rkl-11600/igt@kms_frontbuffer_track...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-rkl-11600/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- fi-rkl-11600:   [PASS][17] -> [SKIP][18] ([i915#3919] / [i915#4098])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cfl-8109u:   NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21132/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][20] ([i915#1072]) +3 similar issues
   [20]: 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: dp 2.0 enabling prep work (rev5)
URL   : https://patchwork.freedesktop.org/series/93800/
State : failure

== Summary ==

Applying: drm/dp: add DP 2.0 UHBR link rate and bw code conversions
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/drm_dp_helper.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/drm_dp_helper.c
No changes -- Patch already applied.
Applying: drm/dp: use more of the extended receiver cap
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/drm_dp_helper.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/drm_dp_helper.c
No changes -- Patch already applied.
Applying: drm/amd/display: Only define DP 2.0 symbols if not already defined
error: sha1 information is lacking or useless 
(drivers/gpu/drm/amd/display/dc/dc_dp_types.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/amd/display: Only define DP 2.0 symbols if not already 
defined
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations

[Shankar, Uma]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Tuesday, September 21, 2021 8:27 PM
> To: Shankar, Uma 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size
> calculations
> 
> On Mon, Sep 06, 2021 at 05:23:42AM +, Shankar, Uma wrote:
> >
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf
> > > Of Ville Syrjala
> > > Sent: Saturday, July 3, 2021 2:16 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb
> > > stride/size calculations
> > >
> > > From: Ville Syrjälä 
> > >
> > > The code to calculate the cfb stride/size is a bit of mess.
> > > The cfb size is getting calculated based purely on the plane stride and 
> > > plane
> height.
> > > That doesn't account for extra alignment we want for the cfb stride.
> > > The gen9 override stride OTOH is just calculated based on the plane
> > > width, and it does try to make things more aligned but any extra
> > > alignment added there is not considered in the cfb size calculations.
> > > So not at all convinced this is working as intended. Additionally
> > > the compression limit handling is split between the cfb allocation
> > > code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just 
> > > confusing.
> > >
> > > Let's streamline the whole thing:
> > > - Start with the plane stride, convert that into cfb stride (cfb is
> > >   always 4 bytes per pixel). All the calculations will assume 1:1
> > >   compression limit since that will give us the max values, and we
> > >   don't yet know how much stolen memory we will be able to allocate
> > > - Align the cfb stride to 512 bytes on modern platforms. This guarantees
> > >   the 4 line segment will be 512 byte aligned regardles of the final
> > >   compression limit we choose later. The 512 byte alignment for the
> > >   segment is required by at least some of the platforms, and just doing
> > >   it always seems like the easiest option
> > > - Figure out if we need to use the override stride or not. For X-tiled
> > >   it's never needed since the plane stride is already 512 byte aligned,
> > >   for Y-tiled it will be needed if the plane stride is not a multiple
> > >   of 512 bytes, and for linear it's apparently always needed because the
> > >   hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
> > >   the PLANE_STRIDE*64 that it use with linear.
> > > - The cfb size will be calculated based on the aligned cfb stride to
> > >   guarantee we actually reserved enough stolen memory and the FBC hw
> > >   won't end up scribbling over whatever else is allocated in stolen
> > > - The compression limit handling we just do fully in the cfb allocation
> > >   code to make things less confusing
> > >
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_fbc.c | 141 ++-
> > >  drivers/gpu/drm/i915/i915_drv.h  |   4 +-
> > >  2 files changed, 90 insertions(+), 55 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index f5cbbc53837c..2baf58af016c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -62,19 +62,54 @@ static void
> > > intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *
> > >   *height = cache->plane.src_h;
> > >  }
> > >
> > > -static int intel_fbc_calculate_cfb_size(struct drm_i915_private 
> > > *dev_priv,
> > > - const struct intel_fbc_state_cache 
> > > *cache)
> > > +/* plane stride in pixels */
> > > +static unsigned int intel_fbc_plane_stride(const struct
> > > +intel_plane_state *plane_state)
> > >  {
> > > - int lines;
> > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + unsigned int stride;
> > > +
> > > + stride = plane_state->view.color_plane[0].stride;
> > > + if (!drm_rotation_90_or_270(plane_state->hw.rotation))
> > > + stride /= fb->format->cpp[0];
> > > +
> > > + return stride;
> > > +}
> > > +
> > > +/* plane stride based cfb stride in bytes, assuming 1:1 compression
> > > +limit */ static unsigned int _intel_fbc_cfb_stride(const struct
> > > +intel_fbc_state_cache *cache) {
> > > + /* FBC always 4 bytes per pixel internally */
> > > + return cache->fb.stride * 4;
> > > +}
> > > +
> > > +/* properly aligned cfb stride in bytes, assuming 1:1 compression
> > > +limit */ static unsigned int intel_fbc_cfb_stride(struct 
> > > drm_i915_private *i915,
> > > +  const struct intel_fbc_state_cache 
> > > *cache)
> > > {
> > > + unsigned int stride = _intel_fbc_cfb_stride(cache);
> > > +
> > > + /*
> > > +  * At least some of the platforms require each 4 line segment to
> > > +  * be 512 byte aligned. Aligning each line to 512 bytes guarantees
> > > +  * that regardless of the compression limit we 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)

[Thomas Hellström]

On 9/22/21 11:05 AM, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
*URL:* 	https://patchwork.freedesktop.org/series/94278/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html 




  CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_21124_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21124_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_21124_full:



  IGT changes


Possible regressions

  * igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
  o shard-tglb: PASS


-> INCOMPLETE






Lakshmi, this failure is unrelated.

The igt@gem_exec_schedule@u-submit-golden-slice plus some other subtests 
have been broken since igt commit


a9987a8d tests/i915/gem_exec_schedule: Convert to intel_ctx_t (v3)

Although the tests typically says SUCCESS, it's because they typically 
are interrupted by the watchdog and move on.


Thanks,

Thomas

Re: [Intel-gfx] [PATCH v4 10/14] drm/i915/ttm: hide shmem objects from TTM LRU

[Christian König]

Am 22.09.21 um 15:34 schrieb Matthew Auld:

On 21/09/2021 12:48, Christian König wrote:

Am 21.09.21 um 13:01 schrieb Matthew Auld:

This is probably a NAK. But ideally we need to somehow prevent TTM from
seeing shmem objects when doing its LRU swap walk. Since these are
EXTERNAL they are ignored anyway, but keeping them in the LRU seems
pretty wasteful.  Trying to use bo_pin() for this is all kinds of nasty
since we need to be able to do the bo_unpin() from the unpopulate hook,
but since that can be called from the BO destroy path we will likely go
down in flames.

An alternative is to maybe just add EXTERNAL objects to some
bdev->external LRU in TTM, or just don't add them at all?


Yeah, that goes into the same direction as why I want to push the LRU 
into the resource for some time.


The problem is that the LRU is needed for multiple things. E.g. 
swapping, GART management, resource constrains, IOMMU teardown etc..


So for now I think that everything should be on the LRU even if it 
isn't valid to be there for some use case.


Ok. Is it a no-go to keep TT_FLAG_EXTERNAL on say bdev->external?


We could add that as a workaround, but I would rather aim for cleaning 
that up more thoughtfully.


Regards,
Christian.





Regards,
Christian.



Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Christian König 
---
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 17 +
  1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c

index 174aebe11264..b438ddb52764 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -800,6 +800,22 @@ static unsigned long i915_ttm_io_mem_pfn(struct 
ttm_buffer_object *bo,

  return ((base + sg_dma_address(sg)) >> PAGE_SHIFT) + ofs;
  }
+static void i915_ttm_del_from_lru_notify(struct ttm_buffer_object *bo)
+{
+    struct i915_ttm_tt *i915_tt =
+    container_of(bo->ttm, typeof(*i915_tt), ttm);
+
+    /* Idealy we need to prevent TTM from seeing shmem objects when 
doing
+ * its LRU swap walk. Since these are EXTERNAL they are ignored 
anyway,
+ * but keeping them in the LRU is pretty waseful. Trying to use 
bo_pin()
+ * for this is very nasty since we need to be able to do the 
bo_unpin()
+ * from the unpopulate hook, but since that can be called from 
the BO

+ * destroy path we will go down in flames.
+ */
+    if (bo->ttm && ttm_tt_is_populated(bo->ttm) && i915_tt->is_shmem)
+    list_del_init(>lru);
+}
+
  static struct ttm_device_funcs i915_ttm_bo_driver = {
  .ttm_tt_create = i915_ttm_tt_create,
  .ttm_tt_populate = i915_ttm_tt_populate,
@@ -810,6 +826,7 @@ static struct ttm_device_funcs 
i915_ttm_bo_driver = {

  .move = i915_ttm_move,
  .swap_notify = i915_ttm_swap_notify,
  .delete_mem_notify = i915_ttm_delete_mem_notify,
+    .del_from_lru_notify = i915_ttm_del_from_lru_notify,
  .io_mem_reserve = i915_ttm_io_mem_reserve,
  .io_mem_pfn = i915_ttm_io_mem_pfn,
  };

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop stealing of bits from i915_sw_fence function pointer (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer 
(rev3)
URL   : https://patchwork.freedesktop.org/series/94924/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627 -> Patchwork_21131


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/index.html

Known issues


  Here are the changes found in Patchwork_21131 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][3] ([fdo#109315])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][4] ([fdo#109271]) +23 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-ilk-650: [PASS][6] -> [DMESG-WARN][7] ([i915#164]) +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html
- fi-bdw-5557u:   NOTRUN -> [WARN][8] ([i915#3718])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  NOTRUN -> [FAIL][9] ([i915#1888])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][10] ([i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][12] ([i915#1155])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-cfl-8109u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cfl-8109u:   NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][19] ([i915#3301])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21131/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u:   [INCOMPLETE][20] ([i915#155]) -> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Drop stealing of bits from i915_sw_fence function pointer (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer 
(rev3)
URL   : https://patchwork.freedesktop.org/series/94924/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4d52201ec9d6 drm/i915: Drop stealing of bits from i915_sw_fence function pointer
-:8: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'?
#8: 
seperate fields for function pointer and flags. If using two different


-:112: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#112: FILE: drivers/gpu/drm/i915/i915_sw_fence.c:244:
+   BUG_ON(!fn);

total: 0 errors, 2 warnings, 0 checks, 195 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Per client GPU stats (rev4)

[Patchwork]

== Series Details ==

Series: Per client GPU stats (rev4)
URL   : https://patchwork.freedesktop.org/series/92574/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10627 -> Patchwork_21130


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/index.html

Known issues


  Here are the changes found in Patchwork_21130 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][3] ([fdo#109315])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][4] ([fdo#109271]) +23 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][6] ([i915#3718])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  NOTRUN -> [FAIL][7] ([i915#1888])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][10] ([i915#1155])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-icl-y:   [PASS][11] -> [DMESG-FAIL][12] ([i915#2291])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-icl-y/igt@i915_selftest@live@gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-icl-y/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-cfl-8109u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cfl-8109u:   NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][19] ([i915#3301])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21130/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u:   [INCOMPLETE][20] ([i915#155]) -> [PASS][21]
   [20]: 

Re: [Intel-gfx] [PATCH 20/27] drm/i915/guc: Connect UAPI to GuC multi-lrc interface

[Matthew Brost]

On Mon, Sep 20, 2021 at 05:09:28PM -0700, John Harrison wrote:
> On 8/20/2021 15:44, Matthew Brost wrote:
> > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> > 
> > IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
> > media UMD: link to come
> Is this link still not available?
> 

Have it now: https://github.com/intel/media-driver/pull/1252

> Also, see 'kernel test robot' emails saying that sparse is complaining about
> something I don't understand but presumably needs to be fixed.
>

Yea, those warning need to be fixed.
 
> 
> > 
> > v2:
> >   (Daniel Vetter)
> >- Add IGT link and placeholder for media UMD link
> > 
> > Cc: Tvrtko Ursulin 
> > Signed-off-by: Matthew Brost 
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c   | 220 +-
> >   .../gpu/drm/i915/gem/i915_gem_context_types.h |   6 +
> >   drivers/gpu/drm/i915/gt/intel_context_types.h |   9 +-
> >   drivers/gpu/drm/i915/gt/intel_engine.h|  12 +-
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c |   6 +-
> >   .../drm/i915/gt/intel_execlists_submission.c  |   6 +-
> >   drivers/gpu/drm/i915/gt/selftest_execlists.c  |  12 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
> >   include/uapi/drm/i915_drm.h   | 128 ++
> >   9 files changed, 485 insertions(+), 28 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index bcaaf514876b..de0fd145fb47 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -522,9 +522,149 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
> > __user *base, void *data)
> > return 0;
> >   }
> > +static int
> > +set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user 
> > *base,
> > + void *data)
> > +{
> > +   struct i915_context_engines_parallel_submit __user *ext =
> > +   container_of_user(base, typeof(*ext), base);
> > +   const struct set_proto_ctx_engines *set = data;
> > +   struct drm_i915_private *i915 = set->i915;
> > +   u64 flags;
> > +   int err = 0, n, i, j;
> > +   u16 slot, width, num_siblings;
> > +   struct intel_engine_cs **siblings = NULL;
> > +   intel_engine_mask_t prev_mask;
> > +
> > +   /* Disabling for now */
> > +   return -ENODEV;
> > +
> > +   if (!(intel_uc_uses_guc_submission(>gt.uc)))
> > +   return -ENODEV;
> This needs a FIXME comment to say that exec list will be added later.
> 

Sure.

> > +
> > +   if (get_user(slot, >engine_index))
> > +   return -EFAULT;
> > +
> > +   if (get_user(width, >width))
> > +   return -EFAULT;
> > +
> > +   if (get_user(num_siblings, >num_siblings))
> > +   return -EFAULT;
> > +
> > +   if (slot >= set->num_engines) {
> > +   drm_dbg(>drm, "Invalid placement value, %d >= %d\n",
> > +   slot, set->num_engines);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
> > +   drm_dbg(>drm,
> > +   "Invalid placement[%d], already occupied\n", slot);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (get_user(flags, >flags))
> > +   return -EFAULT;
> > +
> > +   if (flags) {
> > +   drm_dbg(>drm, "Unknown flags 0x%02llx", flags);
> > +   return -EINVAL;
> > +   }
> > +
> > +   for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
> > +   err = check_user_mbz(>mbz64[n]);
> > +   if (err)
> > +   return err;
> > +   }
> > +
> > +   if (width < 2) {
> > +   drm_dbg(>drm, "Width (%d) < 2\n", width);
> > +   return -EINVAL;
> > +   }
> > +
> > +   if (num_siblings < 1) {
> > +   drm_dbg(>drm, "Number siblings (%d) < 1\n",
> > +   num_siblings);
> > +   return -EINVAL;
> > +   }
> > +
> > +   siblings = kmalloc_array(num_siblings * width,
> > +sizeof(*siblings),
> > +GFP_KERNEL);
> > +   if (!siblings)
> > +   return -ENOMEM;
> > +
> > +   /* Create contexts / engines */
> > +   for (i = 0; i < width; ++i) {
> > +   intel_engine_mask_t current_mask = 0;
> > +   struct i915_engine_class_instance prev_engine;
> > +
> > +   for (j = 0; j < num_siblings; ++j) {
> > +   struct i915_engine_class_instance ci;
> > +
> > +   n = i * num_siblings + j;
> > +   if (copy_from_user(, >engines[n], sizeof(ci))) {
> > +   err = -EFAULT;
> > +   goto out_err;
> > +   }
> > +
> > +   siblings[n] =
> > +   intel_engine_lookup_user(i915, ci.engine_class,
> > +

Re: [Intel-gfx] [PATCH 15/27] drm/i915/guc: Implement multi-lrc submission

[Matthew Brost]

On Mon, Sep 20, 2021 at 02:48:52PM -0700, John Harrison wrote:
> On 8/20/2021 15:44, Matthew Brost wrote:
> > Implement multi-lrc submission via a single workqueue entry and single
> > H2G. The workqueue entry contains an updated tail value for each
> > request, of all the contexts in the multi-lrc submission, and updates
> > these values simultaneously. As such, the tasklet and bypass path have
> > been updated to coalesce requests into a single submission.
> > 
> > Signed-off-by: Matthew Brost 
> > ---
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.c|  21 ++
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h|   8 +
> >   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  24 +-
> >   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   6 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 312 +++---
> >   drivers/gpu/drm/i915/i915_request.h   |   8 +
> >   6 files changed, 317 insertions(+), 62 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index fbfcae727d7f..879aef662b2e 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -748,3 +748,24 @@ void intel_guc_load_status(struct intel_guc *guc, 
> > struct drm_printer *p)
> > }
> > }
> >   }
> > +
> > +void intel_guc_write_barrier(struct intel_guc *guc)
> > +{
> > +   struct intel_gt *gt = guc_to_gt(guc);
> > +
> > +   if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
> > +   GEM_BUG_ON(guc->send_regs.fw_domains);
> Granted, this patch is just moving code from one file to another not
> changing it. However, I think it would be worth adding a blank line in here.
> Otherwise the 'this register' comment below can be confusingly read as
> referring to the send_regs.fw_domain entry above.
> 
> And maybe add a comment why it is a bug for the send_regs value to be set?
> I'm not seeing any obvious connection between it and the reset of this code.
> 

Can add a blank line. I think the GEM_BUG_ON relates to being able to
use intel_uncore_write_fw vs intel_uncore_write. Can add comment.

> > +   /*
> > +* This register is used by the i915 and GuC for MMIO based
> > +* communication. Once we are in this code CTBs are the only
> > +* method the i915 uses to communicate with the GuC so it is
> > +* safe to write to this register (a value of 0 is NOP for MMIO
> > +* communication). If we ever start mixing CTBs and MMIOs a new
> > +* register will have to be chosen.
> > +*/
> > +   intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
> > +   } else {
> > +   /* wmb() sufficient for a barrier if in smem */
> > +   wmb();
> > +   }
> > +}
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 3f95b1b4f15c..0ead2406d03c 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -37,6 +37,12 @@ struct intel_guc {
> > /* Global engine used to submit requests to GuC */
> > struct i915_sched_engine *sched_engine;
> > struct i915_request *stalled_request;
> > +   enum {
> > +   STALL_NONE,
> > +   STALL_REGISTER_CONTEXT,
> > +   STALL_MOVE_LRC_TAIL,
> > +   STALL_ADD_REQUEST,
> > +   } submission_stall_reason;
> > /* intel_guc_recv interrupt related state */
> > spinlock_t irq_lock;
> > @@ -332,4 +338,6 @@ void intel_guc_submission_cancel_requests(struct 
> > intel_guc *guc);
> >   void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
> > +void intel_guc_write_barrier(struct intel_guc *guc);
> > +
> >   #endif
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > index 20c710a74498..10d1878d2826 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > @@ -377,28 +377,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
> > return ++ct->requests.last_fence;
> >   }
> > -static void write_barrier(struct intel_guc_ct *ct)
> > -{
> > -   struct intel_guc *guc = ct_to_guc(ct);
> > -   struct intel_gt *gt = guc_to_gt(guc);
> > -
> > -   if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
> > -   GEM_BUG_ON(guc->send_regs.fw_domains);
> > -   /*
> > -* This register is used by the i915 and GuC for MMIO based
> > -* communication. Once we are in this code CTBs are the only
> > -* method the i915 uses to communicate with the GuC so it is
> > -* safe to write to this register (a value of 0 is NOP for MMIO
> > -* communication). If we ever start mixing CTBs and MMIOs a new
> > -* register will have to be chosen.
> > -*/
> > -   intel_uncore_write_fw(gt->uncore, 

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Only keep PSR enabled if there is active planes

[Gwan-gyeong Mun]

Looks good to me.
Reviewed-by: Gwan-gyeong Mun 

On 9/21/21 3:41 AM, José Roberto de Souza wrote:

PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.

Similar behavior was fixed during the pipe disable sequence by
commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before 
planes").

intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.

Cc: Ville Syrjälä 
Cc: Gwan-gyeong Mun 
Signed-off-by: José Roberto de Souza 
---
  drivers/gpu/drm/i915/display/intel_ddi.c  |   2 -
  drivers/gpu/drm/i915/display/intel_display.c  |  14 +-
  .../drm/i915/display/intel_display_types.h|   3 +-
  drivers/gpu/drm/i915/display/intel_dp.c   |   6 +-
  drivers/gpu/drm/i915/display/intel_dp.h   |   2 +-
  drivers/gpu/drm/i915/display/intel_psr.c  | 140 ++
  drivers/gpu/drm/i915/display/intel_psr.h  |  11 +-
  7 files changed, 98 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bba0ab99836b1..a4667741d3548 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3034,7 +3034,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state 
*state,
intel_dp_stop_link_train(intel_dp, crtc_state);
  
  	intel_edp_backlight_on(crtc_state, conn_state);

-   intel_psr_enable(intel_dp, crtc_state, conn_state);
  
  	if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
@@ -3255,7 +3254,6 @@ static void intel_ddi_update_pipe_dp(struct 
intel_atomic_state *state,
  
  	intel_ddi_set_dp_msa(crtc_state, conn_state);
  
-	intel_psr_update(intel_dp, crtc_state, conn_state);

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_drrs_update(intel_dp, crtc_state);
  
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c

index f6c0c595f6313..ddcd8d6efc788 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8093,10 +8093,12 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, 
bp_gamma);
  
-		PIPE_CONF_CHECK_BOOL(has_psr);

-   PIPE_CONF_CHECK_BOOL(has_psr2);
-   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-   PIPE_CONF_CHECK_I(dc3co_exitline);
+   if (current_config->active_planes) {
+   PIPE_CONF_CHECK_BOOL(has_psr);
+   PIPE_CONF_CHECK_BOOL(has_psr2);
+   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+   PIPE_CONF_CHECK_I(dc3co_exitline);
+   }
}
  
  	PIPE_CONF_CHECK_BOOL(double_wide);

@@ -8153,7 +8155,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
}
  
-	if (fastset && (current_config->has_psr || pipe_config->has_psr))

+   if (current_config->has_psr || pipe_config->has_psr)
PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,

~intel_hdmi_infoframe_enable(DP_SDP_VSC));
else
@@ -10207,6 +10209,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
intel_encoders_update_prepare(state);
  
  	intel_dbuf_pre_plane_update(state);

+   intel_psr_pre_plane_update(state);
  
  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

if (new_crtc_state->uapi.async_flip)
@@ -10270,6 +10273,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
}
  
  	intel_dbuf_post_plane_update(state);

+   intel_psr_post_plane_update(state);
  
  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

intel_post_plane_update(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e9e806d90eec4..c900bfbb7cc52 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1056,12 +1056,14 @@ struct intel_crtc_state {
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
  
+	/* PSR is supported but might not be enabled due the lack of enabled planes */

bool has_psr;
bool has_psr2;
bool enable_psr2_sel_fetch;
bool 

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Only keep PSR enabled if there is active planes

[Gwan-gyeong Mun]

Looks good to me.
Reviewed-by: Gwan-gyeong Mun 

On 9/21/21 3:41 AM, José Roberto de Souza wrote:

PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.

Similar behavior was fixed during the pipe disable sequence by
commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before 
planes").

intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.

Cc: Ville Syrjälä 
Cc: Gwan-gyeong Mun 
Signed-off-by: José Roberto de Souza 
---
  drivers/gpu/drm/i915/display/intel_ddi.c  |   2 -
  drivers/gpu/drm/i915/display/intel_display.c  |  14 +-
  .../drm/i915/display/intel_display_types.h|   3 +-
  drivers/gpu/drm/i915/display/intel_dp.c   |   6 +-
  drivers/gpu/drm/i915/display/intel_dp.h   |   2 +-
  drivers/gpu/drm/i915/display/intel_psr.c  | 140 ++
  drivers/gpu/drm/i915/display/intel_psr.h  |  11 +-
  7 files changed, 98 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bba0ab99836b1..a4667741d3548 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3034,7 +3034,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state 
*state,
intel_dp_stop_link_train(intel_dp, crtc_state);
  
  	intel_edp_backlight_on(crtc_state, conn_state);

-   intel_psr_enable(intel_dp, crtc_state, conn_state);
  
  	if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
@@ -3255,7 +3254,6 @@ static void intel_ddi_update_pipe_dp(struct 
intel_atomic_state *state,
  
  	intel_ddi_set_dp_msa(crtc_state, conn_state);
  
-	intel_psr_update(intel_dp, crtc_state, conn_state);

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_drrs_update(intel_dp, crtc_state);
  
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c

index f6c0c595f6313..ddcd8d6efc788 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8093,10 +8093,12 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
if (bp_gamma)
PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, 
bp_gamma);
  
-		PIPE_CONF_CHECK_BOOL(has_psr);

-   PIPE_CONF_CHECK_BOOL(has_psr2);
-   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-   PIPE_CONF_CHECK_I(dc3co_exitline);
+   if (current_config->active_planes) {
+   PIPE_CONF_CHECK_BOOL(has_psr);
+   PIPE_CONF_CHECK_BOOL(has_psr2);
+   PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+   PIPE_CONF_CHECK_I(dc3co_exitline);
+   }
}
  
  	PIPE_CONF_CHECK_BOOL(double_wide);

@@ -8153,7 +8155,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
}
  
-	if (fastset && (current_config->has_psr || pipe_config->has_psr))

+   if (current_config->has_psr || pipe_config->has_psr)
PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,

~intel_hdmi_infoframe_enable(DP_SDP_VSC));
else
@@ -10207,6 +10209,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
intel_encoders_update_prepare(state);
  
  	intel_dbuf_pre_plane_update(state);

+   intel_psr_pre_plane_update(state);
  
  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

if (new_crtc_state->uapi.async_flip)
@@ -10270,6 +10273,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
}
  
  	intel_dbuf_post_plane_update(state);

+   intel_psr_post_plane_update(state);
  
  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

intel_post_plane_update(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e9e806d90eec4..c900bfbb7cc52 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1056,12 +1056,14 @@ struct intel_crtc_state {
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
  
+	/* PSR is supported but might not be enabled due the lack of enabled planes */

bool has_psr;
bool has_psr2;
bool enable_psr2_sel_fetch;
bool 

Re: [Intel-gfx] [PATCH 17/27] drm/i915/guc: Implement multi-lrc reset

[Matthew Brost]

On Mon, Sep 20, 2021 at 03:44:18PM -0700, John Harrison wrote:
> On 8/20/2021 15:44, Matthew Brost wrote:
> 
> Update context and full GPU reset to work with multi-lrc. The idea is
> parent context tracks all the active requests inflight for itself and
> its' children. The parent context owns the reset replaying / canceling
> 
> its' -> its
> 
> 
> requests as needed.
> 
> Signed-off-by: Matthew Brost 
> ---
>  drivers/gpu/drm/i915/gt/intel_context.c   | 11 ++--
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 63 +--
>  2 files changed, 51 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
> b/drivers/gpu/drm/i915/gt/intel_context.c
> index 00d1aee6d199..5615be32879c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -528,20 +528,21 @@ struct i915_request 
> *intel_context_create_request(struct intel_context *ce)
> 
>  struct i915_request *intel_context_find_active_request(struct 
> intel_context *ce)
>  {
> +   struct intel_context *parent = intel_context_to_parent(ce);
> struct i915_request *rq, *active = NULL;
> unsigned long flags;
> 
> GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
> 
> Should this not check the parent as well/instead?
> 

I don't think so. The 'ce' could be a not parallel context, a parent
context, or a child context. 

> And to be clear, this can be called on regular contexts (where ce == parent)
> and on both the parent or child contexts of multi-LRC contexts (where ce may 
> or
> may not match parent)?
>

Right. The parent owns the parent->guc_state.lock/requests and search
that list for the first non-completed request that matches submitted
'ce'.
 
> 
> 
> 
> -   spin_lock_irqsave(>guc_state.lock, flags);
> -   list_for_each_entry_reverse(rq, >guc_state.requests,
> +   spin_lock_irqsave(>guc_state.lock, flags);
> +   list_for_each_entry_reverse(rq, >guc_state.requests,
> sched.link) {
> -   if (i915_request_completed(rq))
> +   if (i915_request_completed(rq) && rq->context == ce)
> 
> 'rq->context == ce' means:
> 
>  1. single-LRC context, rq is owned by ce
>  2. multi-LRC context, ce is child, rq really belongs to ce but is being
> tracked by parent
>  3. multi-LRC context, ce is parent, rq really is owned by ce
> 
> So when 'rq->ce != ce', it means that the request is owned by a different 
> child
> to 'ce' but within the same multi-LRC group. So we want to ignore that request
> and keep searching until we find one that is really owned by the target ce?
>

All correct.
 
> 
> break;
> 
> -   active = rq;
> +   active = (rq->context == ce) ? rq : active;
> 
> Would be clearer to say 'if(rq->ce != ce) continue;' and leave 'active = rq;'
> alone?
>

Yes, that is probably cleaner.
 
> And again, the intention is to ignore requests that are owned by other members
> of the same multi-LRC group?
> 
> Would be good to add some documentation to this function to explain the above
> (assuming my description is correct?).
>

Will add a comment explaining this.
 
> 
> }
> -   spin_unlock_irqrestore(>guc_state.lock, flags);
> +   spin_unlock_irqrestore(>guc_state.lock, flags);
> 
> return active;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index f0b60fecf253..e34e0ea9136a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -670,6 +670,11 @@ static int rq_prio(const struct i915_request *rq)
> return rq->sched.attr.priority;
>  }
> 
> +static inline bool is_multi_lrc(struct intel_context *ce)
> +{
> +   return intel_context_is_parallel(ce);
> +}
> +
>  static bool is_multi_lrc_rq(struct i915_request *rq)
>  {
> return intel_context_is_parallel(rq->context);
> @@ -1179,10 +1184,13 @@ __unwind_incomplete_requests(struct intel_context 
> *ce)
> 
>  static void __guc_reset_context(struct intel_context *ce, bool stalled)
>  {
> +   bool local_stalled;
> struct i915_request *rq;
> unsigned long flags;
> u32 head;
> +   int i, number_children = ce->guc_number_children;
> 
> If this is a child context, does it not need to pull the child count from the
> parent? Likewise the list/link pointers below? Or does each child context have
> a full list of its siblings + parent?
> 

This function shouldn't be called by a child. Will add
GEM_BUG_ON(intel_context_is_child(ce)) to this function.

> 
> bool skip = false;
> +   struct intel_context *parent = ce;
> 
> 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Per client GPU stats (rev4)

[Patchwork]

== Series Details ==

Series: Per client GPU stats (rev4)
URL   : https://patchwork.freedesktop.org/series/92574/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:379: warning: Function 
parameter or member 'client_link' not described in 'i915_gem_context'

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per client GPU stats (rev4)

[Patchwork]

== Series Details ==

Series: Per client GPU stats (rev4)
URL   : https://patchwork.freedesktop.org/series/92574/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' 
- different lock contexts for basic block

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per client GPU stats (rev4)

[Patchwork]

== Series Details ==

Series: Per client GPU stats (rev4)
URL   : https://patchwork.freedesktop.org/series/92574/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d3ced17ae466 drm/i915: Explicitly track DRM clients
-:88: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#88: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 231 lines checked
23952d0281f4 drm/i915: Make GEM contexts track DRM clients
aa77a600c1f2 drm/i915: Track runtime spent in closed and unreachable GEM 
contexts
6f240d00ff32 drm/i915: Track all user contexts per client
13cdce7379be drm/i915: Track context current active time
-:139: WARNING:LINE_SPACING: Missing a blank line after declarations
#139: FILE: drivers/gpu/drm/i915/gt/intel_context_types.h:143:
+   u32 last;
+   I915_SELFTEST_DECLARE(u32 num_underflow);

total: 0 errors, 1 warnings, 0 checks, 296 lines checked
4c4f367b390e drm: Document fdinfo format specification
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#40: 
new file mode 100644

-:45: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#45: FILE: Documentation/gpu/drm-usage-stats.rst:1:
+.. _drm-client-usage-stats:

total: 0 errors, 2 warnings, 0 checks, 104 lines checked
91c47a76ce10 drm/i915: Expose client engine utilisation via fdinfo

[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/display: split and constify vtable (rev7)

[Patchwork]

== Series Details ==

Series: i915/display: split and constify vtable (rev7)
URL   : https://patchwork.freedesktop.org/series/94459/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10627 -> Patchwork_21129


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21129 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21129, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21129:

### IGT changes ###

 Possible regressions 

  * igt@kms_busy@basic@modeset:
- fi-skl-6600u:   [PASS][1] -> [DMESG-WARN][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-skl-6600u/igt@kms_busy@ba...@modeset.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-skl-6600u/igt@kms_busy@ba...@modeset.html
- fi-cml-u2:  [PASS][3] -> [DMESG-WARN][4] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-cml-u2/igt@kms_busy@ba...@modeset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-cml-u2/igt@kms_busy@ba...@modeset.html

  * igt@runner@aborted:
- fi-rkl-11600:   NOTRUN -> [FAIL][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-rkl-11600/igt@run...@aborted.html
- fi-tgl-y:   NOTRUN -> [FAIL][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-tgl-y/igt@run...@aborted.html
- fi-tgl-1115g4:  NOTRUN -> [FAIL][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-tgl-1115g4/igt@run...@aborted.html
- fi-tgl-u2:  NOTRUN -> [FAIL][8]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-tgl-u2/igt@run...@aborted.html

  
 Warnings 

  * igt@runner@aborted:
- fi-rkl-guc: [FAIL][9] ([i915#3928]) -> [FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-rkl-guc/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-rkl-guc/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {fi-tgl-dsi}:   NOTRUN -> [FAIL][11]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-tgl-dsi/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][12]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-ehl-2/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_21129 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-kbl-soraka/igt@kms_busy@ba...@flip.html

  * igt@kms_busy@basic@modeset:
- fi-kbl-soraka:  [PASS][16] -> [DMESG-WARN][17] ([i915#95])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10627/fi-kbl-soraka/igt@kms_busy@ba...@modeset.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-kbl-soraka/igt@kms_busy@ba...@modeset.html

  * igt@runner@aborted:
- fi-kbl-x1275:   NOTRUN -> [FAIL][18] ([i915#1569] / [i915#192] / 
[i915#193] / [i915#194] / [i915#3363])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-kbl-x1275/igt@run...@aborted.html
- fi-cfl-8700k:   NOTRUN -> [FAIL][19] ([i915#3363] / [k.org#202107] / 
[k.org#202109])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u:   NOTRUN -> [FAIL][20] ([i915#1814] / [i915#2426] / 
[i915#3363])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u:   NOTRUN -> [FAIL][21] ([i915#3363] / [k.org#202107] / 
[k.org#202109])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2:  NOTRUN -> [FAIL][22] ([i915#1569] / [i915#3363])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21129/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][23] ([i915#3363] / [k.org#202321])
   [23]: 

[Intel-gfx] [PATCH] drm/i915: Drop stealing of bits from i915_sw_fence function pointer

[Matthew Brost]

Rather than stealing bits from i915_sw_fence function pointer use
seperate fields for function pointer and flags. If using two different
fields, the 4 byte alignment for the i915_sw_fence function pointer can
also be dropped.

v2:
 (CI)
  - Set new function field rather than flags in __i915_sw_fence_init
v3:
 (Tvrtko)
  - Remove BUG_ON(!fence->flags) in reinit as that will now blow up
  - Only define fence->flags if CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is
defined

Signed-off-by: Matthew Brost 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
 drivers/gpu/drm/i915/i915_request.c   |  4 +--
 drivers/gpu/drm/i915/i915_sw_fence.c  | 28 +++
 drivers/gpu/drm/i915/i915_sw_fence.h  | 23 +++
 drivers/gpu/drm/i915/i915_sw_fence_work.c |  2 +-
 .../gpu/drm/i915/selftests/i915_sw_fence.c|  2 +-
 drivers/gpu/drm/i915/selftests/lib_sw_fence.c |  8 +++---
 8 files changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a7ca38613f89..6d5bb55ffc82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10323,7 +10323,7 @@ static void intel_atomic_commit_work(struct work_struct 
*work)
intel_atomic_commit_tail(state);
 }
 
-static int __i915_sw_fence_call
+static int
 intel_atomic_commit_ready(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify notify)
 {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..df5fec5c3da8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -800,7 +800,7 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
 }
 
-static int __i915_sw_fence_call
+static int
 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_gem_engines *engines =
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index ce446716d092..945d3025a0b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -719,7 +719,7 @@ void i915_request_cancel(struct i915_request *rq, int error)
intel_context_cancel_request(rq->context, rq);
 }
 
-static int __i915_sw_fence_call
+static int
 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_request *request =
@@ -755,7 +755,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
return NOTIFY_DONE;
 }
 
-static int __i915_sw_fence_call
+static int
 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index c589a681da77..f10d31818ecc 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -18,7 +18,9 @@
 #define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
 #endif
 
+#ifdef CONFIG_DRM_I915_SW_FENCE_CHECK_DAG
 static DEFINE_SPINLOCK(i915_sw_fence_lock);
+#endif
 
 #define WQ_FLAG_BITS \
BITS_PER_TYPE(typeof_member(struct wait_queue_entry, flags))
@@ -34,7 +36,7 @@ enum {
 
 static void *i915_sw_fence_debug_hint(void *addr)
 {
-   return (void *)(((struct i915_sw_fence *)addr)->flags & 
I915_SW_FENCE_MASK);
+   return (void *)(((struct i915_sw_fence *)addr)->fn);
 }
 
 #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -126,10 +128,7 @@ static inline void debug_fence_assert(struct i915_sw_fence 
*fence)
 static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify state)
 {
-   i915_sw_fence_notify_t fn;
-
-   fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
-   return fn(fence, state);
+   return fence->fn(fence, state);
 }
 
 #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -242,10 +241,13 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
  const char *name,
  struct lock_class_key *key)
 {
-   BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+   BUG_ON(!fn);
 
__init_waitqueue_head(>wait, name, key);
-   fence->flags = (unsigned long)fn;
+   fence->fn = fn;
+#ifdef CONFIG_DRM_I915_SW_FENCE_CHECK_DAG
+   fence->flags = 0;
+#endif
 
i915_sw_fence_reinit(fence);
 }
@@ -257,7 +259,6 @@ void i915_sw_fence_reinit(struct i915_sw_fence *fence)
atomic_set(>pending, 1);
fence->error = 0;
 
-   I915_SW_FENCE_BUG_ON(!fence->flags);
I915_SW_FENCE_BUG_ON(!list_empty(>wait.head));
 }
 
@@ -279,6 +280,7 @@ static int 

[Intel-gfx] [PATCH 2/7] drm/i915: Make GEM contexts track DRM clients

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Make GEM contexts keep a reference to i915_drm_client for the whole of
of their lifetime which will come handy in following patches.

v2: Don't bother supporting selftests contexts from debugfs. (Chris)
v3 (Lucas): Finish constructing ctx before adding it to the list
v4 (Ram): Rebase.
v5: Trivial rebase for proto ctx changes.
v6: Rebase after clients no longer track name and pid.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson  # v5
Reviewed-by: Aravind Iddamsetty  # v5
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 5 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..70340663136e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -956,6 +956,9 @@ static void i915_gem_context_release_work(struct 
work_struct *work)
if (vm)
i915_vm_put(vm);
 
+   if (ctx->client)
+   i915_drm_client_put(ctx->client);
+
mutex_destroy(>engines_mutex);
mutex_destroy(>lut_mutex);
 
@@ -1373,6 +1376,8 @@ static void gem_context_register(struct i915_gem_context 
*ctx,
ctx->file_priv = fpriv;
 
ctx->pid = get_task_pid(current, PIDTYPE_PID);
+   ctx->client = i915_drm_client_get(fpriv->client);
+
snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
 current->comm, pid_nr(ctx->pid));
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index c4617e4d9fa9..598c57ac5cdf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -277,6 +277,9 @@ struct i915_gem_context {
/** @link: place with _i915_private.context_list */
struct list_head link;
 
+   /** @client: struct i915_drm_client */
+   struct i915_drm_client *client;
+
/**
 * @ref: reference count
 *
-- 
2.30.2

[Intel-gfx] [PATCH 3/7] drm/i915: Track runtime spent in closed and unreachable GEM contexts

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

As contexts are abandoned we want to remember how much GPU time they used
(per class) so later we can used it for smarter purposes.

As GEM contexts are closed we want to have the DRM client remember how
much GPU time they used (per class) so later we can used it for smarter
purposes.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Aravind Iddamsetty 
Reviewed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
 drivers/gpu/drm/i915/i915_drm_client.h  |  7 ++
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 70340663136e..9b37723b70a9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -800,23 +800,44 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
 }
 
+static void accumulate_runtime(struct i915_drm_client *client,
+  struct i915_gem_engines *engines)
+{
+   struct i915_gem_engines_iter it;
+   struct intel_context *ce;
+
+   if (!client)
+   return;
+
+   /* Transfer accumulated runtime to the parent GEM context. */
+   for_each_gem_engine(ce, engines, it) {
+   unsigned int class = ce->engine->uabi_class;
+
+   GEM_BUG_ON(class >= ARRAY_SIZE(client->past_runtime));
+   atomic64_add(intel_context_get_total_runtime_ns(ce),
+>past_runtime[class]);
+   }
+}
+
 static int __i915_sw_fence_call
 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_gem_engines *engines =
container_of(fence, typeof(*engines), fence);
+   struct i915_gem_context *ctx = engines->ctx;
 
switch (state) {
case FENCE_COMPLETE:
if (!list_empty(>link)) {
-   struct i915_gem_context *ctx = engines->ctx;
unsigned long flags;
 
spin_lock_irqsave(>stale.lock, flags);
list_del(>link);
spin_unlock_irqrestore(>stale.lock, flags);
}
-   i915_gem_context_put(engines->ctx);
+   accumulate_runtime(ctx->client, engines);
+   i915_gem_context_put(ctx);
+
break;
 
case FENCE_FREE:
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h 
b/drivers/gpu/drm/i915/i915_drm_client.h
index e8986ad51176..9d80d9f715ee 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -9,6 +9,8 @@
 #include 
 #include 
 
+#include "gt/intel_engine_types.h"
+
 struct drm_i915_private;
 
 struct i915_drm_clients {
@@ -24,6 +26,11 @@ struct i915_drm_client {
unsigned int id;
 
struct i915_drm_clients *clients;
+
+   /**
+* @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
+*/
+   atomic64_t past_runtime[MAX_ENGINE_CLASS + 1];
 };
 
 void i915_drm_clients_init(struct i915_drm_clients *clients,
-- 
2.30.2

[Intel-gfx] [PATCH 4/7] drm/i915: Track all user contexts per client

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We soon want to start answering questions like how much GPU time is the
context belonging to a client which exited still using.

To enable this we start tracking all context belonging to a client on a
separate list.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Aravind Iddamsetty 
Reviewed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   | 12 
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h |  3 +++
 drivers/gpu/drm/i915/i915_drm_client.c|  2 ++
 drivers/gpu/drm/i915/i915_drm_client.h|  5 +
 4 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 9b37723b70a9..a1ef6be28899 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1190,6 +1190,7 @@ static void set_closed_name(struct i915_gem_context *ctx)
 
 static void context_close(struct i915_gem_context *ctx)
 {
+   struct i915_drm_client *client;
struct i915_address_space *vm;
 
/* Flush any concurrent set_engines() */
@@ -1226,6 +1227,13 @@ static void context_close(struct i915_gem_context *ctx)
list_del(>link);
spin_unlock(>i915->gem.contexts.lock);
 
+   client = ctx->client;
+   if (client) {
+   spin_lock(>ctx_lock);
+   list_del_rcu(>client_link);
+   spin_unlock(>ctx_lock);
+   }
+
mutex_unlock(>mutex);
 
/*
@@ -1406,6 +1414,10 @@ static void gem_context_register(struct i915_gem_context 
*ctx,
old = xa_store(>context_xa, id, ctx, GFP_KERNEL);
WARN_ON(old);
 
+   spin_lock(>client->ctx_lock);
+   list_add_tail_rcu(>client_link, >client->ctx_list);
+   spin_unlock(>client->ctx_lock);
+
spin_lock(>gem.contexts.lock);
list_add_tail(>link, >gem.contexts.list);
spin_unlock(>gem.contexts.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 598c57ac5cdf..b878e1b13b38 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -280,6 +280,9 @@ struct i915_gem_context {
/** @client: struct i915_drm_client */
struct i915_drm_client *client;
 
+   /** link: _client.context_list */
+   struct list_head client_link;
+
/**
 * @ref: reference count
 *
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
index e61e9ba15256..91a8559bebf7 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -38,6 +38,8 @@ struct i915_drm_client *i915_drm_client_add(struct 
i915_drm_clients *clients)
goto err;
 
kref_init(>kref);
+   spin_lock_init(>ctx_lock);
+   INIT_LIST_HEAD(>ctx_list);
client->clients = clients;
 
return client;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h 
b/drivers/gpu/drm/i915/i915_drm_client.h
index 9d80d9f715ee..7416e18aa33c 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -7,6 +7,8 @@
 #define __I915_DRM_CLIENT_H__
 
 #include 
+#include 
+#include 
 #include 
 
 #include "gt/intel_engine_types.h"
@@ -25,6 +27,9 @@ struct i915_drm_client {
 
unsigned int id;
 
+   spinlock_t ctx_lock; /* For add/remove from ctx_list. */
+   struct list_head ctx_list; /* List of contexts belonging to client. */
+
struct i915_drm_clients *clients;
 
/**
-- 
2.30.2

[Intel-gfx] [PATCH 6/7] drm: Document fdinfo format specification

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Proposal to standardise the fdinfo text format as optionally output by DRM
drivers.

Idea is that a simple but, well defined, spec will enable generic
userspace tools to be written while at the same time avoiding a more heavy
handed approach of adding a mid-layer to DRM.

i915 implements a subset of the spec, everything apart from the memory
stats currently, and a matching intel_gpu_top tool exists.

Open is to see if AMD can migrate to using the proposed GPU utilisation
key-value pairs, or if they are not workable to see whether to go
vendor specific, or if a standardised  alternative can be found which is
workable for both drivers.

Same for the memory utilisation key-value pairs proposal.

v2:
 * Update for removal of name and pid.

v3:
 * 'Drm-driver' tag will be obtained from struct drm_driver.name. (Daniel)

Signed-off-by: Tvrtko Ursulin 
Cc: David M Nieto 
Cc: Christian König 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Acked-by: Christian König 
---
 Documentation/gpu/drm-usage-stats.rst | 97 +++
 Documentation/gpu/index.rst   |  1 +
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/gpu/drm-usage-stats.rst

diff --git a/Documentation/gpu/drm-usage-stats.rst 
b/Documentation/gpu/drm-usage-stats.rst
new file mode 100644
index ..c669026be244
--- /dev/null
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -0,0 +1,97 @@
+.. _drm-client-usage-stats:
+
+==
+DRM client usage stats
+==
+
+DRM drivers can choose to export partly standardised text output via the
+`fops->show_fdinfo()` as part of the driver specific file operations registered
+in the `struct drm_driver` object registered with the DRM core.
+
+One purpose of this output is to enable writing as generic as practicaly
+feasible `top(1)` like userspace monitoring tools.
+
+Given the differences between various DRM drivers the specification of the
+output is split between common and driver specific parts. Having said that,
+wherever possible effort should still be made to standardise as much as
+possible.
+
+File format specification
+=
+
+- File shall contain one key value pair per one line of text.
+- Colon character (`:`) must be used to delimit keys and values.
+- All keys shall be prefixed with `drm-`.
+- Whitespace between the delimiter and first non-whitespace character shall be
+  ignored when parsing.
+- Neither keys or values are allowed to contain whitespace characters.
+- Numerical key value pairs can end with optional unit string.
+- Data type of the value is fixed as defined in the specification.
+
+Key types
+-
+
+1. Mandatory, fully standardised.
+2. Optional, fully standardised.
+3. Driver specific.
+
+Data types
+--
+
+-  - Unsigned integer without defining the maximum value.
+-  - String excluding any above defined reserved characters or whitespace.
+
+Mandatory fully standardised keys
+-
+
+- drm-driver: 
+
+String shall contain the name this driver registered as via the respective
+`struct drm_driver` data structure.
+
+Optional fully standardised keys
+
+
+- drm-pdev: 
+
+For PCI devices this should contain the PCI slot address of the device in
+question.
+
+- drm-client-id: 
+
+Unique value relating to the open DRM file descriptor used to distinguish
+duplicated and shared file descriptors. Conceptually the value should map 1:1
+to the in kernel representation of `struct drm_file` instances.
+
+Uniqueness of the value shall be either globally unique, or unique within the
+scope of each device, in which case `drm-pdev` shall be present as well.
+
+Userspace should make sure to not double account any usage statistics by using
+the above described criteria in order to associate data to individual clients.
+
+- drm-engine-:  ns
+
+GPUs usually contain multiple execution engines. Each shall be given a stable
+and unique name (str), with possible values documented in the driver specific
+documentation.
+
+Value shall be in specified time units which the respective GPU engine spent
+busy executing workloads belonging to this client.
+
+Values are not required to be constantly monotonic if it makes the driver
+implementation easier, but are required to catch up with the previously 
reported
+larger value within a reasonable period. Upon observing a value lower than what
+was previously read, userspace is expected to stay with that larger previous
+value until a monotonic update is seen.
+
+- drm-memory-:  [KiB|MiB]
+
+Each possible memory type which can be used to store buffer objects by the
+GPU in question shall be given a stable and unique name to be returned as the
+string here.
+
+Value shall reflect the amount of storage currently consumed by the buffer
+object belong to this client, in the respective memory region.
+
+Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
+indicating kibi- 

[Intel-gfx] [PATCH 5/7] drm/i915: Track context current active time

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Track context active (on hardware) status together with the start
timestamp.

This will be used to provide better granularity of context
runtime reporting in conjunction with already tracked pphwsp accumulated
runtime.

The latter is only updated on context save so does not give us visibility
to any currently executing work.

As part of the patch the existing runtime tracking data is moved under the
new ce->stats member and updated under the seqlock. This provides the
ability to atomically read out accumulated plus active runtime.

v2:
 * Rename and make __intel_context_get_active_time unlocked.

v3:
 * Use GRAPHICS_VER.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Aravind Iddamsetty  #  v1
Reviewed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_context.c   | 27 ++-
 drivers/gpu/drm/i915/gt/intel_context.h   | 15 ---
 drivers/gpu/drm/i915/gt/intel_context_types.h | 24 +++--
 .../drm/i915/gt/intel_execlists_submission.c  | 23 
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c|  4 +++
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 27 ++-
 drivers/gpu/drm/i915/gt/intel_lrc.h   | 24 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +++
 drivers/gpu/drm/i915/i915_gpu_error.c |  9 +++
 drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
 10 files changed, 116 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index ff637147b1a9..ae97c311d65b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -382,7 +382,7 @@ intel_context_init(struct intel_context *ce, struct 
intel_engine_cs *engine)
ce->ring = NULL;
ce->ring_size = SZ_4K;
 
-   ewma_runtime_init(>runtime.avg);
+   ewma_runtime_init(>stats.runtime.avg);
 
ce->vm = i915_vm_get(engine->gt->vm);
 
@@ -532,6 +532,31 @@ struct i915_request 
*intel_context_find_active_request(struct intel_context *ce)
return active;
 }
 
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+{
+   u64 total, active;
+
+   total = ce->stats.runtime.total;
+   if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+   total *= ce->engine->gt->clock_period_ns;
+
+   active = READ_ONCE(ce->stats.active);
+   if (active)
+   active = intel_context_clock() - active;
+
+   return total + active;
+}
+
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+{
+   u64 avg = ewma_runtime_read(>stats.runtime.avg);
+
+   if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+   avg *= ce->engine->gt->clock_period_ns;
+
+   return avg;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_context.c"
 #endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h 
b/drivers/gpu/drm/i915/gt/intel_context.h
index c41098950746..2aaffe1bb388 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -296,18 +296,13 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, >flags);
 }
 
-static inline u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
-{
-   const u32 period = ce->engine->gt->clock_period_ns;
-
-   return READ_ONCE(ce->runtime.total) * period;
-}
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
 
-static inline u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+static inline u64 intel_context_clock(void)
 {
-   const u32 period = ce->engine->gt->clock_period_ns;
-
-   return mul_u32_u32(ewma_runtime_read(>runtime.avg), period);
+   /* As we mix CS cycles with CPU clocks, use the raw monotonic clock. */
+   return ktime_get_raw_fast_ns();
 }
 
 #endif /* __INTEL_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 930569a1a01f..2a8a8d207691 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -35,6 +35,9 @@ struct intel_context_ops {
 #define COPS_HAS_INFLIGHT_BIT 0
 #define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT)
 
+#define COPS_RUNTIME_CYCLES_BIT 1
+#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
+
int (*alloc)(struct intel_context *ce);
 
void (*ban)(struct intel_context *ce, struct i915_request *rq);
@@ -128,14 +131,19 @@ struct intel_context {
} lrc;
u32 tag; /* cookie passed to HW to track this context on submission */
 
-   /* Time on GPU as tracked by the hw. */
-   struct {
-   struct ewma_runtime avg;
-   u64 total;
-   u32 last;
-   I915_SELFTEST_DECLARE(u32 num_underflow);
-   

[Intel-gfx] [PATCH 7/7] drm/i915: Expose client engine utilisation via fdinfo

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.

Example of the output:

  pos:0
  flags:  012
  mnt_id: 21
  drm-driver: i915
  drm-pdev:   :00:02.0
  drm-client-id:  7
  drm-engine-render:  9288864723 ns
  drm-engine-copy:2035071108 ns
  drm-engine-video:   0 ns
  drm-engine-video-enhance:   0 ns

v2:
 * Update for removal of name and pid.

v3:
 * Use drm_driver.name.

Signed-off-by: Tvrtko Ursulin 
Cc: David M Nieto 
Cc: Christian König 
Cc: Daniel Vetter 
Acked-by: Christian König 
---
 Documentation/gpu/drm-usage-stats.rst  |  6 +++
 Documentation/gpu/i915.rst | 27 ++
 drivers/gpu/drm/i915/i915_drm_client.c | 73 ++
 drivers/gpu/drm/i915/i915_drm_client.h |  4 ++
 drivers/gpu/drm/i915/i915_drv.c|  3 ++
 5 files changed, 113 insertions(+)

diff --git a/Documentation/gpu/drm-usage-stats.rst 
b/Documentation/gpu/drm-usage-stats.rst
index c669026be244..6952f8389d07 100644
--- a/Documentation/gpu/drm-usage-stats.rst
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -95,3 +95,9 @@ object belong to this client, in the respective memory region.
 
 Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
 indicating kibi- or mebi-bytes.
+
+===
+Driver specific implementations
+===
+
+:ref:`i915-usage-stats`
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 311e10400708..36cd6f74fb1b 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -700,3 +700,30 @@ The style guide for ``i915_reg.h``.
 
 .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
:doc: The i915 register macro definition style guide
+
+.. _i915-usage-stats:
+
+i915 DRM client usage stats implementation
+==
+
+The drm/i915 driver implements the DRM client usage stats specification as
+documented in :ref:`drm-client-usage-stats`.
+
+Example of the output showing the implemented key value pairs and entirety of
+the currenly possible format options:
+
+::
+
+  pos:0
+  flags:  012
+  mnt_id: 21
+  drm-driver: i915
+  drm-pdev:   :00:02.0
+  drm-client-id:  7
+  drm-engine-render:  9288864723 ns
+  drm-engine-copy:2035071108 ns
+  drm-engine-video:   0 ns
+  drm-engine-video-enhance:   0 ns
+
+Possible `drm-engine-` key names are: `render`, `copy`, `video` and
+`video-enhance`.
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
index 91a8559bebf7..06dbd20ce763 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -7,6 +7,11 @@
 #include 
 #include 
 
+#include 
+
+#include 
+
+#include "gem/i915_gem_context.h"
 #include "i915_drm_client.h"
 #include "i915_gem.h"
 #include "i915_utils.h"
@@ -68,3 +73,71 @@ void i915_drm_clients_fini(struct i915_drm_clients *clients)
GEM_BUG_ON(!xa_empty(>xarray));
xa_destroy(>xarray);
 }
+
+#ifdef CONFIG_PROC_FS
+static const char * const uabi_class_names[] = {
+   [I915_ENGINE_CLASS_RENDER] = "render",
+   [I915_ENGINE_CLASS_COPY] = "copy",
+   [I915_ENGINE_CLASS_VIDEO] = "video",
+   [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+};
+
+static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
+{
+   struct i915_gem_engines_iter it;
+   struct intel_context *ce;
+   u64 total = 0;
+
+   for_each_gem_engine(ce, rcu_dereference(ctx->engines), it) {
+   if (ce->engine->uabi_class != class)
+   continue;
+
+   total += intel_context_get_total_runtime_ns(ce);
+   }
+
+   return total;
+}
+
+static void
+show_client_class(struct seq_file *m,
+ struct i915_drm_client *client,
+ unsigned int class)
+{
+   const struct list_head *list = >ctx_list;
+   u64 total = atomic64_read(>past_runtime[class]);
+   struct i915_gem_context *ctx;
+
+   rcu_read_lock();
+   list_for_each_entry_rcu(ctx, list, client_link)
+   total += busy_add(ctx, class);
+   rcu_read_unlock();
+
+   return seq_printf(m, "drm-engine-%s:\t%llu ns\n",
+ uabi_class_names[class], total);
+}
+
+void i915_drm_client_fdinfo(struct seq_file *m, struct file *f)
+{
+   struct drm_file *file = f->private_data;
+   struct drm_i915_file_private *file_priv = file->driver_priv;
+   struct drm_i915_private *i915 = file_priv->dev_priv;
+   struct i915_drm_client *client = file_priv->client;
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   unsigned int i;
+
+   /*
+* **
+* For text output format description please 

[Intel-gfx] [PATCH 0/7] Per client GPU stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Same old work but now rebased and series ending with some DRM docs proposing
the common specification which should enable nice common userspace tools to be
written.

For the moment I only have intel_gpu_top converted to use this and that seems to
work okay.

v2:
 * Added prototype of possible amdgpu changes and spec updates to align with the
   common spec.

v3:
 * Documented that 'drm-driver' tag shall correspond with
   struct drm_driver.name.

v4:
 * Dropped amdgpu conversion from the series for now until AMD folks can find
   some time to finish that patch.

Tvrtko Ursulin (7):
  drm/i915: Explicitly track DRM clients
  drm/i915: Make GEM contexts track DRM clients
  drm/i915: Track runtime spent in closed and unreachable GEM contexts
  drm/i915: Track all user contexts per client
  drm/i915: Track context current active time
  drm: Document fdinfo format specification
  drm/i915: Expose client engine utilisation via fdinfo

 Documentation/gpu/drm-usage-stats.rst | 103 +
 Documentation/gpu/i915.rst|  27 
 Documentation/gpu/index.rst   |   1 +
 drivers/gpu/drm/i915/Makefile |   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  42 -
 .../gpu/drm/i915/gem/i915_gem_context_types.h |   6 +
 drivers/gpu/drm/i915/gt/intel_context.c   |  27 +++-
 drivers/gpu/drm/i915/gt/intel_context.h   |  15 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |  24 ++-
 .../drm/i915/gt/intel_execlists_submission.c  |  23 ++-
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c|   4 +
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  27 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.h   |  24 +++
 drivers/gpu/drm/i915/gt/selftest_lrc.c|  10 +-
 drivers/gpu/drm/i915/i915_drm_client.c| 143 ++
 drivers/gpu/drm/i915/i915_drm_client.h|  66 
 drivers/gpu/drm/i915/i915_drv.c   |   9 ++
 drivers/gpu/drm/i915/i915_drv.h   |   5 +
 drivers/gpu/drm/i915/i915_gem.c   |  21 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c |   9 +-
 drivers/gpu/drm/i915/i915_gpu_error.h |   2 +-
 21 files changed, 537 insertions(+), 56 deletions(-)
 create mode 100644 Documentation/gpu/drm-usage-stats.rst
 create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c
 create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h

-- 
2.30.2

[Intel-gfx] [PATCH 1/7] drm/i915: Explicitly track DRM clients

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Tracking DRM clients more explicitly will allow later patches to
accumulate past and current GPU usage in a centralised place and also
consolidate access to owning task pid/name.

Unique client id is also assigned for the purpose of distinguishing/
consolidating between multiple file descriptors owned by the same process.

v2:
 Chris Wilson:
 * Enclose new members into dedicated structs.
 * Protect against failed sysfs registration.

v3:
 * sysfs_attr_init.

v4:
 * Fix for internal clients.

v5:
 * Use cyclic ida for client id. (Chris)
 * Do not leak pid reference. (Chris)
 * Tidy code with some locals.

v6:
 * Use xa_alloc_cyclic to simplify locking. (Chris)
 * No need to unregister individial sysfs files. (Chris)
 * Rebase on top of fpriv kref.
 * Track client closed status and reflect in sysfs.

v7:
 * Make drm_client more standalone concept.

v8:
 * Simplify sysfs show. (Chris)
 * Always track name and pid.

v9:
 * Fix cyclic id assignment.

v10:
 * No need for a mutex around xa_alloc_cyclic.
 * Refactor sysfs into own function.
 * Unregister sysfs before freeing pid and name.
 * Move clients setup into own function.

v11:
 * Call clients init directly from driver init. (Chris)

v12:
 * Do not fail client add on id wrap. (Maciej)

v13 (Lucas): Rebase.

v14:
 * Dropped sysfs bits.

v15:
 * Dropped tracking of pid/ and name.
 * Dropped RCU freeing of the client object.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson  # v11
Reviewed-by: Aravind Iddamsetty  # v11
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/Makefile  |  5 +-
 drivers/gpu/drm/i915/i915_drm_client.c | 68 ++
 drivers/gpu/drm/i915/i915_drm_client.h | 50 +++
 drivers/gpu/drm/i915/i915_drv.c|  6 +++
 drivers/gpu/drm/i915/i915_drv.h|  5 ++
 drivers/gpu/drm/i915/i915_gem.c| 21 ++--
 6 files changed, 150 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c
 create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 335a8c668848..8187c9e52a79 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,8 +32,9 @@ subdir-ccflags-y += -I$(srctree)/$(src)
 # Please keep these build lists sorted!
 
 # core driver code
-i915-y += i915_drv.o \
- i915_config.o \
+i915-y += i915_config.o \
+ i915_drm_client.o \
+ i915_drv.o \
  i915_irq.o \
  i915_getparam.o \
  i915_mitigations.o \
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
new file mode 100644
index ..e61e9ba15256
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+
+#include "i915_drm_client.h"
+#include "i915_gem.h"
+#include "i915_utils.h"
+
+void i915_drm_clients_init(struct i915_drm_clients *clients,
+  struct drm_i915_private *i915)
+{
+   clients->i915 = i915;
+   clients->next_id = 0;
+
+   xa_init_flags(>xarray, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
+}
+
+struct i915_drm_client *i915_drm_client_add(struct i915_drm_clients *clients)
+{
+   struct i915_drm_client *client;
+   struct xarray *xa = >xarray;
+   int ret;
+
+   client = kzalloc(sizeof(*client), GFP_KERNEL);
+   if (!client)
+   return ERR_PTR(-ENOMEM);
+
+   xa_lock_irq(xa);
+   ret = __xa_alloc_cyclic(xa, >id, client, xa_limit_32b,
+   >next_id, GFP_KERNEL);
+   xa_unlock_irq(xa);
+   if (ret < 0)
+   goto err;
+
+   kref_init(>kref);
+   client->clients = clients;
+
+   return client;
+
+err:
+   kfree(client);
+
+   return ERR_PTR(ret);
+}
+
+void __i915_drm_client_free(struct kref *kref)
+{
+   struct i915_drm_client *client =
+   container_of(kref, typeof(*client), kref);
+   struct xarray *xa = >clients->xarray;
+   unsigned long flags;
+
+   xa_lock_irqsave(xa, flags);
+   __xa_erase(xa, client->id);
+   xa_unlock_irqrestore(xa, flags);
+   kfree(client);
+}
+
+void i915_drm_clients_fini(struct i915_drm_clients *clients)
+{
+   GEM_BUG_ON(!xa_empty(>xarray));
+   xa_destroy(>xarray);
+}
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h 
b/drivers/gpu/drm/i915/i915_drm_client.h
new file mode 100644
index ..e8986ad51176
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __I915_DRM_CLIENT_H__
+#define __I915_DRM_CLIENT_H__
+
+#include 
+#include 
+
+struct drm_i915_private;
+
+struct i915_drm_clients {
+   struct drm_i915_private *i915;
+
+   struct xarray xarray;
+   u32 next_id;
+};
+
+struct 

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled

[Souza, Jose]

On Wed, 2021-09-22 at 16:41 +0300, Ville Syrjälä wrote:
> On Tue, Sep 21, 2021 at 10:37:53PM +, Souza, Jose wrote:
> > On Tue, 2021-09-21 at 16:35 +0300, Ville Syrjälä wrote:
> > > On Fri, Sep 17, 2021 at 09:33:59PM +, Souza, Jose wrote:
> > > > On Fri, 2021-09-17 at 20:49 +0300, Ville Syrjälä wrote:
> > > > > On Fri, Sep 17, 2021 at 05:02:21PM +, Souza, Jose wrote:
> > > > > > On Fri, 2021-09-17 at 16:04 +0300, Ville Syrjälä wrote:
> > > > > > > On Thu, Sep 16, 2021 at 05:09:08PM +, Souza, Jose wrote:
> > > > > > > > On Thu, 2021-09-16 at 16:17 +0300, Ville Syrjälä wrote:
> > > > > > > > > On Wed, Sep 15, 2021 at 06:18:35PM +, Souza, Jose wrote:
> > > > > > > > > > On Wed, 2021-09-15 at 17:58 +0300, Ville Syrjälä wrote:
> > > > > > > > > > > On Tue, Sep 14, 2021 at 02:25:05PM -0700, José Roberto de 
> > > > > > > > > > > Souza wrote:
> > > > > > > > > > > > Not sure why but when moving the cursor fast it causes 
> > > > > > > > > > > > some artifacts
> > > > > > > > > > > > of the cursor to be left in the cursor path, adding 
> > > > > > > > > > > > some pixels above
> > > > > > > > > > > > the cursor to the damaged area fixes the issue, so 
> > > > > > > > > > > > leaving this as a
> > > > > > > > > > > > workaround until proper fix is found.
> > > > > > > > > > > 
> > > > > > > > > > > Have you tried warping the cursor clear across the screen 
> > > > > > > > > > > while
> > > > > > > > > > > a partial update is already pending? I think it will go 
> > > > > > > > > > > badly.
> > > > > > > > > > 
> > > > > > > > > > You mean move the cursor for example from 0x0 to 500x500 in 
> > > > > > > > > > one frame?
> > > > > > > > > > It will mark as damaged the previous area and the new one.
> > > > > > > > > 
> > > > > > > > > Legacy cursor updates bypass all that stuff so you're not 
> > > > > > > > > going to
> > > > > > > > > updating the sel fetch area for the other planes.
> > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > In fact I'm thinking the mailbox style legacy cursor 
> > > > > > > > > > > updates are just
> > > > > > > > > > > fundementally incompatible with partial updates since the 
> > > > > > > > > > > cursor
> > > > > > > > > > > can move outside of the already committed update region 
> > > > > > > > > > > any time.
> > > > > > > > > > > Ie. I suspect while the cursor is visible we simply can't 
> > > > > > > > > > > do partial
> > > > > > > > > > > updates.
> > > > > > > > > > 
> > > > > > > > > > Probably I did not understand what you want to say, but 
> > > > > > > > > > each cursor update will be in one frame, updating the 
> > > > > > > > > > necessary area.
> > > > > > > > > 
> > > > > > > > > The legacy cursor uses mailbox updates so there is no 1:1 
> > > > > > > > > relationship
> > > > > > > > > between actual scanned out frames and cursor ioctl calls. You 
> > > > > > > > > can
> > > > > > > > > have umpteen thousand cursor updates per frame.
> > > > > > > > 
> > > > > > > > Not if intel_legacy_cursor_update() is changed to go to the 
> > > > > > > > slow path and do one atomic commit for each move.
> > > > > > > > https://patchwork.freedesktop.org/patch/453192/?series=94522=1
> > > > > > > 
> > > > > > > That's not going to fly. The whole reason for the legacy cursor 
> > > > > > > thing is
> > > > > > > that X likes to do thousands of cursor updates per frame.
> > > > > > 
> > > > > > From user experience perspective there is no issues in converting 
> > > > > > to atomic commit, those 3 videos that I shared with you have this 
> > > > > > conversion. 
> > > > > 
> > > > > I don't know what you've tested but the legacy cursor fastpath is very
> > > > > much needed. We've have numerous bug reports whenever it has
> > > > > accidentally regressed, and I've witnessed the carnage myself as well.
> > > > > Hmm, I guess you didn't actually disable it fully. To do that you
> > > > > would have to clear state->legacy_cursor_update explicitly somewhere.
> > > > 
> > > > Thanks for pointing out state->legacy_cursor_update and yes setting it 
> > > > to false makes causes the cursor to lag.
> > > > 
> > > > > 
> > > > > Either way I just retested the earlier patches just with the 
> > > > > nonblocking
> > > > > commit for dirtyfb hacked in, and I left the cursor code using the
> > > > > half fast path you made it take. The user experience is still as bad
> > > > > as before. Just moving the mouse around makes glxgears stutter, and 
> > > > > the
> > > > > reported fps drops to ~400 from that alone. And doing anything more
> > > > > involved like moving windows around is still a total fail.
> > > > 
> > > > I have tested it in a TGL and ADL-P, will try to get some gen9 to try 
> > > > it.
> > > > Other than that I don't know what could this big difference between our 
> > > > setups.
> > > > I'm using Mate like you with 'enable software compositing window 
> > > > manager' disabled.
> > > 
> > > Not sure.
> > > 
> > > BTW another 

Re: [Intel-gfx] [PATCH] drm/i915: Drop stealing of bits from i915_sw_fence function pointer

[Matthew Brost]

On Wed, Sep 22, 2021 at 04:25:04PM +0100, Tvrtko Ursulin wrote:
> 
> On 22/09/2021 16:21, Tvrtko Ursulin wrote:
> > 
> > On 22/09/2021 15:57, Matthew Brost wrote:
> > > Rather than stealing bits from i915_sw_fence function pointer use
> > > seperate fields for function pointer and flags. If using two different
> > > fields, the 4 byte alignment for the i915_sw_fence function pointer can
> > > also be dropped.
> > > 
> > > v2:
> > >   (CI)
> > >    - Set new function field rather than flags in __i915_sw_fence_init
> > > 
> > > Signed-off-by: Matthew Brost 
> > > ---
> > >   drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
> > >   drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
> > >   drivers/gpu/drm/i915/i915_request.c   |  4 ++--
> > >   drivers/gpu/drm/i915/i915_sw_fence.c  | 12 +--
> > >   drivers/gpu/drm/i915/i915_sw_fence.h  | 21 +--
> > >   drivers/gpu/drm/i915/i915_sw_fence_work.c |  2 +-
> > >   .../gpu/drm/i915/selftests/i915_sw_fence.c    |  2 +-
> > >   drivers/gpu/drm/i915/selftests/lib_sw_fence.c |  4 ++--
> > >   8 files changed, 23 insertions(+), 26 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index a7ca38613f89..6d5bb55ffc82 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -10323,7 +10323,7 @@ static void intel_atomic_commit_work(struct
> > > work_struct *work)
> > >   intel_atomic_commit_tail(state);
> > >   }
> > > -static int __i915_sw_fence_call
> > > +static int
> > >   intel_atomic_commit_ready(struct i915_sw_fence *fence,
> > >     enum i915_sw_fence_notify notify)
> > >   {
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > index c2ab0e22db0a..df5fec5c3da8 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > @@ -800,7 +800,7 @@ static void free_engines_rcu(struct rcu_head *rcu)
> > >   free_engines(engines);
> > >   }
> > > -static int __i915_sw_fence_call
> > > +static int
> > >   engines_notify(struct i915_sw_fence *fence, enum
> > > i915_sw_fence_notify state)
> > >   {
> > >   struct i915_gem_engines *engines =
> > > diff --git a/drivers/gpu/drm/i915/i915_request.c
> > > b/drivers/gpu/drm/i915/i915_request.c
> > > index ce446716d092..945d3025a0b6 100644
> > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > @@ -719,7 +719,7 @@ void i915_request_cancel(struct i915_request
> > > *rq, int error)
> > >   intel_context_cancel_request(rq->context, rq);
> > >   }
> > > -static int __i915_sw_fence_call
> > > +static int
> > >   submit_notify(struct i915_sw_fence *fence, enum
> > > i915_sw_fence_notify state)
> > >   {
> > >   struct i915_request *request =
> > > @@ -755,7 +755,7 @@ submit_notify(struct i915_sw_fence *fence, enum
> > > i915_sw_fence_notify state)
> > >   return NOTIFY_DONE;
> > >   }
> > > -static int __i915_sw_fence_call
> > > +static int
> > >   semaphore_notify(struct i915_sw_fence *fence, enum
> > > i915_sw_fence_notify state)
> > >   {
> > >   struct i915_request *rq = container_of(fence, typeof(*rq),
> > > semaphore);
> > > diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
> > > b/drivers/gpu/drm/i915/i915_sw_fence.c
> > > index c589a681da77..1c080dd1f718 100644
> > > --- a/drivers/gpu/drm/i915/i915_sw_fence.c
> > > +++ b/drivers/gpu/drm/i915/i915_sw_fence.c
> > > @@ -34,7 +34,7 @@ enum {
> > >   static void *i915_sw_fence_debug_hint(void *addr)
> > >   {
> > > -    return (void *)(((struct i915_sw_fence *)addr)->flags &
> > > I915_SW_FENCE_MASK);
> > > +    return (void *)(((struct i915_sw_fence *)addr)->fn);
> > >   }
> > >   #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
> > > @@ -126,10 +126,7 @@ static inline void debug_fence_assert(struct
> > > i915_sw_fence *fence)
> > >   static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
> > >     enum i915_sw_fence_notify state)
> > >   {
> > > -    i915_sw_fence_notify_t fn;
> > > -
> > > -    fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
> > > -    return fn(fence, state);
> > > +    return fence->fn(fence, state);
> > >   }
> > >   #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
> > > @@ -242,10 +239,11 @@ void __i915_sw_fence_init(struct i915_sw_fence
> > > *fence,
> > >     const char *name,
> > >     struct lock_class_key *key)
> > >   {
> > > -    BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
> > > +    BUG_ON(!fn);
> > >   __init_waitqueue_head(>wait, name, key);
> > > -    fence->flags = (unsigned long)fn;
> > > +    fence->fn = fn;
> > > +    fence->flags = 0;
> > >   i915_sw_fence_reinit(fence);
> > >   }
> > > diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h
> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev7)

[Patchwork]

== Series Details ==

Series: i915/display: split and constify vtable (rev7)
URL   : https://patchwork.freedesktop.org/series/94459/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
587d41d45da4 drm/i915/uncore: split the fw get function into separate vfunc
2c15ba24ea1a drm/i915/pm: drop get_fifo_size vfunc.
3891d89ead96 drm/i915: make update_wm take a dev_priv.
666a5ee103d4 drm/i915/wm: provide wrappers around watermark vfuncs calls (v2)
-:10: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 
'existence'?
#10: 
One thing to note is that the code checks the existance of some
  ^

-:29: CHECK:LINE_SPACING: Please don't use multiple blank lines
#29: FILE: drivers/gpu/drm/i915/display/intel_display.c:129:
 
+

-:73: WARNING:LINE_SPACING: Missing a blank line after declarations
#73: FILE: drivers/gpu/drm/i915/display/intel_display.c:173:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.compute_pipe_wm)

-:82: WARNING:LINE_SPACING: Missing a blank line after declarations
#82: FILE: drivers/gpu/drm/i915/display/intel_display.c:182:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (!dev_priv->display.compute_intermediate_wm)

-:94: WARNING:LINE_SPACING: Missing a blank line after declarations
#94: FILE: drivers/gpu/drm/i915/display/intel_display.c:194:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.initial_watermarks) {

-:105: WARNING:LINE_SPACING: Missing a blank line after declarations
#105: FILE: drivers/gpu/drm/i915/display/intel_display.c:205:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.atomic_update_watermarks)

-:113: WARNING:LINE_SPACING: Missing a blank line after declarations
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:213:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.optimize_watermarks)

-:120: WARNING:LINE_SPACING: Missing a blank line after declarations
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:220:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.compute_global_watermarks)

-:134: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (16, 20)
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:2632:
+   if (!intel_initial_watermarks(state, crtc))
+   if (new_crtc_state->update_wm_pre)

-:135: WARNING:TABSTOP: Statements should start on a tabstop
#135: FILE: drivers/gpu/drm/i915/display/intel_display.c:2633:
+   if (new_crtc_state->update_wm_pre)

-:176: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 12)
#176: FILE: drivers/gpu/drm/i915/display/intel_display.c:3676:
+   if (!intel_initial_watermarks(state, crtc))
+   intel_update_watermarks(dev_priv);

total: 0 errors, 10 warnings, 1 checks, 319 lines checked
d064324410a5 drm/i915: add wrappers around cdclk vtable funcs.
-:32: WARNING:LINE_SPACING: Missing a blank line after declarations
#32: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:71:
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   return dev_priv->display.bw_calc_min_cdclk(state);

total: 0 errors, 1 warnings, 0 checks, 127 lines checked
6c34acc82bf4 drm/i915/display: add intel_fdi_link_train wrapper.
9209bf88e3d6 drm/i915: split clock gating init from display vtable
c1f5b502c262 drm/i915: split watermark vfuncs from display vtable.
6de505ea22e9 drm/i915: split color functions from display vtable
b43ad494fb30 drm/i915: split audio functions from display vtable
02500cc6bc12 drm/i915: split cdclk functions from display vtable.
3856fade357f drm/i915: split irq hotplug function from display vtable
4dd08ab5875f drm/i915: split fdi link training from display vtable.
c4b9847c3bef drm/i915: split the dpll clock compute out from display vtable.
8b02fe332309 drm/i915: constify fdi link training vtable
cb661e0b73ca drm/i915: constify hotplug function vtable.
2e62bc8a9786 drm/i915: constify color function vtable.
-:197: CHECK:BRACES: Unbalanced braces around else statement
#197: FILE: drivers/gpu/drm/i915/display/intel_color.c:2194:
+   } else

total: 0 errors, 0 warnings, 1 checks, 187 lines checked
523632d6053b drm/i915: constify the audio function vtable
c821ffb519c1 drm/i915: constify the dpll clock vtable
7bf097d0efa6 drm/i915: constify the cdclk vtable
ba86233a6aea drm/i915: drop unused function ptr and comments.
66b4fe4263a1 drm/i915: constify display function vtable
92611ae09018 drm/i915: constify clock gating init vtable.
40e25093e553 drm/i915: constify display wm vtable

Re: [Intel-gfx] [PATCH] drm/i915: Drop stealing of bits from i915_sw_fence function pointer

[Tvrtko Ursulin]

On 22/09/2021 16:21, Tvrtko Ursulin wrote:


On 22/09/2021 15:57, Matthew Brost wrote:

Rather than stealing bits from i915_sw_fence function pointer use
seperate fields for function pointer and flags. If using two different
fields, the 4 byte alignment for the i915_sw_fence function pointer can
also be dropped.

v2:
  (CI)
   - Set new function field rather than flags in __i915_sw_fence_init

Signed-off-by: Matthew Brost 
---
  drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
  drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
  drivers/gpu/drm/i915/i915_request.c   |  4 ++--
  drivers/gpu/drm/i915/i915_sw_fence.c  | 12 +--
  drivers/gpu/drm/i915/i915_sw_fence.h  | 21 +--
  drivers/gpu/drm/i915/i915_sw_fence_work.c |  2 +-
  .../gpu/drm/i915/selftests/i915_sw_fence.c    |  2 +-
  drivers/gpu/drm/i915/selftests/lib_sw_fence.c |  4 ++--
  8 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c

index a7ca38613f89..6d5bb55ffc82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10323,7 +10323,7 @@ static void intel_atomic_commit_work(struct 
work_struct *work)

  intel_atomic_commit_tail(state);
  }
-static int __i915_sw_fence_call
+static int
  intel_atomic_commit_ready(struct i915_sw_fence *fence,
    enum i915_sw_fence_notify notify)
  {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c

index c2ab0e22db0a..df5fec5c3da8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -800,7 +800,7 @@ static void free_engines_rcu(struct rcu_head *rcu)
  free_engines(engines);
  }
-static int __i915_sw_fence_call
+static int
  engines_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)

  {
  struct i915_gem_engines *engines =
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c

index ce446716d092..945d3025a0b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -719,7 +719,7 @@ void i915_request_cancel(struct i915_request *rq, 
int error)

  intel_context_cancel_request(rq->context, rq);
  }
-static int __i915_sw_fence_call
+static int
  submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify 
state)

  {
  struct i915_request *request =
@@ -755,7 +755,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)

  return NOTIFY_DONE;
  }
-static int __i915_sw_fence_call
+static int
  semaphore_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)

  {
  struct i915_request *rq = container_of(fence, typeof(*rq), 
semaphore);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c

index c589a681da77..1c080dd1f718 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -34,7 +34,7 @@ enum {
  static void *i915_sw_fence_debug_hint(void *addr)
  {
-    return (void *)(((struct i915_sw_fence *)addr)->flags & 
I915_SW_FENCE_MASK);

+    return (void *)(((struct i915_sw_fence *)addr)->fn);
  }
  #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -126,10 +126,7 @@ static inline void debug_fence_assert(struct 
i915_sw_fence *fence)

  static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
    enum i915_sw_fence_notify state)
  {
-    i915_sw_fence_notify_t fn;
-
-    fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
-    return fn(fence, state);
+    return fence->fn(fence, state);
  }
  #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -242,10 +239,11 @@ void __i915_sw_fence_init(struct i915_sw_fence 
*fence,

    const char *name,
    struct lock_class_key *key)
  {
-    BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+    BUG_ON(!fn);
  __init_waitqueue_head(>wait, name, key);
-    fence->flags = (unsigned long)fn;
+    fence->fn = fn;
+    fence->flags = 0;
  i915_sw_fence_reinit(fence);
  }
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h

index 30a863353ee6..70ba1789aa89 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -17,26 +17,25 @@
  struct completion;
  struct dma_resv;
+struct i915_sw_fence;
+
+enum i915_sw_fence_notify {
+    FENCE_COMPLETE,
+    FENCE_FREE
+};
+
+typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
+  enum i915_sw_fence_notify state);
  struct i915_sw_fence {
  wait_queue_head_t wait;
+    i915_sw_fence_notify_t fn;
  unsigned long flags;


Looks good to me. I'd just make the flags narrower now that they can be, 
and put them down..



  atomic_t pending;


.. here as unsigned int and so we save 4 bytes, 

Re: [Intel-gfx] [PATCH] drm/i915: Drop stealing of bits from i915_sw_fence function pointer

[Tvrtko Ursulin]

On 22/09/2021 15:57, Matthew Brost wrote:

Rather than stealing bits from i915_sw_fence function pointer use
seperate fields for function pointer and flags. If using two different
fields, the 4 byte alignment for the i915_sw_fence function pointer can
also be dropped.

v2:
  (CI)
   - Set new function field rather than flags in __i915_sw_fence_init

Signed-off-by: Matthew Brost 
---
  drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
  drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
  drivers/gpu/drm/i915/i915_request.c   |  4 ++--
  drivers/gpu/drm/i915/i915_sw_fence.c  | 12 +--
  drivers/gpu/drm/i915/i915_sw_fence.h  | 21 +--
  drivers/gpu/drm/i915/i915_sw_fence_work.c |  2 +-
  .../gpu/drm/i915/selftests/i915_sw_fence.c|  2 +-
  drivers/gpu/drm/i915/selftests/lib_sw_fence.c |  4 ++--
  8 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a7ca38613f89..6d5bb55ffc82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10323,7 +10323,7 @@ static void intel_atomic_commit_work(struct work_struct 
*work)
intel_atomic_commit_tail(state);
  }
  
-static int __i915_sw_fence_call

+static int
  intel_atomic_commit_ready(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify notify)
  {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..df5fec5c3da8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -800,7 +800,7 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
  }
  
-static int __i915_sw_fence_call

+static int
  engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
  {
struct i915_gem_engines *engines =
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index ce446716d092..945d3025a0b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -719,7 +719,7 @@ void i915_request_cancel(struct i915_request *rq, int error)
intel_context_cancel_request(rq->context, rq);
  }
  
-static int __i915_sw_fence_call

+static int
  submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
  {
struct i915_request *request =
@@ -755,7 +755,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
return NOTIFY_DONE;
  }
  
-static int __i915_sw_fence_call

+static int
  semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
  {
struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index c589a681da77..1c080dd1f718 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -34,7 +34,7 @@ enum {
  
  static void *i915_sw_fence_debug_hint(void *addr)

  {
-   return (void *)(((struct i915_sw_fence *)addr)->flags & 
I915_SW_FENCE_MASK);
+   return (void *)(((struct i915_sw_fence *)addr)->fn);
  }
  
  #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS

@@ -126,10 +126,7 @@ static inline void debug_fence_assert(struct i915_sw_fence 
*fence)
  static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify state)
  {
-   i915_sw_fence_notify_t fn;
-
-   fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
-   return fn(fence, state);
+   return fence->fn(fence, state);
  }
  
  #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS

@@ -242,10 +239,11 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
  const char *name,
  struct lock_class_key *key)
  {
-   BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+   BUG_ON(!fn);
  
  	__init_waitqueue_head(>wait, name, key);

-   fence->flags = (unsigned long)fn;
+   fence->fn = fn;
+   fence->flags = 0;
  
  	i915_sw_fence_reinit(fence);

  }
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h
index 30a863353ee6..70ba1789aa89 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -17,26 +17,25 @@
  
  struct completion;

  struct dma_resv;
+struct i915_sw_fence;
+
+enum i915_sw_fence_notify {
+   FENCE_COMPLETE,
+   FENCE_FREE
+};
+
+typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
+ enum i915_sw_fence_notify state);
  
  struct i915_sw_fence {

wait_queue_head_t wait;
+   i915_sw_fence_notify_t fn;
unsigned long flags;


Looks good to me. I'd just make the flags narrower now that they can be, 
and 

Re: [Intel-gfx] [PATCH 01/26] dma-buf: add dma_resv_for_each_fence_unlocked v4

[Tvrtko Ursulin]

On 22/09/2021 15:50, Christian König wrote:

Am 22.09.21 um 16:36 schrieb Tvrtko Ursulin:

+
+/**
+ * dma_resv_iter_first_unlocked - first fence in an unlocked 
dma_resv obj.

+ * @cursor: the cursor with the current position
+ *
+ * Returns the first fence from an unlocked dma_resv obj.
+ */
+struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter 
*cursor)

+{
+    rcu_read_lock();
+    do {
+    dma_resv_iter_restart_unlocked(cursor);
+    dma_resv_iter_walk_unlocked(cursor);
+    } while (read_seqcount_retry(>obj->seq, cursor->seq));
+    rcu_read_unlock();
+
+    return cursor->fence;
+}
+EXPORT_SYMBOL(dma_resv_iter_first_unlocked);


Why is this one split from dma_resv_iter_begin and even exported?


I've split it to be able to use dma_resv_iter_begin in both the unlocked 
and locked iterator.


Ok.




I couldn't find any users in the series.


This is used in the dma_resv_for_each_fence_unlocked() macro to return 
the first fence.


Doh!


+
+/**
+ * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv 
obj.

+ * @cursor: the cursor with the current position
+ *
+ * Returns the next fence from an unlocked dma_resv obj.
+ */
+struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter 
*cursor)

+{
+    bool restart;
+
+    rcu_read_lock();
+    cursor->is_restarted = false;
+    restart = read_seqcount_retry(>obj->seq, cursor->seq);
+    do {
+    if (restart)
+    dma_resv_iter_restart_unlocked(cursor);
+    dma_resv_iter_walk_unlocked(cursor);
+    restart = true;
+    } while (read_seqcount_retry(>obj->seq, cursor->seq));
+    rcu_read_unlock();
+
+    return cursor->fence;
+}
+EXPORT_SYMBOL(dma_resv_iter_next_unlocked);


Couldn't dma_resv_iter_first_unlocked and dma_resv_iter_next_unlocked 
share the same implementation? Especially if you are able to replace 
cursor->is_restarted with cursor->index == -1.


That's what I had initially, but Daniel disliked it for some reason. You 
then need a centralized walk function instead of first/next.


I had some ideas to only consolidate "first" and "next" helpers but never mind, 
yours is fine as well.

Regards,

Tvrtko



Thanks,
Christian.


Regards,

Tvrtko

[Intel-gfx] [PATCH] drm/i915: Drop stealing of bits from i915_sw_fence function pointer

[Matthew Brost]

Rather than stealing bits from i915_sw_fence function pointer use
seperate fields for function pointer and flags. If using two different
fields, the 4 byte alignment for the i915_sw_fence function pointer can
also be dropped.

v2:
 (CI)
  - Set new function field rather than flags in __i915_sw_fence_init

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
 drivers/gpu/drm/i915/i915_request.c   |  4 ++--
 drivers/gpu/drm/i915/i915_sw_fence.c  | 12 +--
 drivers/gpu/drm/i915/i915_sw_fence.h  | 21 +--
 drivers/gpu/drm/i915/i915_sw_fence_work.c |  2 +-
 .../gpu/drm/i915/selftests/i915_sw_fence.c|  2 +-
 drivers/gpu/drm/i915/selftests/lib_sw_fence.c |  4 ++--
 8 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a7ca38613f89..6d5bb55ffc82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10323,7 +10323,7 @@ static void intel_atomic_commit_work(struct work_struct 
*work)
intel_atomic_commit_tail(state);
 }
 
-static int __i915_sw_fence_call
+static int
 intel_atomic_commit_ready(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify notify)
 {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..df5fec5c3da8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -800,7 +800,7 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
 }
 
-static int __i915_sw_fence_call
+static int
 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_gem_engines *engines =
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index ce446716d092..945d3025a0b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -719,7 +719,7 @@ void i915_request_cancel(struct i915_request *rq, int error)
intel_context_cancel_request(rq->context, rq);
 }
 
-static int __i915_sw_fence_call
+static int
 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_request *request =
@@ -755,7 +755,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
return NOTIFY_DONE;
 }
 
-static int __i915_sw_fence_call
+static int
 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
 {
struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index c589a681da77..1c080dd1f718 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -34,7 +34,7 @@ enum {
 
 static void *i915_sw_fence_debug_hint(void *addr)
 {
-   return (void *)(((struct i915_sw_fence *)addr)->flags & 
I915_SW_FENCE_MASK);
+   return (void *)(((struct i915_sw_fence *)addr)->fn);
 }
 
 #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -126,10 +126,7 @@ static inline void debug_fence_assert(struct i915_sw_fence 
*fence)
 static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
  enum i915_sw_fence_notify state)
 {
-   i915_sw_fence_notify_t fn;
-
-   fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
-   return fn(fence, state);
+   return fence->fn(fence, state);
 }
 
 #ifdef CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS
@@ -242,10 +239,11 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
  const char *name,
  struct lock_class_key *key)
 {
-   BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+   BUG_ON(!fn);
 
__init_waitqueue_head(>wait, name, key);
-   fence->flags = (unsigned long)fn;
+   fence->fn = fn;
+   fence->flags = 0;
 
i915_sw_fence_reinit(fence);
 }
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h
index 30a863353ee6..70ba1789aa89 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -17,26 +17,25 @@
 
 struct completion;
 struct dma_resv;
+struct i915_sw_fence;
+
+enum i915_sw_fence_notify {
+   FENCE_COMPLETE,
+   FENCE_FREE
+};
+
+typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *,
+ enum i915_sw_fence_notify state);
 
 struct i915_sw_fence {
wait_queue_head_t wait;
+   i915_sw_fence_notify_t fn;
unsigned long flags;
atomic_t pending;
int error;
 };
 
 #define I915_SW_FENCE_CHECKED_BIT  0 /* used internally for DAG checking */
-#define I915_SW_FENCE_PRIVATE_BIT  1 

Re: [Intel-gfx] [PATCH 13/26] drm/i915: use the new iterator in i915_gem_busy_ioctl

[Tvrtko Ursulin]

On 22/09/2021 15:31, Christian König wrote:

Am 22.09.21 um 12:21 schrieb Tvrtko Ursulin:


On 22/09/2021 10:10, Christian König wrote:

This makes the function much simpler since the complex
retry logic is now handled else where.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/i915/gem/i915_gem_busy.c | 35 ++--
  1 file changed, 14 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_busy.c 
b/drivers/gpu/drm/i915/gem/i915_gem_busy.c

index 6234e17259c1..313afb4a11c7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_busy.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_busy.c
@@ -82,8 +82,8 @@ i915_gem_busy_ioctl(struct drm_device *dev, void 
*data,

  {
  struct drm_i915_gem_busy *args = data;
  struct drm_i915_gem_object *obj;
-    struct dma_resv_list *list;
-    unsigned int seq;
+    struct dma_resv_iter cursor;
+    struct dma_fence *fence;
  int err;
    err = -ENOENT;
@@ -109,27 +109,20 @@ i915_gem_busy_ioctl(struct drm_device *dev, 
void *data,
   * to report the overall busyness. This is what the wait-ioctl 
does.

   *
   */
-retry:
-    seq = raw_read_seqcount(>base.resv->seq);
-
-    /* Translate the exclusive fence to the READ *and* WRITE engine */
-    args->busy = 
busy_check_writer(dma_resv_excl_fence(obj->base.resv));

-
-    /* Translate shared fences to READ set of engines */
-    list = dma_resv_shared_list(obj->base.resv);
-    if (list) {
-    unsigned int shared_count = list->shared_count, i;
-
-    for (i = 0; i < shared_count; ++i) {
-    struct dma_fence *fence =
-    rcu_dereference(list->shared[i]);
-
+    args->busy = false;


You can drop this line, especially since it is not a boolean. With that:


I just realized that this won't work. We still need to initialize the 
return value when there is no fence at all in the resv object.




Reviewed-by: Tvrtko Ursulin 


Does that still counts if I set args->busy to zero?


Ah yes, my bad, apologies. You can keep the r-b.

Regards,

Tvrtko



Thanks,
Christian.



Regards,

Tvrtko


+    dma_resv_iter_begin(, obj->base.resv, true);
+    dma_resv_for_each_fence_unlocked(, fence) {
+    if (dma_resv_iter_is_restarted())
+    args->busy = 0;
+
+    if (dma_resv_iter_is_exclusive())
+    /* Translate the exclusive fence to the READ *and* WRITE 
engine */

+    args->busy |= busy_check_writer(fence);
+    else
+    /* Translate shared fences to READ set of engines */
  args->busy |= busy_check_reader(fence);
-    }
  }
-
-    if (args->busy && read_seqcount_retry(>base.resv->seq, seq))
-    goto retry;
+    dma_resv_iter_end();
    err = 0;
  out:

Re: [Intel-gfx] [PATCH] drm/i915/display: Add HDR mode helper function

[Ville Syrjälä]

On Tue, Sep 07, 2021 at 05:06:58PM +0530, Tejas Upadhyay wrote:
> Add helper function with returns if HDR mode in on
> 
> Signed-off-by: Tejas Upadhyay 

Sorry for the lag. This kept slipping my mind.

I fixed up the alignment a bit and pushed to drm-intel-next. Thanks.

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1f447ba776c7..51008600a180 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -182,6 +182,12 @@ static void intel_update_czclk(struct drm_i915_private 
> *dev_priv)
>   dev_priv->czclk_freq);
>  }
>  
> +static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
> +{
> + return (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
> + BIT(PLANE_CURSOR))) == 0;
> +}
> +
>  /* WA Display #0827: Gen9:all */
>  static void
>  skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
> @@ -5257,8 +5263,7 @@ static void bdw_set_pipemisc(const struct 
> intel_crtc_state *crtc_state)
>   PIPEMISC_YUV420_MODE_FULL_BLEND;
>  
>   if (DISPLAY_VER(dev_priv) >= 11 &&
> - (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
> -BIT(PLANE_CURSOR))) == 0)
> + is_hdr_mode(crtc_state))
>   val |= PIPEMISC_HDR_MODE_PRECISION;
>  
>   if (DISPLAY_VER(dev_priv) >= 12)
> -- 
> 2.31.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 01/26] dma-buf: add dma_resv_for_each_fence_unlocked v4

[Tvrtko Ursulin]

On 22/09/2021 10:10, Christian König wrote:

Abstract the complexity of iterating over all the fences
in a dma_resv object.

The new loop handles the whole RCU and retry dance and
returns only fences where we can be sure we grabbed the
right one.

v2: fix accessing the shared fences while they might be freed,
 improve kerneldoc, rename _cursor to _iter, add
 dma_resv_iter_is_exclusive, add dma_resv_iter_begin/end

v3: restructor the code, move rcu_read_lock()/unlock() into the
 iterator, add dma_resv_iter_is_restarted()

v4: fix NULL deref when no explicit fence exists, drop superflous
 rcu_read_lock()/unlock() calls.

Signed-off-by: Christian König 
---
  drivers/dma-buf/dma-resv.c | 95 ++
  include/linux/dma-resv.h   | 95 ++
  2 files changed, 190 insertions(+)

diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 84fbe60629e3..7768140ab36d 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -323,6 +323,101 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, struct 
dma_fence *fence)
  }
  EXPORT_SYMBOL(dma_resv_add_excl_fence);
  
+/**

+ * dma_resv_iter_restart_unlocked - restart the unlocked iterator
+ * @cursor: The dma_resv_iter object to restart
+ *
+ * Restart the unlocked iteration by initializing the cursor object.
+ */
+static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor)
+{
+   cursor->seq = read_seqcount_begin(>obj->seq);
+   cursor->index = -1;
+   if (cursor->all_fences)
+   cursor->fences = dma_resv_shared_list(cursor->obj);
+   else
+   cursor->fences = NULL;
+   cursor->is_restarted = true;
+}
+
+/**
+ * dma_resv_iter_walk_unlocked - walk over fences in a dma_resv obj
+ * @cursor: cursor to record the current position
+ *
+ * Return all the fences in the dma_resv object which are not yet signaled.
+ * The returned fence has an extra local reference so will stay alive.
+ * If a concurrent modify is detected the whole iterration is started over 
again.


iteration


+ */
+static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor)
+{
+   struct dma_resv *obj = cursor->obj;
+
+   do {
+   /* Drop the reference from the previous round */
+   dma_fence_put(cursor->fence);
+
+   if (cursor->index++ == -1) {
+   cursor->fence = dma_resv_excl_fence(obj);
+
+   } else if (!cursor->fences ||
+  cursor->index >= cursor->fences->shared_count) {
+   cursor->fence = NULL;
+
+   } else {
+   struct dma_resv_list *fences = cursor->fences;
+   unsigned int idx = cursor->index;
+
+   cursor->fence = rcu_dereference(fences->shared[idx]);
+   }
+   if (cursor->fence)
+   cursor->fence = dma_fence_get_rcu(cursor->fence);
+   } while (cursor->fence && dma_fence_is_signaled(cursor->fence));
+}
+
+/**
+ * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj.
+ * @cursor: the cursor with the current position
+ *
+ * Returns the first fence from an unlocked dma_resv obj.
+ */
+struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor)
+{
+   rcu_read_lock();
+   do {
+   dma_resv_iter_restart_unlocked(cursor);
+   dma_resv_iter_walk_unlocked(cursor);
+   } while (read_seqcount_retry(>obj->seq, cursor->seq));
+   rcu_read_unlock();
+
+   return cursor->fence;
+}
+EXPORT_SYMBOL(dma_resv_iter_first_unlocked);


Why is this one split from dma_resv_iter_begin and even exported? I 
couldn't find any users in the series.



+
+/**
+ * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj.
+ * @cursor: the cursor with the current position
+ *
+ * Returns the next fence from an unlocked dma_resv obj.
+ */
+struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor)
+{
+   bool restart;
+
+   rcu_read_lock();
+   cursor->is_restarted = false;
+   restart = read_seqcount_retry(>obj->seq, cursor->seq);
+   do {
+   if (restart)
+   dma_resv_iter_restart_unlocked(cursor);
+   dma_resv_iter_walk_unlocked(cursor);
+   restart = true;
+   } while (read_seqcount_retry(>obj->seq, cursor->seq));
+   rcu_read_unlock();
+
+   return cursor->fence;
+}
+EXPORT_SYMBOL(dma_resv_iter_next_unlocked);


Couldn't dma_resv_iter_first_unlocked and dma_resv_iter_next_unlocked 
share the same implementation? Especially if you are able to replace 
cursor->is_restarted with cursor->index == -1.



+
  /**
   * dma_resv_copy_fences - Copy all fences from src to dst.
   * @dst: the destination reservation object
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
index 9100dd3dc21f..baf77a542392 

[Intel-gfx] [PATCH 24/24] drm/i915: constify display wm vtable

[Jani Nikula]

From: Dave Airlie 

Use a nop table for the cases where CxSR doesn't init properly.

v2: use a nop table (Jani)

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 -
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 80 ++--
 3 files changed, 75 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8add1920c2cc..3d452f364d09 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct 
drm_device *dev,
  */
 static void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-   if (dev_priv->wm_disp.update_wm)
-   dev_priv->wm_disp.update_wm(dev_priv);
+   if (dev_priv->wm_disp->update_wm)
+   dev_priv->wm_disp->update_wm(dev_priv);
 }
 
 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->wm_disp.compute_pipe_wm)
-   return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+   if (dev_priv->wm_disp->compute_pipe_wm)
+   return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
 }
 
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct 
intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (!dev_priv->wm_disp.compute_intermediate_wm)
+   if (!dev_priv->wm_disp->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(_priv->drm,
-   !dev_priv->wm_disp.compute_pipe_wm))
+   !dev_priv->wm_disp->compute_pipe_wm))
return 0;
-   return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+   return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
 }
 
 static bool intel_initial_watermarks(struct intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->wm_disp.initial_watermarks) {
-   dev_priv->wm_disp.initial_watermarks(state, crtc);
+   if (dev_priv->wm_disp->initial_watermarks) {
+   dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct 
intel_atomic_state *state,
   struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->wm_disp.atomic_update_watermarks)
-   dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+   if (dev_priv->wm_disp->atomic_update_watermarks)
+   dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
 }
 
 static void intel_optimize_watermarks(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->wm_disp.optimize_watermarks)
-   dev_priv->wm_disp.optimize_watermarks(state, crtc);
+   if (dev_priv->wm_disp->optimize_watermarks)
+   dev_priv->wm_disp->optimize_watermarks(state, crtc);
 }
 
 static void intel_compute_global_watermarks(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->wm_disp.compute_global_watermarks)
-   dev_priv->wm_disp.compute_global_watermarks(state);
+   if (dev_priv->wm_disp->compute_global_watermarks)
+   dev_priv->wm_disp->compute_global_watermarks(state);
 }
 
 /* returns HPLL frequency in kHz */
@@ -3734,7 +3734,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state 
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-   if (!dev_priv->wm_disp.initial_watermarks)
+   if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
 
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11414,7 +11414,7 @@ static void sanitize_watermarks(struct drm_i915_private 
*dev_priv)
int i;
 
/* Only supported on platforms that use atomic watermark design */
-   if (!dev_priv->wm_disp.optimize_watermarks)
+   if (!dev_priv->wm_disp->optimize_watermarks)
return;
 
state = drm_atomic_state_alloc(_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h 

[Intel-gfx] [PATCH 23/24] drm/i915: constify clock gating init vtable.

[Jani Nikula]

From: Dave Airlie 

I used a macro to avoid making any really silly mistakes here.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 78 +++--
 2 files changed, 55 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6a6d08219526..390091b898d5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
 
/* pm private clock gating functions */
-   struct drm_i915_clock_gating_funcs clock_gating_funcs;
+   const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 826216a115fd..0a5c1e3c798b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct 
drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+   dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,36 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
 }
 
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs 
= { \
+   .init_clock_gating = platform##_init_clock_gating,  \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
 /**
  * intel_init_clock_gating_hooks - setup the clock gating hooks
  * @dev_priv: device private
@@ -7898,52 +7928,52 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_ALDERLAKE_P(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
adlp_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_DG1(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
dg1_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
-   dev_priv->clock_gating_funcs.init_clock_gating = 
gen12lp_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
-   dev_priv->clock_gating_funcs.init_clock_gating = 
icl_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
cfl_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
skl_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
kbl_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
bxt_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
glk_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
bdw_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
chv_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
-   dev_priv->clock_gating_funcs.init_clock_gating = 
hsw_init_clock_gating;
+   dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_IVYBRIDGE(dev_priv))
-   

[Intel-gfx] [PATCH 22/24] drm/i915: constify display function vtable

[Jani Nikula]

From: Dave Airlie 

Make nice clear tables instead of having things in two places.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 81 
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 2 files changed, 52 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 5495c04e777b..8add1920c2cc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3788,7 +3788,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc 
*crtc,
 
drm_WARN_ON(_priv->drm, IS_ERR(temp_crtc_state) || ret);
 
-   dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+   dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
 
drm_atomic_state_put(state);
 
@@ -5999,7 +5999,7 @@ static bool intel_crtc_get_pipe_config(struct 
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-   if (!i915->display.get_pipe_config(crtc, crtc_state))
+   if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
 
crtc_state->hw.active = true;
@@ -9807,7 +9807,7 @@ static void intel_enable_crtc(struct intel_atomic_state 
*state,
 
intel_crtc_update_active_timings(new_crtc_state);
 
-   dev_priv->display.crtc_enable(state, crtc);
+   dev_priv->display->crtc_enable(state, crtc);
 
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9895,7 +9895,7 @@ static void intel_old_crtc_state_disables(struct 
intel_atomic_state *state,
 */
intel_crtc_disable_pipe_crc(crtc);
 
-   dev_priv->display.crtc_disable(state, crtc);
+   dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10274,7 +10274,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
}
 
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
-   dev_priv->display.commit_modeset_enables(state);
+   dev_priv->display->commit_modeset_enables(state);
 
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11277,6 +11277,46 @@ static const struct drm_mode_config_funcs 
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
 };
 
+static const struct drm_i915_display_funcs skl_display_funcs = {
+   .get_pipe_config = hsw_get_pipe_config,
+   .crtc_enable = hsw_crtc_enable,
+   .crtc_disable = hsw_crtc_disable,
+   .commit_modeset_enables = skl_commit_modeset_enables,
+   .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+   .get_pipe_config = hsw_get_pipe_config,
+   .crtc_enable = hsw_crtc_enable,
+   .crtc_disable = hsw_crtc_disable,
+   .commit_modeset_enables = intel_commit_modeset_enables,
+   .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+   .get_pipe_config = ilk_get_pipe_config,
+   .crtc_enable = ilk_crtc_enable,
+   .crtc_disable = ilk_crtc_disable,
+   .commit_modeset_enables = intel_commit_modeset_enables,
+   .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+   .get_pipe_config = i9xx_get_pipe_config,
+   .crtc_enable = valleyview_crtc_enable,
+   .crtc_disable = i9xx_crtc_disable,
+   .commit_modeset_enables = intel_commit_modeset_enables,
+   .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+   .get_pipe_config = i9xx_get_pipe_config,
+   .crtc_enable = i9xx_crtc_enable,
+   .crtc_disable = i9xx_crtc_disable,
+   .commit_modeset_enables = intel_commit_modeset_enables,
+   .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
 /**
  * intel_init_display_hooks - initialize the display modesetting hooks
  * @dev_priv: device private
@@ -11292,38 +11332,19 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
 
if (DISPLAY_VER(dev_priv) >= 9) {
-   dev_priv->display.get_pipe_config = hsw_get_pipe_config;
-   dev_priv->display.crtc_enable = hsw_crtc_enable;
-   dev_priv->display.crtc_disable = hsw_crtc_disable;
+   dev_priv->display = _display_funcs;
} else if (HAS_DDI(dev_priv)) {
-   dev_priv->display.get_pipe_config = hsw_get_pipe_config;
-   

[Intel-gfx] [PATCH 21/24] drm/i915: drop unused function ptr and comments.

[Jani Nikula]

From: Dave Airlie 

There was some excess comments and an unused vtbl ptr.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4daae67142e..71b72db434b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
 struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
-   void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
-   /* clock updates for mode set */
-   /* cursor updates */
-   /* render clock increase/decrease */
-   /* display clock increase/decrease */
-   /* pll clock increase/decrease */
 };
 
 
-- 
2.30.2

[Intel-gfx] [PATCH 20/24] drm/i915: constify the cdclk vtable

[Jani Nikula]

From: Dave Airlie 

This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++---
 drivers/gpu/drm/i915/i915_drv.h|   2 +-
 2 files changed, 206 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
-   dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+   dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
 }
 
 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+   return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
-   dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+   dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state 
*cdclk_config)
 {
-   return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+   return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 int cdclk)
 {
-   return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+   return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
 
-   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
 }
 
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+   .get_cdclk = skl_get_cdclk,
+   .set_cdclk = skl_set_cdclk,
+   .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+   .get_cdclk = bdw_get_cdclk,
+   .set_cdclk = bdw_set_cdclk,
+   .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+   .get_cdclk = vlv_get_cdclk,
+   .set_cdclk = chv_set_cdclk,
+   .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+   .get_cdclk = vlv_get_cdclk,
+   .set_cdclk = vlv_set_cdclk,
+   .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+   .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+   .get_cdclk = hsw_get_cdclk,
+   .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ 

[Intel-gfx] [PATCH 19/24] drm/i915: constify the dpll clock vtable

[Jani Nikula]

From: Dave Airlie 

Most the dpll vtable into read-only memory.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c |  6 +--
 drivers/gpu/drm/i915/display/intel_dpll.c| 48 
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 3 files changed, 44 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f3c8f8a4127e..5495c04e777b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6826,10 +6826,10 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
crtc_state->update_wm_post = true;
 
if (mode_changed && crtc_state->hw.enable &&
-   dev_priv->dpll_funcs.crtc_compute_clock &&
+   dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
-   ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+   ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8856,7 +8856,7 @@ static void intel_modeset_clear_plls(struct 
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
 
-   if (!dev_priv->dpll_funcs.crtc_compute_clock)
+   if (!dev_priv->dpll_funcs)
return;
 
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7811f19acb6a..784e3ee658b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1365,25 +1365,57 @@ static int i8xx_crtc_compute_clock(struct 
intel_crtc_state *crtc_state)
return 0;
 }
 
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+   .crtc_compute_clock = hsw_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+   .crtc_compute_clock = ilk_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+   .crtc_compute_clock = chv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+   .crtc_compute_clock = vlv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+   .crtc_compute_clock = g4x_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+   .crtc_compute_clock = pnv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+   .crtc_compute_clock = i9xx_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+   .crtc_compute_clock = i8xx_crtc_compute_clock,
+};
+
 void
 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
 {
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
hsw_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
ilk_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
chv_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
vlv_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_G4X(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
g4x_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
-   dev_priv->dpll_funcs.crtc_compute_clock = 
pnv_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
-   dev_priv->dpll_funcs.crtc_compute_clock = 
i9xx_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
else
-   dev_priv->dpll_funcs.crtc_compute_clock = 
i8xx_crtc_compute_clock;
+   dev_priv->dpll_funcs = _dpll_funcs;
 }
 
 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 363afe0f58b7..5f63773deaa0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
 
/* display pll funcs */
-   struct intel_dpll_funcs dpll_funcs;
+   const struct intel_dpll_funcs *dpll_funcs;
 
/* Display functions */
struct drm_i915_display_funcs display;
-- 
2.30.2

[Intel-gfx] [PATCH 18/24] drm/i915: constify the audio function vtable

[Jani Nikula]

From: Dave Airlie 

Move the functions into read-only tables.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
 drivers/gpu/drm/i915/i915_drv.h|  2 +-
 2 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..0a6ad74d9173 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder 
*encoder,
 
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 
-   if (dev_priv->audio_funcs.audio_codec_enable)
-   dev_priv->audio_funcs.audio_codec_enable(encoder,
-crtc_state,
-conn_state);
+   if (dev_priv->audio_funcs)
+   dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
 
mutex_lock(_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder 
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
 
-   if (dev_priv->audio_funcs.audio_codec_disable)
-   dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+   if (dev_priv->audio_funcs)
+   dev_priv->audio_funcs->audio_codec_disable(encoder,
+  old_crtc_state,
+  old_conn_state);
 
mutex_lock(_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder 
*encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 }
 
+static const struct intel_audio_funcs g4x_audio_funcs = {
+   .audio_codec_enable = g4x_audio_codec_enable,
+   .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+   .audio_codec_enable = ilk_audio_codec_enable,
+   .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+   .audio_codec_enable = hsw_audio_codec_enable,
+   .audio_codec_disable = hsw_audio_codec_disable,
+};
+
 /**
  * intel_init_audio_hooks - Set up chip specific audio hooks
  * @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder 
*encoder,
 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_G4X(dev_priv)) {
-   dev_priv->audio_funcs.audio_codec_enable = 
g4x_audio_codec_enable;
-   dev_priv->audio_funcs.audio_codec_disable = 
g4x_audio_codec_disable;
+   dev_priv->audio_funcs = _audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-   dev_priv->audio_funcs.audio_codec_enable = 
ilk_audio_codec_enable;
-   dev_priv->audio_funcs.audio_codec_disable = 
ilk_audio_codec_disable;
+   dev_priv->audio_funcs = _audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
-   dev_priv->audio_funcs.audio_codec_enable = 
hsw_audio_codec_enable;
-   dev_priv->audio_funcs.audio_codec_disable = 
hsw_audio_codec_disable;
+   dev_priv->audio_funcs = _audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
-   dev_priv->audio_funcs.audio_codec_enable = 
ilk_audio_codec_enable;
-   dev_priv->audio_funcs.audio_codec_disable = 
ilk_audio_codec_disable;
+   dev_priv->audio_funcs = _audio_funcs;
}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f20b9167019..363afe0f58b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
 
/* Display internal audio functions */
-   struct intel_audio_funcs audio_funcs;
+   const struct intel_audio_funcs *audio_funcs;
 
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
-- 
2.30.2

[Intel-gfx] [PATCH 17/24] drm/i915: constify color function vtable.

[Jani Nikula]

From: Dave Airlie 

This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.

v2: fixed IVB mistake (Jani)

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
 drivers/gpu/drm/i915/i915_drv.h|   2 +-
 2 files changed, 93 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct 
intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   dev_priv->color_funcs.load_luts(crtc_state);
+   dev_priv->color_funcs->load_luts(crtc_state);
 }
 
 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   dev_priv->color_funcs.color_commit(crtc_state);
+   dev_priv->color_funcs->color_commit(crtc_state);
 }
 
 static bool intel_can_preload_luts(const struct intel_crtc_state 
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   return dev_priv->color_funcs.color_check(crtc_state);
+   return dev_priv->color_funcs->color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   if (dev_priv->color_funcs.read_luts)
-   dev_priv->color_funcs.read_luts(crtc_state);
+   if (dev_priv->color_funcs->read_luts)
+   dev_priv->color_funcs->read_luts(crtc_state);
 }
 
 static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state 
*crtc_state)
}
 }
 
+static const struct intel_color_funcs chv_color_funcs = {
+   .color_check = chv_color_check,
+   .color_commit = i9xx_color_commit,
+   .load_luts = chv_load_luts,
+   .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+   .color_check = i9xx_color_check,
+   .color_commit = i9xx_color_commit,
+   .load_luts = i965_load_luts,
+   .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+   .color_check = i9xx_color_check,
+   .color_commit = i9xx_color_commit,
+   .load_luts = i9xx_load_luts,
+   .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+   .color_check = icl_color_check,
+   .color_commit = skl_color_commit,
+   .load_luts = icl_load_luts,
+   .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+   .color_check = glk_color_check,
+   .color_commit = skl_color_commit,
+   .load_luts = glk_load_luts,
+   .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+   .color_check = ivb_color_check,
+   .color_commit = skl_color_commit,
+   .load_luts = bdw_load_luts,
+   .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+   .color_check = ivb_color_check,
+   .color_commit = hsw_color_commit,
+   .load_luts = bdw_load_luts,
+   .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+   .color_check = ivb_color_check,
+   .color_commit = hsw_color_commit,
+   .load_luts = ivb_load_luts,
+   .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+   .color_check = ivb_color_check,
+   .color_commit = ilk_color_commit,
+   .load_luts = ivb_load_luts,
+   .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+   .color_check = ilk_color_check,
+   .color_commit = ilk_color_commit,
+   .load_luts = ilk_load_luts,
+   .read_luts = ilk_read_luts,
+};
+
 void intel_color_init(struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
 
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
-   dev_priv->color_funcs.color_check = chv_color_check;
-   dev_priv->color_funcs.color_commit = i9xx_color_commit;
-   dev_priv->color_funcs.load_luts = chv_load_luts;
-   dev_priv->color_funcs.read_luts = chv_read_luts;
+   dev_priv->color_funcs = _color_funcs;
} else if 

[Intel-gfx] [PATCH 16/24] drm/i915: constify hotplug function vtable.

[Jani Nikula]

From: Dave Airlie 

Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_hotplug.c |  4 +--
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/i915_irq.c  | 28 +++-
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct 
drm_i915_private *dev_priv)
 
 static void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-   if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
-   i915->hotplug_funcs.hpd_irq_setup(i915);
+   if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+   i915->hotplug_funcs->hpd_irq_setup(i915);
 }
 
 static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a31738dd6378..5f1eb471abd8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
 
/* irq display functions */
-   struct intel_hotplug_funcs hotplug_funcs;
+   const struct intel_hotplug_funcs *hotplug_funcs;
 
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..77680bca46ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
 }
 
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+   .hpd_irq_setup = platform##_hpd_irq_setup,   \
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
 /**
  * intel_irq_init - initializes irq support
  * @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
i915_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
dg1_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
gen11_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
bxt_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
icp_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
spt_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
else
-   dev_priv->hotplug_funcs.hpd_irq_setup = 
ilk_hpd_irq_setup;
+   dev_priv->hotplug_funcs = _hpd_funcs;
}
 }
 
-- 
2.30.2

[Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.

[Jani Nikula]

From: Dave Airlie 

This moves all the cdclk related functions into their own vtable.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
 drivers/gpu/drm/i915/i915_drv.h|   8 +-
 2 files changed, 78 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
-   dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+   dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
 }
 
 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   return dev_priv->display.bw_calc_min_cdclk(state);
+   return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
-   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+   dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state 
*cdclk_config)
 {
-   return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+   return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
 }
 
 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 int cdclk)
 {
-   return dev_priv->display.calc_voltage_level(cdclk);
+   return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
 }
 
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
 
-   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+   if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private 
*dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_DG2(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
-   dev_priv->display.set_cdclk = bxt_set_cdclk;
-   dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-   dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-   dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+   dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+   dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+   dev_priv->cdclk_funcs.modeset_calc_cdclk = 
bxt_modeset_calc_cdclk;
+   dev_priv->cdclk_funcs.calc_voltage_level = 
tgl_calc_voltage_level;
 

[Intel-gfx] [PATCH 15/24] drm/i915: constify fdi link training vtable

[Jani Nikula]

From: Dave Airlie 

Put the vtable into ro memory.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_fdi.c | 20 
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
b/drivers/gpu/drm/i915/display/intel_fdi.c
index f828bebe8962..af01d1fa761e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+   dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
 }
 
 /* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private 
*dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
 }
 
+static const struct intel_fdi_funcs ilk_funcs = {
+   .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+   .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+   .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
 void
 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
 {
if (IS_IRONLAKE(dev_priv)) {
-   dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+   dev_priv->fdi_funcs = _funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
-   dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+   dev_priv->fdi_funcs = _funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
-   dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+   dev_priv->fdi_funcs = _funcs;
}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 954b16ee857f..a31738dd6378 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
 
/* fdi display functions */
-   struct intel_fdi_funcs fdi_funcs;
+   const struct intel_fdi_funcs *fdi_funcs;
 
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
-- 
2.30.2

[Intel-gfx] [PATCH 13/24] drm/i915: split fdi link training from display vtable.

[Jani Nikula]

From: Dave Airlie 

It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_fdi.c |  8 
 drivers/gpu/drm/i915/i915_drv.h  | 11 ---
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
b/drivers/gpu/drm/i915/display/intel_fdi.c
index d20669e53663..f828bebe8962 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   dev_priv->display.fdi_link_train(crtc, crtc_state);
+   dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
 }
 
 /* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
 {
if (IS_IRONLAKE(dev_priv)) {
-   dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+   dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
-   dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+   dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
-   dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+   dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9aff1f32676a..62a7d67cbc2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 };
 
+struct intel_fdi_funcs {
+   void (*fdi_link_train)(struct intel_crtc *crtc,
+  const struct intel_crtc_state *crtc_state);
+};
+
 struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
 * fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
 
-   void (*fdi_link_train)(struct intel_crtc *crtc,
-  const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
 
+   /* fdi display functions */
+   struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
 
-- 
2.30.2

[Intel-gfx] [PATCH 14/24] drm/i915: split the dpll clock compute out from display vtable.

[Jani Nikula]

From: Dave Airlie 

this single function might be possible to merge later, but
for now it's simple to just split it out.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_dpll.c| 16 
 drivers/gpu/drm/i915/i915_drv.h  |  8 +++-
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a32c9a4ac888..f3c8f8a4127e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6826,10 +6826,10 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
crtc_state->update_wm_post = true;
 
if (mode_changed && crtc_state->hw.enable &&
-   dev_priv->display.crtc_compute_clock &&
+   dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
-   ret = dev_priv->display.crtc_compute_clock(crtc_state);
+   ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8856,7 +8856,7 @@ static void intel_modeset_clear_plls(struct 
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
 
-   if (!dev_priv->display.crtc_compute_clock)
+   if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
 
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 487d8721ecf8..7811f19acb6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1369,21 +1369,21 @@ void
 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
 {
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
-   dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
-   dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
-   dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
-   dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
-   dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
-   dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
-   dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
i9xx_crtc_compute_clock;
else
-   dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+   dev_priv->dpll_funcs.crtc_compute_clock = 
i8xx_crtc_compute_clock;
 }
 
 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 62a7d67cbc2e..954b16ee857f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
   const struct intel_crtc_state *crtc_state);
 };
 
+struct intel_dpll_funcs {
+   int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
 struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
 * fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
 struct intel_initial_plane_config *);
-   int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct intel_fdi_funcs fdi_funcs;
 
+   /* display pll funcs */
+   struct intel_dpll_funcs dpll_funcs;
+

[Intel-gfx] [PATCH 12/24] drm/i915: split irq hotplug function from display vtable

[Jani Nikula]

From: Dave Airlie 

This provide a service from irq to display, so make it separate

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_hotplug.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h  |  9 -
 drivers/gpu/drm/i915/i915_irq.c  | 14 +++---
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct 
drm_i915_private *dev_priv)
 
 static void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-   if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
-   i915->display.hpd_irq_setup(i915);
+   if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+   i915->hotplug_funcs.hpd_irq_setup(i915);
 }
 
 static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b0715d51be32..9aff1f32676a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
 };
 
+struct intel_hotplug_funcs {
+   void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
 struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
 * fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
 
void (*fdi_link_train)(struct intel_crtc *crtc,
   const struct intel_crtc_state *crtc_state);
-   void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
 
+   /* irq display functions */
+   struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
-   dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
-   dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
-   dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-   dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-   dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
-   dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
spt_hpd_irq_setup;
else
-   dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+   dev_priv->hotplug_funcs.hpd_irq_setup = 
ilk_hpd_irq_setup;
}
 }
 
-- 
2.30.2

[Intel-gfx] [PATCH 10/24] drm/i915: split audio functions from display vtable

[Jani Nikula]

From: Dave Airlie 

These are only used internally in the audio code

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
 drivers/gpu/drm/i915/i915_drv.h| 19 +++--
 2 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 
-   if (dev_priv->display.audio_codec_enable)
-   dev_priv->display.audio_codec_enable(encoder,
+   if (dev_priv->audio_funcs.audio_codec_enable)
+   dev_priv->audio_funcs.audio_codec_enable(encoder,
 crtc_state,
 conn_state);
 
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder 
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
 
-   if (dev_priv->display.audio_codec_disable)
-   dev_priv->display.audio_codec_disable(encoder,
+   if (dev_priv->audio_funcs.audio_codec_disable)
+   dev_priv->audio_funcs.audio_codec_disable(encoder,
  old_crtc_state,
  old_conn_state);
 
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder 
*encoder,
 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_G4X(dev_priv)) {
-   dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
-   dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+   dev_priv->audio_funcs.audio_codec_enable = 
g4x_audio_codec_enable;
+   dev_priv->audio_funcs.audio_codec_disable = 
g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-   dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
-   dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+   dev_priv->audio_funcs.audio_codec_enable = 
ilk_audio_codec_enable;
+   dev_priv->audio_funcs.audio_codec_disable = 
ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
-   dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
-   dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+   dev_priv->audio_funcs.audio_codec_enable = 
hsw_audio_codec_enable;
+   dev_priv->audio_funcs.audio_codec_disable = 
hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
-   dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
-   dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+   dev_priv->audio_funcs.audio_codec_enable = 
ilk_audio_codec_enable;
+   dev_priv->audio_funcs.audio_codec_disable = 
ilk_audio_codec_disable;
}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e35b721d1130..4a8f33bfb04f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
 };
 
+struct intel_audio_funcs {
+   void (*audio_codec_enable)(struct intel_encoder *encoder,
+  const struct intel_crtc_state *crtc_state,
+  const struct drm_connector_state 
*conn_state);
+   void (*audio_codec_disable)(struct intel_encoder *encoder,
+   const struct intel_crtc_state 
*old_crtc_state,
+   const struct drm_connector_state 
*old_conn_state);
+};
+
 struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
  struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
 struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
-   void (*audio_codec_enable)(struct intel_encoder *encoder,
-  const struct intel_crtc_state *crtc_state,
-  const struct drm_connector_state 
*conn_state);
-   void (*audio_codec_disable)(struct intel_encoder *encoder,
-   const struct intel_crtc_state 
*old_crtc_state,
- 

[Intel-gfx] [PATCH 09/24] drm/i915: split color functions from display vtable

[Jani Nikula]

From: Dave Airlie 

These are only used internally in the color module

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
 drivers/gpu/drm/i915/i915_drv.h| 39 +++--
 2 files changed, 54 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct 
intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   dev_priv->display.load_luts(crtc_state);
+   dev_priv->color_funcs.load_luts(crtc_state);
 }
 
 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   dev_priv->display.color_commit(crtc_state);
+   dev_priv->color_funcs.color_commit(crtc_state);
 }
 
 static bool intel_can_preload_luts(const struct intel_crtc_state 
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   return dev_priv->display.color_check(crtc_state);
+   return dev_priv->color_funcs.color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-   if (dev_priv->display.read_luts)
-   dev_priv->display.read_luts(crtc_state);
+   if (dev_priv->color_funcs.read_luts)
+   dev_priv->color_funcs.read_luts(crtc_state);
 }
 
 static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
 
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
-   dev_priv->display.color_check = chv_color_check;
-   dev_priv->display.color_commit = i9xx_color_commit;
-   dev_priv->display.load_luts = chv_load_luts;
-   dev_priv->display.read_luts = chv_read_luts;
+   dev_priv->color_funcs.color_check = chv_color_check;
+   dev_priv->color_funcs.color_commit = i9xx_color_commit;
+   dev_priv->color_funcs.load_luts = chv_load_luts;
+   dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
-   dev_priv->display.color_check = i9xx_color_check;
-   dev_priv->display.color_commit = i9xx_color_commit;
-   dev_priv->display.load_luts = i965_load_luts;
-   dev_priv->display.read_luts = i965_read_luts;
+   dev_priv->color_funcs.color_check = i9xx_color_check;
+   dev_priv->color_funcs.color_commit = i9xx_color_commit;
+   dev_priv->color_funcs.load_luts = i965_load_luts;
+   dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
-   dev_priv->display.color_check = i9xx_color_check;
-   dev_priv->display.color_commit = i9xx_color_commit;
-   dev_priv->display.load_luts = i9xx_load_luts;
-   dev_priv->display.read_luts = i9xx_read_luts;
+   dev_priv->color_funcs.color_check = i9xx_color_check;
+   dev_priv->color_funcs.color_commit = i9xx_color_commit;
+   dev_priv->color_funcs.load_luts = i9xx_load_luts;
+   dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
-   dev_priv->display.color_check = icl_color_check;
+   dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
-   dev_priv->display.color_check = glk_color_check;
+   dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
-   dev_priv->display.color_check = ivb_color_check;
+   dev_priv->color_funcs.color_check = ivb_color_check;
else
-   dev_priv->display.color_check = ilk_color_check;
+   dev_priv->color_funcs.color_check = ilk_color_check;
 
if (DISPLAY_VER(dev_priv) >= 9)
-   dev_priv->display.color_commit = skl_color_commit;
+   dev_priv->color_funcs.color_commit = skl_color_commit;
else if 

[Intel-gfx] [PATCH 06/24] drm/i915/display: add intel_fdi_link_train wrapper.

[Jani Nikula]

From: Dave Airlie 

This wraps the fdi link training vfunc to make it clearer.

Suggested by Jani.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c | 8 
 drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 5a02c9e1dca8..c32ac150212d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct 
intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
 
/* For PCH output, training FDI link */
-   dev_priv->display.fdi_link_train(crtc, crtc_state);
+   intel_fdi_link_train(crtc, crtc_state);
 
/* We need to program the right clock selection before writing the pixel
 * mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 96ff12ad0873..d20669e53663 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,14 @@
 #include "intel_fdi.h"
 #include "intel_sideband.h"
 
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+   dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
 /* units of 100MHz */
 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h 
b/drivers/gpu/drm/i915/display/intel_fdi.h
index 60acf2133145..61cb216a09f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
 void lpt_fdi_program_mphy(struct drm_i915_private *i915);
 
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
 #endif
-- 
2.30.2

[Intel-gfx] [PATCH 08/24] drm/i915: split watermark vfuncs from display vtable.

[Jani Nikula]

From: Dave Airlie 

These are the watermark api between display and pm.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 -
 drivers/gpu/drm/i915/i915_drv.h  | 24 
 drivers/gpu/drm/i915/intel_pm.c  | 40 ++--
 3 files changed, 53 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index c32ac150212d..a32c9a4ac888 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct 
drm_device *dev,
  */
 static void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-   if (dev_priv->display.update_wm)
-   dev_priv->display.update_wm(dev_priv);
+   if (dev_priv->wm_disp.update_wm)
+   dev_priv->wm_disp.update_wm(dev_priv);
 }
 
 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->display.compute_pipe_wm)
-   return dev_priv->display.compute_pipe_wm(state, crtc);
+   if (dev_priv->wm_disp.compute_pipe_wm)
+   return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
 }
 
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct 
intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (!dev_priv->display.compute_intermediate_wm)
+   if (!dev_priv->wm_disp.compute_intermediate_wm)
return 0;
if (drm_WARN_ON(_priv->drm,
-   !dev_priv->display.compute_pipe_wm))
+   !dev_priv->wm_disp.compute_pipe_wm))
return 0;
-   return dev_priv->display.compute_intermediate_wm(state, crtc);
+   return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
 }
 
 static bool intel_initial_watermarks(struct intel_atomic_state *state,
 struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->display.initial_watermarks) {
-   dev_priv->display.initial_watermarks(state, crtc);
+   if (dev_priv->wm_disp.initial_watermarks) {
+   dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct 
intel_atomic_state *state,
   struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->display.atomic_update_watermarks)
-   dev_priv->display.atomic_update_watermarks(state, crtc);
+   if (dev_priv->wm_disp.atomic_update_watermarks)
+   dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
 }
 
 static void intel_optimize_watermarks(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->display.optimize_watermarks)
-   dev_priv->display.optimize_watermarks(state, crtc);
+   if (dev_priv->wm_disp.optimize_watermarks)
+   dev_priv->wm_disp.optimize_watermarks(state, crtc);
 }
 
 static void intel_compute_global_watermarks(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-   if (dev_priv->display.compute_global_watermarks)
-   dev_priv->display.compute_global_watermarks(state);
+   if (dev_priv->wm_disp.compute_global_watermarks)
+   dev_priv->wm_disp.compute_global_watermarks(state);
 }
 
 /* returns HPLL frequency in kHz */
@@ -3734,7 +3734,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state 
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-   if (!dev_priv->display.initial_watermarks)
+   if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
 
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11393,7 +11393,7 @@ static void sanitize_watermarks(struct drm_i915_private 
*dev_priv)
int i;
 
/* Only supported on platforms that use atomic watermark design */
-   if (!dev_priv->display.optimize_watermarks)
+   if (!dev_priv->wm_disp.optimize_watermarks)
return;
 
state = drm_atomic_state_alloc(_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 

[Intel-gfx] [PATCH 07/24] drm/i915: split clock gating init from display vtable

[Jani Nikula]

From: Dave Airlie 

This function is only used inside intel_pm.c

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h |  9 ++-
 drivers/gpu/drm/i915/intel_pm.c | 48 -
 2 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a098a1bc83b1..497a466ed0cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
 struct intel_limit;
 struct dpll;
 
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+   void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
 struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
  struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state 
*old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
   const struct intel_crtc_state *crtc_state);
-   void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
 
+   /* pm private clock gating functions */
+   struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..add50ff01d7c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct 
drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   dev_priv->display.init_clock_gating(dev_priv);
+   dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct 
drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
if (IS_ALDERLAKE_P(dev_priv))
-   dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
-   dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
-   dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
-   dev_priv->display.init_clock_gating = icl_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = skl_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
-   dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
-   dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
-   dev_priv->display.init_clock_gating = glk_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
-   dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
-   dev_priv->display.init_clock_gating = chv_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
-   dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+   dev_priv->clock_gating_funcs.init_clock_gating = 
hsw_init_clock_gating;
else if 

[Intel-gfx] [PATCH 05/24] drm/i915: add wrappers around cdclk vtable funcs.

[Jani Nikula]

From: Dave Airlie 

This adds wrappers around all the vtable callers so they are in
one place.

Suggested by Jani.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c| 47 +++
 drivers/gpu/drm/i915/display/intel_cdclk.h|  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_power.c|  2 +-
 4 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..0e09f259914f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
  * dividers can be programmed correctly.
  */
 
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+  struct intel_cdclk_config *cdclk_config)
+{
+   dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state 
*cdclk_config)
+{
+   return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+int cdclk)
+{
+   return dev_priv->display.calc_voltage_level(cdclk);
+}
+
 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
 * at least what the CDCLK frequency requires.
 */
cdclk_config->voltage_level =
-   dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+   intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private 
*dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
-   dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+   intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
 
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
-   dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+   intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
 
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
 _priv->gmbus_mutex);
}
 
-   dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+   intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
 
for_each_intel_dp(_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2424,7 +2455,7 @@ static int bxt_modeset_calc_cdclk(struct 
intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
 
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2433,7 +2464,7 @@ static int bxt_modeset_calc_cdclk(struct 
intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
-   dev_priv->display.calc_voltage_level(cdclk);
+   intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2525,7 +2556,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
 
-   ret = 

[Intel-gfx] [PATCH 04/24] drm/i915/wm: provide wrappers around watermark vfuncs calls (v2)

[Jani Nikula]

From: Dave Airlie 

This moves one wrapper from the pm->display side, and creates
wrappers for all the others, this should simplify things later.

One thing to note is that the code checks the existance of some
of these ptrs, so the wrappers are a bit complicated by that.

Suggested by Jani.

v2: fixup warnings in wrong place error.

Reviewed-by: Jani Nikula 
Signed-off-by: Dave Airlie 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 187 ---
 drivers/gpu/drm/i915/intel_pm.c  |  39 
 drivers/gpu/drm/i915/intel_pm.h  |   1 -
 3 files changed, 123 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 1c1129d8a424..331c9030a8c1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,101 @@ static void ilk_pfit_enable(const struct intel_crtc_state 
*crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 struct drm_modeset_acquire_ctx *ctx);
 
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current 
modes
+ * @dev_priv: i915 device
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ *   - normal (i.e. non-self-refresh)
+ *   - self-refresh (SR) mode
+ *   - lines are large relative to FIFO size (buffer can hold up to 2)
+ *   - lines are small relative to FIFO size (buffer can hold more than 2
+ * lines), so need to account for TLB latency
+ *
+ *   The normal calculation is:
+ * watermark = dotclock * bytes per pixel * latency
+ *   where latency is platform & configuration dependent (we assume pessimal
+ *   values here).
+ *
+ *   The SR calculation is:
+ * watermark = (trunc(latency/line time)+1) * surface width *
+ *   bytes per pixel
+ *   where
+ * line time = htotal / dotclock
+ * surface width = hdisplay for normal plane and 64 for cursor
+ *   and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that.  And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+   if (dev_priv->display.update_wm)
+   dev_priv->display.update_wm(dev_priv);
+}
+
+static int intel_compute_pipe_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.compute_pipe_wm)
+   return dev_priv->display.compute_pipe_wm(state, crtc);
+   return 0;
+}
+
+static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (!dev_priv->display.compute_intermediate_wm)
+   return 0;
+   if (drm_WARN_ON(_priv->drm,
+   !dev_priv->display.compute_pipe_wm))
+   return 0;
+   return dev_priv->display.compute_intermediate_wm(state, crtc);
+}
+
+static bool intel_initial_watermarks(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.initial_watermarks) {
+   dev_priv->display.initial_watermarks(state, crtc);
+   return true;
+   }
+   return false;
+}
+
+static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.atomic_update_watermarks)
+   dev_priv->display.atomic_update_watermarks(state, crtc);
+}
+
+static void intel_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.optimize_watermarks)
+   dev_priv->display.optimize_watermarks(state, crtc);
+}
+
+static void intel_compute_global_watermarks(struct intel_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   if (dev_priv->display.compute_global_watermarks)
+   dev_priv->display.compute_global_watermarks(state);
+}
+
 /* returns HPLL frequency in kHz */
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 {
@@ -2528,9 +2623,8 @@ static void intel_pre_plane_update(struct