[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF
== Series Details == Series: series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF URL : https://patchwork.freedesktop.org/series/96039/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21386_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21386_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21386_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21386_full: ### Piglit changes ### Possible regressions * spec@arb_texture_multisample@texelfetch fs sampler2dms 4 1x130-501x130: - pig-kbl-iris: NOTRUN -> [FAIL][1] [1]: None Known issues Here are the changes found in Patchwork_21386_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-snb5/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-apl8/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +5 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][5] ([i915#280]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-tglb6/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl1/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-kbl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) +5 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk6/igt@gem_exec_whis...@basic-queues-forked.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-glk9/igt@gem_exec_whis...@basic-queues-forked.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-kbl4/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4270]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-tglb1/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][17] ([i915#2724]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-snb5/igt@gem_userptr_bl...@vma-merge.html - shard-apl: NOTRUN -> [FAIL][18] ([i915#3318]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-apl8/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#2856]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-tglb1/igt@gen9_exec_pa...@bb-start-out.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglb: NOTRUN -> [WARN][20] ([i915#2681] / [i915#2684]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/shard-tglb1/igt@i915_pm_rc6_reside...@rc6-idle.html *
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Add struct to hold IP version
== Series Details == Series: series starting with [1/3] drm/i915: Add struct to hold IP version URL : https://patchwork.freedesktop.org/series/96038/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21385_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21385_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21385_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21385_full: ### IGT changes ### Possible regressions * igt@sysfs_heartbeat_interval@precise@vcs1: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb5/igt@sysfs_heartbeat_interval@prec...@vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb1/igt@sysfs_heartbeat_interval@prec...@vcs1.html Known issues Here are the changes found in Patchwork_21385_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-snb7/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-apl6/igt@gem_ctx_isolation@preservation...@bcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-apl3/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][7] ([i915#280]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb8/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb2/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk6/igt@gem_exec_whis...@basic-queues-forked.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-glk7/igt@gem_exec_whis...@basic-queues-forked.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-apl7/igt@gem_huc_c...@huc-copy.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#4270]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb2/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][14] ([i915#3002]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-apl7/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][15] ([i915#2724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-snb7/igt@gem_userptr_bl...@vma-merge.html - shard-apl: NOTRUN -> [FAIL][16] ([i915#3318]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-apl2/igt@gem_userptr_bl...@vma-merge.html * igt@gen7_exec_parse@chained-batch: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109289]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb1/igt@gen7_exec_pa...@chained-batch.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#2856]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/shard-tglb2/igt@gen9_exec_pa...@bb-start-out.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglb: NOTRUN -> [WARN][19] ([i915#2681] / [i915#2684]) [19]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Connect engine busyness stats from GuC to pmu
On Tue, Oct 19, 2021 at 09:32:07AM +0100, Tvrtko Ursulin wrote: On 18/10/2021 19:35, Umesh Nerlige Ramappa wrote: On Mon, Oct 18, 2021 at 08:58:01AM +0100, Tvrtko Ursulin wrote: On 16/10/2021 00:47, Umesh Nerlige Ramappa wrote: With GuC handling scheduling, i915 is not aware of the time that a context is scheduled in and out of the engine. Since i915 pmu relies on this info to provide engine busyness to the user, GuC shares this info with i915 for all engines using shared memory. For each engine, this info contains: - total busyness: total time that the context was running (total) - id: id of the running context (id) - start timestamp: timestamp when the context started running (start) At the time (now) of sampling the engine busyness, if the id is valid (!= ~0), and start is non-zero, then the context is considered to be active and the engine busyness is calculated using the below equation engine busyness = total + (now - start) All times are obtained from the gt clock base. For inactive contexts, engine busyness is just equal to the total. The start and total values provided by GuC are 32 bits and wrap around in a few minutes. Since perf pmu provides busyness as 64 bit monotonically increasing values, there is a need for this implementation to account for overflows and extend the time to 64 bits before returning busyness to the user. In order to do that, a worker runs periodically at frequency = 1/8th the time it takes for the timestamp to wrap. As an example, that would be once in 27 seconds for a gt clock frequency of 19.2 MHz. Note: There might be an overaccounting of busyness due to the fact that GuC may be updating the total and start values while kmd is reading them. (i.e kmd may read the updated total and the stale start). In such a case, user may see higher busyness value followed by smaller ones which would eventually catch up to the higher value. v2: (Tvrtko) - Include details in commit message - Move intel engine busyness function into execlist code - Use union inside engine->stats - Use natural type for ping delay jiffies - Drop active_work condition checks - Use for_each_engine if iterating all engines - Drop seq locking, use spinlock at guc level to update engine stats - Document worker specific details v3: (Tvrtko/Umesh) - Demarcate guc and execlist stat objects with comments - Document known over-accounting issue in commit - Provide a consistent view of guc state - Add hooks to gt park/unpark for guc busyness - Stop/start worker in gt park/unpark path - Drop inline - Move spinlock and worker inits to guc initialization - Drop helpers that are called only once v4: (Tvrtko/Matt/Umesh) - Drop addressed opens from commit message - Get runtime pm in ping, remove from the park path - Use cancel_delayed_work_sync in disable_submission path - Update stats during reset prepare - Skip ping if reset in progress - Explicitly name execlists and guc stats objects - Since disable_submission is called from many places, move resetting stats to intel_guc_submission_reset_prepare v5: (Tvrtko) - Add a trylock helper that does not sleep and synchronize PMU event callbacks and worker with gt reset v6: (CI BAT failures) - DUTs using execlist submission failed to boot since __gt_unpark is called during i915 load. This ends up calling the guc busyness unpark hook and results in kiskstarting an uninitialized worker. Let park/unpark hooks check if guc submission has been initialized. - drop cant_sleep() from trylock hepler since rcu_read_lock takes care of that. v7: (CI) Fix igt@i915_selftest@live@gt_engines - For guc mode of submission the engine busyness is derived from gt time domain. Use gt time elapsed as reference in the selftest. - Increase busyness calculation to 10ms duration to ensure batch runs longer and falls within the busyness tolerances in selftest. [snip] diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 75569666105d..24358bef6691 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -234,6 +234,7 @@ static int live_engine_busy_stats(void *arg) struct i915_request *rq; ktime_t de, dt; ktime_t t[2]; + u32 gt_stamp; if (!intel_engine_supports_stats(engine)) continue; @@ -251,10 +252,16 @@ static int live_engine_busy_stats(void *arg) ENGINE_TRACE(engine, "measuring idle time\n"); preempt_disable(); de = intel_engine_get_busy_time(engine, [0]); - udelay(100); + gt_stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP); + udelay(1); de = ktime_sub(intel_engine_get_busy_time(engine, [1]), de); + gt_stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP) - gt_stamp; preempt_enable(); - dt = ktime_sub(t[1], t[0]); + + dt = intel_engine_uses_guc(engine) ? +
[Intel-gfx] ✗ Fi.CI.IGT: failure for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5)
== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5) URL : https://patchwork.freedesktop.org/series/95880/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21384_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21384_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21384_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21384_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole@pipe-b-planes: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb3/igt@kms_plane@plane-position-h...@pipe-b-planes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb8/igt@kms_plane@plane-position-h...@pipe-b-planes.html Known issues Here are the changes found in Patchwork_21384_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-snb2/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-apl6/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@engines: - shard-tglb: NOTRUN -> [SKIP][6] ([i915#280]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb2/igt@gem_ctx_s...@engines.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2842]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb2/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb1/igt@gem_huc_c...@huc-copy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-apl6/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-kbl4/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-tglb2/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][21] ([i915#2724]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/shard-snb2/igt@gem_userptr_bl...@vma-merge.html -
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF
== Series Details == Series: series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF URL : https://patchwork.freedesktop.org/series/96039/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21386 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/index.html Known issues Here are the changes found in Patchwork_21386 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#4103]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@c-dp1: - fi-cfl-8109u: [PASS][11] -> [FAIL][12] ([i915#4165]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][14] -> [DMESG-WARN][15] ([i915#295]) +18 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][18] ([i915#4269]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21386/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][20] ([i915#3363]) -> [FAIL][21] ([i915#3363] / [i915#4312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [21]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF
== Series Details == Series: series starting with [1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF URL : https://patchwork.freedesktop.org/series/96039/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add struct to hold IP version
== Series Details == Series: series starting with [1/3] drm/i915: Add struct to hold IP version URL : https://patchwork.freedesktop.org/series/96038/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21385 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/index.html Known issues Here are the changes found in Patchwork_21385 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([i915#1372]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][18] ([i915#3363]) -> [FAIL][19] ([i915#3363] / [i915#4312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21385/fi-icl-u2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1372]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Add struct to hold IP version
== Series Details == Series: series starting with [1/3] drm/i915: Add struct to hold IP version URL : https://patchwork.freedesktop.org/series/96038/ State : warning == Summary == $ dim checkpatch origin/drm-tip 41a0609f8b33 drm/i915: Add struct to hold IP version -:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #44: FILE: drivers/gpu/drm/i915/i915_drv.h:1331: +#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics.ver, \ + INTEL_INFO(i915)->graphics.rel) -:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #53: FILE: drivers/gpu/drm/i915/i915_drv.h:1337: +#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.arch, \ + INTEL_INFO(i915)->media.rel) total: 0 errors, 0 warnings, 2 checks, 139 lines checked bd6fdf51759f drm/i915: Track media IP stepping separated from GT -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #34: FILE: drivers/gpu/drm/i915/i915_drv.h:1362: +#define IS_MEDIA_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ +INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) total: 0 errors, 0 warnings, 1 checks, 133 lines checked 92310e925ccb drm/i915: Rename GT_STEP to GRAPHICS_STEP -:206: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #206: FILE: drivers/gpu/drm/i915/i915_drv.h:1358: +#define IS_GRAPHICS_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ +INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) -:217: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #217: FILE: drivers/gpu/drm/i915/i915_drv.h:1538: +#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) -:221: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #221: FILE: drivers/gpu/drm/i915/i915_drv.h:1540: +#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \ + (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until)) -:228: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #228: FILE: drivers/gpu/drm/i915/i915_drv.h:1545: +#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ + (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) -:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #238: FILE: drivers/gpu/drm/i915/i915_drv.h:1554: +#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ +IS_GRAPHICS_STEP(__i915, since, until)) -:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #244: FILE: drivers/gpu/drm/i915/i915_drv.h:1558: +#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ +IS_GRAPHICS_STEP(__i915, since, until)) -:254: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #254: FILE: drivers/gpu/drm/i915/i915_drv.h:1565: +#define IS_DG1_GRAPHICS_STEP(p, since, until) \ + (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until)) -:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #264: FILE: drivers/gpu/drm/i915/i915_drv.h:1574: +#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ +IS_GRAPHICS_STEP(__i915, since, until)) -:274: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #274: FILE: drivers/gpu/drm/i915/i915_drv.h:1582: +#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ +IS_GRAPHICS_STEP(__i915, since, until)) -:281: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #281: FILE: drivers/gpu/drm/i915/i915_drv.h:1586: +#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ + (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) -:291: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #291: FILE: drivers/gpu/drm/i915/i915_drv.h:1603: +#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ +IS_GRAPHICS_STEP(__i915, since, until)) total: 0 errors, 0 warnings, 11 checks, 309 lines checked
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
== Series Details == Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name URL : https://patchwork.freedesktop.org/series/96017/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21383_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21383_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21383_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21383_full: ### IGT changes ### Possible regressions * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-tglb: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_flip_scaled_...@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html Known issues Here are the changes found in Patchwork_21383_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#280]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb2/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][19] ([i915#2724]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) [20]:
[Intel-gfx] [PATCH 2/2] drm/i915/display: Add warn_on in intel_psr_pause()
Right now the only user of psr_pause/resume is intel_cdclk but
additional users will be added in the future and we may need
do reference counting for PSR pause and resume, for now only adding a
warn_on so this cases do not go unnoticed.
Cc: Mika Kahola
Cc: Jouni Hogander
Cc: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a205fd5023bb..49c2dfbd40554 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1346,6 +1346,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
*/
void intel_psr_pause(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_psr *psr = _dp->psr;
if (!CAN_PSR(intel_dp))
@@ -1358,6 +1359,9 @@ void intel_psr_pause(struct intel_dp *intel_dp)
return;
}
+ /* If we ever hit this, we will need to add refcount to pause/resume */
+ drm_WARN_ON(_priv->drm, psr->paused);
+
intel_psr_exit(intel_dp);
intel_psr_wait_exit_locked(intel_dp);
psr->paused = true;
--
2.33.1
[Intel-gfx] [PATCH 1/2] drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF
This power domain to disable DC states will be used in places outside
of DPLL, so making the name more generic.
Cc: Radhakrishna Sripada
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index d88da0d0f05ac..6637760d24e0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -155,8 +155,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "MODESET";
case POWER_DOMAIN_GT_IRQ:
return "GT_IRQ";
- case POWER_DOMAIN_DPLL_DC_OFF:
- return "DPLL_DC_OFF";
+ case POWER_DOMAIN_DC_OFF:
+ return "DC_OFF";
case POWER_DOMAIN_TC_COLD_OFF:
return "TC_COLD_OFF";
default:
@@ -2803,7 +2803,7 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
ICL_PW_2_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) | \
+ BIT_ULL(POWER_DOMAIN_DC_OFF) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define ICL_DDI_IO_A_POWER_DOMAINS ( \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 0612e4b6e3c81..d54b7574ed373 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -117,7 +117,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
- POWER_DOMAIN_DPLL_DC_OFF,
+ POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_TC_COLD_OFF,
POWER_DOMAIN_INIT,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ca69b67bbc231..fc8fda77483ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3741,7 +3741,7 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
* domain.
*/
pll->wakeref = intel_display_power_get(dev_priv,
-
POWER_DOMAIN_DPLL_DC_OFF);
+ POWER_DOMAIN_DC_OFF);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -3848,7 +3848,7 @@ static void combo_pll_disable(struct drm_i915_private
*dev_priv,
if (IS_JSL_EHL(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4)
- intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
pll->wakeref);
}
@@ -4232,7 +4232,7 @@ static void readout_dpll_hw_state(struct drm_i915_private
*i915,
if (IS_JSL_EHL(i915) && pll->on &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
pll->wakeref = intel_display_power_get(i915,
-
POWER_DOMAIN_DPLL_DC_OFF);
+ POWER_DOMAIN_DC_OFF);
}
pll->state.pipe_mask = 0;
--
2.33.1
[Intel-gfx] [PATCH 1/3] drm/i915: Add struct to hold IP version
Adding a structure to standardize access to IP versioning as future
platforms will have this information populated at runtime.
The constant platform display version is not using this new struct but
the runtime variant will definitely use it.
Cc: Radhakrishna Sripada
Cc: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 12 ++--
drivers/gpu/drm/i915/i915_pci.c | 18 +-
drivers/gpu/drm/i915/intel_device_info.c | 19 ---
drivers/gpu/drm/i915/intel_device_info.h | 12
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
6 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1e5b75ae99329..bdf85d202c55c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -808,7 +808,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
return PTR_ERR(i915);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
+ if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
i915->drm.driver_features &= ~DRIVER_ATOMIC;
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f4..26b6e2b8bb5e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1327,15 +1327,15 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
-#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
-#define GRAPHICS_VER_FULL(i915)
IP_VER(INTEL_INFO(i915)->graphics_ver, \
- INTEL_INFO(i915)->graphics_rel)
+#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver)
+#define GRAPHICS_VER_FULL(i915)
IP_VER(INTEL_INFO(i915)->graphics.ver, \
+ INTEL_INFO(i915)->graphics.rel)
#define IS_GRAPHICS_VER(i915, from, until) \
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
-#define MEDIA_VER(i915)(INTEL_INFO(i915)->media_ver)
-#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media_ver, \
- INTEL_INFO(i915)->media_rel)
+#define MEDIA_VER(i915)(INTEL_INFO(i915)->media.ver)
+#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.arch, \
+ INTEL_INFO(i915)->media.rel)
#define IS_MEDIA_VER(i915, from, until) \
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d3..5e6795853dc31 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -32,8 +32,8 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .graphics_ver = (x), \
- .media_ver = (x), \
+ .graphics.ver = (x), \
+ .media.ver = (x), \
.display.ver = (x)
#define I845_PIPE_OFFSETS \
@@ -899,7 +899,7 @@ static const struct intel_device_info rkl_info = {
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
DGFX_FEATURES,
- .graphics_rel = 10,
+ .graphics.rel = 10,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
@@ -986,8 +986,8 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .graphics_ver = 12, \
- .graphics_rel = 50, \
+ .graphics.ver = 12, \
+ .graphics.rel = 50, \
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
@@ -1005,8 +1005,8 @@ static const struct intel_device_info adl_p_info = {
.ppgtt_type = INTEL_PPGTT_FULL
#define XE_HPM_FEATURES \
- .media_ver = 12, \
- .media_rel = 50
+ .media.ver = 12, \
+ .media.rel = 50
__maybe_unused
static const struct intel_device_info xehpsdv_info = {
@@ -1030,8 +1030,8 @@ static const struct intel_device_info dg2_info = {
XE_HPM_FEATURES,
XE_LPD_FEATURES,
DGFX_FEATURES,
- .graphics_rel = 55,
- .media_rel = 55,
+ .graphics.rel = 55,
+ .media.rel = 55,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 305facedd2841..6e6b317bc33ce 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++
[Intel-gfx] [PATCH 3/3] drm/i915: Rename GT_STEP to GRAPHICS_STEP
As now graphics and media can have different steppings this patch is
renaming all _GT_STEP macros to _GRAPHICS_STEP.
Future platforms will properly choose between _MEDIA_STEP and
_GRAPHICS_STEP for each new workaround.
Cc: Matt Atwood
Cc: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 +++---
drivers/gpu/drm/i915/i915_drv.h | 46 ++---
drivers/gpu/drm/i915/intel_pm.c | 6 +--
drivers/gpu/drm/i915/intel_step.c | 12 +++---
drivers/gpu/drm/i915/intel_step.h | 2 +-
8 files changed, 51 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 461844dffd7ed..e320610dd0b81 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
- if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0))
+ if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 15f9ada28a7ab..9c253ba593c65 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -424,7 +424,7 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
table->unused_entries_index = I915_MOCS_PTE;
if (IS_DG2(i915)) {
- if (IS_DG2_GT_STEP(i915, G10, STEP_A0, STEP_B0)) {
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
table->table = dg2_mocs_table_g10_ax;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index afb35d2e5c734..aec838ecb2ef2 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -158,7 +158,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
u64 *start, u32 *size)
{
- if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_C0))
+ if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
return false;
*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e1f3625308891..37bec83e4750c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -482,7 +482,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs
*engine,
gen9_ctx_workarounds_init(engine, wal);
/* WaToEnableHwFixForPushConstHWBug:kbl */
- if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER))
+ if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
@@ -916,7 +916,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaInPlaceDecompressionHang:skl */
- if (IS_SKL_GT_STEP(gt->i915, STEP_A0, STEP_H0))
+ if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
@@ -928,7 +928,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
gen9_gt_workarounds_init(gt, wal);
/* WaDisableDynamicCreditSharing:kbl */
- if (IS_KBL_GT_STEP(gt->i915, 0, STEP_C0))
+ if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -1136,7 +1136,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
- IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0))
+ IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1190,19 +1190,19 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
gen12_gt_workarounds_init(gt, wal);
/* Wa_1409420604:tgl */
- if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0))
+
[Intel-gfx] [PATCH 2/3] drm/i915: Track media IP stepping separated from GT
Graphics and media IPs can have different stepping so a new field is
needed in intel_step_info.
The next patch will take care of rename gt_step to graphics_step.
Cc: Radhakrishna Sripada
Cc: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++
drivers/gpu/drm/i915/intel_step.c | 69 ---
drivers/gpu/drm/i915/intel_step.h | 1 +
3 files changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26b6e2b8bb5e8..9559cda7382f2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1349,6 +1349,7 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
+#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
#define IS_DISPLAY_STEP(__i915, since, until) \
(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
@@ -1358,6 +1359,10 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until))
+#define IS_MEDIA_STEP(__i915, since, until) \
+ (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
+INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) <
(until))
+
static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info *info,
enum intel_platform p)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 6cf9676313959..1cf8f0bb0b5e5 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -23,7 +23,8 @@
* use a macro to define these to make it easier to identify the platforms
* where the two steppings can deviate.
*/
-#define COMMON_STEP(x) .gt_step = STEP_##x, .display_step = STEP_##x
+#define COMMON_STEP(x) .gt_step = STEP_##x, .display_step = STEP_##x,
.media_step = STEP_##x
+#define COMMON_GT_MEDIA_STEP(x) .gt_step = STEP_##x, .media_step = STEP_##x
static const struct intel_step_info skl_revids[] = {
[0x6] = { COMMON_STEP(G0) },
@@ -33,13 +34,13 @@ static const struct intel_step_info skl_revids[] = {
};
static const struct intel_step_info kbl_revids[] = {
- [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
- [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
- [3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
- [4] = { .gt_step = STEP_F0, .display_step = STEP_C0 },
- [5] = { .gt_step = STEP_C0, .display_step = STEP_B1 },
- [6] = { .gt_step = STEP_D1, .display_step = STEP_B1 },
- [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
+ [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
+ [2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
+ [3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 },
+ [4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 },
+ [5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 },
+ [6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 },
+ [7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 },
};
static const struct intel_step_info bxt_revids[] = {
@@ -63,16 +64,16 @@ static const struct intel_step_info jsl_ehl_revids[] = {
};
static const struct intel_step_info tgl_uy_revids[] = {
- [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
- [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
- [3] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
+ [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
+ [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
+ [2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
+ [3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
static const struct intel_step_info tgl_revids[] = {
- [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
- [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
+ [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
+ [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 },
};
static const struct intel_step_info rkl_revids[] = {
@@ -87,38 +88,38 @@ static const struct intel_step_info dg1_revids[] = {
};
static const struct intel_step_info adls_revids[] = {
- [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
- [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
-
[Intel-gfx] ✓ Fi.CI.BAT: success for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5)
== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5) URL : https://patchwork.freedesktop.org/series/95880/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21384 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/index.html Known issues Here are the changes found in Patchwork_21384 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#4103]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#1072]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#3301]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][14] ([i915#3363]) -> [FAIL][15] ([i915#3363] / [i915#4312]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21384/fi-icl-u2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Participating hosts (36 -> 35) -- Additional (2): fi-tgl-1115g4 fi-ilk-650 Missing(3): fi-kbl-soraka fi-bsw-cyan bat-dg1-6 Build changes - * Linux: CI_DRM_10762 -> Patchwork_21384 CI-20190529: 20190529
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable MIPI DSI video mode on ADLP (rev2)
== Series Details == Series: Enable MIPI DSI video mode on ADLP (rev2) URL : https://patchwork.freedesktop.org/series/95928/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21382_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21382_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#280]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb2/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-skl9/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2842]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-kbl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb1/igt@gem_huc_c...@huc-copy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl8/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][16] ([i915#2724]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-snb7/igt@gem_userptr_bl...@vma-merge.html - shard-apl: NOTRUN -> [FAIL][17] ([i915#3318]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl3/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#2856]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@gen9_exec_pa...@bb-start-out.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglb: NOTRUN -> [WARN][20] ([i915#2681] / [i915#2684]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb1/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@i915_pm_rpm@system-suspend: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#2411] / [i915#456]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb3/igt@i915_pm_...@system-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/shard-tglb7/igt@i915_pm_...@system-suspend.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#2521]) [23]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5)
== Series Details == Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev5) URL : https://patchwork.freedesktop.org/series/95880/ State : warning == Summary == $ dim checkpatch origin/drm-tip 34716383fea8 gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info 1180ca83baa8 drm/vc4: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 6467b8c22e2e drm/radeon: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: drm_get_edid() - which internally calls drm_connector_update_edid_property(). total: 0 errors, 1 warnings, 0 checks, 111 lines checked 4f4be9d8da74 drm/tegra: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 4e2489b2ac97 drm/gma500: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi d343d69908cd drm/exynos: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi a43989d686a3 drm/msm: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 045c9182b766 drm/sun4i: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 199244a0b398 drm/sti: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 7c1d51956f94 drm/rockchip: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 5f65b0c735df drm/bridge: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 69ae884f14bd drm/nouveau: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi 415fad5a7f91 drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi
[Intel-gfx] ✓ Fi.CI.IGT: success for remove duplicate include in mock_region.c
== Series Details == Series: remove duplicate include in mock_region.c URL : https://patchwork.freedesktop.org/series/96009/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21381_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21381_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-apl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][3] ([i915#280]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb8/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-skl3/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][12] ([i915#2658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-apl3/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-kbl1/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb1/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][15] ([i915#3318]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-apl2/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#2856]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb1/igt@gen9_exec_pa...@bb-start-out.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglb: NOTRUN -> [WARN][17] ([i915#2681] / [i915#2684]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb1/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@i915_pm_rpm@system-suspend: - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#2411] / [i915#456]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb3/igt@i915_pm_...@system-suspend.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-tglb7/igt@i915_pm_...@system-suspend.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-kbl6/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][21] ([i915#3743]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/shard-skl2/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][22]
Re: [Intel-gfx] [PATCH v3 13/13] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi
drm_get_edid() internally calls to drm_connector_update_edid_property()
and then drm_add_display_info(), which parses the EDID.
This happens in the function intel_hdmi_set_edid() and
intel_sdvo_tmds_sink_detect() (via intel_sdvo_get_edid()).
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
This is a TODO task in Documentation/gpu/todo.rst
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b04685bb6439..008e5b0ba408 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
to_intel_connector(connector)->detect_edid = edid;
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
- intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+ intel_hdmi->has_hdmi_sink = connector->display_info.is_hdmi;
connected = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6cb27599ea03..b4065e4df644 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector
*connector)
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
status = connector_status_connected;
if (intel_sdvo_connector->is_hdmi) {
- intel_sdvo->has_hdmi_monitor =
drm_detect_hdmi_monitor(edid);
intel_sdvo->has_hdmi_audio =
drm_detect_monitor_audio(edid);
+ intel_sdvo->has_hdmi_monitor =
+
connector->display_info.is_hdmi;
}
} else
status = connector_status_disconnected;
--
2.33.0
Re: [Intel-gfx] [PATCH v3 01/13] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info
According to the documentation, drm_add_edid_modes
"... Also fills out the _display_info structure and ELD in @connector
with any information which can be derived from the edid."
drm_add_edid_modes accepts a struct edid *edid parameter which may have a
value or may be null. When it is not null, connector->display_info and
connector->eld are updated according to the edid. When edid=NULL, only
connector->eld is reset. Reset connector->display_info to be consistent
and accurate.
Since drm_edid_is_valid() considers NULL as an invalid EDID, simplify the
code to avoid duplicating code in the case of NULL/error.
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/drm_edid.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..a019a26ede7a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5356,14 +5356,14 @@ int drm_add_edid_modes(struct drm_connector *connector,
struct edid *edid)
int num_modes = 0;
u32 quirks;
- if (edid == NULL) {
- clear_eld(connector);
- return 0;
- }
if (!drm_edid_is_valid(edid)) {
+ /* edid == NULL or invalid here */
clear_eld(connector);
- drm_warn(connector->dev, "%s: EDID invalid.\n",
-connector->name);
+ drm_reset_display_info(connector);
+ if (edid)
+ drm_warn(connector->dev,
+"[CONNECTOR:%d:%s] EDID invalid.\n",
+connector->base.id, connector->name);
return 0;
}
--
2.33.0
Re: [Intel-gfx] [PATCH v2 01/13] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info
On Tue, Oct 19, 2021 at 09:35:08PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 16, 2021 at 08:42:14PM +0200, Claudio Suarez wrote:
> > According to the documentation, drm_add_edid_modes
> > "... Also fills out the _display_info structure and ELD in @connector
> > with any information which can be derived from the edid."
> >
> > drm_add_edid_modes accepts a struct edid *edid parameter which may have a
> > value or may be null. When it is not null, connector->display_info and
> > connector->eld are updated according to the edid. When edid=NULL, only
> > connector->eld is reset. Reset connector->display_info to be consistent
> > and accurate.
> >
> > Signed-off-by: Claudio Suarez
> > ---
> > drivers/gpu/drm/drm_edid.c | 11 +--
> > 1 file changed, 5 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 6325877c5fd6..c643db17782c 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -5356,14 +5356,13 @@ int drm_add_edid_modes(struct drm_connector
> > *connector, struct edid *edid)
> > int num_modes = 0;
> > u32 quirks;
> >
> > - if (edid == NULL) {
> > - clear_eld(connector);
> > - return 0;
> > - }
> > if (!drm_edid_is_valid(edid)) {
>
> OK, so drm_edid_is_valid() will happily accept NULL and considers
> it invalid. You may want to mention that explicitly in the commit
> message.
Thank you for your comments, I appreciate :)
I'm sending new mails with the new commit messages.
> > + /* edid == NULL or invalid here */
> > clear_eld(connector);
> > - drm_warn(connector->dev, "%s: EDID invalid.\n",
> > -connector->name);
> > + drm_reset_display_info(connector);
> > + if (edid)
> > + drm_warn(connector->dev, "%s: EDID invalid.\n",
> > +connector->name);
>
> Could you respin this to use the standard [CONNECTOR:%d:%s] form
> while at it? Or I guess a patch to mass convert the whole drm_edid.c
> might be another option.
Good point.
I like the idea of a new patch. I'll start working on it. I can change
this drm_warn here to avoid merge conflicts.
> Patch looks good.
> Reviewed-by: Ville Syrjälä
Thanks!
BR
Claudio Suarez.
[Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/bios: gracefully disable dual eDP for now"
== Series Details == Series: Revert "drm/i915/bios: gracefully disable dual eDP for now" URL : https://patchwork.freedesktop.org/series/96006/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21379_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21379_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21379_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21379_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@drm-resources-equal: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb6/igt@i915_pm_...@drm-resources-equal.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-iclb4/igt@i915_pm_...@drm-resources-equal.html Known issues Here are the changes found in Patchwork_21379_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#280]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-tglb1/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-skl8/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][7] ([i915#2842]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-tglb5/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +4 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_reloc@basic-gtt-wc: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#62]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-apl1/igt@gem_exec_re...@basic-gtt-wc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-apl6/igt@gem_exec_re...@basic-gtt-wc.html - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl4/igt@gem_exec_re...@basic-gtt-wc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-kbl6/igt@gem_exec_re...@basic-gtt-wc.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-apl2/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-apl3/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/shard-kbl2/igt@gem_pr...@exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][22] ([i915#4270]) [22]:
Re: [Intel-gfx] [PATCH 12/28] drm/amdgpu: use new iterator in amdgpu_ttm_bo_eviction_valuable
Am 2021-10-19 um 7:36 a.m. schrieb Christian König:
> Am 13.10.21 um 16:07 schrieb Daniel Vetter:
>> On Tue, Oct 05, 2021 at 01:37:26PM +0200, Christian König wrote:
>>> Simplifying the code a bit.
>>>
>>> Signed-off-by: Christian König
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 --
>>> 1 file changed, 4 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> index e8d70b6e6737..722e3c9e8882 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> @@ -1345,10 +1345,9 @@ static bool
>>> amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
>>> const struct ttm_place *place)
>>> {
>>> unsigned long num_pages = bo->resource->num_pages;
>>> + struct dma_resv_iter resv_cursor;
>>> struct amdgpu_res_cursor cursor;
>>> - struct dma_resv_list *flist;
>>> struct dma_fence *f;
>>> - int i;
>>> /* Swapout? */
>>> if (bo->resource->mem_type == TTM_PL_SYSTEM)
>>> @@ -1362,14 +1361,9 @@ static bool
>>> amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
>>> * If true, then return false as any KFD process needs all its
>>> BOs to
>>> * be resident to run successfully
>>> */
>>> - flist = dma_resv_shared_list(bo->base.resv);
>>> - if (flist) {
>>> - for (i = 0; i < flist->shared_count; ++i) {
>>> - f = rcu_dereference_protected(flist->shared[i],
>>> - dma_resv_held(bo->base.resv));
>>> - if (amdkfd_fence_check_mm(f, current->mm))
>>> - return false;
>>> - }
>>> + dma_resv_for_each_fence(_cursor, bo->base.resv, true, f) {
>> ^false?
>>
>> At least I'm not seeing the code look at the exclusive fence here.
>
> Yes, but that's correct. We need to look at all potential fences.
amdkfd_fence_check_mm is only meaningful for KFD eviction fences, and
they are always added as shared fences. I think setting all_fences =
false would return only the exclusive fence.
Regards,
Felix
>
> It's a design problem in KFD if you ask me, but that is a completely
> different topic.
>
> Christian.
>
>> -Daniel
>>
>>> + if (amdkfd_fence_check_mm(f, current->mm))
>>> + return false;
>>> }
>>> switch (bo->resource->mem_type) {
>>> --
>>> 2.25.1
>>>
>
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
== Series Details == Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name URL : https://patchwork.freedesktop.org/series/96017/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21383 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/index.html Known issues Here are the changes found in Patchwork_21383 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: NOTRUN -> [FAIL][4] ([i915#1888]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#109285]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#3301]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][15] ([i915#4269]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][17] ([i915#3363]) -> [FAIL][18] ([i915#3363] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-icl-u2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2575]:
Re: [Intel-gfx] [PATCH 05/20] drm/i915/hdmi: Extract intel_hdmi_output_format()
On Fri, 15 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reorganize the HDMI 4:2:0 handling a bit by introducing
> intel_hdmi_output_format(). We already have the DP counterpart
> and I want to unify the 4:2:0 handling across both a bit.
>
> Signed-off-by: Ville Syrjälä
Patches 1-5,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 35 ++-
> 1 file changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 18e7ef125827..7e6af959bf83 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2157,34 +2157,43 @@ static bool intel_hdmi_has_audio(struct intel_encoder
> *encoder,
> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> }
>
> +static enum intel_output_format
> +intel_hdmi_output_format(struct intel_connector *connector,
> + bool ycbcr_420_output)
> +{
> + if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
> + return INTEL_OUTPUT_FORMAT_YCBCR420;
> + else
> + return INTEL_OUTPUT_FORMAT_RGB;
> +}
> +
> static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> const struct drm_connector_state
> *conn_state)
> {
> - struct drm_connector *connector = conn_state->connector;
> - struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode =
> _state->hw.adjusted_mode;
> + const struct drm_display_info *info = >base.display_info;
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
> int ret;
> - bool ycbcr_420_only;
>
> - ycbcr_420_only = drm_mode_is_420_only(>display_info,
> adjusted_mode);
> - if (connector->ycbcr_420_allowed && ycbcr_420_only) {
> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> - } else {
> - if (!connector->ycbcr_420_allowed && ycbcr_420_only)
> - drm_dbg_kms(>drm,
> - "YCbCr 4:2:0 mode but YCbCr 4:2:0 output
> not possible. Falling back to RGB.\n");
> + crtc_state->output_format = intel_hdmi_output_format(connector,
> ycbcr_420_only);
> +
> + if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
> + drm_dbg_kms(>drm,
> + "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not
> possible. Falling back to RGB.\n");
> crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
> }
>
> ret = intel_hdmi_compute_clock(encoder, crtc_state);
> if (ret) {
> if (intel_hdmi_is_ycbcr420(crtc_state) ||
> - !connector->ycbcr_420_allowed ||
> - !drm_mode_is_420_also(>display_info,
> adjusted_mode))
> + !connector->base.ycbcr_420_allowed ||
> + !drm_mode_is_420_also(info, adjusted_mode))
> return ret;
>
> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + crtc_state->output_format = intel_hdmi_output_format(connector,
> true);
> ret = intel_hdmi_compute_clock(encoder, crtc_state);
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 6/6] drm/i915/dp: Sanitize link common rate array lookups
On Mon, 18 Oct 2021, Imre Deak wrote:
> Add an assert that lookups from the intel_dp->common_rates[] array
> are always valid.
The one thought I had here was that if we're adding helper functions for
accessing common rates, they should probably be of the form "this is the
rate I have now, give me a slower rate" instead of making the index part
of the interface. The index doesn't really mean anything, and if we want
to avoid overflows, it should be hidden from the interfaces.
But again, can be follow-up.
BR,
Jani.
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 33 -
> 1 file changed, 16 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f8082eb8e7263..3869d454c10f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -267,10 +267,19 @@ static int intel_dp_common_len_rate_limit(const struct
> intel_dp *intel_dp,
> intel_dp->num_common_rates, max_rate);
> }
>
> +static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
> +{
> + if (drm_WARN_ON(_to_i915(intel_dp)->drm,
> + index < 0 || index >= intel_dp->num_common_rates))
> + return 162000;
> +
> + return intel_dp->common_rates[index];
> +}
> +
> /* Theoretical max between source and sink */
> static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> {
> - return intel_dp->common_rates[intel_dp->num_common_rates - 1];
> + return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> }
>
> /* Theoretical max between source and sink */
> @@ -610,13 +619,13 @@ int intel_dp_get_link_train_fallback_values(struct
> intel_dp *intel_dp,
> if (index > 0) {
> if (intel_dp_is_edp(intel_dp) &&
> !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> -
> intel_dp->common_rates[index - 1],
> +
> intel_dp_common_rate(intel_dp, index - 1),
> lane_count)) {
> drm_dbg_kms(>drm,
> "Retrying Link training for eDP with same
> parameters\n");
> return 0;
> }
> - intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
> + intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
> - 1);
> intel_dp->max_link_lane_count = lane_count;
> } else if (lane_count > 1) {
> if (intel_dp_is_edp(intel_dp) &&
> @@ -1056,14 +1065,11 @@ static void intel_dp_print_rates(struct intel_dp
> *intel_dp)
> int
> intel_dp_max_link_rate(struct intel_dp *intel_dp)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> int len;
>
> len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
> - if (drm_WARN_ON(>drm, len <= 0))
> - return 162000;
>
> - return intel_dp->common_rates[len - 1];
> + return intel_dp_common_rate(intel_dp, len - 1);
> }
>
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> @@ -1260,7 +1266,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> output_bpp);
>
> for (i = 0; i < intel_dp->num_common_rates; i++) {
> - link_rate = intel_dp->common_rates[i];
> + link_rate = intel_dp_common_rate(intel_dp, i);
> if (link_rate < limits->min_rate ||
> link_rate > limits->max_rate)
> continue;
> @@ -1508,17 +1514,10 @@ intel_dp_compute_link_config(struct intel_encoder
> *encoder,
> _config->hw.adjusted_mode;
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct link_config_limits limits;
> - int common_len;
> int ret;
>
> - common_len = intel_dp_common_len_rate_limit(intel_dp,
> - intel_dp->max_link_rate);
> -
> - /* No common link rates between source and sink */
> - drm_WARN_ON(encoder->base.dev, common_len <= 0);
> -
> - limits.min_rate = intel_dp->common_rates[0];
> - limits.max_rate = intel_dp->common_rates[common_len - 1];
> + limits.min_rate = intel_dp_common_rate(intel_dp, 0);
> + limits.max_rate = intel_dp_max_link_rate(intel_dp);
>
> limits.min_lane_count = 1;
> limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
On Tue, 19 Oct 2021, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 10:39:08AM +0300, Imre Deak wrote:
>> On Tue, Oct 19, 2021 at 10:37:33AM +0300, Jani Nikula wrote:
>> > On Tue, 19 Oct 2021, Imre Deak wrote:
>> > > On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote:
>> > >> On Mon, 18 Oct 2021, Imre Deak wrote:
>> > >> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until
>> > >> > the
>> > >> > DPCD capabilities are successfully read from the sink. During this
>> > >> > time
>> > >> > intel_dp->num_common_rates is 0 which can lead to a
>> > >> >
>> > >> > intel_dp->common_rates[-1](*)
>> > >> >
>> > >> > access, which is an undefined behaviour, in the following cases:
>> > >> >
>> > >> > - In intel_dp_sync_state(), if the encoder is enabled without a sink
>> > >> > connected to the encoder's connector (BIOS enabled a monitor, but
>> > >> > the
>> > >> > user unplugged the monitor until the driver loaded).
>> > >> > - In intel_dp_sync_state() if the encoder is enabled with a sink
>> > >> > connected, but for some reason the DPCD read has failed.
>> > >> > - In intel_dp_compute_link_config() if modesetting a connector without
>> > >> > a sink connected on it.
>> > >> > - In intel_dp_compute_link_config() if modesetting a connector with a
>> > >> > a sink connected on it, but before probing the connector first.
>> > >> >
>> > >> > To avoid the (*) access in all the above cases, make sure that the
>> > >> > sink
>> > >> > rate table - and hence the common rate table - is always valid, by
>> > >> > setting a default minimum sink rate when registering the connector
>> > >> > before anything could use it.
>> > >> >
>> > >> > I also considered setting all the DP link rates by default, so that
>> > >> > modesetting with higher resolution modes also succeeds in the last two
>> > >> > cases above. However in case a sink is not connected that would stop
>> > >> > working after the first modeset, due to the LT fallback logic. So this
>> > >> > would need more work, beyond the scope of this fix.
>> > >> >
>> > >> > As I mentioned in the previous patch, I don't think the issue this
>> > >> > patch
>> > >> > fixes is user visible, however it is an undefined behaviour by
>> > >> > definition and triggers a BUG() in CONFIG_UBSAN builds, hence
>> > >> > CC:stable.
>> > >>
>> > >> I think the question here, and in the following patches, is whether this
>> > >> papers over potential bugs elsewhere.
>> > >>
>> > >> Would the original bug fixed by patch 1 have been detected if all the
>> > >> safeguards here had been in place? Point being, we shouldn't be doing
>> > >> any of these things before we've read the dpcd.
>> > >
>> > > Modesets are possible even without a connected sink or a read-out DPCD,
>> > > so the link parameters need to be valid even without those.
>> >
>> > Modeset on a disconnected DP? How?
>>
>> Yes, just do a modeset on it. It doesn't have to be disconnected either,
>> you can modeset a DP connector before probing it.
>
> Jani,
>
> any objections to merge patches 2-6 as well? In a summary the reasons:
>
> - Fix userspace triggerable WARNs().
> - Fix undefined behavior triggerring BUG() in UBSAN builds
> (in addition to the case the first patch fixes).
> - Validate the DP_MAX_LINK_RATE value we read from DPCD.
> - It unifies some open-coded functionality (patch 3 and 6).
I have some reservations about adding more stuff that we cache, as well
as more functions to call to reset the state... but I don't really have
concrete proposals either right now, and this makes forward progress.
Ack.
BR,
Jani.
>
>> > BR,
>> > Jani.
>> >
>> >
>> > >
>> > >> BR,
>> > >> Jani.
>> > >>
>> > >>
>> > >> >
>> > >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
>> > >> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
>> > >> > Suggested-by: Ville Syrjälä
>> > >> > Cc: Ville Syrjälä
>> > >> > Cc:
>> > >> > Signed-off-by: Imre Deak
>> > >> > ---
>> > >> > drivers/gpu/drm/i915/display/intel_dp.c | 8
>> > >> > 1 file changed, 8 insertions(+)
>> > >> >
>> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > >> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > >> > index 23de500d56b52..153ae944a354b 100644
>> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > >> > @@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct
>> > >> > intel_crtc_state *crtc_state)
>> > >> > return crtc_state->port_clock >= 100;
>> > >> > }
>> > >> >
>> > >> > +static void intel_dp_set_default_sink_rates(struct intel_dp
>> > >> > *intel_dp)
>> > >> > +{
>> > >> > + intel_dp->sink_rates[0] = 162000;
>> > >> > + intel_dp->num_sink_rates = 1;
>> > >> > +}
>> > >> > +
>> > >> > /* update sink rates from dpcd */
>> > >> > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>> > >> > {
>> > >> > @@ -5003,6 +5009,8 @@
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
== Series Details == Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name URL : https://patchwork.freedesktop.org/series/96017/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify handling of modifiers (rev11)
== Series Details == Series: drm/i915: Simplify handling of modifiers (rev11) URL : https://patchwork.freedesktop.org/series/95579/ State : success == Summary == CI Bug Log - changes from CI_DRM_10761_full -> Patchwork_21378_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21378_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-apl8/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-apl2/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_param@invalid-param-set: - shard-skl: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-skl10/igt@gem_ctx_pa...@invalid-param-set.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-skl5/igt@gem_ctx_pa...@invalid-param-set.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_ctx_sseu@invalid-sseu: - shard-tglb: NOTRUN -> [SKIP][7] ([i915#280]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb1/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-iclb7/igt@gem_exec_fair@basic-n...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-iclb5/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-apl1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb1/igt@gem_...@create-regular-context-1.html * igt@gem_userptr_blits@dmabuf-sync: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-skl9/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@invalid-mmap-offset-unsync: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb2/igt@gem_userptr_bl...@invalid-mmap-offset-unsync.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][20] ([i915#3318]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-apl8/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#456]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/shard-tglb1/igt@gem_workarou...@suspend-resume.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/shard-tglb7/igt@gem_workarou...@suspend-resume.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable MIPI DSI video mode on ADLP (rev2)
== Series Details ==
Series: Enable MIPI DSI video mode on ADLP (rev2)
URL : https://patchwork.freedesktop.org/series/95928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21382
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/index.html
Known issues
Here are the changes found in Patchwork_21382 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [PASS][4] -> [DMESG-WARN][5] ([i915#1982] /
[i915#262])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#1155])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][16] ([i915#1602] / [i915#2029] /
[i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][17] ([i915#4269]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@runner@aborted:
- fi-icl-u2: [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#3363] /
[i915#4312])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21382/fi-icl-u2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]:
Re: [Intel-gfx] [PATCH v2 13/13] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi
On Sat, Oct 16, 2021 at 08:42:26PM +0200, Claudio Suarez wrote:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi where possible.
We still need proof in the commit message that display_info
is actually populated by the time this gets called.
>
> This is a TODO task in Documentation/gpu/todo.rst
>
> Signed-off-by: Claudio Suarez
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b04685bb6439..008e5b0ba408 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
> to_intel_connector(connector)->detect_edid = edid;
> if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
> intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
> - intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
> + intel_hdmi->has_hdmi_sink = connector->display_info.is_hdmi;
>
> connected = true;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 6cb27599ea03..b4065e4df644 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector
> *connector)
> if (edid->input & DRM_EDID_INPUT_DIGITAL) {
> status = connector_status_connected;
> if (intel_sdvo_connector->is_hdmi) {
> - intel_sdvo->has_hdmi_monitor =
> drm_detect_hdmi_monitor(edid);
> intel_sdvo->has_hdmi_audio =
> drm_detect_monitor_audio(edid);
> + intel_sdvo->has_hdmi_monitor =
> +
> connector->display_info.is_hdmi;
> }
> } else
> status = connector_status_disconnected;
> --
> 2.33.0
>
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid
On Tue, Oct 19, 2021 at 10:39:08AM +0300, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 10:37:33AM +0300, Jani Nikula wrote:
> > On Tue, 19 Oct 2021, Imre Deak wrote:
> > > On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote:
> > >> On Mon, 18 Oct 2021, Imre Deak wrote:
> > >> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
> > >> > DPCD capabilities are successfully read from the sink. During this time
> > >> > intel_dp->num_common_rates is 0 which can lead to a
> > >> >
> > >> > intel_dp->common_rates[-1](*)
> > >> >
> > >> > access, which is an undefined behaviour, in the following cases:
> > >> >
> > >> > - In intel_dp_sync_state(), if the encoder is enabled without a sink
> > >> > connected to the encoder's connector (BIOS enabled a monitor, but the
> > >> > user unplugged the monitor until the driver loaded).
> > >> > - In intel_dp_sync_state() if the encoder is enabled with a sink
> > >> > connected, but for some reason the DPCD read has failed.
> > >> > - In intel_dp_compute_link_config() if modesetting a connector without
> > >> > a sink connected on it.
> > >> > - In intel_dp_compute_link_config() if modesetting a connector with a
> > >> > a sink connected on it, but before probing the connector first.
> > >> >
> > >> > To avoid the (*) access in all the above cases, make sure that the sink
> > >> > rate table - and hence the common rate table - is always valid, by
> > >> > setting a default minimum sink rate when registering the connector
> > >> > before anything could use it.
> > >> >
> > >> > I also considered setting all the DP link rates by default, so that
> > >> > modesetting with higher resolution modes also succeeds in the last two
> > >> > cases above. However in case a sink is not connected that would stop
> > >> > working after the first modeset, due to the LT fallback logic. So this
> > >> > would need more work, beyond the scope of this fix.
> > >> >
> > >> > As I mentioned in the previous patch, I don't think the issue this
> > >> > patch
> > >> > fixes is user visible, however it is an undefined behaviour by
> > >> > definition and triggers a BUG() in CONFIG_UBSAN builds, hence
> > >> > CC:stable.
> > >>
> > >> I think the question here, and in the following patches, is whether this
> > >> papers over potential bugs elsewhere.
> > >>
> > >> Would the original bug fixed by patch 1 have been detected if all the
> > >> safeguards here had been in place? Point being, we shouldn't be doing
> > >> any of these things before we've read the dpcd.
> > >
> > > Modesets are possible even without a connected sink or a read-out DPCD,
> > > so the link parameters need to be valid even without those.
> >
> > Modeset on a disconnected DP? How?
>
> Yes, just do a modeset on it. It doesn't have to be disconnected either,
> you can modeset a DP connector before probing it.
Jani,
any objections to merge patches 2-6 as well? In a summary the reasons:
- Fix userspace triggerable WARNs().
- Fix undefined behavior triggerring BUG() in UBSAN builds
(in addition to the case the first patch fixes).
- Validate the DP_MAX_LINK_RATE value we read from DPCD.
- It unifies some open-coded functionality (patch 3 and 6).
> > BR,
> > Jani.
> >
> >
> > >
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >> >
> > >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4297
> > >> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4298
> > >> > Suggested-by: Ville Syrjälä
> > >> > Cc: Ville Syrjälä
> > >> > Cc:
> > >> > Signed-off-by: Imre Deak
> > >> > ---
> > >> > drivers/gpu/drm/i915/display/intel_dp.c | 8
> > >> > 1 file changed, 8 insertions(+)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > index 23de500d56b52..153ae944a354b 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > >> > @@ -120,6 +120,12 @@ bool intel_dp_is_uhbr(const struct
> > >> > intel_crtc_state *crtc_state)
> > >> >return crtc_state->port_clock >= 100;
> > >> > }
> > >> >
> > >> > +static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
> > >> > +{
> > >> > + intel_dp->sink_rates[0] = 162000;
> > >> > + intel_dp->num_sink_rates = 1;
> > >> > +}
> > >> > +
> > >> > /* update sink rates from dpcd */
> > >> > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> > >> > {
> > >> > @@ -5003,6 +5009,8 @@ intel_dp_init_connector(struct
> > >> > intel_digital_port *dig_port,
> > >> >}
> > >> >
> > >> >intel_dp_set_source_rates(intel_dp);
> > >> > + intel_dp_set_default_sink_rates(intel_dp);
> > >> > + intel_dp_set_common_rates(intel_dp);
> > >> >
> > >> >if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > >> >intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> > >>
> > >> --
> > >> Jani
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP (rev2)
== Series Details == Series: Enable MIPI DSI video mode on ADLP (rev2) URL : https://patchwork.freedesktop.org/series/95928/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
Re: [Intel-gfx] [PATCH v2 01/13] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info
On Sat, Oct 16, 2021 at 08:42:14PM +0200, Claudio Suarez wrote:
> According to the documentation, drm_add_edid_modes
> "... Also fills out the _display_info structure and ELD in @connector
> with any information which can be derived from the edid."
>
> drm_add_edid_modes accepts a struct edid *edid parameter which may have a
> value or may be null. When it is not null, connector->display_info and
> connector->eld are updated according to the edid. When edid=NULL, only
> connector->eld is reset. Reset connector->display_info to be consistent
> and accurate.
>
> Signed-off-by: Claudio Suarez
> ---
> drivers/gpu/drm/drm_edid.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 6325877c5fd6..c643db17782c 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5356,14 +5356,13 @@ int drm_add_edid_modes(struct drm_connector
> *connector, struct edid *edid)
> int num_modes = 0;
> u32 quirks;
>
> - if (edid == NULL) {
> - clear_eld(connector);
> - return 0;
> - }
> if (!drm_edid_is_valid(edid)) {
OK, so drm_edid_is_valid() will happily accept NULL and considers
it invalid. You may want to mention that explicitly in the commit
message.
> + /* edid == NULL or invalid here */
> clear_eld(connector);
> - drm_warn(connector->dev, "%s: EDID invalid.\n",
> - connector->name);
> + drm_reset_display_info(connector);
> + if (edid)
> + drm_warn(connector->dev, "%s: EDID invalid.\n",
> + connector->name);
Could you respin this to use the standard [CONNECTOR:%d:%s] form
while at it? Or I guess a patch to mass convert the whole drm_edid.c
might be another option.
Patch looks good.
Reviewed-by: Ville Syrjälä
> return 0;
> }
>
> --
> 2.33.0
>
>
--
Ville Syrjälä
Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for remove duplicate include in mock_region.c
== Series Details == Series: remove duplicate include in mock_region.c URL : https://patchwork.freedesktop.org/series/96009/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21381 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/index.html Known issues Here are the changes found in Patchwork_21381 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@userptr: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-kbl-soraka/igt@amdgpu/amd_ba...@userptr.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([fdo#109315] / [i915#2575]) +16 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([i915#1372]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#4103]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#1072]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#3301]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][17] ([i915#3363]) -> [FAIL][18] ([i915#3363] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21381/fi-icl-u2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#3301]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi (rev3)
On Mon, Oct 18, 2021 at 11:04:40AM +0200, Claudio Suarez wrote: > > Hi all, > > On Sun, Oct 17, 2021 at 05:11:46PM -, Patchwork wrote: > > == Series Details == > > > > Series: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi > > (rev3) > > URL : https://patchwork.freedesktop.org/series/95880/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_10744_full -> Patchwork_21360_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_21360_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_21360_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_21360_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_bw@linear-tiling-6-displays-3840x2160p: > > - shard-tglb: NOTRUN -> [SKIP][1] > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21360/shard-tglb2/igt@kms...@linear-tiling-6-displays-3840x2160p.html > > This is a false positive, isn't it ? Yes, looks like unrelated nonsense. > > - The test is skiped, not failed: > > Test requirement not met in function run_test_linear_tiling, file > ../tests/kms_bw.c:155: > Test requirement: !(pipe > num_pipes) > ASIC does not have 5 pipes > Subtest linear-tiling-6-displays-3840x2160p: SKIP (0.000s) > Starting subtest: linear-tiling-6-displays-3840x2160p > Subtest linear-tiling-6-displays-3840x2160p: SKIP (0.000s) > > > - linear-tiling-6-* is not even listed in > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21359/index.html > > Do I have to do anything ? I have verified manually. > > Where can I find the "bug team" ? Is this list ? I've occasionally wondered about that myself... -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH 03/20] drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
On Tue, Oct 19, 2021 at 09:16:33PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Rename intel_hdmi_port_clock() into intel_hdmi_tmds_clock(), and
> > move the 4:2:0 TMDS clock halving into intel_hdmi_tmds_clock() so
> > the callers don't have to worry about such details.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +++
> > 1 file changed, 12 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 37ce8a621973..e97c83535965 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1868,8 +1868,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > return MODE_OK;
> > }
> >
> > -static int intel_hdmi_port_clock(int clock, int bpc)
> > +static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
> > {
> > + /* YCBCR420 TMDS rate requirement is half the pixel clock */
> > + if (ycbcr420_output)
> > + clock /= 2;
> > +
> > /*
> > * Need to adjust the port link by:
> > * 1.5x for 12bpc
> > @@ -1932,25 +1936,22 @@ intel_hdmi_mode_clock_valid(struct drm_connector
> > *connector, int clock,
> > struct intel_hdmi *hdmi =
> > intel_attached_hdmi(to_intel_connector(connector));
> > enum drm_mode_status status;
> >
> > - if (ycbcr420_output)
> > - clock /= 2;
> > -
> > /* check if we can do 8bpc */
> > - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> > + status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8,
> > ycbcr420_output),
> >true, has_hdmi_sink);
> >
> > /* if we can't do 8bpc we may still be able to do 12bpc */
> > if (status != MODE_OK &&
> > intel_hdmi_source_bpc_possible(i915, 12) &&
> > intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink,
> > ycbcr420_output))
> > - status = hdmi_port_clock_valid(hdmi,
> > intel_hdmi_port_clock(clock, 12),
> > + status = hdmi_port_clock_valid(hdmi,
> > intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
> >true, has_hdmi_sink);
> >
> > /* if we can't do 8,12bpc we may still be able to do 10bpc */
> > if (status != MODE_OK &&
> > intel_hdmi_source_bpc_possible(i915, 10) &&
> > intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink,
> > ycbcr420_output))
> > - status = hdmi_port_clock_valid(hdmi,
> > intel_hdmi_port_clock(clock, 10),
> > + status = hdmi_port_clock_valid(hdmi,
> > intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
> >true, has_hdmi_sink);
> >
> > return status;
> > @@ -2057,12 +2058,13 @@ static int intel_hdmi_compute_bpc(struct
> > intel_encoder *encoder,
> > int clock)
> > {
> > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> > + bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
> > int bpc;
> >
> > for (bpc = 12; bpc >= 10; bpc -= 2) {
> > if (hdmi_deep_color_possible(crtc_state, bpc) &&
> > hdmi_port_clock_valid(intel_hdmi,
> > - intel_hdmi_port_clock(clock, bpc),
> > + intel_hdmi_tmds_clock(clock, bpc,
> > ycbcr420_output),
>
> Does not having the clock /= 2 here mean the check was bogus before this
> patch?
Previously the /2 was done by the caller (intel_hdmi_compute_clock()).
So nothing should be different here.
>
> BR,
> Jani.
>
>
> > true, crtc_state->has_hdmi_sink) ==
> > MODE_OK)
> > return bpc;
> > }
> > @@ -2082,13 +2084,10 @@ static int intel_hdmi_compute_clock(struct
> > intel_encoder *encoder,
> > if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> > clock *= 2;
> >
> > - /* YCBCR420 TMDS rate requirement is half the pixel clock */
> > - if (intel_hdmi_is_ycbcr420(crtc_state))
> > - clock /= 2;
> > -
> > bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
> >
> > - crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
> > + crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> > +
> > intel_hdmi_is_ycbcr420(crtc_state));
> >
> > /*
> > * pipe_bpp could already be below 8bpc due to
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 03/20] drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
On Fri, 15 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename intel_hdmi_port_clock() into intel_hdmi_tmds_clock(), and
> move the 4:2:0 TMDS clock halving into intel_hdmi_tmds_clock() so
> the callers don't have to worry about such details.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +++
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 37ce8a621973..e97c83535965 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1868,8 +1868,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_OK;
> }
>
> -static int intel_hdmi_port_clock(int clock, int bpc)
> +static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
> {
> + /* YCBCR420 TMDS rate requirement is half the pixel clock */
> + if (ycbcr420_output)
> + clock /= 2;
> +
> /*
>* Need to adjust the port link by:
>* 1.5x for 12bpc
> @@ -1932,25 +1936,22 @@ intel_hdmi_mode_clock_valid(struct drm_connector
> *connector, int clock,
> struct intel_hdmi *hdmi =
> intel_attached_hdmi(to_intel_connector(connector));
> enum drm_mode_status status;
>
> - if (ycbcr420_output)
> - clock /= 2;
> -
> /* check if we can do 8bpc */
> - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> + status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8,
> ycbcr420_output),
> true, has_hdmi_sink);
>
> /* if we can't do 8bpc we may still be able to do 12bpc */
> if (status != MODE_OK &&
> intel_hdmi_source_bpc_possible(i915, 12) &&
> intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink,
> ycbcr420_output))
> - status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 12),
> + status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
> true, has_hdmi_sink);
>
> /* if we can't do 8,12bpc we may still be able to do 10bpc */
> if (status != MODE_OK &&
> intel_hdmi_source_bpc_possible(i915, 10) &&
> intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink,
> ycbcr420_output))
> - status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 10),
> + status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
> true, has_hdmi_sink);
>
> return status;
> @@ -2057,12 +2058,13 @@ static int intel_hdmi_compute_bpc(struct
> intel_encoder *encoder,
> int clock)
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> + bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
> int bpc;
>
> for (bpc = 12; bpc >= 10; bpc -= 2) {
> if (hdmi_deep_color_possible(crtc_state, bpc) &&
> hdmi_port_clock_valid(intel_hdmi,
> - intel_hdmi_port_clock(clock, bpc),
> + intel_hdmi_tmds_clock(clock, bpc,
> ycbcr420_output),
Does not having the clock /= 2 here mean the check was bogus before this
patch?
BR,
Jani.
> true, crtc_state->has_hdmi_sink) ==
> MODE_OK)
> return bpc;
> }
> @@ -2082,13 +2084,10 @@ static int intel_hdmi_compute_clock(struct
> intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> clock *= 2;
>
> - /* YCBCR420 TMDS rate requirement is half the pixel clock */
> - if (intel_hdmi_is_ycbcr420(crtc_state))
> - clock /= 2;
> -
> bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
>
> - crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
> + crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> +
> intel_hdmi_is_ycbcr420(crtc_state));
>
> /*
>* pipe_bpp could already be below 8bpc due to
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v3 5/5] drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()
On Tue, Oct 05, 2021 at 10:40:18PM -0400, Lyude Paul wrote:
> Hooray! We've managed to hit enough bugs upstream that I've been able to
> come up with a pretty solid explanation for how backlight controls are
> actually supposed to be detected and used these days. As well, having the
> rest of the PWM bits in VESA's backlight interface implemented seems to
> have fixed all of the problematic brightness controls laptop panels that
> we've hit so far.
>
> So, let's actually document this instead of just calling the laptop panels
> liars. As well, I would like to formally apologize to all of the laptop
> panels I called liars. I'm sorry laptop panels, hopefully you can all
> forgive me and we can move past this~
>
> Signed-off-by: Lyude Paul
> ---
> .../drm/i915/display/intel_dp_aux_backlight.c| 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 91daf9ab50e8..04a52d6a74ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -455,11 +455,17 @@ int intel_dp_aux_init_backlight_funcs(struct
> intel_connector *connector)
> }
>
> /*
> - * A lot of eDP panels in the wild will report supporting both the
> - * Intel proprietary backlight control interface, and the VESA
> - * backlight control interface. Many of these panels are liars though,
> - * and will only work with the Intel interface. So, always probe for
> - * that first.
> + * Since Intel has their own backlight control interface, the majority
> of machines out there
> + * using DPCD backlight controls with Intel GPUs will be using this
> interface as opposed to
> + * the VESA interface. However, other GPUs (such as Nvidia's) will
> always use the VESA
> + * interface. This means that there's quite a number of panels out
> there that will advertise
> + * support for both interfaces, primarily systems with Intel/Nvidia
> hybrid GPU setups.
> + *
> + * There's a catch to this though: on many panels that advertise
> support for both
> + * interfaces, the VESA backlight interface will stop working once
> we've programmed the
> + * panel with Intel's OUI - which is also required for us to be able to
> detect Intel's
> + * backlight interface at all. This means that the only sensible way
> for us to detect both
> + * interfaces is to probe for Intel's first, and VESA's second.
>*/
You know a lot more about this than I do.
Acked-by: Ville Syrjälä
> if (try_intel_interface &&
> intel_dp_aux_supports_hdr_backlight(connector)) {
> drm_dbg_kms(dev, "Using Intel proprietary eDP backlight
> controls\n");
> --
> 2.31.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add support for panels with VESA backlights with PWM enable/disable
On Tue, Oct 05, 2021 at 10:40:14PM -0400, Lyude Paul wrote:
> This simply adds proper support for panel backlights that can be controlled
> via VESA's backlight control protocol, but which also require that we
> enable and disable the backlight via PWM instead of via the DPCD interface.
> We also enable this by default, in order to fix some people's backlights
> that were broken by not having this enabled.
>
> For reference, backlights that require this and use VESA's backlight
> interface tend to be laptops with hybrid GPUs, but this very well may
> change in the future.
>
> Signed-off-by: Lyude Paul
> Link: https://gitlab.freedesktop.org/drm/intel/-/issues/3680
> Fixes: fe7d52bccab6 ("drm/i915/dp: Don't use DPCD backlights that need PWM
> enable/disable")
> Cc: # v5.12+
> ---
> .../drm/i915/display/intel_dp_aux_backlight.c | 24 ++-
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 569d17b4d00f..594fdc7453ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -293,6 +293,10 @@ intel_dp_aux_vesa_enable_backlight(const struct
> intel_crtc_state *crtc_state,
> struct intel_panel *panel = >panel;
> struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> + if (!panel->backlight.edp.vesa.info.aux_enable)
> + panel->backlight.pwm_funcs->enable(crtc_state, conn_state,
> +
> panel->backlight.pwm_level_max);
What't the story here with the non-inverted max vs. pontetially inverted
0 in the counterpart?
> +
> drm_edp_backlight_enable(_dp->aux,
> >backlight.edp.vesa.info, level);
> }
>
> @@ -304,6 +308,10 @@ static void intel_dp_aux_vesa_disable_backlight(const
> struct drm_connector_state
> struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> drm_edp_backlight_disable(_dp->aux,
> >backlight.edp.vesa.info);
> +
> + if (!panel->backlight.edp.vesa.info.aux_enable)
> + panel->backlight.pwm_funcs->disable(old_conn_state,
> +
> intel_backlight_invert_pwm_level(connector, 0));
> }
>
> static int intel_dp_aux_vesa_setup_backlight(struct intel_connector
> *connector, enum pipe pipe)
> @@ -321,6 +329,15 @@ static int intel_dp_aux_vesa_setup_backlight(struct
> intel_connector *connector,
> if (ret < 0)
> return ret;
>
> + if (!panel->backlight.edp.vesa.info.aux_enable) {
> + ret = panel->backlight.pwm_funcs->setup(connector, pipe);
> + if (ret < 0) {
> + drm_err(>drm,
> + "Failed to setup PWM backlight controls for eDP
> backlight: %d\n",
> + ret);
> + return ret;
> + }
> + }
> panel->backlight.max = panel->backlight.edp.vesa.info.max;
> panel->backlight.min = 0;
> if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> @@ -340,12 +357,7 @@ intel_dp_aux_supports_vesa_backlight(struct
> intel_connector *connector)
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - /* TODO: We currently only support AUX only backlight configurations,
> not backlights which
> - * require a mix of PWM and AUX controls to work. In the mean time,
> these machines typically
> - * work just fine using normal PWM controls anyway.
> - */
> - if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> - drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> + if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> drm_dbg_kms(>drm, "AUX Backlight Control Supported!\n");
> return true;
> }
> --
> 2.31.1
--
Ville Syrjälä
Intel
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: Increase DRM_OBJECT_MAX_PROPERTY by 18. (rev2)
== Series Details == Series: drm: Increase DRM_OBJECT_MAX_PROPERTY by 18. (rev2) URL : https://patchwork.freedesktop.org/series/95440/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21380 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21380 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21380, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21380: ### IGT changes ### Possible regressions * igt@kms_force_connector_basic@force-edid: - fi-skl-6700k2: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-skl-6700k2/igt@kms_force_connector_ba...@force-edid.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-skl-6700k2/igt@kms_force_connector_ba...@force-edid.html Known issues Here are the changes found in Patchwork_21380 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +35 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([fdo#109315]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#1155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21380/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-icl-u2: [FAIL][18] ([i915#3363]) -> [FAIL][19] ([i915#3363] / [i915#4312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@run...@aborted.html [19]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Increase DRM_OBJECT_MAX_PROPERTY by 18. (rev2)
== Series Details ==
Series: drm: Increase DRM_OBJECT_MAX_PROPERTY by 18. (rev2)
URL : https://patchwork.freedesktop.org/series/95440/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4252f133017b drm: Increase DRM_OBJECT_MAX_PROPERTY by 18.
-:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#8:
> > On Wed, Oct 13, 2021 at 07:35:48PM +0200, Sebastian Andrzej Siewior wrote:
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit c7fcbf251397 ("drm/plane: check
that fb_damage is set up when used")'
#9:
> > > c7fcbf2513973 -> does not boot
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit c7fcbf251397 ("drm/plane: check
that fb_damage is set up when used")'
#10:
> > > c7fcbf2513973 + 2f425cf5242a0 -> boots, 18 x DRM_OBJECT_MAX_PROPERTY
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6f11f37459d8 ("drm/plane: remove
drm_helper_get_plane_damage_clips")'
#11:
> > > 6f11f37459d8f -> boots, 0 x DRM_OBJECT_MAX_PROPERTY
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6f11f37459d8 ("drm/plane: remove
drm_helper_get_plane_damage_clips")'
#12:
> > > 6f11f37459d8f + 2f425cf5242a0 -> boots, 18 x DRM_OBJECT_MAX_PROPERTY
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2f425cf5242a ("drm: Fix oops in
damage self-tests by mocking damage property")'
#15:
> > 2f425cf5242a0 on top (not merged), and that already got you the warning
-:24: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6f11f37459d8 ("drm/plane: remove
drm_helper_get_plane_damage_clips")'
#24:
> attached. dmesg.txt is 6f11f37459d8f and the other is 6f11f37459d8f +
-:46: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 7 errors, 1 warnings, 0 checks, 7 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/bios: gracefully disable dual eDP for now"
== Series Details == Series: Revert "drm/i915/bios: gracefully disable dual eDP for now" URL : https://patchwork.freedesktop.org/series/96006/ State : success == Summary == CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21379 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/index.html Known issues Here are the changes found in Patchwork_21379 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-ilk-650/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][6] -> [INCOMPLETE][7] ([i915#2940]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@c-dp1: - fi-cfl-8109u: [PASS][13] -> [FAIL][14] ([i915#4165]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][16] -> [DMESG-WARN][17] ([i915#295]) +18 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#3301]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21379/fi-bsw-kefka/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][21] ([i915#1602] / [i915#2029] / [i915#4312]) [21]:
Re: [Intel-gfx] [PATCH] Revert "drm/i915/bios: gracefully disable dual eDP for now"
On Tue, 2021-10-19 at 14:43 +0300, Jani Nikula wrote:
> This reverts commit 05734ca2a8f76c9eb3890b3c9dfc3467f03105c1.
>
> It's not graceful, instead it leads to boot time warning splats in the
> case it is supposed to handle gracefully. Apparently the BIOS/GOP
> enabling the port we end up skipping leads to state readout
> problems. Back to the drawing board.
Reviewed-by: José Roberto de Souza
>
> References:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21255/bat-adlp-4/boot0.txt
> Fixes: 05734ca2a8f7 ("drm/i915/bios: gracefully disable dual eDP for now")
> Cc: José Roberto de Souza
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Cc: Swati Sharma
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 47 ---
> 1 file changed, 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index b99907c656bb..f9776ca85de3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1930,50 +1930,6 @@ static int _intel_bios_max_tmds_clock(const struct
> intel_bios_encoder_data *devd
> }
> }
>
> -static enum port get_edp_port(struct drm_i915_private *i915)
> -{
> - const struct intel_bios_encoder_data *devdata;
> - enum port port;
> -
> - for_each_port(port) {
> - devdata = i915->vbt.ports[port];
> -
> - if (devdata && intel_bios_encoder_supports_edp(devdata))
> - return port;
> - }
> -
> - return PORT_NONE;
> -}
> -
> -/*
> - * FIXME: The power sequencer and backlight code currently do not support
> more
> - * than one set registers, at least not on anything other than VLV/CHV. It
> will
> - * clobber the registers. As a temporary workaround, gracefully prevent more
> - * than one eDP from being registered.
> - */
> -static void sanitize_dual_edp(struct intel_bios_encoder_data *devdata,
> - enum port port)
> -{
> - struct drm_i915_private *i915 = devdata->i915;
> - struct child_device_config *child = >child;
> - enum port p;
> -
> - /* CHV might not clobber PPS registers. */
> - if (IS_CHERRYVIEW(i915))
> - return;
> -
> - p = get_edp_port(i915);
> - if (p == PORT_NONE)
> - return;
> -
> - drm_dbg_kms(>drm, "both ports %c and %c configured as eDP, "
> - "disabling port %c eDP\n", port_name(p), port_name(port),
> - port_name(port));
> -
> - child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
> - child->device_type &= ~DEVICE_TYPE_INTERNAL_CONNECTOR;
> -}
> -
> static bool is_port_valid(struct drm_i915_private *i915, enum port port)
> {
> /*
> @@ -2031,9 +1987,6 @@ static void parse_ddi_port(struct drm_i915_private
> *i915,
> supports_typec_usb, supports_tbt,
> devdata->dsc != NULL);
>
> - if (is_edp)
> - sanitize_dual_edp(devdata, port);
> -
> if (is_dvi)
> sanitize_ddc_pin(devdata, port);
>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/i915/bios: gracefully disable dual eDP for now"
== Series Details == Series: Revert "drm/i915/bios: gracefully disable dual eDP for now" URL : https://patchwork.freedesktop.org/series/96006/ State : warning == Summary == $ dim checkpatch origin/drm-tip 69eeeadd313f Revert "drm/i915/bios: gracefully disable dual eDP for now" -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: References: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21255/bat-adlp-4/boot0.txt total: 0 errors, 1 warnings, 0 checks, 59 lines checked
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
On Tue, Oct 19, 2021 at 06:33:12PM +0300, Vudum, Lakshminarayana wrote: > Re-reported. Looks like kms_bw tests are broken? Thanks. Yes, I think so. > -Original Message- > From: Deak, Imre > Sent: Tuesday, October 19, 2021 5:54 AM > To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana > > Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in > lack of a valid DPCD (rev2) > > Hi Lakshmi, > > the failure below is expected, could we add cibug filter for it? > > On Tue, Oct 19, 2021 at 12:52:22AM +, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > > URL : https://patchwork.freedesktop.org/series/95948/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_21374_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_21374_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_21374_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > > - shard-apl: NOTRUN -> [FAIL][1] +2 similar issues > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > > t@kms...@linear-tiling-4-displays-1920x1080p.html > > The test is broken, since it assumes it can set any mode on any connector. > However these modesets won't through a WARN() any more after this change. > > > Warnings > > > > * igt@kms_bw@linear-tiling-3-displays-2560x1440p: > > - shard-apl: [DMESG-FAIL][2] ([i915#4298]) -> [FAIL][3] +2 > > similar issues > >[2]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html > >[3]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl7/ig > > t@kms...@linear-tiling-3-displays-2560x1440p.html > > > > > > Known issues > > > > > > Here are the changes found in Patchwork_21374_full that come from known > > issues: > > > > ### IGT changes ### > > > > Issues hit > > > > * igt@gem_create@create-massive: > > - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) > >[4]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > > t@gem_cre...@create-massive.html > > > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1373]) > >[5]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html > >[6]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/i > > gt@gem_ctx_isolation@preservation...@rcs0.html > > > > * igt@gem_ctx_param@set-priority-not-supported: > > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314]) > >[7]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/i > > gt@gem_ctx_pa...@set-priority-not-supported.html > > > > * igt@gem_ctx_persistence@legacy-engines-hostile: > > - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) > >[8]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/ig > > t@gem_ctx_persiste...@legacy-engines-hostile.html > > > > * igt@gem_ctx_persistence@many-contexts: > > - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410]) > >[9]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/i > > gt@gem_ctx_persiste...@many-contexts.html > > > > * igt@gem_eio@unwedge-stress: > > - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / > > [i915#3063] / [i915#3648]) > >[10]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html > >[11]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/i > > gt@gem_...@unwedge-stress.html > > > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > > - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) > >[12]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/ig > > t@gem_exec_fair@basic-none-r...@rcs0.html > > > > * igt@gem_exec_fair@basic-pace@rcs0: > > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar > > issue > >[13]: > >
[Intel-gfx] [PATCH 2/2] drm/i915/dp: use drm_dp_phy_name() for logging
Drop the local intel_dp_phy_name() function, and replace with
drm_dp_phy_name(). This lets us drop a number of local buffers.
v2: Rebase
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä # v1
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_dp_link_training.c | 83 ---
1 file changed, 36 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a72f2dc93718..81f93733fcc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -37,17 +37,6 @@ static void intel_dp_reset_lttpr_count(struct intel_dp
*intel_dp)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
}
-static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
-char *buf, size_t buf_size)
-{
- if (dp_phy == DP_PHY_DPRX)
- snprintf(buf, buf_size, "DPRX");
- else
- snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
-
- return buf;
-}
-
static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
@@ -59,20 +48,19 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp
*intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
- char phy_name[10];
-
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
if (drm_dp_read_lttpr_phy_caps(_dp->aux, dp_phy, phy_caps) < 0) {
drm_dbg_kms(_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
- encoder->base.base.id, encoder->base.name,
phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return;
}
drm_dbg_kms(_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
- encoder->base.base.id, encoder->base.name, phy_name,
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy),
(int)sizeof(intel_dp->lttpr_phy_caps[0]),
phy_caps);
}
@@ -406,14 +394,13 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
int lane;
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(>drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes:
%d, "
"TX FFE request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_TX_FFE_ARGS(link_status));
} else {
@@ -421,7 +408,7 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
"vswing request: " TRAIN_REQ_FMT ", "
"pre-emphasis request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_VSWING_ARGS(link_status),
TRAIN_REQ_PREEMPH_ARGS(link_status));
@@ -486,13 +473,12 @@ intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp,
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
- char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(>drm,
"[ENCODER:%d:%s][%s] Using DP training pattern
TPS%c\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name,
sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
@@ -529,13 +515,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
if (intel_dp_is_uhbr(crtc_state)) {
[Intel-gfx] [PATCH 1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
Add a helper for getting the DP PHY name. In the interest of caller
simplicity and to avoid allocations and passing in of buffers, duplicate
the const strings to return. It's a minor penalty to pay for simplicity
in all the call sites.
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 21 +
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ada0a1ff262d..2c36fad88781 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -314,6 +314,27 @@ void drm_dp_link_train_channel_eq_delay(const struct
drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
+{
+ static const char * const phy_names[] = {
+ [DP_PHY_DPRX] = "DPRX",
+ [DP_PHY_LTTPR1] = "LTTPR 1",
+ [DP_PHY_LTTPR2] = "LTTPR 2",
+ [DP_PHY_LTTPR3] = "LTTPR 3",
+ [DP_PHY_LTTPR4] = "LTTPR 4",
+ [DP_PHY_LTTPR5] = "LTTPR 5",
+ [DP_PHY_LTTPR6] = "LTTPR 6",
+ [DP_PHY_LTTPR7] = "LTTPR 7",
+ [DP_PHY_LTTPR8] = "LTTPR 8",
+ };
+
+ if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names))
+ return "";
+
+ return phy_names[dp_phy];
+}
+EXPORT_SYMBOL(drm_dp_phy_name);
+
void drm_dp_lttpr_link_train_clock_recovery_delay(void)
{
usleep_range(100, 200);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index afdf7f4183f9..39a249d99a51 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -2132,6 +2132,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector
*connector,
const struct drm_dp_desc *desc);
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
+
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
--
2.30.2
Re: [Intel-gfx] [PATCH 24/28] drm: use new iterator in drm_gem_plane_helper_prepare_fb v2
Am 19.10.21 um 16:30 schrieb Daniel Vetter:
On Tue, Oct 19, 2021 at 03:02:26PM +0200, Christian König wrote:
Am 13.10.21 um 16:23 schrieb Daniel Vetter:
On Tue, Oct 05, 2021 at 01:37:38PM +0200, Christian König wrote:
Makes the handling a bit more complex, but avoids the use of
dma_resv_get_excl_unlocked().
v2: improve coding and documentation
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_gem_atomic_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_atomic_helper.c
b/drivers/gpu/drm/drm_gem_atomic_helper.c
index e570398abd78..8534f78d4d6d 100644
--- a/drivers/gpu/drm/drm_gem_atomic_helper.c
+++ b/drivers/gpu/drm/drm_gem_atomic_helper.c
@@ -143,6 +143,7 @@
*/
int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
{
+ struct dma_resv_iter cursor;
struct drm_gem_object *obj;
struct dma_fence *fence;
@@ -150,9 +151,17 @@ int drm_gem_plane_helper_prepare_fb(struct drm_plane
*plane, struct drm_plane_st
return 0;
obj = drm_gem_fb_get_obj(state->fb, 0);
- fence = dma_resv_get_excl_unlocked(obj->resv);
- drm_atomic_set_fence_for_plane(state, fence);
+ dma_resv_iter_begin(, obj->resv, false);
+ dma_resv_for_each_fence_unlocked(, fence) {
+ /* TODO: We only use the first write fence here and need to fix
+* the drm_atomic_set_fence_for_plane() API to accept more than
+* one. */
I'm confused, right now there is only one write fence. So no need to
iterate, and also no need to add a TODO. If/when we add more write fences
then I think this needs to be revisited, and ofc then we do need to update
the set_fence helpers to carry an entire array of fences.
Well could be that I misunderstood you, but in your last explanation it
sounded like the drm_atomic_set_fence_for_plane() function needs fixing
anyway because a plane could have multiple BOs.
So in my understanding what we need is a
drm_atomic_add_dependency_for_plane() function which records that a certain
fence needs to be signaled before a flip.
Yeah that's another issue, but in practice there's no libva which decodes
into planar yuv with different fences between the planes. So not a bug in
practice.
But this is entirely orthogonal to you picking up the wrong fence here if
there's not exclusive fence set:
- old code: Either pick the exclusive fence, or not fence if the exclusive
one is not set.
- new code: Pick the exclusive fence or the first shared fence
Hui what?
We use "dma_resv_iter_begin(, obj->resv, *false*);" here which
means that only the exclusive fence is returned and no shared fences
whatsoever.
My next step is to replace the boolean with a bunch of use case
describing enums. I hope that will make it much clearer what's going on
here.
Christian.
New behaviour is busted, because scanning out and reading from a buffer at
the same time (for the next frame, e.g. to copy over damaged areas or some
other tricks) is very much a supported thing. Atomic _only_ wants to look
at the exclusive fence slot, which mean "there is an implicitly synced
write to this buffers". Implicitly synced reads _must_ be ignored.
Now amdgpu doesn't have this distinction in its uapi, but many drivers do.
-Daniel
Support for more than one write fence then comes totally naturally.
Christian.
-Daniel
+ dma_fence_get(fence);
+ break;
+ }
+ dma_resv_iter_end();
+ drm_atomic_set_fence_for_plane(state, fence);
return 0;
}
EXPORT_SYMBOL_GPL(drm_gem_plane_helper_prepare_fb);
--
2.25.1
Re: [Intel-gfx] [V2 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
On Tue, 19 Oct 2021, Vandita Kulkarni wrote:
> Update ADL_P device info to support DSI0, DSI1
>
> v2: Re-define cpu_transcoder_mask only (Jani)
>
> Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_pci.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..44c3577be748 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
> #define XE_LPD_FEATURES \
> .abox_mask = GENMASK(1, 0),
> \
> .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
> \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> .dbuf.size = 4096,
> \
> .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> BIT(DBUF_S4),
> \
> @@ -955,12 +953,16 @@ static const struct intel_device_info adl_s_info = {
> [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> \
> },
> \
> .trans_offsets = {
> \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> \
> },
> \
> XE_LPD_CURSOR_OFFSETS
>
> @@ -969,6 +971,9 @@ static const struct intel_device_info adl_p_info = {
> XE_LPD_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_P),
> .require_force_probe = 1,
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> +BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> @@ -1038,6 +1043,8 @@ static const struct intel_device_info dg2_info = {
> BIT(VECS0) | BIT(VECS1) |
> BIT(VCS0) | BIT(VCS2),
> .require_force_probe = 1,
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> +BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> };
>
> #undef PLATFORM
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [V2 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Tue, 19 Oct 2021, Vandita Kulkarni wrote:
> v2: Fix the typo, move out the hardcoding from
> macro(Jani, Ville)
>
> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
> guardband")
> Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
> drivers/gpu/drm/i915/i915_reg.h| 4 +++-
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 168c84a74d30..63dd75c6448a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1271,7 +1271,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct
> intel_encoder *encoder)
> if (DISPLAY_VER(i915) == 13) {
> for_each_dsi_port(port, intel_dsi->ports)
> intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> - TGL_DSI_CHKN_LSHS_GB, 0x4);
> + TGL_DSI_CHKN_LSHS_GB_MASK,
> + TGL_DSI_CHKN_LSHS_GB(4));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9f7a729333f..749b043a3ee3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11715,7 +11715,9 @@ enum skl_power_gate {
> #define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
> _TGL_DSI_CHKN_REG_0, \
> _TGL_DSI_CHKN_REG_1)
> -#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB_MASKREG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
> +(byte_clocks))
>
> /* Display Stream Splitter Control */
> #define DSS_CTL1 _MMIO(0x67400)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: use new link training delay helpers
On Thu, 14 Oct 2021, Jani Nikula wrote:
> Use the new link training delay helpers, fixing the delays for
> 128b/132b.
>
> For existing 8b/10b functionality, this will cause additional 1-byte
> DPCD reads for LTTPR delays instead of using the cached values. It's
> just too complicated to combine generic helpers with local caching in a
> sensible way.
>
> Cc: Ville Syrjälä
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Thanks for the review.
Pushed & got patches 1-2 merged via a topic branch to both drm-misc-next
and drm-intel-next, and pushed patch 3 on top to drm-intel-next.
BR,
Jani.
> ---
> .../drm/i915/display/intel_dp_link_training.c | 38 +++
> 1 file changed, 13 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 85676c953e0a..a72f2dc93718 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -683,15 +683,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> return true;
> }
>
> -static void intel_dp_link_training_clock_recovery_delay(struct intel_dp
> *intel_dp,
> - enum drm_dp_phy dp_phy)
> -{
> - if (dp_phy == DP_PHY_DPRX)
> - drm_dp_link_train_clock_recovery_delay(_dp->aux,
> intel_dp->dpcd);
> - else
> - drm_dp_lttpr_link_train_clock_recovery_delay();
> -}
> -
> static bool intel_dp_adjust_request_changed(const struct intel_crtc_state
> *crtc_state,
> const u8
> old_link_status[DP_LINK_STATUS_SIZE],
> const u8
> new_link_status[DP_LINK_STATUS_SIZE])
> @@ -750,6 +741,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
> u8 link_status[DP_LINK_STATUS_SIZE];
> bool max_vswing_reached = false;
> char phy_name[10];
> + int delay_us;
> +
> + delay_us = drm_dp_read_clock_recovery_delay(_dp->aux,
> + intel_dp->dpcd, dp_phy,
> +
> intel_dp_is_uhbr(crtc_state));
>
> intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> @@ -777,7 +773,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> *intel_dp,
>
> voltage_tries = 1;
> for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> - intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
> + usleep_range(delay_us, 2 * delay_us);
>
> if (drm_dp_dpcd_read_phy_link_status(_dp->aux, dp_phy,
>link_status) < 0) {
> @@ -895,19 +891,6 @@ static u32 intel_dp_training_pattern(struct intel_dp
> *intel_dp,
> return DP_TRAINING_PATTERN_2;
> }
>
> -static void
> -intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
> - enum drm_dp_phy dp_phy)
> -{
> - if (dp_phy == DP_PHY_DPRX) {
> - drm_dp_link_train_channel_eq_delay(_dp->aux,
> intel_dp->dpcd);
> - } else {
> - const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
> -
> - drm_dp_lttpr_link_train_channel_eq_delay(_dp->aux,
> phy_caps);
> - }
> -}
> -
> /*
> * Perform the link training channel equalization phase on the given DP PHY
> * using one of training pattern 2, 3 or 4 depending on the source and
> @@ -925,6 +908,11 @@ intel_dp_link_training_channel_equalization(struct
> intel_dp *intel_dp,
> u8 link_status[DP_LINK_STATUS_SIZE];
> bool channel_eq = false;
> char phy_name[10];
> + int delay_us;
> +
> + delay_us = drm_dp_read_channel_eq_delay(_dp->aux,
> + intel_dp->dpcd, dp_phy,
> + intel_dp_is_uhbr(crtc_state));
>
> intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> @@ -944,8 +932,8 @@ intel_dp_link_training_channel_equalization(struct
> intel_dp *intel_dp,
> }
>
> for (tries = 0; tries < 5; tries++) {
> - intel_dp_link_training_channel_equalization_delay(intel_dp,
> - dp_phy);
> + usleep_range(delay_us, 2 * delay_us);
> +
> if (drm_dp_dpcd_read_phy_link_status(_dp->aux, dp_phy,
>link_status) < 0) {
> drm_err(>drm,
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PULL] topic/drm-dp-training-delay-helpers for drm-misc-next and drm-intel-next
On Tue, 19 Oct 2021, Maxime Ripard wrote: > On Tue, Oct 19, 2021 at 12:59:57PM +0300, Jani Nikula wrote: >> >> Hi all - >> >> These are the drm dp helpers for figuring out link training delays, to >> be pulled to both drm-misc-next and drm-intel-next. >> >> >> topic/drm-dp-training-delay-helpers-2021-10-19: >> Core Changes: >> - drm dp helpers for figuring out link training delays > > Merged into drm-misc-next, thanks! And with that, also to drm-intel-next, thank you! BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
Re-reported. Looks like kms_bw tests are broken? -Original Message- From: Deak, Imre Sent: Tuesday, October 19, 2021 5:54 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) Hi Lakshmi, the failure below is expected, could we add cibug filter for it? On Tue, Oct 19, 2021 at 12:52:22AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > URL : https://patchwork.freedesktop.org/series/95948/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_21374_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21374_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21374_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > - shard-apl: NOTRUN -> [FAIL][1] +2 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > t@kms...@linear-tiling-4-displays-1920x1080p.html The test is broken, since it assumes it can set any mode on any connector. However these modesets won't through a WARN() any more after this change. > Warnings > > * igt@kms_bw@linear-tiling-3-displays-2560x1440p: > - shard-apl: [DMESG-FAIL][2] ([i915#4298]) -> [FAIL][3] +2 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl7/ig > t@kms...@linear-tiling-3-displays-2560x1440p.html > > > Known issues > > > Here are the changes found in Patchwork_21374_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_create@create-massive: > - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/ig > t@gem_cre...@create-massive.html > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1373]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/i > gt@gem_ctx_isolation@preservation...@rcs0.html > > * igt@gem_ctx_param@set-priority-not-supported: > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/i > gt@gem_ctx_pa...@set-priority-not-supported.html > > * igt@gem_ctx_persistence@legacy-engines-hostile: > - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/ig > t@gem_ctx_persiste...@legacy-engines-hostile.html > > * igt@gem_ctx_persistence@many-contexts: > - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/i > gt@gem_ctx_persiste...@many-contexts.html > > * igt@gem_eio@unwedge-stress: > - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / > [i915#3063] / [i915#3648]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/i > gt@gem_...@unwedge-stress.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/ig > t@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar > issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl1/ig > t@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_fair@basic-pace@vcs0: > - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html >
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Remove check for low voltage sku for max dp source rate (rev3)
== Series Details == Series: drm/i915/display: Remove check for low voltage sku for max dp source rate (rev3) URL : https://patchwork.freedesktop.org/series/95444/ State : success == Summary == CI Bug Log - changes from CI_DRM_10758_full -> Patchwork_21377_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21377_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][2] ([i915#280]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-tglb6/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][3] ([i915#2846]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-apl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10758/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10758/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-tglb6/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2849]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10758/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][12] ([i915#2658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-snb6/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-kbl3/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][14] ([i915#3002]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-apl1/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][15] ([i915#2724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-snb6/igt@gem_userptr_bl...@vma-merge.html - shard-kbl: NOTRUN -> [FAIL][16] ([i915#3318]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-kbl3/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: NOTRUN -> [DMESG-WARN][17] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3777]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-apl1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-kbl3/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][20] ([i915#3763]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-skl2/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_bw@linear-tiling-4-displays-3840x2160p: - shard-apl: NOTRUN -> [DMESG-FAIL][21] ([i915#4298]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/shard-apl7/igt@kms...@linear-tiling-4-displays-3840x2160p.html *
[Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
For the PHY enable/disable signalling to propagate
between Dispaly and PHY, DDI clocks need to be running when
enabling the PHY.
Bspec: 49188 says gate the clocks after enabling the
DDI Buffer.
We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
clocks after pll mapping") which gates the clocks much before,
as per the older spec. This commit nullifies its effect and makes
sure that the clocks are not gated while we enable the DDI
buffer.
v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 63dd75c6448a..e5ef5c4a32d7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1135,8 +1135,6 @@ static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
/* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder);
@@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder,
/* step 4c: configure voltage swing and skew */
gen11_dsi_voltage_swing_program_seq(encoder);
+ gen11_dsi_ungate_clocks(encoder);
+
/* enable DDI buffer */
gen11_dsi_enable_ddi_buffer(encoder);
@@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder,
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, crtc_state);
- /* Step 4l: Gate DDI clocks */
- if (DISPLAY_VER(dev_priv) == 11)
- gen11_dsi_gate_clocks(encoder);
+ gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
2.32.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Simplify handling of modifiers (rev11)
== Series Details ==
Series: drm/i915: Simplify handling of modifiers (rev11)
URL : https://patchwork.freedesktop.org/series/95579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10761 -> Patchwork_21378
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/index.html
Known issues
Here are the changes found in Patchwork_21378 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-guc: [PASS][4] -> [DMESG-FAIL][5] ([i915#2291] /
[i915#541])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#4269])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][8] ([i915#3921]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [FAIL][10] ([i915#4165]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#295]) -> [PASS][13] +14
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10761/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21378/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (38 -> 36)
--
Missing(2): fi-bsw-cyan bat-dg1-6
Build changes
-
* Linux: CI_DRM_10761 -> Patchwork_21378
CI-20190529: 20190529
CI_DRM_10761: 944d824a8c70a3984d0723229f2c3b9a2fa8452c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6255: 9b0881254557edeaf273b2196309fc4e22ea0312 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21378: e3d9c9af236fc8502ad5208d3df31fe2b53ca6d0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e3d9c9af236f drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
59db1f84b02f drm/i915: Move is_ccs_modifier() to intel_fb.c
820b82990550 drm/i915: Add a platform independent way to check for CCS AUX
planes
d6523db285fa drm/i915: Handle CCS CC planes separately from CCS AUX planes
a01da1211d1f drm/i915: Add a platform independent way to get the RC CCS CC plane
c2f251e1d2cd drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
66b8cb174dbb drm/i915: Unexport is_semiplanar_uv_plane()
5d9bdcb9dfee drm/i915: Simplify the modifier check for
[Intel-gfx] [V2 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
Update ADL_P device info to support DSI0, DSI1
v2: Re-define cpu_transcoder_mask only (Jani)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/i915_pci.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..44c3577be748 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
#define XE_LPD_FEATURES \
.abox_mask = GENMASK(1, 0),
\
.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
\
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
\
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
\
.dbuf.size = 4096,
\
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
\
BIT(DBUF_S4),
\
@@ -955,12 +953,16 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_B] = PIPE_B_OFFSET,
\
[TRANSCODER_C] = PIPE_C_OFFSET,
\
[TRANSCODER_D] = PIPE_D_OFFSET,
\
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
\
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
\
},
\
.trans_offsets = {
\
[TRANSCODER_A] = TRANSCODER_A_OFFSET,
\
[TRANSCODER_B] = TRANSCODER_B_OFFSET,
\
[TRANSCODER_C] = TRANSCODER_C_OFFSET,
\
[TRANSCODER_D] = TRANSCODER_D_OFFSET,
\
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
\
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
\
},
\
XE_LPD_CURSOR_OFFSETS
@@ -969,6 +971,9 @@ static const struct intel_device_info adl_p_info = {
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
.require_force_probe = 1,
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
.display.has_psr_hw_tracking = 0,
@@ -1038,6 +1043,8 @@ static const struct intel_device_info dg2_info = {
BIT(VECS0) | BIT(VECS1) |
BIT(VCS0) | BIT(VCS2),
.require_force_probe = 1,
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
#undef PLATFORM
--
2.32.0
[Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
MIPI DSI transcoder cannot be in video mode to support any of the display C states. Bspec: 49195 (For DC*co DSI transcoders cannot be in video mode) Bspec: 49193 (Hardware does not support DC5 or DC6 with MIPI DSI enabled) Bspec: 49188 (desc of DSI_DCSTATE_CTL talks about cmd mode PM control v2: Align to the power domain ordering (Jani) Add bspec references (Imre) Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display_power.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index d88da0d0f05a..b989ddd3d023 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -3106,6 +3106,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_PORT_DSI) |\ BIT_ULL(POWER_DOMAIN_INIT)) #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) -- 2.32.0
[Intel-gfx] [V2 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
v2: Fix the typo, move out the hardcoding from
macro(Jani, Ville)
Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
guardband")
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 168c84a74d30..63dd75c6448a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1271,7 +1271,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder
*encoder)
if (DISPLAY_VER(i915) == 13) {
for_each_dsi_port(port, intel_dsi->ports)
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
-TGL_DSI_CHKN_LSHS_GB, 0x4);
+TGL_DSI_CHKN_LSHS_GB_MASK,
+TGL_DSI_CHKN_LSHS_GB(4));
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9f7a729333f..749b043a3ee3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11715,7 +11715,9 @@ enum skl_power_gate {
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
_TGL_DSI_CHKN_REG_0, \
_TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
+ (byte_clocks))
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
--
2.32.0
[Intel-gfx] [V2 0/4] Enable MIPI DSI video mode on ADLP
v2: Addressed the review comments on v1. Vandita Kulkarni (4): drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB drm/i915/dsi/xelpd: Add DSI transcoder support drm/i915/dsi/xelpd: Disable DC states in Video mode drm/i915/dsi: Ungate clock before enabling the phy drivers/gpu/drm/i915/display/icl_dsi.c | 11 +-- drivers/gpu/drm/i915/display/intel_display_power.c | 1 + drivers/gpu/drm/i915/i915_pci.c| 11 +-- drivers/gpu/drm/i915/i915_reg.h| 4 +++- 4 files changed, 18 insertions(+), 9 deletions(-) -- 2.32.0
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
== Series Details == Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) URL : https://patchwork.freedesktop.org/series/95948/ State : success == Summary == CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21374_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] ([i915#1373]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> [SKIP][4] ([fdo#109314]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@legacy-engines-hostile: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-hostile.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: NOTRUN -> [FAIL][6] ([i915#2410]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063] / [i915#3648]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_params@no-blt: - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@no-blt.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@secure-non-master.html * igt@gem_exec_schedule@u-semaphore-user: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +195 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_exec_sched...@u-semaphore-user.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl3/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111656]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_mmap_...@coherency.html * igt@gem_pread@exhaustion: - shard-tglb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_pr...@exhaustion.html * igt@gem_pxp@reject-modify-context-protection-on: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb1/igt@gem_...@reject-modify-context-protection-on.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb7/igt@gem_...@verify-pxp-stale-buf-optout-execution.html * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs: - shard-iclb: NOTRUN -> [SKIP][22]
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Simplify handling of modifiers (rev11)
== Series Details == Series: drm/i915: Simplify handling of modifiers (rev11) URL : https://patchwork.freedesktop.org/series/95579/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev11)
== Series Details == Series: drm/i915: Simplify handling of modifiers (rev11) URL : https://patchwork.freedesktop.org/series/95579/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8cb40d7e0dbd drm/i915: Add a table with a descriptor for all i915 modifiers -:30: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #30: - Use from, until display version fields in modifier_desc instead of a mask. (Jani) total: 0 errors, 1 warnings, 0 checks, 675 lines checked 01ccea448c51 drm/i915: Move intel_get_format_info() to intel_fb.c -:284: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'format_list' - possible side-effects? #284: FILE: drivers/gpu/drm/i915/display/intel_fb.c:119: +#define FORMAT_OVERRIDE(format_list) \ + .formats = format_list, \ + .format_count = ARRAY_SIZE(format_list) total: 0 errors, 0 warnings, 1 checks, 351 lines checked 14c3d888d981 drm/i915: Add tiling attribute to the modifier descriptor 5d9bdcb9dfee drm/i915: Simplify the modifier check for interlaced scanout support 66b8cb174dbb drm/i915: Unexport is_semiplanar_uv_plane() c2f251e1d2cd drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c a01da1211d1f drm/i915: Add a platform independent way to get the RC CCS CC plane d6523db285fa drm/i915: Handle CCS CC planes separately from CCS AUX planes 820b82990550 drm/i915: Add a platform independent way to check for CCS AUX planes 59db1f84b02f drm/i915: Move is_ccs_modifier() to intel_fb.c e3d9c9af236f drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
Re: [Intel-gfx] [PATCH 24/28] drm: use new iterator in drm_gem_plane_helper_prepare_fb v2
On Tue, Oct 19, 2021 at 03:02:26PM +0200, Christian König wrote:
> Am 13.10.21 um 16:23 schrieb Daniel Vetter:
> > On Tue, Oct 05, 2021 at 01:37:38PM +0200, Christian König wrote:
> > > Makes the handling a bit more complex, but avoids the use of
> > > dma_resv_get_excl_unlocked().
> > >
> > > v2: improve coding and documentation
> > >
> > > Signed-off-by: Christian König
> > > ---
> > > drivers/gpu/drm/drm_gem_atomic_helper.c | 13 +++--
> > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_gem_atomic_helper.c
> > > b/drivers/gpu/drm/drm_gem_atomic_helper.c
> > > index e570398abd78..8534f78d4d6d 100644
> > > --- a/drivers/gpu/drm/drm_gem_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_gem_atomic_helper.c
> > > @@ -143,6 +143,7 @@
> > >*/
> > > int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct
> > > drm_plane_state *state)
> > > {
> > > + struct dma_resv_iter cursor;
> > > struct drm_gem_object *obj;
> > > struct dma_fence *fence;
> > > @@ -150,9 +151,17 @@ int drm_gem_plane_helper_prepare_fb(struct drm_plane
> > > *plane, struct drm_plane_st
> > > return 0;
> > > obj = drm_gem_fb_get_obj(state->fb, 0);
> > > - fence = dma_resv_get_excl_unlocked(obj->resv);
> > > - drm_atomic_set_fence_for_plane(state, fence);
> > > + dma_resv_iter_begin(, obj->resv, false);
> > > + dma_resv_for_each_fence_unlocked(, fence) {
> > > + /* TODO: We only use the first write fence here and need to fix
> > > + * the drm_atomic_set_fence_for_plane() API to accept more than
> > > + * one. */
> > I'm confused, right now there is only one write fence. So no need to
> > iterate, and also no need to add a TODO. If/when we add more write fences
> > then I think this needs to be revisited, and ofc then we do need to update
> > the set_fence helpers to carry an entire array of fences.
>
> Well could be that I misunderstood you, but in your last explanation it
> sounded like the drm_atomic_set_fence_for_plane() function needs fixing
> anyway because a plane could have multiple BOs.
>
> So in my understanding what we need is a
> drm_atomic_add_dependency_for_plane() function which records that a certain
> fence needs to be signaled before a flip.
Yeah that's another issue, but in practice there's no libva which decodes
into planar yuv with different fences between the planes. So not a bug in
practice.
But this is entirely orthogonal to you picking up the wrong fence here if
there's not exclusive fence set:
- old code: Either pick the exclusive fence, or not fence if the exclusive
one is not set.
- new code: Pick the exclusive fence or the first shared fence
New behaviour is busted, because scanning out and reading from a buffer at
the same time (for the next frame, e.g. to copy over damaged areas or some
other tricks) is very much a supported thing. Atomic _only_ wants to look
at the exclusive fence slot, which mean "there is an implicitly synced
write to this buffers". Implicitly synced reads _must_ be ignored.
Now amdgpu doesn't have this distinction in its uapi, but many drivers do.
-Daniel
> Support for more than one write fence then comes totally naturally.
>
> Christian.
>
> > -Daniel
> >
> > > + dma_fence_get(fence);
> > > + break;
> > > + }
> > > + dma_resv_iter_end();
> > > + drm_atomic_set_fence_for_plane(state, fence);
> > > return 0;
> > > }
> > > EXPORT_SYMBOL_GPL(drm_gem_plane_helper_prepare_fb);
> > > --
> > > 2.25.1
> > >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH 23/28] drm: use new iterator in drm_gem_fence_array_add_implicit v3
Am 13.10.21 um 16:21 schrieb Daniel Vetter:
On Tue, Oct 05, 2021 at 01:37:37PM +0200, Christian König wrote:
Simplifying the code a bit.
v2: add missing rcu_read_lock()/unlock()
v3: switch to locked version
Signed-off-by: Christian König
Reviewed-by: Tvrtko Ursulin
Please make sure you also apply this to the new copy of this code in
drm/sched. This one here is up for deletion, once I get all the driver
conversions I have landed ...
Yeah, I do have that. Only added this patch here for completeness so
that I could at least consider dropping the old access functions.
Put I will hold it back, just ping me when the code in question is removed.
Christian.
-Daniel
---
drivers/gpu/drm/drm_gem.c | 26 +-
1 file changed, 5 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 09c820045859..4dcdec6487bb 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1340,31 +1340,15 @@ int drm_gem_fence_array_add_implicit(struct xarray
*fence_array,
struct drm_gem_object *obj,
bool write)
{
- int ret;
- struct dma_fence **fences;
- unsigned int i, fence_count;
-
- if (!write) {
- struct dma_fence *fence =
- dma_resv_get_excl_unlocked(obj->resv);
-
- return drm_gem_fence_array_add(fence_array, fence);
- }
+ struct dma_resv_iter cursor;
+ struct dma_fence *fence;
+ int ret = 0;
- ret = dma_resv_get_fences(obj->resv, NULL,
- _count, );
- if (ret || !fence_count)
- return ret;
-
- for (i = 0; i < fence_count; i++) {
- ret = drm_gem_fence_array_add(fence_array, fences[i]);
+ dma_resv_for_each_fence(, obj->resv, write, fence) {
+ ret = drm_gem_fence_array_add(fence_array, fence);
if (ret)
break;
}
-
- for (; i < fence_count; i++)
- dma_fence_put(fences[i]);
- kfree(fences);
return ret;
}
EXPORT_SYMBOL(drm_gem_fence_array_add_implicit);
--
2.25.1
Re: [Intel-gfx] [PATCH 24/28] drm: use new iterator in drm_gem_plane_helper_prepare_fb v2
Am 13.10.21 um 16:23 schrieb Daniel Vetter:
On Tue, Oct 05, 2021 at 01:37:38PM +0200, Christian König wrote:
Makes the handling a bit more complex, but avoids the use of
dma_resv_get_excl_unlocked().
v2: improve coding and documentation
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_gem_atomic_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_atomic_helper.c
b/drivers/gpu/drm/drm_gem_atomic_helper.c
index e570398abd78..8534f78d4d6d 100644
--- a/drivers/gpu/drm/drm_gem_atomic_helper.c
+++ b/drivers/gpu/drm/drm_gem_atomic_helper.c
@@ -143,6 +143,7 @@
*/
int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
{
+ struct dma_resv_iter cursor;
struct drm_gem_object *obj;
struct dma_fence *fence;
@@ -150,9 +151,17 @@ int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct drm_plane_st
return 0;
obj = drm_gem_fb_get_obj(state->fb, 0);
- fence = dma_resv_get_excl_unlocked(obj->resv);
- drm_atomic_set_fence_for_plane(state, fence);
+ dma_resv_iter_begin(, obj->resv, false);
+ dma_resv_for_each_fence_unlocked(, fence) {
+ /* TODO: We only use the first write fence here and need to fix
+* the drm_atomic_set_fence_for_plane() API to accept more than
+* one. */
I'm confused, right now there is only one write fence. So no need to
iterate, and also no need to add a TODO. If/when we add more write fences
then I think this needs to be revisited, and ofc then we do need to update
the set_fence helpers to carry an entire array of fences.
Well could be that I misunderstood you, but in your last explanation it
sounded like the drm_atomic_set_fence_for_plane() function needs fixing
anyway because a plane could have multiple BOs.
So in my understanding what we need is a
drm_atomic_add_dependency_for_plane() function which records that a
certain fence needs to be signaled before a flip.
Support for more than one write fence then comes totally naturally.
Christian.
-Daniel
+ dma_fence_get(fence);
+ break;
+ }
+ dma_resv_iter_end();
+ drm_atomic_set_fence_for_plane(state, fence);
return 0;
}
EXPORT_SYMBOL_GPL(drm_gem_plane_helper_prepare_fb);
--
2.25.1
Re: [Intel-gfx] [PATCH 23/28] drm: use new iterator in drm_gem_fence_array_add_implicit v3
On Tue, Oct 19, 2021 at 02:54:04PM +0200, Christian König wrote:
> Am 13.10.21 um 16:21 schrieb Daniel Vetter:
> > On Tue, Oct 05, 2021 at 01:37:37PM +0200, Christian König wrote:
> > > Simplifying the code a bit.
> > >
> > > v2: add missing rcu_read_lock()/unlock()
> > > v3: switch to locked version
> > >
> > > Signed-off-by: Christian König
> > > Reviewed-by: Tvrtko Ursulin
> > Please make sure you also apply this to the new copy of this code in
> > drm/sched. This one here is up for deletion, once I get all the driver
> > conversions I have landed ...
>
> Yeah, I do have that. Only added this patch here for completeness so that I
> could at least consider dropping the old access functions.
>
> Put I will hold it back, just ping me when the code in question is removed.
Imo go ahead and push this, the rebasing is trivial since I just delete
code. That way I don't have to remember to do anything :-)
-Daniel
>
> Christian.
>
> > -Daniel
> >
> > > ---
> > > drivers/gpu/drm/drm_gem.c | 26 +-
> > > 1 file changed, 5 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> > > index 09c820045859..4dcdec6487bb 100644
> > > --- a/drivers/gpu/drm/drm_gem.c
> > > +++ b/drivers/gpu/drm/drm_gem.c
> > > @@ -1340,31 +1340,15 @@ int drm_gem_fence_array_add_implicit(struct
> > > xarray *fence_array,
> > >struct drm_gem_object *obj,
> > >bool write)
> > > {
> > > - int ret;
> > > - struct dma_fence **fences;
> > > - unsigned int i, fence_count;
> > > -
> > > - if (!write) {
> > > - struct dma_fence *fence =
> > > - dma_resv_get_excl_unlocked(obj->resv);
> > > -
> > > - return drm_gem_fence_array_add(fence_array, fence);
> > > - }
> > > + struct dma_resv_iter cursor;
> > > + struct dma_fence *fence;
> > > + int ret = 0;
> > > - ret = dma_resv_get_fences(obj->resv, NULL,
> > > - _count, );
> > > - if (ret || !fence_count)
> > > - return ret;
> > > -
> > > - for (i = 0; i < fence_count; i++) {
> > > - ret = drm_gem_fence_array_add(fence_array, fences[i]);
> > > + dma_resv_for_each_fence(, obj->resv, write, fence) {
> > > + ret = drm_gem_fence_array_add(fence_array, fence);
> > > if (ret)
> > > break;
> > > }
> > > -
> > > - for (; i < fence_count; i++)
> > > - dma_fence_put(fences[i]);
> > > - kfree(fences);
> > > return ret;
> > > }
> > > EXPORT_SYMBOL(drm_gem_fence_array_add_implicit);
> > > --
> > > 2.25.1
> > >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [Intel-gfx] [PULL] topic/drm-dp-training-delay-helpers for drm-misc-next and drm-intel-next
On Tue, Oct 19, 2021 at 12:59:57PM +0300, Jani Nikula wrote: > > Hi all - > > These are the drm dp helpers for figuring out link training delays, to > be pulled to both drm-misc-next and drm-intel-next. > > > topic/drm-dp-training-delay-helpers-2021-10-19: > Core Changes: > - drm dp helpers for figuring out link training delays Merged into drm-misc-next, thanks! Maxime signature.asc Description: PGP signature
Re: [Intel-gfx] [RFC PATCH] drm: Increase DRM_OBJECT_MAX_PROPERTY by 18.
On 2021-10-19 14:24:29 [+0200], Daniel Vetter wrote: > > Ah dmesg help me understand what's going on. Does the below patch help? If > it's this one that would also explain why intel CI hasn't hit it - it's a > leak between tests and we run them all individually instead of once at > boot-up. Yes, it does. Thank you. Tested-by: Sebastian Andrzej Siewior > Cheers, Daniel Sebastian
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
Hi Lakshmi, the failure below is expected, could we add cibug filter for it? On Tue, Oct 19, 2021 at 12:52:22AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) > URL : https://patchwork.freedesktop.org/series/95948/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10753_full -> Patchwork_21374_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_21374_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21374_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21374_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_bw@linear-tiling-4-displays-1920x1080p: > - shard-apl: NOTRUN -> [FAIL][1] +2 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@kms...@linear-tiling-4-displays-1920x1080p.html The test is broken, since it assumes it can set any mode on any connector. However these modesets won't through a WARN() any more after this change. > Warnings > > * igt@kms_bw@linear-tiling-3-displays-2560x1440p: > - shard-apl: [DMESG-FAIL][2] ([i915#4298]) -> [FAIL][3] +2 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl7/igt@kms...@linear-tiling-3-displays-2560x1440p.html > > > Known issues > > > Here are the changes found in Patchwork_21374_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_create@create-massive: > - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-apl3/igt@gem_cre...@create-massive.html > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1373]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb1/igt@gem_ctx_isolation@preservation...@rcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html > > * igt@gem_ctx_param@set-priority-not-supported: > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109314]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb8/igt@gem_ctx_pa...@set-priority-not-supported.html > > * igt@gem_ctx_persistence@legacy-engines-hostile: > - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-hostile.html > > * igt@gem_ctx_persistence@many-contexts: > - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html > > * igt@gem_eio@unwedge-stress: > - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / > [i915#3063] / [i915#3648]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb2/igt@gem_...@unwedge-stress.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb2/igt@gem_...@unwedge-stress.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-glk9/igt@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar > issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_fair@basic-pace@vcs0: > - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10753/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html > > * igt@gem_exec_params@no-blt: > - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109283]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21374/shard-iclb4/igt@gem_exec_par...@no-blt.html > > *
Re: [Intel-gfx] [PATCH linux-next] drm/i915/display: Remove unused variable and its assignment.
> This one we could use. For some reason we hardcode it to > 1 now, which is correct for our use cases but I don't really> see a reason to > hardcode it here. We are supposed to calculate> it correctly after all, and > chv_crtc_clock_get() also just blindly> reads it out.> > > bestm2_frac = > crtc_state->dpll.m2 & 0x3f;> > -bestm1 = crtc_state->dpll.m1;> > This > one is a bit trickier since I don't think the spec even> gives us other > values. But we could assert that it's correct.> > Some something along these > lines I think would be best:> + drm_WARN_ON(_priv->drm, bestm1 != 2);> > vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),> > DPIO_CHV_M1_DIV_BY_2 |> - 1 << DPIO_CHV_N_DIV_SHIFT);> + > bestn << DPIO_CHV_N_DIV_SHIFT); Thanks for your kind response ! Does that means the variable will be used by the hardware？if so as far as I see it, I don't seem to see the relevant interface.
Re: [Intel-gfx] [PATCH linux-next] drm/i915/display: Remove unused variable and its assignment.
> This one we could use. For some reason we hardcode it to > 1 now, which is correct for our use cases but I don't really> see a reason to > hardcode it here. We are supposed to calculate> it correctly after all, and > chv_crtc_clock_get() also just blindly> reads it out.> > > bestm2_frac = > crtc_state->dpll.m2 & 0x3f;> > -bestm1 = crtc_state->dpll.m1;> > This > one is a bit trickier since I don't think the spec even> gives us other > values. But we could assert that it's correct.> > Some something along these > lines I think would be best:> + drm_WARN_ON(_priv->drm, bestm1 != 2);> > vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),> > DPIO_CHV_M1_DIV_BY_2 |> - 1 << DPIO_CHV_N_DIV_SHIFT);> + > bestn << DPIO_CHV_N_DIV_SHIFT); Thanks for your kind response ! Does that means the variable will be used by the hardware？if so as far as I see it, I don't seem to see the relevant interface.
[Intel-gfx] [PATCH] remove duplicate include in mock_region.c
From: Ran Jianping 'drm/ttm/ttm_placement.h' included in 'drivers/gpu/drm/i915/selftests/mock_region.c' is duplicated. It is also included on the 9 line. Reported-by: Zeal Robot Signed-off-by: Ran Jianping --- drivers/gpu/drm/i915/selftests/mock_region.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_region.c b/drivers/gpu/drm/i915/selftests/mock_region.c index efa86dffe3c6..75793008c4ef 100644 --- a/drivers/gpu/drm/i915/selftests/mock_region.c +++ b/drivers/gpu/drm/i915/selftests/mock_region.c @@ -6,8 +6,6 @@ #include #include -#include - #include "gem/i915_gem_region.h" #include "intel_memory_region.h" #include "intel_region_ttm.h" -- 2.25.1
Re: [Intel-gfx] [PATCH 12/28] drm/amdgpu: use new iterator in amdgpu_ttm_bo_eviction_valuable
Am 13.10.21 um 16:07 schrieb Daniel Vetter:
On Tue, Oct 05, 2021 at 01:37:26PM +0200, Christian König wrote:
Simplifying the code a bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e8d70b6e6737..722e3c9e8882 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1345,10 +1345,9 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
const struct ttm_place *place)
{
unsigned long num_pages = bo->resource->num_pages;
+ struct dma_resv_iter resv_cursor;
struct amdgpu_res_cursor cursor;
- struct dma_resv_list *flist;
struct dma_fence *f;
- int i;
/* Swapout? */
if (bo->resource->mem_type == TTM_PL_SYSTEM)
@@ -1362,14 +1361,9 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct
ttm_buffer_object *bo,
* If true, then return false as any KFD process needs all its BOs to
* be resident to run successfully
*/
- flist = dma_resv_shared_list(bo->base.resv);
- if (flist) {
- for (i = 0; i < flist->shared_count; ++i) {
- f = rcu_dereference_protected(flist->shared[i],
- dma_resv_held(bo->base.resv));
- if (amdkfd_fence_check_mm(f, current->mm))
- return false;
- }
+ dma_resv_for_each_fence(_cursor, bo->base.resv, true, f) {
^false?
At least I'm not seeing the code look at the exclusive fence here.
Yes, but that's correct. We need to look at all potential fences.
It's a design problem in KFD if you ask me, but that is a completely
different topic.
Christian.
-Daniel
+ if (amdkfd_fence_check_mm(f, current->mm))
+ return false;
}
switch (bo->resource->mem_type) {
--
2.25.1
Re: [Intel-gfx] [PATCH 14/28] drm/msm: use new iterator in msm_gem_describe
Am 13.10.21 um 16:14 schrieb Daniel Vetter:
On Tue, Oct 05, 2021 at 01:37:28PM +0200, Christian König wrote:
Simplifying the code a bit. Also drop the RCU read side lock since the
object is locked anyway.
Untested since I can't get the driver to compile on !ARM.
Cross-compiler install is pretty easy and you should have that for pushing
drm changes to drm-misc :-)
I do have cross compile setups for some architectures, but I seriously
can't do that for every single driver.
With only a bit of work we allowed MSM to be compile tested on other
architectures as well now. That even yielded a couple of missing
includes and dependencies in MSM which just don't matter on ARM.
Signed-off-by: Christian König
Assuming this compiles, it looks correct.
Yes it does.
Reviewed-by: Daniel Vetter
Thanks,
Christian.
---
drivers/gpu/drm/msm/msm_gem.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 40a9863f5951..5bd511f07c07 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -880,7 +880,7 @@ void msm_gem_describe(struct drm_gem_object *obj, struct
seq_file *m,
{
struct msm_gem_object *msm_obj = to_msm_bo(obj);
struct dma_resv *robj = obj->resv;
- struct dma_resv_list *fobj;
+ struct dma_resv_iter cursor;
struct dma_fence *fence;
struct msm_gem_vma *vma;
uint64_t off = drm_vma_node_start(>vma_node);
@@ -955,22 +955,13 @@ void msm_gem_describe(struct drm_gem_object *obj, struct
seq_file *m,
seq_puts(m, "\n");
}
- rcu_read_lock();
- fobj = dma_resv_shared_list(robj);
- if (fobj) {
- unsigned int i, shared_count = fobj->shared_count;
-
- for (i = 0; i < shared_count; i++) {
- fence = rcu_dereference(fobj->shared[i]);
+ dma_resv_for_each_fence(, robj, true, fence) {
+ if (dma_resv_iter_is_exclusive())
+ describe_fence(fence, "Exclusive", m);
+ else
describe_fence(fence, "Shared", m);
- }
}
- fence = dma_resv_excl_fence(robj);
- if (fence)
- describe_fence(fence, "Exclusive", m);
- rcu_read_unlock();
-
msm_gem_unlock(obj);
}
--
2.25.1
Re: [Intel-gfx] [PATCH linux-next] drm/i915/display: Remove unused variable and its assignment.
> This one we could use. For some reason we hardcode it to > 1 now, which is correct for our use cases but I don't really> see a reason to > hardcode it here. We are supposed to calculate> it correctly after all, and > chv_crtc_clock_get() also just blindly> reads it out.> > > bestm2_frac = > crtc_state->dpll.m2 & 0x3f;> > -bestm1 = crtc_state->dpll.m1;> > This > one is a bit trickier since I don't think the spec even> gives us other > values. But we could assert that it's correct.> > Some something along these > lines I think would be best:> + drm_WARN_ON(_priv->drm, bestm1 != 2);> > vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),> > DPIO_CHV_M1_DIV_BY_2 |> - 1 << DPIO_CHV_N_DIV_SHIFT);> + > bestn << DPIO_CHV_N_DIV_SHIFT); Thanks for your kind response ! Does that means the variable will be used by the hardware？if so as far as I see it, I don't seem to see the relevant interface.
Re: [Intel-gfx] [PATCH 1/3] drm/dp: add helpers to read link training delays
On Mon, 18 Oct 2021, Maxime Ripard wrote: > Hi Jani, > > On Fri, Oct 15, 2021 at 06:21:35PM +0300, Jani Nikula wrote: >> On Thu, 14 Oct 2021, Jani Nikula wrote: >> > The link training delays are different and/or available in different >> > DPCD offsets depending on: >> > >> > - Clock recovery vs. channel equalization >> > - DPRX vs. LTTPR >> > - 128b/132b vs. 8b/10b >> > - DPCD 1.4+ vs. earlier >> > >> > Add helpers to get the correct delays in us, reading DPCD if >> > necessary. This is more straightforward than trying to retrofit the >> > existing helpers to take 128b/132b into account. >> > >> > Having to pass in the DPCD receiver cap field seems unavoidable, because >> > reading it involves checking the revision and reading extended receiver >> > cap. So unfortunately the interface is mixed cached and read as needed. >> > >> > v2: Remove delay_us < 0 check and the whole local var (Ville) >> > >> > Cc: Ville Syrjälä >> > Reviewed-by: Ville Syrjälä >> > Signed-off-by: Jani Nikula >> >> Maarten, Maxime, Thomas - >> >> Ack on the first two patches in this series? >> >> Should we merge them via a topic branch to both drm-misc-next and >> drm-intel-next, or is it fine to merge them all via drm-intel-next? We >> might be at a point in the development cycle that it takes a while to >> get the branches in sync again. > > I guess the easiest would be to send a PR so that we can merge it in the > two branches then. Sent. https://lore.kernel.org/r/878ryps5b6@intel.com BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [RFC PATCH] drm: Increase DRM_OBJECT_MAX_PROPERTY by 18.
On Thu, Oct 14, 2021 at 03:47:31PM +0200, Sebastian Andrzej Siewior wrote: > On 2021-10-14 15:21:22 [+0200], Daniel Vetter wrote: > > On Wed, Oct 13, 2021 at 07:35:48PM +0200, Sebastian Andrzej Siewior wrote: > > > c7fcbf2513973 -> does not boot > > > c7fcbf2513973 + 2f425cf5242a0 -> boots, 18 x DRM_OBJECT_MAX_PROPERTY > > > 6f11f37459d8f -> boots, 0 x DRM_OBJECT_MAX_PROPERTY > > > 6f11f37459d8f + 2f425cf5242a0 -> boots, 18 x DRM_OBJECT_MAX_PROPERTY > > > > Just to check, you've built 6f11f37459d8f, and then you cherry-picked > > 2f425cf5242a0 on top (not merged), and that already got you the warning > > flood? > > Correct. > > > I'm probably blind, but I'm really not seeing where this pile of > > properties is coming from. Can you pls also boot with drm.debug=0xe and > > attach full dmesg? Plus your .config please. > > attached. dmesg.txt is 6f11f37459d8f and the other is 6f11f37459d8f + > 2f425cf5242a0. Ah dmesg help me understand what's going on. Does the below patch help? If it's this one that would also explain why intel CI hasn't hit it - it's a leak between tests and we run them all individually instead of once at boot-up. Cheers, Daniel diff --git a/drivers/gpu/drm/selftests/test-drm_damage_helper.c b/drivers/gpu/drm/selftests/test-drm_damage_helper.c index 1c19a5d3eefb..8d8d8e214c28 100644 --- a/drivers/gpu/drm/selftests/test-drm_damage_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_damage_helper.c @@ -30,6 +30,7 @@ static void mock_setup(struct drm_plane_state *state) mock_device.driver = _driver; mock_device.mode_config.prop_fb_damage_clips = _prop; mock_plane.dev = _device; + mock_obj_props.count = 0; mock_plane.base.properties = _obj_props; mock_prop.base.id = 1; /* 0 is an invalid id */ mock_prop.dev = _device; -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Remove check for low voltage sku for max dp source rate (rev3)
== Series Details == Series: drm/i915/display: Remove check for low voltage sku for max dp source rate (rev3) URL : https://patchwork.freedesktop.org/series/95444/ State : success == Summary == CI Bug Log - changes from CI_DRM_10758 -> Patchwork_21377 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/index.html Changes --- No changes found Participating hosts (38 -> 36) -- Missing(2): fi-bsw-cyan bat-dg1-6 Build changes - * Linux: CI_DRM_10758 -> Patchwork_21377 CI-20190529: 20190529 CI_DRM_10758: 8d0a08c4502a98ae3a6d533edaa2aabc2e491585 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6254: 51792e987da03ba2a6faf5857c12f1d173c87def @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21377: 342ca9feb4a1b9a564c50498d03c82c71745ba55 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 342ca9feb4a1 drm/i915/display: Remove check for low voltage sku for max dp source rate == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21377/index.html
Re: [Intel-gfx] [PATCH] drm/locking: fix __stack_depot_* name conflict
On Mon, 18 Oct 2021, Jani Nikula wrote:
> From: Stephen Rothwell
>
> Commit cd06ab2fd48f ("drm/locking: add backtrace for locking contended
> locks without backoff") added functions named __stack_depot_* in drm
> which conflict with stack depot. Rename to __drm_stack_depot_*.
>
> v2 by Jani:
> - Also rename __stack_depot_print
>
> References: https://lore.kernel.org/r/20211015202648.25844...@canb.auug.org.au
> Fixes: cd06ab2fd48f ("drm/locking: add backtrace for locking contended locks
> without backoff")
> Cc: Daniel Vetter
> Signed-off-by: Stephen Rothwell
> Signed-off-by: Jani Nikula
Pushed to drm-misc-next with Daniel's IRC r-b. Thanks for the original
patch and review.
BR,
Jani.
> ---
> drivers/gpu/drm/drm_modeset_lock.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_modeset_lock.c
> b/drivers/gpu/drm/drm_modeset_lock.c
> index 4d32b61fa1fd..c97323365675 100644
> --- a/drivers/gpu/drm/drm_modeset_lock.c
> +++ b/drivers/gpu/drm/drm_modeset_lock.c
> @@ -79,7 +79,7 @@
> static DEFINE_WW_CLASS(crtc_ww_class);
>
> #if IS_ENABLED(CONFIG_DRM_DEBUG_MODESET_LOCK)
> -static noinline depot_stack_handle_t __stack_depot_save(void)
> +static noinline depot_stack_handle_t __drm_stack_depot_save(void)
> {
> unsigned long entries[8];
> unsigned int n;
> @@ -89,7 +89,7 @@ static noinline depot_stack_handle_t
> __stack_depot_save(void)
> return stack_depot_save(entries, n, GFP_NOWAIT | __GFP_NOWARN);
> }
>
> -static void __stack_depot_print(depot_stack_handle_t stack_depot)
> +static void __drm_stack_depot_print(depot_stack_handle_t stack_depot)
> {
> struct drm_printer p = drm_debug_printer("drm_modeset_lock");
> unsigned long *entries;
> @@ -108,11 +108,11 @@ static void __stack_depot_print(depot_stack_handle_t
> stack_depot)
> kfree(buf);
> }
> #else /* CONFIG_DRM_DEBUG_MODESET_LOCK */
> -static depot_stack_handle_t __stack_depot_save(void)
> +static depot_stack_handle_t __drm_stack_depot_save(void)
> {
> return 0;
> }
> -static void __stack_depot_print(depot_stack_handle_t stack_depot)
> +static void __drm_stack_depot_print(depot_stack_handle_t stack_depot)
> {
> }
> #endif /* CONFIG_DRM_DEBUG_MODESET_LOCK */
> @@ -266,7 +266,7 @@ EXPORT_SYMBOL(drm_modeset_acquire_fini);
> void drm_modeset_drop_locks(struct drm_modeset_acquire_ctx *ctx)
> {
> if (WARN_ON(ctx->contended))
> - __stack_depot_print(ctx->stack_depot);
> + __drm_stack_depot_print(ctx->stack_depot);
>
> while (!list_empty(>locked)) {
> struct drm_modeset_lock *lock;
> @@ -286,7 +286,7 @@ static inline int modeset_lock(struct drm_modeset_lock
> *lock,
> int ret;
>
> if (WARN_ON(ctx->contended))
> - __stack_depot_print(ctx->stack_depot);
> + __drm_stack_depot_print(ctx->stack_depot);
>
> if (ctx->trylock_only) {
> lockdep_assert_held(>ww_ctx);
> @@ -317,7 +317,7 @@ static inline int modeset_lock(struct drm_modeset_lock
> *lock,
> ret = 0;
> } else if (ret == -EDEADLK) {
> ctx->contended = lock;
> - ctx->stack_depot = __stack_depot_save();
> + ctx->stack_depot = __drm_stack_depot_save();
> }
>
> return ret;
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
On Tue, Oct 19, 2021 at 01:24:51PM +0300, Jani Nikula wrote: > On Mon, 18 Oct 2021, Vandita Kulkarni wrote: > > MIPI DSI transcoder cannot be in video mode to support any of the > > display C states. > > Imre, could you review this one please? > > The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and > POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and > POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account. You mean they are not listed in the power_domain->power_well mappings. Those power domains don't use any power wells above PW#1. PW#0/1 is handled "automatically" by DMC, so we don't have to toggle the power for those manually. However they still need a runtime PM reference, since whatever HW domain you want to use, the PCI device must be in the runtime resumed state. This is ensured by the always-on power well, which every domain has a dependency on. The transcoder power domains are acquired in get_crtc_power_domains(), doesn't the DSI encoder using the DSI_A/C transcoders? Yes, POWER_DOMAIN_TRANSCODER is now broken wrt. DSI due to POWER_DOMAIN_TRANSCODER_VDSC_PW2. So that would need to be moved after the TRANSCODER_DSI_C. And the POWER_DOMAIN_TRANSCODER macro could be also simplified afaics. Otherwise this patch looks ok to me, just the bspec links would be good to have here too. > > > Signed-off-by: Vandita Kulkarni > > --- > > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 709569211c85..8406db5e573e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct > > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_MODESET) | \ > > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > - BIT_ULL(POWER_DOMAIN_INIT)) > > + BIT_ULL(POWER_DOMAIN_INIT)) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DSI) > > Everywhere else POWER_DOMAIN_INIT is last in the list. > > BR, > Jani. > > > > > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS > > BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) > > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS > > BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) > > -- > Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/dp: Add missing TPS4 programming bits
On Tue, Oct 19, 2021 at 02:52:15PM +0300, Jani Nikula wrote:
> On Mon, 19 Jul 2021, Khaled Almahallawy wrote:
> > Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to Specs:50484).
> > TPS4 is CP2520 Pattern 3 (refer to DP2.0 spaces Table 3-11, DPCD 00248h
> > LINK_QUAL_PATTERN_SELECT, and DP PHY 1.4 CTS - Appendix A - Compliance
> > EYE Pattern(CP2520; Normative))
> >
> > For TPS4, setting bits 20:19 to value != 00b, leads to a non-TPS4 pattern.
> > This is confirmed using DP Scope running DP1.4 PHY CTS.
> >
> > To avoid any accidental wrong setting of bits 20:19, set it correctly for
> > TPS4 LT pattern selection. This programming sequence is the same used by EV.
>
> Do we need this?
I think what we need is some place to initialize DP_TP_CTL fully.
Right now it seems to be just all RMW.
>
> BR,
> Jani.
>
> >
> > Cc: Manasi Navare
> > Cc: Ville Syrjälä
> > CC: José Roberto de Souza
> > Cc: Imre Deak
> > Signed-off-by: Khaled Almahallawy
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 26a3aa73fcc4..54b4b28fdc74 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3412,6 +3412,8 @@ static void intel_ddi_set_link_train(struct intel_dp
> > *intel_dp,
> > break;
> > case DP_TRAINING_PATTERN_4:
> > temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> > + temp &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> > + temp |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
> > break;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 943fe485c662..a65998df9994 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10176,6 +10176,10 @@ enum skl_power_gate {
> > #define DP_TP_CTL_MODE_SST(0 << 27)
> > #define DP_TP_CTL_MODE_MST(1 << 27)
> > #define DP_TP_CTL_FORCE_ACT (1 << 25)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> > +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
> > #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
> > #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
> > #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] drm/i915/dp: Add missing TPS4 programming bits
On Mon, 19 Jul 2021, Khaled Almahallawy wrote:
> Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to Specs:50484).
> TPS4 is CP2520 Pattern 3 (refer to DP2.0 spaces Table 3-11, DPCD 00248h
> LINK_QUAL_PATTERN_SELECT, and DP PHY 1.4 CTS - Appendix A - Compliance
> EYE Pattern(CP2520; Normative))
>
> For TPS4, setting bits 20:19 to value != 00b, leads to a non-TPS4 pattern.
> This is confirmed using DP Scope running DP1.4 PHY CTS.
>
> To avoid any accidental wrong setting of bits 20:19, set it correctly for
> TPS4 LT pattern selection. This programming sequence is the same used by EV.
Do we need this?
BR,
Jani.
>
> Cc: Manasi Navare
> Cc: Ville Syrjälä
> CC: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: Khaled Almahallawy
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 4
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 26a3aa73fcc4..54b4b28fdc74 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3412,6 +3412,8 @@ static void intel_ddi_set_link_train(struct intel_dp
> *intel_dp,
> break;
> case DP_TRAINING_PATTERN_4:
> temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + temp &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> + temp |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
> break;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe485c662..a65998df9994 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10176,6 +10176,10 @@ enum skl_power_gate {
> #define DP_TP_CTL_MODE_SST (0 << 27)
> #define DP_TP_CTL_MODE_MST (1 << 27)
> #define DP_TP_CTL_FORCE_ACT (1 << 25)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
> #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
> #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
> #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, October 19, 2021 5:16 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Deak, Imre ; Roper, Matthew D
>
> Subject: RE: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>
> On Tue, 19 Oct 2021, "Kulkarni, Vandita"
> wrote:
> >> -Original Message-
> >> From: Nikula, Jani
> >> Sent: Tuesday, October 19, 2021 3:48 PM
> >> To: Kulkarni, Vandita ; intel-
> >> g...@lists.freedesktop.org
> >> Cc: Deak, Imre ; Roper, Matthew D
> >> ; Kulkarni, Vandita
> >>
> >> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling
> >> the phy
> >>
> >> On Mon, 18 Oct 2021, Vandita Kulkarni
> wrote:
> >> > For the PHY enable/disable signalling to propagate between Dispaly
> >> > and PHY, DDI clocks need to be running when enabling the PHY.
> >> >
> >>
> >> A bspec reference would be useful:
> >>
> >> Bspec: NNN
> >>
> >> > Signed-off-by: Vandita Kulkarni
> >> > ---
> >> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
> >> > 1 file changed, 3 insertions(+), 5 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > index 8c166f92f8bd..77cd01ecfa80 100644
> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > @@ -1135,8 +1135,6 @@ static void
> >> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> >> >const struct intel_crtc_state
> >> > *crtc_state) {
> >> > -struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >> > -
> >> > /* step 4a: power up all lanes of the DDI used by DSI */
> >> > gen11_dsi_power_up_lanes(encoder);
> >> >
> >> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> > /* step 4c: configure voltage swing and skew */
> >> > gen11_dsi_voltage_swing_program_seq(encoder);
> >> >
> >> > +gen11_dsi_ungate_clocks(encoder);
> >> > +
> >> > /* enable DDI buffer */
> >> > gen11_dsi_enable_ddi_buffer(encoder);
> >> >
> >> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> >> intel_encoder *encoder,
> >> > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> >> > gen11_dsi_configure_transcoder(encoder, crtc_state);
> >> >
> >> > -/* Step 4l: Gate DDI clocks */
> >> > -if (DISPLAY_VER(dev_priv) == 11)
> >> > -gen11_dsi_gate_clocks(encoder);
> >> > +gen11_dsi_gate_clocks(encoder);
> >>
> >> So how does this relate to
> >> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll
> >> mapping")
> >
> > As per the latest bspec, this change doesn't seem to be valid anymore.
> > It is marked with removed tag.
> > When TGL got added this change came in.
> >
> > But now with ADL the whole thing is marked as removed.
> > So, Do you suggest that I submit a revert for this change ?
>
> No, just an explanation and maybe that commit reference in the commit
> message.
Okay, will do that.
Thanks,
Vandita
>
> BR,
> Jani.
>
> >
> > Thanks,
> > Vandita
> >>
> >> > }
> >> >
> >> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
On Tue, 19 Oct 2021, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, October 19, 2021 3:48 PM
>> To: Kulkarni, Vandita ; intel-
>> g...@lists.freedesktop.org
>> Cc: Deak, Imre ; Roper, Matthew D
>> ; Kulkarni, Vandita
>>
>> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>>
>> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
>> > For the PHY enable/disable signalling to propagate between Dispaly and
>> > PHY, DDI clocks need to be running when enabling the PHY.
>> >
>>
>> A bspec reference would be useful:
>>
>> Bspec: NNN
>>
>> > Signed-off-by: Vandita Kulkarni
>> > ---
>> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
>> > 1 file changed, 3 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 8c166f92f8bd..77cd01ecfa80 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1135,8 +1135,6 @@ static void
>> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> > const struct intel_crtc_state *crtc_state)
>> > {
>> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > -
>> >/* step 4a: power up all lanes of the DDI used by DSI */
>> >gen11_dsi_power_up_lanes(encoder);
>> >
>> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> >/* step 4c: configure voltage swing and skew */
>> >gen11_dsi_voltage_swing_program_seq(encoder);
>> >
>> > + gen11_dsi_ungate_clocks(encoder);
>> > +
>> >/* enable DDI buffer */
>> >gen11_dsi_enable_ddi_buffer(encoder);
>> >
>> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>> >/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> >gen11_dsi_configure_transcoder(encoder, crtc_state);
>> >
>> > - /* Step 4l: Gate DDI clocks */
>> > - if (DISPLAY_VER(dev_priv) == 11)
>> > - gen11_dsi_gate_clocks(encoder);
>> > + gen11_dsi_gate_clocks(encoder);
>>
>> So how does this relate to
>> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
>
> As per the latest bspec, this change doesn't seem to be valid anymore.
> It is marked with removed tag.
> When TGL got added this change came in.
>
> But now with ADL the whole thing is marked as removed.
> So, Do you suggest that I submit a revert for this change ?
No, just an explanation and maybe that commit reference in the commit
message.
BR,
Jani.
>
> Thanks,
> Vandita
>>
>> > }
>> >
>> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
On Tue, 19 Oct 2021, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, October 19, 2021 3:44 PM
>> To: Kulkarni, Vandita ; intel-
>> g...@lists.freedesktop.org
>> Cc: Deak, Imre ; Roper, Matthew D
>> ; Kulkarni, Vandita
>>
>> Subject: Re: [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
>>
>> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
>> > Update ADL_P device info to support DSI0, DSI1
>> >
>> > Signed-off-by: Vandita Kulkarni
>> > ---
>> > drivers/gpu/drm/i915/i915_pci.c | 31 -
>> --
>> > 1 file changed, 28 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > b/drivers/gpu/drm/i915/i915_pci.c index 169837de395d..a2dd5a38fdf5
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info =
>> > { #define XE_LPD_FEATURES \
>> >.abox_mask = GENMASK(1, 0),
>> \
>> >.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
>> \
>> > - .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> \
>> >.dbuf.size = 4096,
>> \
>> >.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
>> \
>> >BIT(DBUF_S4),
>> \
>> > @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
>> >.display.has_psr = 1,
>> \
>> >.display.ver = 13,
>> \
>> >.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> \
>> > + XE_LPD_CURSOR_OFFSETS
>> > +
>> > +#define ADLP_TRANSCODERS \
>> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
>> \
>> > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>> \
>> >.pipe_offsets = {
>> \
>> >[TRANSCODER_A] = PIPE_A_OFFSET,
>> \
>> >[TRANSCODER_B] = PIPE_B_OFFSET,
>> \
>> >[TRANSCODER_C] = PIPE_C_OFFSET,
>> \
>> >[TRANSCODER_D] = PIPE_D_OFFSET,
>> \
>> > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
>> \
>> > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
>> \
>> >},
>> \
>> >.trans_offsets = {
>> \
>> >[TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> \
>> >[TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> \
>> >[TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> \
>> >[TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> \
>> > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
>> \
>> > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
>> \
>>
>> I think you could just add these changes to XE_LPD_FEATURES, and have
>> separate .cpu_transcoder_mask initialization for ADLP and DG2.
>
> Okay got it. So its ok to have the pipe_offsets or transcoder offsets added
> unless we are not defining it in the .cpu_transcoder_mask
> Will make this change.
Yeah, the *_offsets are only used if referenced, and having them should
not make a difference. It's the .cpu_transcoder_mask and .pipe_mask that
matter.
BR,
Hani.
>
> Thanks,
> Vandita
>>
>> Compare GEN12_FEATURES.
>>
>> BR,
>> Jani.
>>
>> > + }
>> \
>> > +
>> > +#define DG2_TRANSCODERS \
>> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) | \
>> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> \
>> > + .pipe_offsets = {
>> \
>> > + [TRANSCODER_A] = PIPE_A_OFFSET,
>> \
>> > + [TRANSCODER_B] = PIPE_B_OFFSET,
>> \
>> > + [TRANSCODER_C] = PIPE_C_OFFSET,
>> \
>> > + [TRANSCODER_D] = PIPE_D_OFFSET,
>> \
>> >},
>> \
>> > - XE_LPD_CURSOR_OFFSETS
>> > + .trans_offsets = {
>> \
>> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> \
>> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> \
>> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> \
>> > + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> \
>> > + }
>> \
>> >
>> > static const struct intel_device_info adl_p_info = {
>> >GEN12_FEATURES,
>> >XE_LPD_FEATURES,
>> > + ADLP_TRANSCODERS,
>> >PLATFORM(INTEL_ALDERLAKE_P),
>> >.require_force_probe = 1,
>> >.display.has_cdclk_crawl = 1,
>> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
>> >XE_HP_FEATURES,
>> >XE_HPM_FEATURES,
>> >XE_LPD_FEATURES,
>> > + DG2_TRANSCODERS,
>> >DGFX_FEATURES,
>> >.graphics_rel = 55,
>> >.media_rel = 55,
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> -Original Message-
> From: Intel-gfx On Behalf Of
> Kulkarni, Vandita
> Sent: Tuesday, October 19, 2021 5:03 PM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre ; Roper, Matthew D
>
> Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before
> enabling the phy
>
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Tuesday, October 19, 2021 3:48 PM
> > To: Kulkarni, Vandita ; intel-
> > g...@lists.freedesktop.org
> > Cc: Deak, Imre ; Roper, Matthew D
> > ; Kulkarni, Vandita
> >
> > Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling
> > the phy
> >
> > On Mon, 18 Oct 2021, Vandita Kulkarni
> wrote:
> > > For the PHY enable/disable signalling to propagate between Dispaly
> > > and PHY, DDI clocks need to be running when enabling the PHY.
> > >
> >
> > A bspec reference would be useful:
> >
> > Bspec: NNN
Bspec: 49187
> >
> > > Signed-off-by: Vandita Kulkarni
> > > ---
> > > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
> > > 1 file changed, 3 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > index 8c166f92f8bd..77cd01ecfa80 100644
> > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > @@ -1135,8 +1135,6 @@ static void
> > > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state) {
> > > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > -
> > > /* step 4a: power up all lanes of the DDI used by DSI */
> > > gen11_dsi_power_up_lanes(encoder);
> > >
> > > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> > intel_encoder *encoder,
> > > /* step 4c: configure voltage swing and skew */
> > > gen11_dsi_voltage_swing_program_seq(encoder);
> > >
> > > + gen11_dsi_ungate_clocks(encoder);
> > > +
> > > /* enable DDI buffer */
> > > gen11_dsi_enable_ddi_buffer(encoder);
> > >
> > > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> > intel_encoder *encoder,
> > > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> > > gen11_dsi_configure_transcoder(encoder, crtc_state);
> > >
> > > - /* Step 4l: Gate DDI clocks */
> > > - if (DISPLAY_VER(dev_priv) == 11)
> > > - gen11_dsi_gate_clocks(encoder);
> > > + gen11_dsi_gate_clocks(encoder);
> >
> > So how does this relate to
> > 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll
> > mapping")
>
> As per the latest bspec, this change doesn't seem to be valid anymore.
> It is marked with removed tag.
> When TGL got added this change came in.
>
> But now with ADL the whole thing is marked as removed.
And the gating is now added after enabling DDI Buffer
> So, Do you suggest that I submit a revert for this change ?
>
> Thanks,
> Vandita
> >
> > > }
> > >
> > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH] Revert "drm/i915/bios: gracefully disable dual eDP for now"
This reverts commit 05734ca2a8f76c9eb3890b3c9dfc3467f03105c1.
It's not graceful, instead it leads to boot time warning splats in the
case it is supposed to handle gracefully. Apparently the BIOS/GOP
enabling the port we end up skipping leads to state readout
problems. Back to the drawing board.
References:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21255/bat-adlp-4/boot0.txt
Fixes: 05734ca2a8f7 ("drm/i915/bios: gracefully disable dual eDP for now")
Cc: José Roberto de Souza
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Swati Sharma
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 47 ---
1 file changed, 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index b99907c656bb..f9776ca85de3 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1930,50 +1930,6 @@ static int _intel_bios_max_tmds_clock(const struct
intel_bios_encoder_data *devd
}
}
-static enum port get_edp_port(struct drm_i915_private *i915)
-{
- const struct intel_bios_encoder_data *devdata;
- enum port port;
-
- for_each_port(port) {
- devdata = i915->vbt.ports[port];
-
- if (devdata && intel_bios_encoder_supports_edp(devdata))
- return port;
- }
-
- return PORT_NONE;
-}
-
-/*
- * FIXME: The power sequencer and backlight code currently do not support more
- * than one set registers, at least not on anything other than VLV/CHV. It will
- * clobber the registers. As a temporary workaround, gracefully prevent more
- * than one eDP from being registered.
- */
-static void sanitize_dual_edp(struct intel_bios_encoder_data *devdata,
- enum port port)
-{
- struct drm_i915_private *i915 = devdata->i915;
- struct child_device_config *child = >child;
- enum port p;
-
- /* CHV might not clobber PPS registers. */
- if (IS_CHERRYVIEW(i915))
- return;
-
- p = get_edp_port(i915);
- if (p == PORT_NONE)
- return;
-
- drm_dbg_kms(>drm, "both ports %c and %c configured as eDP, "
- "disabling port %c eDP\n", port_name(p), port_name(port),
- port_name(port));
-
- child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
- child->device_type &= ~DEVICE_TYPE_INTERNAL_CONNECTOR;
-}
-
static bool is_port_valid(struct drm_i915_private *i915, enum port port)
{
/*
@@ -2031,9 +1987,6 @@ static void parse_ddi_port(struct drm_i915_private *i915,
supports_typec_usb, supports_tbt,
devdata->dsc != NULL);
- if (is_edp)
- sanitize_dual_edp(devdata, port);
-
if (is_dvi)
sanitize_ddc_pin(devdata, port);
--
2.30.2
Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, October 19, 2021 3:44 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Deak, Imre ; Roper, Matthew D
> ; Kulkarni, Vandita
>
> Subject: Re: [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
>
> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> > Update ADL_P device info to support DSI0, DSI1
> >
> > Signed-off-by: Vandita Kulkarni
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 31 -
> --
> > 1 file changed, 28 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index 169837de395d..a2dd5a38fdf5
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info =
> > { #define XE_LPD_FEATURES \
> > .abox_mask = GENMASK(1, 0),
> \
> > .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
> \
> > - .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> > .dbuf.size = 4096,
> \
> > .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> > BIT(DBUF_S4),
> \
> > @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
> > .display.has_psr = 1,
> \
> > .display.ver = 13,
> \
> > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> \
> > + XE_LPD_CURSOR_OFFSETS
> > +
> > +#define ADLP_TRANSCODERS \
> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> \
> > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> \
> > .pipe_offsets = {
> \
> > [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> > [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> > [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> > [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> \
> > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> \
> > },
> \
> > .trans_offsets = {
> \
> > [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> > [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> > [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> > [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> \
> > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> \
>
> I think you could just add these changes to XE_LPD_FEATURES, and have
> separate .cpu_transcoder_mask initialization for ADLP and DG2.
Okay got it. So its ok to have the pipe_offsets or transcoder offsets added
unless we are not defining it in the .cpu_transcoder_mask
Will make this change.
Thanks,
Vandita
>
> Compare GEN12_FEATURES.
>
> BR,
> Jani.
>
> > + }
> \
> > +
> > +#define DG2_TRANSCODERS \
> > + .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) | \
> > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> > + .pipe_offsets = {
> \
> > + [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> > + [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> > + [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> > + [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> > },
> \
> > - XE_LPD_CURSOR_OFFSETS
> > + .trans_offsets = {
> \
> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> > + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> > + }
> \
> >
> > static const struct intel_device_info adl_p_info = {
> > GEN12_FEATURES,
> > XE_LPD_FEATURES,
> > + ADLP_TRANSCODERS,
> > PLATFORM(INTEL_ALDERLAKE_P),
> > .require_force_probe = 1,
> > .display.has_cdclk_crawl = 1,
> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
> > XE_HP_FEATURES,
> > XE_HPM_FEATURES,
> > XE_LPD_FEATURES,
> > + DG2_TRANSCODERS,
> > DGFX_FEATURES,
> > .graphics_rel = 55,
> > .media_rel = 55,
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, October 19, 2021 3:48 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Deak, Imre ; Roper, Matthew D
> ; Kulkarni, Vandita
>
> Subject: Re: [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
>
> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> > For the PHY enable/disable signalling to propagate between Dispaly and
> > PHY, DDI clocks need to be running when enabling the PHY.
> >
>
> A bspec reference would be useful:
>
> Bspec: NNN
>
> > Signed-off-by: Vandita Kulkarni
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
> > 1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 8c166f92f8bd..77cd01ecfa80 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1135,8 +1135,6 @@ static void
> > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -
> > /* step 4a: power up all lanes of the DDI used by DSI */
> > gen11_dsi_power_up_lanes(encoder);
> >
> > @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> > /* step 4c: configure voltage swing and skew */
> > gen11_dsi_voltage_swing_program_seq(encoder);
> >
> > + gen11_dsi_ungate_clocks(encoder);
> > +
> > /* enable DDI buffer */
> > gen11_dsi_enable_ddi_buffer(encoder);
> >
> > @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> > /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> > gen11_dsi_configure_transcoder(encoder, crtc_state);
> >
> > - /* Step 4l: Gate DDI clocks */
> > - if (DISPLAY_VER(dev_priv) == 11)
> > - gen11_dsi_gate_clocks(encoder);
> > + gen11_dsi_gate_clocks(encoder);
>
> So how does this relate to
> 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
As per the latest bspec, this change doesn't seem to be valid anymore.
It is marked with removed tag.
When TGL got added this change came in.
But now with ADL the whole thing is marked as removed.
So, Do you suggest that I submit a revert for this change ?
Thanks,
Vandita
>
> > }
> >
> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, October 19, 2021 4:21 PM
> To: Nikula, Jani
> Cc: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org; Deak, Imre ; Roper,
> Matthew D
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for
> wakeup GB
>
> On Tue, Oct 19, 2021 at 01:41:50PM +0300, Ville Syrjälä wrote:
> > On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> > > On Tue, 19 Oct 2021, Ville Syrjälä wrote:
> > > > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> > > >> On Mon, 18 Oct 2021, Vandita Kulkarni
> wrote:
> > > >>
> > > >> Commit message goes here.
> > > >>
> > > >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP
> > > >> > to HS wakeup guardband")
> > > >> > Signed-off-by: Vandita Kulkarni
> > > >> > ---
> > > >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > > >> > drivers/gpu/drm/i915/i915_reg.h| 3 ++-
> > > >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> > > >> >
> > > >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > index 9ee62707ec72..8c166f92f8bd 100644
> > > >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > >> > @@ -1271,7 +1271,7 @@ static void
> adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> > > >> > if (DISPLAY_VER(i915) == 13) {
> > > >> > for_each_dsi_port(port, intel_dsi->ports)
> > > >> > intel_de_rmw(i915,
> TGL_DSI_CHKN_REG(port),
> > > >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> > > >> > + TGL_DSI_CHKN_LSHS_GB_MASK,
> > > >> > +TGL_DSI_CHKN_LSHS_GB_MASK);
> > > >>
> > > >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
Yes, my bad.
> > > >
> > > > IMO the value should never be named that. It should be
> > > > TGL_DSI_CHKN_LSHS_GB_.
> > >
> > > Alternatively,
> > >
> > > #define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
> > >
> > > and
> > >
> > > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > >TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
> > >
> > > ?
> > >
> > > We're using the value in a specific place that references a w/a, so
> > > the magic 4 isn't too bad.
This seems more appropriate will make this change.
Thanks.
> >
> > Yeah, for parametrized defines I think the "_" is not
> > needed. Probably not even desired. The argument passed in is the
> > "_" essentially.
>
> Oh and, yes, I think having the magic number in the code is fine for cases
> like
> this. I'd say I probably even prefer it that way.
> As long as the whole register value isn't a single magic hex constant that I
> have to decode by hand to see what bitfields are getting what values.
Thanks, will use the hardcoding in icl_dsi.
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Tue, Oct 19, 2021 at 01:41:50PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> > On Tue, 19 Oct 2021, Ville Syrjälä wrote:
> > > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> > >> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> > >>
> > >> Commit message goes here.
> > >>
> > >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS
> > >> > wakeup guardband")
> > >> > Signed-off-by: Vandita Kulkarni
> > >> > ---
> > >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > >> > drivers/gpu/drm/i915/i915_reg.h| 3 ++-
> > >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > index 9ee62707ec72..8c166f92f8bd 100644
> > >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > >> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct
> > >> > intel_encoder *encoder)
> > >> >if (DISPLAY_VER(i915) == 13) {
> > >> >for_each_dsi_port(port, intel_dsi->ports)
> > >> >intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> > >> > + TGL_DSI_CHKN_LSHS_GB_MASK,
> > >> > TGL_DSI_CHKN_LSHS_GB_MASK);
> > >>
> > >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
> > >
> > > IMO the value should never be named that. It should be
> > > TGL_DSI_CHKN_LSHS_GB_.
> >
> > Alternatively,
> >
> > #define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
> > REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
> >
> > and
> >
> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
> >
> > ?
> >
> > We're using the value in a specific place that references a w/a, so the
> > magic 4 isn't too bad.
>
> Yeah, for parametrized defines I think the "_" is
> not needed. Probably not even desired. The argument passed in
> is the "_" essentially.
Oh and, yes, I think having the magic number in the code is fine
for cases like this. I'd say I probably even prefer it that way.
As long as the whole register value isn't a single magic hex constant
that I have to decode by hand to see what bitfields are getting what
values.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Tue, Oct 19, 2021 at 01:28:10PM +0300, Jani Nikula wrote:
> On Tue, 19 Oct 2021, Ville Syrjälä wrote:
> > On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> >> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> >>
> >> Commit message goes here.
> >>
> >> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS
> >> > wakeup guardband")
> >> > Signed-off-by: Vandita Kulkarni
> >> > ---
> >> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> >> > drivers/gpu/drm/i915/i915_reg.h| 3 ++-
> >> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > index 9ee62707ec72..8c166f92f8bd 100644
> >> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct
> >> > intel_encoder *encoder)
> >> > if (DISPLAY_VER(i915) == 13) {
> >> > for_each_dsi_port(port, intel_dsi->ports)
> >> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> >> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
> >> > + TGL_DSI_CHKN_LSHS_GB_MASK,
> >> > TGL_DSI_CHKN_LSHS_GB_MASK);
> >>
> >> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
> >
> > IMO the value should never be named that. It should be
> > TGL_DSI_CHKN_LSHS_GB_.
>
> Alternatively,
>
> #define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
>
> and
>
> intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
>TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
>
> ?
>
> We're using the value in a specific place that references a w/a, so the
> magic 4 isn't too bad.
Yeah, for parametrized defines I think the "_" is
not needed. Probably not even desired. The argument passed in
is the "_" essentially.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Tue, 19 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
>>
>> Commit message goes here.
>>
>> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS
>> > wakeup guardband")
>> > Signed-off-by: Vandita Kulkarni
>> > ---
>> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
>> > drivers/gpu/drm/i915/i915_reg.h| 3 ++-
>> > 2 files changed, 3 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > index 9ee62707ec72..8c166f92f8bd 100644
>> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct
>> > intel_encoder *encoder)
>> >if (DISPLAY_VER(i915) == 13) {
>> >for_each_dsi_port(port, intel_dsi->ports)
>> >intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
>> > - TGL_DSI_CHKN_LSHS_GB, 0x4);
>> > + TGL_DSI_CHKN_LSHS_GB_MASK,
>> > TGL_DSI_CHKN_LSHS_GB_MASK);
>>
>> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
>
> IMO the value should never be named that. It should be
> TGL_DSI_CHKN_LSHS_GB_.
Alternatively,
#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)
REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, (byte_clocks))
and
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB(4));
?
We're using the value in a specific place that references a w/a, so the
magic 4 isn't too bad.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
On Mon, 18 Oct 2021, Vandita Kulkarni wrote: > MIPI DSI transcoder cannot be in video mode to support any of the > display C states. Imre, could you review this one please? The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account. > Signed-off-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index 709569211c85..8406db5e573e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > BIT_ULL(POWER_DOMAIN_MODESET) | \ > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > - BIT_ULL(POWER_DOMAIN_INIT)) > + BIT_ULL(POWER_DOMAIN_INIT)) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DSI) Everywhere else POWER_DOMAIN_INIT is last in the list. BR, Jani. > > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS > BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS > BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy
On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> For the PHY enable/disable signalling to propagate
> between Dispaly and PHY, DDI clocks need to be running when
> enabling the PHY.
>
A bspec reference would be useful:
Bspec: NNN
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 8c166f92f8bd..77cd01ecfa80 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1135,8 +1135,6 @@ static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
> /* step 4a: power up all lanes of the DDI used by DSI */
> gen11_dsi_power_up_lanes(encoder);
>
> @@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
> *encoder,
> /* step 4c: configure voltage swing and skew */
> gen11_dsi_voltage_swing_program_seq(encoder);
>
> + gen11_dsi_ungate_clocks(encoder);
> +
> /* enable DDI buffer */
> gen11_dsi_enable_ddi_buffer(encoder);
>
> @@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
> *encoder,
> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> gen11_dsi_configure_transcoder(encoder, crtc_state);
>
> - /* Step 4l: Gate DDI clocks */
> - if (DISPLAY_VER(dev_priv) == 11)
> - gen11_dsi_gate_clocks(encoder);
> + gen11_dsi_gate_clocks(encoder);
So how does this relate to
991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
> }
>
> static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
>
> Commit message goes here.
>
> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
> > guardband")
> > Signed-off-by: Vandita Kulkarni
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h| 3 ++-
> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 9ee62707ec72..8c166f92f8bd 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct
> > intel_encoder *encoder)
> > if (DISPLAY_VER(i915) == 13) {
> > for_each_dsi_port(port, intel_dsi->ports)
> > intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> > -TGL_DSI_CHKN_LSHS_GB, 0x4);
> > +TGL_DSI_CHKN_LSHS_GB_MASK,
> > TGL_DSI_CHKN_LSHS_GB_MASK);
>
> I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
IMO the value should never be named that. It should be
TGL_DSI_CHKN_LSHS_GB_.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
> Update ADL_P device info to support DSI0, DSI1
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/i915_pci.c | 31 ---
> 1 file changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..a2dd5a38fdf5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info = {
> #define XE_LPD_FEATURES \
> .abox_mask = GENMASK(1, 0),
> \
> .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
> \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> .dbuf.size = 4096,
> \
> .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> BIT(DBUF_S4),
> \
> @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
> .display.has_psr = 1,
> \
> .display.ver = 13,
> \
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> \
> + XE_LPD_CURSOR_OFFSETS
> +
> +#define ADLP_TRANSCODERS \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> \
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> \
> .pipe_offsets = {
> \
> [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> \
> },
> \
> .trans_offsets = {
> \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> \
I think you could just add these changes to XE_LPD_FEATURES, and have
separate .cpu_transcoder_mask initialization for ADLP and DG2.
Compare GEN12_FEATURES.
BR,
Jani.
> + }
> \
> +
> +#define DG2_TRANSCODERS \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> + .pipe_offsets = {
> \
> + [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> + [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> + [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> + [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> },
> \
> - XE_LPD_CURSOR_OFFSETS
> + .trans_offsets = {
> \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> + }
> \
>
> static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> XE_LPD_FEATURES,
> + ADLP_TRANSCODERS,
> PLATFORM(INTEL_ALDERLAKE_P),
> .require_force_probe = 1,
> .display.has_cdclk_crawl = 1,
> @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
> XE_HP_FEATURES,
> XE_HPM_FEATURES,
> XE_LPD_FEATURES,
> +
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
Commit message goes here.
> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
> guardband")
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h| 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9ee62707ec72..8c166f92f8bd 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct
> intel_encoder *encoder)
> if (DISPLAY_VER(i915) == 13) {
> for_each_dsi_port(port, intel_dsi->ports)
> intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> - TGL_DSI_CHKN_LSHS_GB, 0x4);
> + TGL_DSI_CHKN_LSHS_GB_MASK,
> TGL_DSI_CHKN_LSHS_GB_MASK);
I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.
BR,
Jani.
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..e4b1f80ca5eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11728,7 +11728,8 @@ enum skl_power_gate {
> #define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
> _TGL_DSI_CHKN_REG_0, \
> _TGL_DSI_CHKN_REG_1)
> -#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB_MASKREG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
>
> /* Display Stream Splitter Control */
> #define DSS_CTL1 _MMIO(0x67400)
--
Jani Nikula, Intel Open Source Graphics Center
