date:20220325

On Wed, Mar 23, 2022 at 10:17:49PM +0200, Imre Deak wrote:
> Accessing the DDI_BUF_CTL register without the port's DDI clock being
> enabled (to set/clear the TypeC PHY ownership for the port) can lead to
> a corrupted value read during any i915 register access right after the
> DDI clock is enabled.
> 
> The root cause is the way clock synchronization works for this register,
> controlled by the CHICKEN_DCPR_1 DDI_CLOCK_REG_ACCESS flag. Correctly
> this flag should be cleared on ADLP (see the Bspec link below), however
> after bootup the flag is set.
> 
> One easily reproducible issue is an unclaimed register access of the
> PWR_WELL_CTL_DDI2 register, programmed right after DDI clock enabling to
> enable the port's DDI_IO power well (see the HSDES, VLK links below).
> With the correct setting above this problem can't be reproduced.
> 
> Bspec: 49189
> HSDES: 18019028154
> VLK: 28328, 28655
> 
> Cc: Jouni Högander 
> Cc: Arthur J Runyan 
> Signed-off-by: Imre Deak 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d652f19ff93..d83bd7a75c788 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5939,6 +5939,7 @@
>  #define   ICL_DELAY_PMRSPREG_BIT(22)
>  #define   DISABLE_FLR_SRCREG_BIT(15)
>  #define   MASK_WAKEMEM   REG_BIT(13)
> +#define   DDI_CLOCK_REG_ACCESS   REG_BIT(7)
>  
>  #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
>  #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2c3cd4d775daf..4291963013c51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7470,6 +7470,9 @@ static void adlp_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  
>   /* Wa_22011091694:adlp */
>   intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
> +
> + /* Bspec/49189 Initialize Sequence */
> + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
>  }
>  
>  static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

2022-03-25 Thread Ceraolo Spurio, Daniele





On 3/25/2022 11:37 AM, Das, Nirmoy wrote:


On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:

In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if something goes wrong
during the wait, leading to us hitting a GEM_BUG_ON in the GuC wait
function.
To fix this, make sure to only return the timeout if it is positive.

Fixes: b97060a99b01b ("drm/i915/guc: Update intel_gt_wait_for_idle to 
work with GuC")

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matthew Brost 
Cc: John Harrison 
---
  drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c

index edb881d756309..ef70c209976d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -197,7 +197,7 @@ out_active: spin_lock(>lock);
  active_count++;
    if (remaining_timeout)
-    *remaining_timeout = timeout;
+    *remaining_timeout = timeout > 0 ? timeout : 0;



Should the last flush_submission() be  "if ( timeout > 0 
&_submission(gt, timeout))" ?


I considered it, but flush_submission only checks for timeout != 0 so it 
won't accidentally make use of a negative value thinking it's positive. 
I don't know if the flush is purposely done even if timeout is negative 
or if that's a mistake, but that code has been there long before we 
modified the function to return the remaining timeout and never seems to 
have caused issues, so I decided not to change it.


Daniele




Nirmoy


    return active_count ? timeout : 0;
  }

[Intel-gfx] ✗ Fi.CI.BAT: failure for docs: gpu: i915.rst: Fix DRRS documentation

== Series Details ==

Series: docs: gpu: i915.rst: Fix DRRS documentation
URL   : https://patchwork.freedesktop.org/series/101806/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22691


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22691 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22691, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/index.html

Participating hosts (46 -> 33)
--

  Additional (1): fi-pnv-d510 
  Missing(14): fi-bdw-samus shard-tglu bat-dg1-6 bat-dg2-8 bat-dg2-9 
fi-bsw-cyan bat-adlp-6 fi-cfl-guc bat-adlp-4 bat-hsw-1 bat-rpls-1 bat-rpls-2 
bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22691:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-elk-e7500:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html
- fi-bsw-n3050:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html
- fi-glk-dsi: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_linear_blits@basic:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-pnv-d510/igt@gem_render_linear_bl...@basic.html
- fi-snb-2520m:   [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-snb-2520m/igt@gem_render_linear_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-snb-2520m/igt@gem_render_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-cfl-8109u:   [PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-cfl-8109u/igt@gem_render_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-cfl-8109u/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-ilk-650: NOTRUN -> [INCOMPLETE][10]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-ilk-650/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u:   [PASS][11] -> [INCOMPLETE][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_render_tiled_blits@basic:
- {fi-tgl-dsi}:   NOTRUN -> [INCOMPLETE][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-tgl-dsi/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- {fi-hsw-g3258}: [PASS][14] -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html

  
Known issues


  Here are the changes found in Patchwork_22691 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-kbl-x1275:   NOTRUN -> [INCOMPLETE][16] ([i915#1373])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][17] ([fdo#109271]) +9 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-ilk-650: NOTRUN -> [SKIP][18] ([fdo#109271]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-ilk-650/igt@gem_soft...@allocator-basic-reserve.html

  * igt@kms_chamelium@dp-edid-read:
- fi-elk-e7500:   NOTRUN -> [SKIP][19] ([fdo#109271]) +26 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22691/fi-elk-e7500/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050:   NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [20]:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

== Series Details ==

Series: drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout
URL   : https://patchwork.freedesktop.org/series/101805/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22690


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22690 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22690, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/index.html

Participating hosts (46 -> 32)
--

  Additional (1): fi-pnv-d510 
  Missing(15): fi-jsl-1 fi-bdw-samus shard-tglu bat-dg1-6 bat-dg2-8 
bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-hsw-1 bat-rpls-1 bat-rpls-2 
bat-jsl-2 bat-jsl-1 fi-skl-6700k2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22690:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-bsw-n3050:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-glk-dsi: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_linear_blits@basic:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-pnv-d510/igt@gem_render_linear_bl...@basic.html
- fi-snb-2520m:   [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-snb-2520m/igt@gem_render_linear_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-snb-2520m/igt@gem_render_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-bsw-nick:[PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-bsw-nick/igt@gem_render_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-bsw-nick/igt@gem_render_tiled_bl...@basic.html
- fi-kbl-7500u:   [PASS][10] -> [INCOMPLETE][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-kbl-7500u/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-kbl-7500u/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-hsw-4770:[PASS][12] -> [INCOMPLETE][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-hsw-4770/igt@gem_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-hsw-4770/igt@gem_tiled_bl...@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][14]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-ilk-650/igt@gem_tiled_bl...@basic.html
- fi-cfl-8109u:   [PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u:   [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_tiled_blits@basic:
- {fi-hsw-g3258}: [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html

  
Known issues


  Here are the changes found in Patchwork_22690 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][21] ([fdo#109315])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22690/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][22] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [22]:

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

== Series Details ==

Series: drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout
URL   : https://patchwork.freedesktop.org/series/101805/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)

== Series Details ==

Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL   : https://patchwork.freedesktop.org/series/101723/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22688


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22688 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22688, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/index.html

Participating hosts (46 -> 34)
--

  Additional (1): fi-pnv-d510 
  Missing(13): fi-bdw-samus shard-tglu bat-dg1-6 bat-dg2-8 bat-dg2-9 
fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-hsw-1 bat-rpls-1 bat-rpls-2 bat-jsl-2 
bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22688:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_linear_blits@basic:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@gem_render_linear_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-cfl-8109u:   [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u:   [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@core_hotunplug@unbind-rebind:
- {fi-hsw-g3258}: [PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html

  
Known issues


  Here are the changes found in Patchwork_22688 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +9 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-bwr-2160:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#5341])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-bwr-2160/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-bwr-2160:NOTRUN -> [SKIP][12] ([fdo#109271]) +45 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-bwr-2160/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][13] ([i915#2403] / [i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][14] ([i915#4312] / [k.org#202321])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-glk-dsi/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- {fi-adl-ddr5}:  [INCOMPLETE][15] -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_tiled_blits@basic:
- fi-bwr-2160:[INCOMPLETE][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-bwr-2160/igt@gem_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-bwr-2160/igt@gem_tiled_bl...@basic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-bsw-kefka:   [FAIL][19] ([i915#2122]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [20]:

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v7,1/3] i915/gvt: Separate the MMIO tracking table from GVT-g

== Series Details ==

Series: series starting with [v7,1/3] i915/gvt: Separate the MMIO tracking 
table from GVT-g
URL   : https://patchwork.freedesktop.org/series/101803/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_gvt_mmio_table.o
drivers/gpu/drm/i915/intel_gvt_mmio_table.c: In function ‘iterate_bxt_mmio’:
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1232:9: error: ‘BXT_DSI_PLL_CTL’ 
undeclared (first use in this function); did you mean ‘BXT_DE_PLL_CTL’?
  MMIO_D(BXT_DSI_PLL_CTL);
 ^~~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:35:56: note: in definition of macro 
‘MMIO_F’
  ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \
^~~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1232:2: note: in expansion of macro 
‘MMIO_D’
  MMIO_D(BXT_DSI_PLL_CTL);
  ^~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1232:9: note: each undeclared 
identifier is reported only once for each function it appears in
  MMIO_D(BXT_DSI_PLL_CTL);
 ^~~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:35:56: note: in definition of macro 
‘MMIO_F’
  ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \
^~~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1232:2: note: in expansion of macro 
‘MMIO_D’
  MMIO_D(BXT_DSI_PLL_CTL);
  ^~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1233:9: error: ‘BXT_DSI_PLL_ENABLE’ 
undeclared (first use in this function); did you mean ‘BXT_DE_PLL_ENABLE’?
  MMIO_D(BXT_DSI_PLL_ENABLE);
 ^~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:35:56: note: in definition of macro 
‘MMIO_F’
  ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \
^~~
drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1233:2: note: in expansion of macro 
‘MMIO_D’
  MMIO_D(BXT_DSI_PLL_ENABLE);
  ^~
scripts/Makefile.build:288: recipe for target 
'drivers/gpu/drm/i915/intel_gvt_mmio_table.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_gvt_mmio_table.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)

== Series Details ==

Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL   : https://patchwork.freedesktop.org/series/101723/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

Re: [Intel-gfx] [PATCH] docs: gpu: i915.rst: Fix DRRS documentation

On Fri, Mar 25, 2022 at 11:38:32AM -0700, José Roberto de Souza wrote:
> intel_drrs_enable() and intel_drrs_disable() were renamed to
> intel_drrs_activate() and intel_drrs_deactivate() in commit
> 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS") and it is
> causing warnings when generating the kernel documentation.
> 
> But as for a while DRRS has its own file, so here just let the tool
> generate the documentation for all exported and documented functions
> in intel_drrs.c.
> 
> Cc: Ville Syrjälä 
> Cc: Rodrigo Vivi 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Ville Syrjälä 

> ---
>  Documentation/gpu/i915.rst | 14 +-
>  1 file changed, 1 insertion(+), 13 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index bcaefc952764e..0f08693d05cdf 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -187,19 +187,7 @@ Display Refresh Rate Switching (DRRS)
> :doc: Display Refresh Rate Switching (DRRS)
>  
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_enable
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_disable
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_invalidate
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_flush
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_init
> +   :internal:
>  
>  DPIO
>  
> -- 
> 2.35.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

2022-03-25 Thread Das, Nirmoy




On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:

In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if something goes wrong
during the wait, leading to us hitting a GEM_BUG_ON in the GuC wait
function.
To fix this, make sure to only return the timeout if it is positive.

Fixes: b97060a99b01b ("drm/i915/guc: Update intel_gt_wait_for_idle to work with 
GuC")
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matthew Brost 
Cc: John Harrison 
---
  drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..ef70c209976d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -197,7 +197,7 @@ out_active: spin_lock(>lock);
active_count++;
  
  	if (remaining_timeout)

-   *remaining_timeout = timeout;
+   *remaining_timeout = timeout > 0 ? timeout : 0;



Should the last flush_submission() be  "if ( timeout > 0 
&_submission(gt, timeout))" ?



Nirmoy

  
  	return active_count ? timeout : 0;

  }

[Intel-gfx] [PATCH] docs: gpu: i915.rst: Fix DRRS documentation

2022-03-25 Thread José Roberto de Souza

intel_drrs_enable() and intel_drrs_disable() were renamed to
intel_drrs_activate() and intel_drrs_deactivate() in commit
54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS") and it is
causing warnings when generating the kernel documentation.

But as for a while DRRS has its own file, so here just let the tool
generate the documentation for all exported and documented functions
in intel_drrs.c.

Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Signed-off-by: José Roberto de Souza 
---
 Documentation/gpu/i915.rst | 14 +-
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index bcaefc952764e..0f08693d05cdf 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -187,19 +187,7 @@ Display Refresh Rate Switching (DRRS)
:doc: Display Refresh Rate Switching (DRRS)
 
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_enable
-
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_disable
-
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_invalidate
-
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_flush
-
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_init
+   :internal:
 
 DPIO
 
-- 
2.35.1

Re: [Intel-gfx] [PATCH] drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

2022-03-25 Thread Matthew Brost

On Fri, Mar 25, 2022 at 10:58:39AM -0700, Daniele Ceraolo Spurio wrote:
> In intel_gt_wait_for_idle, we use the remaining timeout returned from
> intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
> the returned variable can have a negative value if something goes wrong
> during the wait, leading to us hitting a GEM_BUG_ON in the GuC wait
> function.
> To fix this, make sure to only return the timeout if it is positive.
> 
> Fixes: b97060a99b01b ("drm/i915/guc: Update intel_gt_wait_for_idle to work 
> with GuC")
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Matthew Brost 
> Cc: John Harrison 

Reviewed-by: Matthew Brost 

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> index edb881d756309..ef70c209976d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> @@ -197,7 +197,7 @@ out_active:   spin_lock(>lock);
>   active_count++;
>  
>   if (remaining_timeout)
> - *remaining_timeout = timeout;
> + *remaining_timeout = timeout > 0 ? timeout : 0;
>  
>   return active_count ? timeout : 0;
>  }
> -- 
> 2.25.1
>

Re: [Intel-gfx] [PATCH] docs: gpu: i915.rst: Update DRRS functions names

2022-03-25 Thread Rodrigo Vivi

On Fri, Mar 25, 2022 at 08:10:59PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 25, 2022 at 08:34:36AM -0700, José Roberto de Souza wrote:
> > intel_drrs_enable and intel_drrs_disable where renamed to
> > intel_drrs_activate and intel_drrs_deactivate in commit
> > 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS").
> >
> > Cc: Ville Syrjälä 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  Documentation/gpu/i915.rst | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> > index bcaefc952764e..ab596b0a9f259 100644
> > --- a/Documentation/gpu/i915.rst
> > +++ b/Documentation/gpu/i915.rst
>
> Oh that's whete it's coming from.
>
> > @@ -187,10 +187,10 @@ Display Refresh Rate Switching (DRRS)
> > :doc: Display Refresh Rate Switching (DRRS)
> >
> >  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > -   :functions: intel_drrs_enable
> > +   :functions: intel_drrs_activate
>
> Hmm. Can't we just nuke all these explicit references and let the
> tooling pull in all of it automagically since there's nothing
> else in that file?

Indeed.

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
   :doc: Display Refresh Rate Switching (DRRS)

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
   :internal:

looks the right thing to do here.

And if the other matters, than sort the functions in intel_drrs.c

>
> >
> >  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > -   :functions: intel_drrs_disable
> > +   :functions: intel_drrs_deactivate
> >
> >  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_drrs_invalidate
> > --
> > 2.35.1
>
> --
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH] docs: gpu: i915.rst: Update DRRS functions names

On Fri, Mar 25, 2022 at 08:34:36AM -0700, José Roberto de Souza wrote:
> intel_drrs_enable and intel_drrs_disable where renamed to
> intel_drrs_activate and intel_drrs_deactivate in commit
> 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS").
> 
> Cc: Ville Syrjälä 
> Signed-off-by: José Roberto de Souza 
> ---
>  Documentation/gpu/i915.rst | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index bcaefc952764e..ab596b0a9f259 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst

Oh that's whete it's coming from.

> @@ -187,10 +187,10 @@ Display Refresh Rate Switching (DRRS)
> :doc: Display Refresh Rate Switching (DRRS)
>  
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_enable
> +   :functions: intel_drrs_activate

Hmm. Can't we just nuke all these explicit references and let the
tooling pull in all of it automagically since there's nothing
else in that file?

>  
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> -   :functions: intel_drrs_disable
> +   :functions: intel_drrs_deactivate
>  
>  .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_drrs_invalidate
> -- 
> 2.35.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

On Thu, Mar 24, 2022 at 12:58:32PM +, Souza, Jose wrote:
> On Thu, 2022-03-24 at 13:30 +0200, Ville Syrjälä wrote:
> > On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> > > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > > enabled but that could potentially cause issues as it could have
> > > mismatching values while pipes are being enabled.
> > > 
> > > So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
> > > executed before the function that enables all pipes, leaving all pipes
> > > with a matching A_CREDIT value.
> > > 
> > > While at it, also moving it to intel_pm.c as we are trying to reduce
> > > the gigantic size of it and intel_pm.c have other MBUS programing
> > > sequences.
> > > 
> > > v2:
> > > - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
> > > when it do not needs modeset
> > > - remove the checks to wait a vblank
> > > 
> > > BSpec: 49213
> > > BSpec: 50343
> > > Cc: Ville Syrjälä 
> > > Cc: Stanislav Lisovskiy 
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 37 +--
> > >  drivers/gpu/drm/i915/intel_pm.c  | 47 
> > >  drivers/gpu/drm/i915/intel_pm.h  |  1 +
> > >  3 files changed, 49 insertions(+), 36 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 424cd7e9afe60..ef5076b5e7027 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1824,35 +1824,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
> > > drm_i915_private *dev_priv,
> > >   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
> > >  }
> > >  
> > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool 
> > > joined_mbus)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > - enum pipe pipe = crtc->pipe;
> > > - u32 val;
> > > -
> > > - val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> > > - val &= ~MBUS_DBOX_A_CREDIT_MASK;
> > > - /* Wa_22010947358:adl-p */
> > > - if (IS_ALDERLAKE_P(dev_priv))
> > > - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> > > MBUS_DBOX_A_CREDIT(4);
> > > - else
> > > - val |= MBUS_DBOX_A_CREDIT(2);
> > > -
> > > - val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> > > - if (IS_ALDERLAKE_P(dev_priv)) {
> > > - val |= MBUS_DBOX_BW_CREDIT(2);
> > > - val |= MBUS_DBOX_B_CREDIT(8);
> > > - } else if (DISPLAY_VER(dev_priv) >= 12) {
> > > - val |= MBUS_DBOX_BW_CREDIT(2);
> > > - val |= MBUS_DBOX_B_CREDIT(12);
> > > - } else {
> > > - val |= MBUS_DBOX_BW_CREDIT(1);
> > > - val |= MBUS_DBOX_B_CREDIT(8);
> > > - }
> > > -
> > > - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
> > > -}
> > > -
> > >  static void hsw_set_linetime_wm(const struct intel_crtc_state 
> > > *crtc_state)
> > >  {
> > >   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > @@ -1988,13 +1959,6 @@ static void hsw_crtc_enable(struct 
> > > intel_atomic_state *state,
> > >  
> > >   intel_initial_watermarks(state, crtc);
> > >  
> > > - if (DISPLAY_VER(dev_priv) >= 11) {
> > > - const struct intel_dbuf_state *dbuf_state =
> > > - intel_atomic_get_new_dbuf_state(state);
> > > -
> > > - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
> > > - }
> > > -
> > >   if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> > >   intel_crtc_vblank_on(new_crtc_state);
> > >  
> > > @@ -8599,6 +8563,7 @@ static void intel_atomic_commit_tail(struct 
> > > intel_atomic_state *state)
> > >   intel_encoders_update_prepare(state);
> > >  
> > >   intel_dbuf_pre_plane_update(state);
> > > + intel_mbus_dbox_update(state);
> > >  
> > >   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > >   if (new_crtc_state->do_async_flip)
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index e60c02d760ffa..cf290bb704221 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -8258,3 +8258,50 @@ void intel_dbuf_post_plane_update(struct 
> > > intel_atomic_state *state)
> > >   gen9_dbuf_slices_update(dev_priv,
> > >   new_dbuf_state->enabled_slices);
> > >  }
> > > +
> > > +void intel_mbus_dbox_update(struct intel_atomic_state *state)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > + struct intel_crtc_state *new_crtc_state;
> > > + struct intel_dbuf_state *new_dbuf_state;
> > > + struct intel_crtc *crtc;
> > > + int i;
> > > +
> > > + if (DISPLAY_VER(i915) < 11 || !state->modeset)
> > > + return;
> > > +
> > > + if (HAS_MBUS_JOINING(i915))
> > > + new_dbuf_state =

[Intel-gfx] [PATCH] drm/i915: fix remaining_timeout in intel_gt_retire_requests_timeout

2022-03-25 Thread Daniele Ceraolo Spurio

In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if something goes wrong
during the wait, leading to us hitting a GEM_BUG_ON in the GuC wait
function.
To fix this, make sure to only return the timeout if it is positive.

Fixes: b97060a99b01b ("drm/i915/guc: Update intel_gt_wait_for_idle to work with 
GuC")
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matthew Brost 
Cc: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_gt_requests.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c 
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..ef70c209976d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -197,7 +197,7 @@ out_active: spin_lock(>lock);
active_count++;
 
if (remaining_timeout)
-   *remaining_timeout = timeout;
+   *remaining_timeout = timeout > 0 ? timeout : 0;
 
return active_count ? timeout : 0;
 }
-- 
2.25.1

[Intel-gfx] [PATCH v7 3/3] i915/gvt: Use the initial HW state snapshot saved in i915

2022-03-25 Thread Zhi Wang

The code of saving initial HW state snapshot has been moved into i915.
Let the GVT-g core logic use that snapshot.

Cc: Christoph Hellwig 
Cc: Jason Gunthorpe 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Vivi Rodrigo 
Cc: Zhenyu Wang 
Cc: Zhi Wang 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/gvt/firmware.c | 25 +
 1 file changed, 9 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/firmware.c 
b/drivers/gpu/drm/i915/gvt/firmware.c
index 1a8274a3f4b1..54fe442238c6 100644
--- a/drivers/gpu/drm/i915/gvt/firmware.c
+++ b/drivers/gpu/drm/i915/gvt/firmware.c
@@ -66,22 +66,16 @@ static struct bin_attribute firmware_attr = {
.mmap = NULL,
 };
 
-static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data)
-{
-   *(u32 *)(data + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
-   _MMIO(offset));
-   return 0;
-}
-
 static int expose_firmware_sysfs(struct intel_gvt *gvt)
 {
struct intel_gvt_device_info *info = >device_info;
-   struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
+   struct drm_i915_private *i915 = gvt->gt->i915;
+   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct gvt_firmware_header *h;
void *firmware;
void *p;
unsigned long size, crc32_start;
-   int i, ret;
+   int ret;
 
size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
firmware = vzalloc(size);
@@ -99,17 +93,16 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
 
p = firmware + h->cfg_space_offset;
 
-   for (i = 0; i < h->cfg_space_size; i += 4)
-   pci_read_config_dword(pdev, i, p + i);
-
-   memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
+   memcpy(gvt->firmware.cfg_space, i915->vgpu.initial_cfg_space,
+  info->cfg_space_size);
+   memcpy(p, gvt->firmware.cfg_space, info->cfg_space_size);
 
p = firmware + h->mmio_offset;
 
-   /* Take a snapshot of hw mmio registers. */
-   intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p);
+   memcpy(gvt->firmware.mmio, i915->vgpu.initial_mmio,
+  info->mmio_size);
 
-   memcpy(gvt->firmware.mmio, p, info->mmio_size);
+   memcpy(p, gvt->firmware.mmio, info->mmio_size);
 
crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
-- 
2.25.1

[Intel-gfx] [PATCH v7 2/3] i915/gvt: Save the initial HW state snapshot in i915

2022-03-25 Thread Zhi Wang

Save the initial HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.

v6:

- Remove the reference of intel_gvt_device_info.(Christoph)
- Refine the save_mmio() function. (Christoph)

Cc: Christoph Hellwig 
Cc: Jason Gunthorpe 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Vivi Rodrigo 
Cc: Zhenyu Wang 
Cc: Zhi Wang 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 +
 drivers/gpu/drm/i915/intel_gvt.c | 92 +++-
 2 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 418091484e02..0edc9ecbd403 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -429,6 +429,8 @@ struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
u32 caps;
+   u32 *initial_mmio;
+   u8 *initial_cfg_space;
 };
 
 struct i915_selftest_stash {
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index cf6e98962d82..65daab2c4d9e 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,85 @@ void intel_gvt_sanitize_options(struct drm_i915_private 
*dev_priv)
dev_priv->params.enable_gvt = 0;
 }
 
+static void free_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+   struct i915_virtual_gpu *vgpu = _priv->vgpu;
+
+   vfree(vgpu->initial_mmio);
+   vgpu->initial_mmio = NULL;
+
+   kfree(vgpu->initial_cfg_space);
+   vgpu->initial_cfg_space = NULL;
+}
+
+static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
+ u32 size)
+{
+   struct drm_i915_private *dev_priv = iter->i915;
+   u32 *mmio, i;
+
+   for (i = offset; i < offset + size; i += 4) {
+   mmio = iter->data + i;
+   *mmio = intel_uncore_read_notrace(to_gt(dev_priv)->uncore,
+ _MMIO(i));
+   }
+}
+
+static int handle_mmio(struct intel_gvt_mmio_table_iter *iter,
+  u32 offset, u32 size)
+{
+   if (WARN_ON(!IS_ALIGNED(offset, 4)))
+   return -EINVAL;
+
+   save_mmio(iter, offset, size);
+   return 0;
+}
+
+static int save_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+   struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+   struct i915_virtual_gpu *vgpu = _priv->vgpu;
+   struct intel_gvt_mmio_table_iter iter;
+   void *mem;
+   int i, ret;
+
+   mem = kzalloc(PCI_CFG_SPACE_EXP_SIZE, GFP_KERNEL);
+   if (!mem)
+   return -ENOMEM;
+
+   vgpu->initial_cfg_space = mem;
+
+   for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+   pci_read_config_dword(pdev, i, mem + i);
+
+   mem = vzalloc(2 * SZ_1M);
+   if (!mem) {
+   ret = -ENOMEM;
+   goto err_mmio;
+   }
+
+   vgpu->initial_mmio = mem;
+
+   iter.i915 = dev_priv;
+   iter.data = vgpu->initial_mmio;
+   iter.handle_mmio_cb = handle_mmio;
+
+   ret = intel_gvt_iterate_mmio_table();
+   if (ret)
+   goto err_iterate;
+
+   return 0;
+
+err_iterate:
+   vfree(vgpu->initial_mmio);
+   vgpu->initial_mmio = NULL;
+err_mmio:
+   kfree(vgpu->initial_cfg_space);
+   vgpu->initial_cfg_space = NULL;
+
+   return ret;
+}
+
 /**
  * intel_gvt_init - initialize GVT components
  * @dev_priv: drm i915 private data
@@ -115,15 +194,23 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
 
+   ret = save_initial_hw_state(dev_priv);
+   if (ret) {
+   drm_dbg(_priv->drm, "Fail to save initial HW state\n");
+   goto err_save_hw_state;
+   }
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(_priv->drm, "Fail to init GVT device\n");
-   goto bail;
+   goto err_init_device;
}
 
return 0;
 
-bail:
+err_init_device:
+   free_initial_hw_state(dev_priv);
+err_save_hw_state:
dev_priv->params.enable_gvt = 0;
return 0;
 }
@@ -147,6 +234,7 @@ void intel_gvt_driver_remove(struct drm_i915_private 
*dev_priv)
return;
 
intel_gvt_clean_device(dev_priv);
+   free_initial_hw_state(dev_priv);
 }
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v7 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g

2022-03-25 Thread Zhi Wang

From: Zhi Wang 

To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO tracking table needs to be separated from GVT-g.

v7:

- Keep the marcos of device generation in GVT-g. (Christoph, Jani)

v6:

- Move the mmio_table.c into i915. (Christoph)
- Keep init_device_info and related structures in GVT-g. (Christoph)
- Refine the callbacks of the iterator. (Christoph)
- Move the flags of MMIO register defination to GVT-g. (Chrsitoph)
- Move the mmio block handling to GVT-g.

v5:

- Re-design the mmio table framework. (Christoph)

v4:

- Fix the errors of patch checking scripts.

v3:

- Fix the errors when CONFIG_DRM_I915_WERROR is turned on. (Jani)

v2:

- Implement a mmio table instead of generating it by marco in i915. (Jani)

Cc: Christoph Hellwig 
Cc: Jason Gunthorpe 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Vivi Rodrigo 
Cc: Zhenyu Wang 
Cc: Zhi Wang 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/Makefile   |2 +-
 drivers/gpu/drm/i915/gvt/gvt.h  |3 +-
 drivers/gpu/drm/i915/gvt/handlers.c | 1031 ++-
 drivers/gpu/drm/i915/gvt/mmio.h |1 -
 drivers/gpu/drm/i915/gvt/reg.h  |9 +-
 drivers/gpu/drm/i915/intel_gvt.h|   21 +
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1308 +++
 7 files changed, 1476 insertions(+), 899 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_gvt_mmio_table.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d588d936e3d..cbd1a0a01cda 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -320,7 +320,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
 i915-y += i915_vgpu.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
-i915-y += intel_gvt.o
+i915-y += intel_gvt.o intel_gvt_mmio_table.o
 include $(src)/gvt/Makefile
 endif
 
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0ebffc327528..bfe07c69cfd2 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -36,6 +36,7 @@
 #include 
 
 #include "i915_drv.h"
+#include "intel_gvt.h"
 
 #include "debug.h"
 #include "hypercall.h"
@@ -272,7 +273,7 @@ struct intel_gvt_mmio {
 /* Value of command write of this reg needs to be patched */
 #define F_CMD_WRITE_PATCH  (1 << 8)
 
-   const struct gvt_mmio_block *mmio_block;
+   struct gvt_mmio_block *mmio_block;
unsigned int num_mmio_block;
 
DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 5e3ae5970c6b..1a3702649d8c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -100,12 +100,11 @@ struct intel_gvt_mmio_info 
*intel_gvt_find_mmio_info(struct intel_gvt *gvt,
return NULL;
 }
 
-static int new_mmio_info(struct intel_gvt *gvt,
-   u32 offset, u16 flags, u32 size,
-   u32 addr_mask, u32 ro_mask, u32 device,
-   gvt_mmio_func read, gvt_mmio_func write)
+static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
+  u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
+  gvt_mmio_func read, gvt_mmio_func write)
 {
-   struct intel_gvt_mmio_info *info, *p;
+   struct intel_gvt_mmio_info *p;
u32 start, end, i;
 
if (!intel_gvt_match_device(gvt, device))
@@ -118,32 +117,18 @@ static int new_mmio_info(struct intel_gvt *gvt,
end = offset + size;
 
for (i = start; i < end; i += 4) {
-   info = kzalloc(sizeof(*info), GFP_KERNEL);
-   if (!info)
-   return -ENOMEM;
-
-   info->offset = i;
-   p = intel_gvt_find_mmio_info(gvt, info->offset);
-   if (p) {
-   WARN(1, "dup mmio definition offset %x\n",
-   info->offset);
-   kfree(info);
-
-   /* We return -EEXIST here to make GVT-g load fail.
-* So duplicated MMIO can be found as soon as
-* possible.
-*/
-   return -EEXIST;
+   p = intel_gvt_find_mmio_info(gvt, i);
+   if (!p) {
+   WARN(1, "assign a handler to a non-tracked mmio %x\n",
+   i);
+   return -ENODEV;
}
-
-   info->ro_mask = ro_mask;
-   info->device = device;
-   info->read = read ? read : intel_vgpu_default_mmio_read;
-   info->write = write ? write : intel_vgpu_default_mmio_write;
-   gvt->mmio.mmio_attribute[info->offset / 4] = flags;
-   INIT_HLIST_NODE(>node);
-   hash_add(gvt->mmio.mmio_info_table, >node, info->offset);
-

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

== Series Details ==

Series: series starting with [1/2] drm/i915/ttm: limit where we apply 
TTM_PL_FLAG_CONTIGUOUS (rev2)
URL   : https://patchwork.freedesktop.org/series/101749/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22677_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22677_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22677_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22677_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-skl1/igt@i915_selftest@live@gem_contexts.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@execlists:
- {shard-rkl}:[PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-rkl-6/igt@i915_selftest@l...@execlists.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-rkl-5/igt@i915_selftest@l...@execlists.html

  
Known issues


  Here are the changes found in Patchwork_22677_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-glk:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [FAIL][25], 
[PASS][26], [PASS][27], [PASS][28]) ([i915#4392]) -> ([PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-glk9/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-glk9/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-glk8/boot.html
   [33]:

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for lmem_size modparam

Filed a new issue for the regression
https://gitlab.freedesktop.org/drm/intel/-/issues/5435

Lakshmi.

-Original Message-
From: Auld, Matthew  
Sent: Friday, March 25, 2022 2:49 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for lmem_size modparam

On 24/03/2022 20:15, Patchwork wrote:
> *Patch Details*
> *Series:* lmem_size modparam
> *URL:*https://patchwork.freedesktop.org/series/101744/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/index.html
> 
> 
> 
>   CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22671_full
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_22671_full absolutely 
> need to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_22671_full, please notify your bug team to 
> allow them to document this new failure mode, which will reduce false 
> positives in CI.
> 
> 
> Participating hosts (11 -> 11)
> 
> No changes in participating hosts
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_22671_full:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   * igt@gem_exec_schedule@wide@vcs0:
>   o shard-skl: NOTRUN -> INCOMPLETE
> 
>  gt@gem_exec_schedule@w...@vcs0.html>

Unrelated fail.

> 
> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   * igt@kms_frontbuffer_tracking@fbc-tiling-4:
>   o {shard-tglu}: NOTRUN -> SKIP
> 
>  /igt@kms_frontbuffer_track...@fbc-tiling-4.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_22671_full that come from 
> known
> issues:
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   *
> 
> igt@feature_discovery@psr2:
> 
>   o shard-iclb: NOTRUN -> SKIP
> 
> 
> ([i915#658])
>   *
> 
> igt@gem_ctx_persistence@engines-mixed:
> 
>   o shard-snb: NOTRUN -> SKIP
> 
> 
> ([fdo#109271] / [i915#1099]) +1 similar issue
>   *
> 
> igt@gem_ctx_sseu@engines:
> 
>   o shard-tglb: NOTRUN -> SKIP
> 
> 
> ([i915#280])
>   *
> 
> igt@gem_eio@in-flight-suspend:
> 
>   o shard-kbl: NOTRUN -> INCOMPLETE
> 
> 
> ([i915#3614])
>   *
> 
> igt@gem_eio@unwedge-stress:
> 
>   o shard-iclb: PASS
> 
> 
> -> TIMEOUT
> 
> 
> ([i915#2481] / [i915#3070])
>   *
> 
> igt@gem_exec_balancer@parallel-bb-first:
> 
>   o
> 
> shard-skl: NOTRUN -> SKIP
> 
> 
> ([fdo#109271] / [i915#1888])
> 
>   o
> 
> shard-tglb: NOTRUN -> DMESG-WARN
> 
> 
> ([i915#5076])
> 
>   o
> 
> shard-kbl: NOTRUN -> DMESG-WARN
> 
> 
> ([i915#5076])
> 
>   o
> 
> shard-iclb: NOTRUN -> DMESG-WARN
> 
> 
> ([i915#5076])
> 
>   *
> 
> igt@gem_exec_capture@pi@rcs0:
> 
>   o shard-skl: NOTRUN -> INCOMPLETE
> 
> 
> ([i915#4547])
>   *
> 
> igt@gem_exec_fair@basic-deadline:
> 
>   o
> 
> shard-kbl: PASS
> 
> 
> -> FAIL
> 
> 
>

[Intel-gfx] ✓ Fi.CI.IGT: success for lmem_size modparam

== Series Details ==

Series: lmem_size modparam
URL   : https://patchwork.freedesktop.org/series/101744/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22671_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 13)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22671_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@forcewake:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-rkl-5/igt@i915_susp...@forcewake.html

  
Known issues


  Here are the changes found in Patchwork_22671_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#658])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb7/igt@feature_discov...@psr2.html

  * igt@gem_ctx_persistence@engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-snb5/igt@gem_ctx_persiste...@engines-mixed.html

  * igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#280])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglb3/igt@gem_ctx_s...@engines.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  NOTRUN -> [INCOMPLETE][5] ([i915#3614])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2481] / [i915#3070])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-iclb4/igt@gem_...@unwedge-stress.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-skl:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1888])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl9/igt@gem_exec_balan...@parallel-bb-first.html
- shard-tglb: NOTRUN -> [DMESG-WARN][9] ([i915#5076])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglb5/igt@gem_exec_balan...@parallel-bb-first.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][10] ([i915#5076])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_balan...@parallel-bb-first.html
- shard-iclb: NOTRUN -> [DMESG-WARN][11] ([i915#5076])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][12] ([i915#4547])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl7/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2846])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-kbl1/igt@gem_exec_f...@basic-deadline.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
- shard-skl:  NOTRUN -> [FAIL][15] ([i915#2846])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl9/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][16] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb3/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglb3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][19] -> [FAIL][20] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_schedule@wide@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][21] ([i915#5435])
   [21]:

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4)


Re-reported.

From: Shankar, Uma 
Sent: Friday, March 25, 2022 3:35 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: RE: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support 
to hsw+ (rev4)



From: Patchwork 
mailto:patchw...@emeril.freedesktop.org>>
Sent: Thursday, March 24, 2022 10:43 PM
To: Shankar, Uma mailto:uma.shan...@intel.com>>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to 
hsw+ (rev4)

Patch Details
Series:

drm/i915/display: Extend DP HDR support to hsw+ (rev4)

URL:

https://patchwork.freedesktop.org/series/101708/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/index.html

CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_22670_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22670_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (11 -> 11)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22670_full:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@reset:

 *   shard-skl: NOTRUN -> 
INCOMPLETE
Hi Lakshmi,
This is not related to the change, can you help report it.
Thanks & Regards,
Uma Shankar
Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@kms_frontbuffer_tracking@fbc-tiling-4:

 *   {shard-tglu}: NOTRUN -> 
SKIP

Known issues

Here are the changes found in Patchwork_22670_full that come from known issues:

IGT changes
Issues hit

  *   igt@feature_discovery@psr2:

 *   shard-iclb: NOTRUN -> 
SKIP
 ([i915#658])

  *   igt@gem_eio@kms:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#232])

  *   igt@gem_exec_balancer@parallel-balancer:

 *   shard-iclb: 
PASS
 -> 
SKIP
 ([i915#4525])

  *   igt@gem_exec_balancer@parallel-contexts:

 *   shard-tglb: NOTRUN -> 
DMESG-WARN
 ([i915#5076])

  *   igt@gem_exec_fair@basic-deadline:

 *   shard-skl: NOTRUN -> 
FAIL
 ([i915#2846])

  *   igt@gem_exec_fair@basic-none-solo@rcs0:

 *   shard-tglb: NOTRUN -> 
FAIL
 ([i915#2842])

  *   igt@gem_exec_fair@basic-none-vip@rcs0:

 *   shard-kbl: 
PASS
 -> 
FAIL
 ([i915#2842])
 *   shard-iclb: NOTRUN -> 
FAIL
 ([i915#2842]) +2 similar issues

  *   igt@gem_exec_fair@basic-pace-share@rcs0:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842])

  *   igt@gem_lmem_swapping@basic:

 *   shard-iclb: NOTRUN -> 
SKIP
 ([i915#4613])

  *   igt@gem_lmem_swapping@parallel-multi:

 *   shard-kbl: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#4613])

  *   igt@gem_lmem_swapping@random:

 *   shard-tglb: NOTRUN -> 
SKIP
 ([i915#4613])

  *

[Intel-gfx] ✗ Fi.CI.BAT: failure for docs: gpu: i915.rst: Update DRRS functions names

== Series Details ==

Series: docs: gpu: i915.rst: Update DRRS functions names
URL   : https://patchwork.freedesktop.org/series/101795/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22687


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22687 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22687, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/index.html

Participating hosts (46 -> 34)
--

  Missing(12): fi-bdw-samus shard-tglu bat-dg1-6 bat-dg2-8 bat-dg2-9 
fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22687:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-ilk-650: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_linear_blits@basic:
- fi-elk-e7500:   [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_render_linear_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-elk-e7500/igt@gem_render_linear_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-rkl-guc: [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-rkl-guc/igt@gem_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-rkl-guc/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u:   [PASS][10] -> [INCOMPLETE][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][12] -> [INCOMPLETE][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html

  
 Warnings 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k:   [INCOMPLETE][14] ([i915#1982]) -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html

  
Known issues


  Here are the changes found in Patchwork_22687 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][16] ([fdo#109271]) +17 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-glk-j4005:   NOTRUN -> [SKIP][17] ([fdo#109271]) +17 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-glk-j4005/igt@amdgpu/amd_cs_...@sync-gfx0.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3012])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][19] ([i915#4785])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22687/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-bsw-nick:NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [21]:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Extend DP HDR support to hsw+ (rev4)

== Series Details ==

Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL   : https://patchwork.freedesktop.org/series/101708/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 13)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22670_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
- {shard-tglu}:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglu-2/igt@kms_frontbuffer_track...@fbc-tiling-4.html
- {shard-rkl}:NOTRUN -> [SKIP][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-rkl-6/igt@kms_frontbuffer_track...@fbc-tiling-4.html
- {shard-dg1}:NOTRUN -> [SKIP][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-dg1-19/igt@kms_frontbuffer_track...@fbc-tiling-4.html

  
Known issues


  Here are the changes found in Patchwork_22670_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#658])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@feature_discov...@psr2.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-tglb6/igt@gem_...@kms.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-contexts:
- shard-tglb: NOTRUN -> [DMESG-WARN][9] ([i915#5076])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb2/igt@gem_exec_balan...@parallel-contexts.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-skl10/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-kbl1/igt@gem_exec_fair@basic-none-...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-kbl3/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@random:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb6/igt@gem_lmem_swapp...@random.html

  * igt@gem_lmem_swapping@verify-random:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-skl2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270])
   [21]:

[Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

2022-03-25 Thread Animesh Manna

The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.

DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be right as anyways losing time.

To make the CI execution happy replaced drm_err() to drm_info()
for printing debug info during dsb buffer preparation.

v1: Initial version.
v2: Added print for mmio fallback at out label. [Nirmoy]
v3: Improved debug message. [Nirmoy]

Reviewed-by: Nirmoy Das 
Cc: Nirmoy Das 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..c4affcb216fd 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -283,14 +283,12 @@ void intel_dsb_prepare(struct intel_crtc_state 
*crtc_state)
 
obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
-   drm_err(>drm, "Gem object creation failed\n");
kfree(dsb);
goto out;
}
 
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
-   drm_err(>drm, "Vma creation failed\n");
i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +296,6 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
 
buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
-   drm_err(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
kfree(dsb);
goto out;
@@ -311,6 +308,10 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
dsb->ins_start_offset = 0;
crtc_state->dsb = dsb;
 out:
+   if (!crtc_state->dsb)
+   drm_info(>drm,
+"DSB queue setup failed, will fallback to MMIO for 
display HW programming\n");
+
intel_runtime_pm_put(>runtime_pm, wakeref);
 }
 
-- 
2.29.0

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove check for ComboPHY I/O voltage for DP source rate (rev5)

Filed a new issue and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/5436
igt@gem_exec_whisper@basic-fds-(forked|priority)-all - incomplete - general 
protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7c33

From: Nautiyal, Ankit K 
Sent: Friday, March 25, 2022 2:50 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: RE: ✗ Fi.CI.IGT: failure for Remove check for ComboPHY I/O voltage for 
DP source rate (rev5)

Hello Lakshmi,
The below regressions are known issue and are not related patches:

  *   igt@gem_exec_whisper@basic-fds-forked-all:
 *   shard-kbl: NOTRUN -> 
INCOMPLETE
https://gitlab.freedesktop.org/drm/intel/-/issues/5268

  *   igt@gem_exec_whisper@basic-fds-priority-all:
 *   shard-skl: 
PASS
 -> 
INCOMPLETE
https://gitlab.freedesktop.org/drm/intel/-/issues/5268

  *   igt@perf@enable-disable:
 *   shard-skl: 
PASS
 -> 
FAIL
[https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl5/igt@p...@enable-disable.html
https://gitlab.freedesktop.org/drm/intel/-/issues/1352]
Regards,
Ankit
From: Patchwork 
mailto:patchw...@emeril.freedesktop.org>>
Sent: Wednesday, March 23, 2022 7:40 PM
To: Nautiyal, Ankit K 
mailto:ankit.k.nauti...@intel.com>>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Remove check for ComboPHY I/O voltage for DP 
source rate (rev5)

Patch Details
Series:

Remove check for ComboPHY I/O voltage for DP source rate (rev5)

URL:

https://patchwork.freedesktop.org/series/96293/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/index.html

CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22655_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_22655_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22655_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (12 -> 12)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22655_full:

IGT changes
Possible regressions

  *   igt@gem_exec_whisper@basic-fds-forked-all:
 *   shard-kbl: NOTRUN -> 
INCOMPLETE
  *   igt@gem_exec_whisper@basic-fds-priority-all:
 *   shard-skl: 
PASS
 -> 
INCOMPLETE
  *   igt@perf@enable-disable:
 *   shard-skl: 
PASS
 -> 
FAIL

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@gem_workarounds@suspend-resume-context:
 *   {shard-rkl}: 
PASS
 -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_22655_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_balancer@parallel-balancer:
 *   shard-iclb: 
PASS
 -> 
SKIP
 ([i915#4525])
  *   igt@gem_exec_capture@pi@rcs0:
 *   shard-skl: 
PASS
 -> 
INCOMPLETE
 ([i915#4547])
  *   igt@gem_exec_fair@basic-deadline:
 *   shard-kbl: 
PASS
 ->

[Intel-gfx] ✓ Fi.CI.IGT: success for Remove check for ComboPHY I/O voltage for DP source rate (rev5)

== Series Details ==

Series: Remove check for ComboPHY I/O voltage for DP source rate (rev5)
URL   : https://patchwork.freedesktop.org/series/96293/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22655_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 13)
--

  Additional (1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22655_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_schedule@submit-early-slice@vcs1:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-dg1-13/igt@gem_exec_schedule@submit-early-sl...@vcs1.html

  * igt@gem_workarounds@suspend-resume-context:
- {shard-rkl}:[PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-rkl-1/igt@gem_workarou...@suspend-resume-context.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-rkl-5/igt@gem_workarou...@suspend-resume-context.html

  
Known issues


  Here are the changes found in Patchwork_22655_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-iclb5/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][6] -> [INCOMPLETE][7] ([i915#4547])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-skl9/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl1/igt@gem_exec_f...@basic-deadline.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271]) +45 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-skl10/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-kbl:  NOTRUN -> [INCOMPLETE][15] ([i915#5436])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-kbl1/igt@gem_exec_whis...@basic-fds-forked-all.html

  * igt@gem_exec_whisper@basic-fds-priority-all:
- shard-skl:  [PASS][16] -> [INCOMPLETE][17] ([i915#5436])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-skl1/igt@gem_exec_whis...@basic-fds-priority-all.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-skl6/igt@gem_exec_whis...@basic-fds-priority-all.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-tglb1/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-apl7/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_pxp@fail-invalid-protected-context:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22655/shard-tglb3/igt@gem_...@fail-invalid-protected-context.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270]) +1 similar issue
   [21]:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev2)

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev2)
URL   : https://patchwork.freedesktop.org/series/101792/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22686


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22686 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22686, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/index.html

Participating hosts (46 -> 44)
--

  Additional (1): bat-hsw-1 
  Missing(3): fi-bsw-cyan shard-tglu fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22686:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html
- fi-snb-2600:NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-snb-2600/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_tiled_blits@basic:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-rkl-guc/igt@gem_tiled_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-rkl-guc/igt@gem_tiled_bl...@basic.html
- fi-elk-e7500:   [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][9]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-ilk-650/igt@gem_tiled_bl...@basic.html
- fi-snb-2520m:   NOTRUN -> [INCOMPLETE][10]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-snb-2520m/igt@gem_tiled_bl...@basic.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][11]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][12] -> [INCOMPLETE][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html

  
 Warnings 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k:   [INCOMPLETE][14] ([i915#1982]) -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@core_hotunplug@unbind-rebind:
- {bat-hsw-1}:NOTRUN -> [INCOMPLETE][16]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/bat-hsw-1/igt@core_hotunp...@unbind-rebind.html
- {fi-adl-ddr5}:  [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html
- {fi-hsw-g3258}: [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_tiled_blits@basic:
- {fi-tgl-dsi}:   NOTRUN -> [INCOMPLETE][21]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/fi-tgl-dsi/igt@gem_render_tiled_bl...@basic.html
- {bat-rpls-2}:   [PASS][22] -> [INCOMPLETE][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/bat-rpls-2/igt@gem_render_tiled_bl...@basic.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22686/bat-rpls-2/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- {bat-rpls-1}:   NOTRUN -> [INCOMPLETE][24]
   [24]:

Re: [Intel-gfx] Commit messages

2022-03-25 Thread Paul Menzel

Dear Christian, dear Daniel, dear Alex,

Am 23.03.22 um 16:32 schrieb Christian König:

Am 23.03.22 um 16:24 schrieb Daniel Stone:

On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote:
On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone
wrote:

That's not what anyone's saying here ...

No-one's demanding AMD publish RTL, or internal design docs, or
hardware specs, or URLs to JIRA tickets no-one can access.

This is a large and invasive commit with pretty big ramifications;
containing exactly two lines of commit message, one of which just
duplicates the subject.

It cannot be the case that it's completely impossible to provide any
justification, background, or details, about this commit being made.
Unless, of course, it's to fix a non-public security issue, that is
reasonable justification for eliding some of the details. But then
again, 'huge change which is very deliberately opaque' is a really
good way to draw a lot of attention to the commit, and it would be
better to provide more detail about the change to help it slip under
the radar.

If dri-devel@ isn't allowed to inquire about patches which are posted,
then CCing the list is just a façade; might as well just do it all
internally and periodically dump out pull requests.

I think we are in agreement. I think the withheld information
Christian was referring to was on another thread with Christian and
Paul discussing a workaround for a hardware bug:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.spinics.net%2Flists%2Famd-gfx%2Fmsg75908.htmldata=04%7C01%7Cchristian.koenig%40amd.com%7C6a3f2815d83b4872577008da0ce1347a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637836458652370599%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=QtNB0XHMhTgH%2FNHMwF23Qn%2BgSdYyHJSenbpP%2FHG%2BkxE%3Dreserved=0

(Thank you Microsoft for keeping us safe.)

I guess it proves, how assuming what other people should know/have read,
especially when crossing message threads, is causing confusion and
misunderstandings.

Right, that definitely seems like some crossed wires. I don't see
anything wrong with that commit at all: the commit message and a
comment notes that there is a hardware issue preventing Raven from
being able to do TMZ+GTT, and the code does the very straightforward
and obvious thing to ensure that on VCN 1.0, any TMZ buffer must be
VRAM-placed.

My questions were:

Where is that documented, and how can this be reproduced?

Shouldn’t these be answered by the commit message? In five(?) years,
somebody, maybe even with access to the currently non-public documents,
finds a fault in the commit, and would be helped by having an
document/errata number where to look at. To verify the fix, the
developer would need a method to produce the error, so why not just
share it?

Also, I assume that workarounds often come with downsides, as otherwise
it would have been programmed like this from the beginning, or instead
of “workaround” it would be called “improvement”. Shouldn’t that also be
answered?

So totally made-up example:

Currently, there is a graphics corruption running X on system Y. This is
caused by a hardware bug in Raven ASIC (details internal document
#/AMD-Jira #N), and can be worked around by [what is in the commit
message].

The workaround does not affect the performance, and testing X shows the
error is fixed.

This one, on the other hand, is much less clear ...

Yes, completely agree. I mean a good bunch of comments on commit
messages are certainly valid and we could improve them.

That’d be great.

But this patch here was worked on by both AMD and Intel developers.
Where both sides and I think even people from other companies perfectly
understands why, what, how etc...

When now somebody comes along and asks for a whole explanation of the
context why we do it then that sounds really strange to me.

The motivation should be part of the commit message. I didn’t mean
anyone to rewrite buddy memory allocator Wikipedia article [1]. But the
commit message at hand for switching the allocator is definitely too terse.

Kind regards,

Paul

[1]: https://en.wikipedia.org/wiki/Buddy_memory_allocation

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: constify EDID parsing

== Series Details ==

Series: drm/edid: constify EDID parsing
URL   : https://patchwork.freedesktop.org/series/101787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22682_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22682_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [FAIL][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [PASS][50])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk3/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk5/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk5/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk7/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk6/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk5/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk5/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk4/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk4/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk4/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/shard-glk4/boot.html
   [44]:

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev2)

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev2)
URL   : https://patchwork.freedesktop.org/series/101792/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)

== Series Details ==

Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)
URL   : https://patchwork.freedesktop.org/series/101723/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22685


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22685 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22685, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/index.html

Participating hosts (46 -> 43)
--

  Additional (1): bat-hsw-1 
  Missing(4): fi-bsw-cyan bat-rpls-1 shard-tglu fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22685:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_tiled_blits@basic:
- fi-skl-6700k2:  [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-cfl-8700k:   [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@gem_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-cfl-8700k/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u:   [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
- fi-blb-e6850:   [PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][10] -> [INCOMPLETE][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}:   [PASS][12] -> [INCOMPLETE][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/bat-rpls-2/igt@core_hotunp...@unbind-rebind.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/bat-rpls-2/igt@core_hotunp...@unbind-rebind.html
- {fi-hsw-g3258}: [PASS][14] -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_tiled_blits@basic:
- {fi-tgl-dsi}:   NOTRUN -> [INCOMPLETE][16]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-tgl-dsi/igt@gem_render_tiled_bl...@basic.html
- {fi-ehl-2}: [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-ehl-2/igt@gem_render_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-ehl-2/igt@gem_render_tiled_bl...@basic.html

  
Known issues


  Here are the changes found in Patchwork_22685 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#109315]) 
+17 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@query-info:
- fi-glk-dsi: NOTRUN -> [SKIP][20] ([fdo#109271]) +17 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-glk-dsi/igt@amdgpu/amd_ba...@query-info.html
- fi-tgl-1115g4:  NOTRUN -> [SKIP][21] ([fdo#109315])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][22] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22685/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  *

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

Regression on RKL is related to 
https://gitlab.freedesktop.org/drm/intel/-/issues/4418

Thanks,
Lakshmi.
-Original Message-
From: Auld, Matthew  
Sent: Friday, March 25, 2022 2:49 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: 
limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

On 25/03/2022 09:22, Patchwork wrote:
> *Patch Details*
> *Series:* series starting with [1/2] drm/i915/ttm: limit where we apply 
> TTM_PL_FLAG_CONTIGUOUS (rev2)
> *URL:*https://patchwork.freedesktop.org/series/101749/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/index.html
> 
> 
> 
>   CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22677
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_22677 absolutely need to 
> be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_22677, please notify your bug team to allow 
> them to document this new failure mode, which will reduce false positives in 
> CI.
> 
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/index.html
> 
> 
> Participating hosts (44 -> 40)
> 
> Missing (4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_22677:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   * igt@i915_selftest@live@gt_engines:
>   o fi-rkl-guc: PASS
> 
> 
> -> INCOMPLETE
> 
>  gt@i915_selftest@live@gt_engines.html>

Unrelated fail.

> 
> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   * igt@i915_selftest@live@uncore:
>   o {bat-rpls-2}: NOTRUN -> INCOMPLETE
> 
>  gt@i915_selftest@l...@uncore.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_22677 that come from known issues:
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   * igt@runner@aborted:
>   o fi-rkl-guc: NOTRUN -> FAIL
> 
> 
> (i915#4312 
> )
> 
> 
> Possible fixes
> 
>   *
> 
> igt@i915_module_load@reload:
> 
>   o {bat-rpls-2}: DMESG-WARN
> 
> 
> (i915#4391
> ) -> PASS
> 
> 
>   *
> 
> igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
> 
>   o fi-cfl-8109u: DMESG-WARN
> 
> 
> (i915#295 )
> -> PASS
> 
> 
> +10 similar issues
>   *
> 
> igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
> 
>   o fi-cfl-8109u: DMESG-WARN
> 
> 
> (i915#295 
> / i915#5341
> ) -> PASS
> 
>  /igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html>
> 
> {name}: This element is suppressed. This means it is ignored when 
> computing the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
> 
> Build changes
> 
>   * Linux: CI_DRM_11403 -> Patchwork_22677
> 
> CI-20190529: 20190529
> CI_DRM_11403: 76ccfdacc3c78b22c90127356a2d19241f452208 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6392: 5a78ea9ff9c0a77bec5b094bf7e9d82c9848702b @ 
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_22677: 2c1ea7309b6ade223d932cd43b4f7735d57b32d9 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> == Linux commits ==
> 
> 2c1ea7309b6a drm/i915/migrate: move the sanity check
> 1da8e5cdeb99 drm/i915/ttm: limit

[Intel-gfx] [PATCH] docs: gpu: i915.rst: Update DRRS functions names

2022-03-25 Thread José Roberto de Souza

intel_drrs_enable and intel_drrs_disable where renamed to
intel_drrs_activate and intel_drrs_deactivate in commit
54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS").

Cc: Ville Syrjälä 
Signed-off-by: José Roberto de Souza 
---
 Documentation/gpu/i915.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index bcaefc952764e..ab596b0a9f259 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -187,10 +187,10 @@ Display Refresh Rate Switching (DRRS)
:doc: Display Refresh Rate Switching (DRRS)
 
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_enable
+   :functions: intel_drrs_activate
 
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
-   :functions: intel_drrs_disable
+   :functions: intel_drrs_deactivate
 
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_drrs_invalidate
-- 
2.35.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

== Series Details ==

Series: series starting with [1/2] drm/i915/ttm: limit where we apply 
TTM_PL_FLAG_CONTIGUOUS (rev2)
URL   : https://patchwork.freedesktop.org/series/101749/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22677


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/index.html

Participating hosts (45 -> 42)
--

  Missing(3): shard-dg1 fi-bsw-cyan fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22677:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@uncore:
- {bat-rpls-2}:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/bat-rpls-2/igt@i915_selftest@l...@uncore.html

  
Known issues


  Here are the changes found in Patchwork_22677 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][2] -> [INCOMPLETE][3] ([i915#4418])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][4] ([i915#4312])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/fi-rkl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][5] ([i915#4391]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_module_l...@reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/bat-rpls-2/igt@i915_module_l...@reload.html

  * igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-tglu-5/igt@kms_big...@linear-16bpp-rotate-0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-tglu-1/igt@kms_big...@linear-16bpp-rotate-0.html

  * igt@kms_color@pipe-b-legacy-gamma-reset:
- {shard-rkl}:[SKIP][9] ([i915#4070] / [i915#4098]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-rkl-4/igt@kms_co...@pipe-b-legacy-gamma-reset.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-rkl-6/igt@kms_co...@pipe-b-legacy-gamma-reset.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- {shard-rkl}:[SKIP][11] ([i915#1849] / [i915#4098]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-rkl-4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/shard-rkl-6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u:   [DMESG-WARN][13] ([i915#295] / [i915#5341]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u:   [DMESG-WARN][15] ([i915#295]) -> [PASS][16] +10 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22677/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
  [fdo#111614]:

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)

== Series Details ==

Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)
URL   : https://patchwork.freedesktop.org/series/101723/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127
URL   : https://patchwork.freedesktop.org/series/101792/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22684


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22684 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22684, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/index.html

Participating hosts (46 -> 41)
--

  Missing(5): shard-tglu fi-tgl-1115g4 fi-bsw-cyan bat-adlp-4 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22684:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_tiled_blits@basic:
- fi-ilk-650: NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-ilk-650/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-n3050:   [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-kefka:   [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][8] -> [INCOMPLETE][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
- fi-glk-dsi: [PASS][10] -> [INCOMPLETE][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-elk-e7500:   [PASS][12] -> [INCOMPLETE][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][14] -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-snb-2520m:   NOTRUN -> [INCOMPLETE][16]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-snb-2520m/igt@gem_tiled_bl...@basic.html
- fi-blb-e6850:   [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-blb-e6850/igt@gem_tiled_bl...@basic.html

  
 Warnings 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k:   [INCOMPLETE][19] ([i915#1982]) -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_tiled_blits@basic:
- {fi-hsw-g3258}: [PASS][21] -> [INCOMPLETE][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-hsw-g3258/igt@gem_tiled_bl...@basic.html

  
Known issues


  Here are the changes found in Patchwork_22684 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_render_tiled_blits@basic:
- fi-cfl-guc: [PASS][23] -> [INCOMPLETE][24] ([i915#1982])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-guc/igt@gem_render_tiled_bl...@basic.html
   [24]:

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

2022-03-25 Thread Das, Nirmoy




On 3/25/2022 3:28 PM, Animesh Manna wrote:

The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.

DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be right as anyways losing time.

To make the CI execution happy replaced drm_err() to drm_info()
for printing debug info during dsb buffer preparation.

v1: Initial version.
v2: Added print for mmio fallback at out label. [Nirmoy]

Cc: Nirmoy Das 
Signed-off-by: Animesh Manna 
---
  drivers/gpu/drm/i915/display/intel_dsb.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..86c0cf5a03b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -283,14 +283,12 @@ void intel_dsb_prepare(struct intel_crtc_state 
*crtc_state)
  
  	obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);

if (IS_ERR(obj)) {
-   drm_err(>drm, "Gem object creation failed\n");
kfree(dsb);
goto out;
}
  
  	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);

if (IS_ERR(vma)) {
-   drm_err(>drm, "Vma creation failed\n");
i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +296,6 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
  
  	buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);

if (IS_ERR(buf)) {
-   drm_err(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
kfree(dsb);
goto out;
@@ -311,6 +308,9 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
dsb->ins_start_offset = 0;
crtc_state->dsb = dsb;
  out:
+   if (!crtc_state->dsb)
+   drm_info(>drm, "Fallback to mmio for register 
programming\n");


From the info message, it is hard to know what happened: Something like:

"DSB queue setup failed, will fallback to MMIO for display HW 
programming" should be more understandable.



With such change, this is: Reviewed-by: Nirmoy Das 


Nirmoy



+
intel_runtime_pm_put(>runtime_pm, wakeref);
  }

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL   : https://patchwork.freedesktop.org/series/100532/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22681_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22681_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [FAIL][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk3/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk5/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk5/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk4/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk1/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk9/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk8/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/shard-glk2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk7/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk5/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk5/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk4/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk3/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk3/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/shard-glk3/boot.html
   [44]:

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

2022-03-25 Thread Souza, Jose

On Fri, 2022-03-25 at 14:21 +, Hogander, Jouni wrote:
> Hello Jose,
> 
> See my comments below.
> 
> On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> > Instead of exit PSR when a frontbuffer invalidation happens, we can
> > enable the PSR2 selective fetch continuous full frame, that will keep
> > the panel updated like PSR was disabled but without keeping PSR
> > active.
> 
> with keeping PSR active? I don't think it's like PSR was disabled. New
> full frame is updated only via atomic commit. Having PSR disabled new
> full frame is updated all the time as PSR wasn't existing at all.
> 
> > 
> > So as soon as the frontbuffer flush happens we can disable the
> > continuous full frame and start to do selective fetches much quicker
> > than the path that would enable PSR, that will wait a few frames
> > to actually activate PSR.
> > 
> > Also this approach has proven to fix some glitches found in
> > Alderlake-P
> > when there are a lot of invalidations happening together with page
> > flips.
> > 
> > Some may ask why it is writing to CURSURFLIVE(), it is because
> > that is the way that hardware team provided us to poke display to
> > handle PSR updates, and it is being used since display 9.
> 
> Generic comments:
> 
> Current logic is to disable psr2 in invalidate callback and start
> sending fullframe updates on every vblank period. This is done until
> flush callback where psr2 is re-enabled. Intention is to update
> possible frontbuffer writes between invalidate/flush instantly.
> 
> Now you are changing the logic to update one full frame when

It is not enabling the one full frame, it is enabling the continuous full frame 
so at every vblank panel will be updated until this bit cleared.

> frontbuffer write starts (_psr_invalidate_handle) and another one when
> it stops (_psr_flush_handle) without disabling psr at all. Have I
> understood your patch correctly?
> 
> Propably we wont notice this change as we have these invalidate/flush
> calls scattered around in the code. Also parallel atomic commits are
> triggering updates. In theory we could observe latency in updates
> between invalidate/flush? Do we care? What do you think?
> 
> Do we need to send update in invalidate at all? Isn't that usually
> called before doing any frontbuffer writing? I.e. we would be sending
> frame that is already in RFB?
> 
> > 
> > Cc: Khaled Almahallawy 
> > Cc: Shawn C Lee 
> > Cc: Jouni Högander 
> > Cc: Mika Kahola 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 109 -
> > --
> >  1 file changed, 95 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index d87b357806c91..f7b7b374374b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1450,6 +1450,22 @@ static inline u32
> > man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
> >  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> >  }
> > 
> > +static inline u32 man_trk_ctl_continuos_full_frame(struct
> > drm_i915_private *dev_priv)
> > +{
> > + return IS_ALDERLAKE_P(dev_priv) ?
> > +ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
> > +PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> > +}
> > +
> > +static inline u32 man_trk_ctl_su_region_start_end_mask(struct
> > drm_i915_private *dev_priv)
> > +{
> > + if (IS_ALDERLAKE_P(dev_priv))
> > + return ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK
> > > 
> > +ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
> > + return PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK |
> > +PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
> > +}
> > +
> >  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> >  {
> >   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > @@ -1546,8 +1562,9 @@ void intel_psr2_program_trans_man_trk_ctl(const
> > struct intel_crtc_state *crtc_st
> >   if (!crtc_state->enable_psr2_sel_fetch)
> >   return;
> > 
> > - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> > > cpu_transcoder),
> > -crtc_state->psr2_man_track_ctl);
> > + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> > > cpu_transcoder),
> > +  man_trk_ctl_su_region_start_end_mask(dev_priv),
> > +  crtc_state->psr2_man_track_ctl);
> 
> Should we actually now consider taking psr->lock here?

I don't think we need. mmio writes are syncronized, this will never set 
continuous full frame and will only clear su region start and end.
Also this function is called from a time sensitive section if we spend too much 
time here it will cause vblank evasion warnings.

> 
> >  }
> > 
> >  static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > *crtc_state,
> > @@ -2127,6 +2144,26 @@ static void intel_psr_work(struct

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127
URL   : https://patchwork.freedesktop.org/series/101792/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations
URL   : https://patchwork.freedesktop.org/series/101789/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22683


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22683 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22683, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/index.html

Participating hosts (45 -> 34)
--

  Missing(11): fi-bdw-samus bat-dg1-6 bat-dg2-8 bat-dg2-9 fi-bsw-cyan 
bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22683:

### IGT changes ###

 Possible regressions 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_linear_blits@basic:
- fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bwr-2160/igt@gem_render_linear_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bwr-2160/igt@gem_render_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-guc/igt@gem_render_tiled_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-kbl-guc/igt@gem_render_tiled_bl...@basic.html
- fi-rkl-guc: [PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-rkl-guc/igt@gem_render_tiled_bl...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-rkl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-elk-e7500:   [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][11] -> [INCOMPLETE][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-ilk-650/igt@gem_tiled_bl...@basic.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][14]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html

  
 Warnings 

  * igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k:   [INCOMPLETE][17] ([i915#1982]) -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@core_hotunplug@unbind-rebind:
- {fi-hsw-g3258}: [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html

  
Known issues


  Here are the changes found in Patchwork_22683 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#109315]) 
+17 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][22] ([fdo#109271]) +17 similar issues
   [22]:

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_22014226127

2022-03-25 Thread Matt Roper

On Fri, Mar 25, 2022 at 07:22:49AM -0700, José Roberto de Souza wrote:
> New DG2 workaround added to specification.
> 
> BSpec: 54077
> BSpec: 66622
> BSpec: 54833
> Cc: Matt Roper 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 62e0f075b1de7..17432b075d970 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1088,6 +1088,7 @@
>  #define EU_PERF_CNTL3_MMIO(0xe758)
>  
>  #define LSC_CHICKEN_BIT_0_MMIO(0xe7c8)
> +#define   DISABLE_D8_D16_COASLESCE   REG_BIT(30)
>  #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT   REG_BIT(15)
>  #define LSC_CHICKEN_BIT_0_UDW_MMIO(0xe7c8 + 4)
>  #define   DIS_CHAIN_2XSIMD8  REG_BIT(55 - 32)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index dc06f655a..29c8cd0a81b6f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2624,6 +2624,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
> *engine, struct i915_wa_li
>   wa_write_or(wal, GEN12_GAMCNTRL_CTRL, 
> INVALIDATION_BROADCAST_MODE_DIS |
>   GLOBAL_INVALIDATION_MODE);
>   }
> +
> + if (IS_DG2(i915)) {
> + /* Wa_22014226127:dg2 */
> + wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> + }
>  }
>  
>  static void
> -- 
> 2.35.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

2022-03-25 Thread Animesh Manna

The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.

DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be right as anyways losing time.

To make the CI execution happy replaced drm_err() to drm_info()
for printing debug info during dsb buffer preparation.

v1: Initial version.
v2: Added print for mmio fallback at out label. [Nirmoy]

Cc: Nirmoy Das 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..86c0cf5a03b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -283,14 +283,12 @@ void intel_dsb_prepare(struct intel_crtc_state 
*crtc_state)
 
obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
-   drm_err(>drm, "Gem object creation failed\n");
kfree(dsb);
goto out;
}
 
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
-   drm_err(>drm, "Vma creation failed\n");
i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +296,6 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
 
buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
-   drm_err(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
kfree(dsb);
goto out;
@@ -311,6 +308,9 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
dsb->ins_start_offset = 0;
crtc_state->dsb = dsb;
 out:
+   if (!crtc_state->dsb)
+   drm_info(>drm, "Fallback to mmio for register 
programming\n");
+
intel_runtime_pm_put(>runtime_pm, wakeref);
 }
 
-- 
2.29.0

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_22014226127

2022-03-25 Thread José Roberto de Souza

New DG2 workaround added to specification.

BSpec: 54077
BSpec: 66622
BSpec: 54833
Cc: Matt Roper 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 62e0f075b1de7..17432b075d970 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1088,6 +1088,7 @@
 #define EU_PERF_CNTL3  _MMIO(0xe758)
 
 #define LSC_CHICKEN_BIT_0  _MMIO(0xe7c8)
+#define   DISABLE_D8_D16_COASLESCE REG_BIT(30)
 #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
 #define LSC_CHICKEN_BIT_0_UDW  _MMIO(0xe7c8 + 4)
 #define   DIS_CHAIN_2XSIMD8REG_BIT(55 - 32)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index dc06f655a..29c8cd0a81b6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2624,6 +2624,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, 
INVALIDATION_BROADCAST_MODE_DIS |
GLOBAL_INVALIDATION_MODE);
}
+
+   if (IS_DG2(i915)) {
+   /* Wa_22014226127:dg2 */
+   wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+   }
 }
 
 static void
-- 
2.35.1

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

2022-03-25 Thread Hogander, Jouni

Hello Jose,

See my comments below.

On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> Instead of exit PSR when a frontbuffer invalidation happens, we can
> enable the PSR2 selective fetch continuous full frame, that will keep
> the panel updated like PSR was disabled but without keeping PSR
> active.

with keeping PSR active? I don't think it's like PSR was disabled. New
full frame is updated only via atomic commit. Having PSR disabled new
full frame is updated all the time as PSR wasn't existing at all.

> 
> So as soon as the frontbuffer flush happens we can disable the
> continuous full frame and start to do selective fetches much quicker
> than the path that would enable PSR, that will wait a few frames
> to actually activate PSR.
> 
> Also this approach has proven to fix some glitches found in
> Alderlake-P
> when there are a lot of invalidations happening together with page
> flips.
> 
> Some may ask why it is writing to CURSURFLIVE(), it is because
> that is the way that hardware team provided us to poke display to
> handle PSR updates, and it is being used since display 9.

Generic comments:

Current logic is to disable psr2 in invalidate callback and start
sending fullframe updates on every vblank period. This is done until
flush callback where psr2 is re-enabled. Intention is to update
possible frontbuffer writes between invalidate/flush instantly. 

Now you are changing the logic to update one full frame when
frontbuffer write starts (_psr_invalidate_handle) and another one when
it stops (_psr_flush_handle) without disabling psr at all. Have I
understood your patch correctly?

Propably we wont notice this change as we have these invalidate/flush
calls scattered around in the code. Also parallel atomic commits are
triggering updates. In theory we could observe latency in updates
between invalidate/flush? Do we care? What do you think?

Do we need to send update in invalidate at all? Isn't that usually
called before doing any frontbuffer writing? I.e. we would be sending
frame that is already in RFB?

> 
> Cc: Khaled Almahallawy 
> Cc: Shawn C Lee 
> Cc: Jouni Högander 
> Cc: Mika Kahola 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 109 -
> --
>  1 file changed, 95 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d87b357806c91..f7b7b374374b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1450,6 +1450,22 @@ static inline u32
> man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
>  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
>  }
>  
> +static inline u32 man_trk_ctl_continuos_full_frame(struct
> drm_i915_private *dev_priv)
> +{
> + return IS_ALDERLAKE_P(dev_priv) ?
> +ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
> +PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> +}
> +
> +static inline u32 man_trk_ctl_su_region_start_end_mask(struct
> drm_i915_private *dev_priv)
> +{
> + if (IS_ALDERLAKE_P(dev_priv))
> + return ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK
> |
> +ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
> + return PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK |
> +PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
> +}
> +
>  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  {
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1546,8 +1562,9 @@ void intel_psr2_program_trans_man_trk_ctl(const
> struct intel_crtc_state *crtc_st
>   if (!crtc_state->enable_psr2_sel_fetch)
>   return;
>  
> - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> >cpu_transcoder),
> -crtc_state->psr2_man_track_ctl);
> + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> >cpu_transcoder),
> +  man_trk_ctl_su_region_start_end_mask(dev_priv),
> +  crtc_state->psr2_man_track_ctl);

Should we actually now consider taking psr->lock here?

>  }
>  
>  static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> *crtc_state,
> @@ -2127,6 +2144,26 @@ static void intel_psr_work(struct work_struct
> *work)
>   mutex_unlock(_dp->psr.lock);
>  }
>  
> +static void _psr_invalidate_handle(struct intel_dp *intel_dp,
> +unsigned int
> prev_busy_frontbuffer_bits)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (intel_dp->psr.psr2_sel_fetch_enabled) {
> + u32 val = man_trk_ctl_continuos_full_frame(dev_priv) |
> +   man_trk_ctl_partial_frame_bit_get(dev_priv);
> +
> + /* continuos full frame is already enabled */
> + if (prev_busy_frontbuffer_bits)
> + return;

Should we still trigger the update using CURSURFLIVE? Or do we need
that at all in

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3b931b51817a drm/i915: Make .get_dplls() return int
1b2d4a4a599e drm/i915: Pass dev_priv to intel_shared_dpll_init()
33ae484eb053 drm/i915: Remove pointless dpll_funcs checks
4a49b686c648 drm/i915: Adjust .crtc_compute_clock() calling convention
2e1ac19c4047 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
4e89276790b2 drm/i915: Move the dpll_hw_state clearing to 
intel_dpll_crtc_compute_clock()
3f11772ea836 drm/i915: Clear the dpll_hw_state when disabling a pipe
ca60dc3a2f8a drm/i915: Split out dg2_crtc_compute_clock()
f71777efae30 drm/i915: Add crtc .crtc_get_shared_dpll()
c64fe9a7ba0c drm/i915: Split shared dpll .get_dplls() into compute and get 
phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: 
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+   SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
f78032f898c7 drm/i915: Do .crtc_compute_clock() earlier
4d0d47819c90 drm/i915: Clean up DPLL related debugs
5d0098769f10 drm/i915: Reassign DPLLs only for crtcs going throug 
.compute_config()

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: constify EDID parsing

== Series Details ==

Series: drm/edid: constify EDID parsing
URL   : https://patchwork.freedesktop.org/series/101787/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22682


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/index.html

Participating hosts (43 -> 40)
--

  Missing(3): fi-bsw-cyan shard-tglu fi-kbl-8809g 

Known issues


  Here are the changes found in Patchwork_22682 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#2373] / 
[i915#4983])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  NOTRUN -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  [INCOMPLETE][4] ([i915#4418]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@kms_busy@basic@flip:
- {bat-adlp-6}:   [DMESG-WARN][6] ([i915#3576]) -> [PASS][7] +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/bat-adlp-6/igt@kms_busy@ba...@flip.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22682/bat-adlp-6/igt@kms_busy@ba...@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341


Build changes
-

  * Linux: CI_DRM_11404 -> Patchwork_22682

  CI-20190529: 20190529
  CI_DRM_11404: 8df936777bab46f640732d755138b42dad779c15 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6393: 1d267ea1b829fa10b31a37ccf6b4a970f032784a @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22682: f4c384d459bcaf1744469639b883521f867fa4ac @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f4c384d459bc drm/edid: add more general struct edid constness in the interfaces
8962d0ea725c drm/edid: constify struct edid passed around in callbacks and 
closure
0699bb9a3bd8 drm/edid: constify struct edid passed to detailed blocks
520891b2ea1e drm/edid: constify struct detailed_timing in parsing callbacks
047632ecfcb0 drm/edid: constify struct detailed_timing in lower level parsing
1c90ada3dd1d drm/edid: use struct detailed_timing member access in gtf2 
functions
a720ca2b81fe drm/edid: use struct detailed_timing member access in is_rb()
4d7e2d1d7ed8 drm/edid: pass a timing pointer to is_display_descriptor()
c7362ef166c6 drm/edid: don't modify EDID while parsing

== Logs ==

For more details see:

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: constify EDID parsing

== Series Details ==

Series: drm/edid: constify EDID parsing
URL   : https://patchwork.freedesktop.org/series/101787/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

2022-03-25 Thread Das, Nirmoy




On 3/25/2022 2:22 PM, Manna, Animesh wrote:



-Original Message-
From: Das, Nirmoy 
Sent: Thursday, March 24, 2022 2:39 PM
To: Manna, Animesh ; intel-
g...@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in
dsb_prepare()


On 3/24/2022 8:43 AM, Animesh Manna wrote:

The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.

DSB has extra advantage of faster register programming which may go
away through mmio path. Adding wait for gem resource also may not be
right as anyways losing time.

To make the CI execution happy replaced drm_dbg_kms() to drm_info()
for printing debuf info during dsb buffer preparation.

Signed-off-by: Animesh Manna 
---
   drivers/gpu/drm/i915/display/intel_dsb.c | 8 
   1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..b68dd7bd5271 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -275,7 +275,7 @@ void intel_dsb_prepare(struct intel_crtc_state
*crtc_state)

dsb = kmalloc(sizeof(*dsb), GFP_KERNEL);
if (!dsb) {
-   drm_err(>drm, "DSB object creation failed\n");
+   drm_info(>drm, "DSB object creation failed\n");
return;
}

@@ -283,14 +283,14 @@ void intel_dsb_prepare(struct intel_crtc_state
*crtc_state)

obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
-   drm_err(>drm, "Gem object creation failed\n");
+   drm_info(>drm, "Gem object creation failed\n");

If CI is happy with drm_warn then it makes sense to use drm_warn.

Checked with CI team, seems drm_warn also considered as bug, is it ok to use 
drm_info?



In that case: don't print anything on each error and at out label,  you 
can print an info about the fallback option.



Nirmoy






kfree(dsb);
goto out;
}

vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
-   drm_err(>drm, "Vma creation failed\n");
+   drm_info(>drm, "Vma creation failed\n");


These messages are bit vague, add "DSB VMA creation failed" or something
similar.

With that Acked-by: Nirmoy Das 

Thanks for review, will modify in next version.

Regards,
Animesh
  


Nirmoy



i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +298,7 @@ void intel_dsb_prepare(struct intel_crtc_state
*crtc_state)

buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
-   drm_err(>drm, "Command buffer creation failed\n");
+   drm_info(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(,

I915_VMA_RELEASE_MAP);

kfree(dsb);
goto out;

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

2022-03-25 Thread Manna, Animesh



> -Original Message-
> From: Das, Nirmoy 
> Sent: Thursday, March 24, 2022 2:39 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in
> dsb_prepare()
> 
> 
> On 3/24/2022 8:43 AM, Animesh Manna wrote:
> > The request to aqquire gem resources is failing for DSB in rare
> > scenario where it is busy and the register programming will be done
> > through mmio fallback path.
> >
> > DSB has extra advantage of faster register programming which may go
> > away through mmio path. Adding wait for gem resource also may not be
> > right as anyways losing time.
> >
> > To make the CI execution happy replaced drm_dbg_kms() to drm_info()
> > for printing debuf info during dsb buffer preparation.
> >
> > Signed-off-by: Animesh Manna 
> > ---
> >   drivers/gpu/drm/i915/display/intel_dsb.c | 8 
> >   1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index b34a67309976..b68dd7bd5271 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -275,7 +275,7 @@ void intel_dsb_prepare(struct intel_crtc_state
> > *crtc_state)
> >
> > dsb = kmalloc(sizeof(*dsb), GFP_KERNEL);
> > if (!dsb) {
> > -   drm_err(>drm, "DSB object creation failed\n");
> > +   drm_info(>drm, "DSB object creation failed\n");
> > return;
> > }
> >
> > @@ -283,14 +283,14 @@ void intel_dsb_prepare(struct intel_crtc_state
> > *crtc_state)
> >
> > obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> > if (IS_ERR(obj)) {
> > -   drm_err(>drm, "Gem object creation failed\n");
> > +   drm_info(>drm, "Gem object creation failed\n");
> 
> If CI is happy with drm_warn then it makes sense to use drm_warn.

Checked with CI team, seems drm_warn also considered as bug, is it ok to use 
drm_info?

> 
> 
> > kfree(dsb);
> > goto out;
> > }
> >
> > vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> > if (IS_ERR(vma)) {
> > -   drm_err(>drm, "Vma creation failed\n");
> > +   drm_info(>drm, "Vma creation failed\n");
> 
> 
> These messages are bit vague, add "DSB VMA creation failed" or something
> similar.
> 
> With that Acked-by: Nirmoy Das 

Thanks for review, will modify in next version.

Regards,
Animesh
 
> 
> 
> Nirmoy
> 
> 
> > i915_gem_object_put(obj);
> > kfree(dsb);
> > goto out;
> > @@ -298,7 +298,7 @@ void intel_dsb_prepare(struct intel_crtc_state
> > *crtc_state)
> >
> > buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
> > if (IS_ERR(buf)) {
> > -   drm_err(>drm, "Command buffer creation failed\n");
> > +   drm_info(>drm, "Command buffer creation failed\n");
> > i915_vma_unpin_and_release(,
> I915_VMA_RELEASE_MAP);
> > kfree(dsb);
> > goto out;

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL   : https://patchwork.freedesktop.org/series/100532/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22681


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/index.html

Participating hosts (43 -> 43)
--

  Additional (2): bat-adlm-1 fi-pnv-d510 
  Missing(2): fi-bsw-cyan shard-tglu 

Known issues


  Here are the changes found in Patchwork_22681 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  NOTRUN -> [DMESG-FAIL][1] ([i915#4494] / [i915#4957])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#5341])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][4] ([i915#5127]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [INCOMPLETE][6] ([i915#5414]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/bat-rpls-2/igt@i915_pm_...@module-reload.html
- {bat-adlp-6}:   [DMESG-WARN][8] ([i915#3576]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/bat-adlp-6/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/bat-adlp-6/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  [INCOMPLETE][10] ([i915#4418]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-g3258}: [INCOMPLETE][12] ([i915#3303] / [i915#4785]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11404/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22681/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]:

Re: [Intel-gfx] [PATCH 3/9] drm/edid: use struct detailed_timing member access in is_rb()

On Fri, Mar 25, 2022 at 02:25:25PM +0200, Jani Nikula wrote:
> Use struct detailed_timing member access instead of direct offsets to
> avoid casting.
> 
> Use BUILD_BUG_ON() for sanity check.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> Note: Why can we use range.formula.cvt.flags directly in is_rb() while
> gtf2 functions check for range.flags == 0x02 first to ensure it's gtf2?

Looks to me like is_rb() is just borked.

Other weird stuff I just noticed is get_monitor_range() not doing
anything for flags!=0x1 cases. It also fails to handle the other
flags that were added to byte 4 in EDID 1.4.

> ---
>  drivers/gpu/drm/drm_edid.c | 12 +++-
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 48707eef1dc2..5396fa78e864 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2405,15 +2405,17 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb 
> *cb, void *closure)
>  }
>  
>  static void
> -is_rb(struct detailed_timing *t, void *data)
> +is_rb(struct detailed_timing *timing, void *data)
>  {
> - u8 *r = (u8 *)t;
> + bool *res = data;
>  
> - if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
> + if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))

Calling this 'timing' when it's not is a bit confusing. I'd probably
rename it to something else for all the display descriptor cases.

>   return;
>  
> - if (r[15] & 0x10)
> - *(bool *)data = true;
> + BUILD_BUG_ON(offsetof(typeof(*timing), 
> data.other_data.data.range.formula.cvt.flags) != 15);
> +
> + if (timing->data.other_data.data.range.formula.cvt.flags & 0x10)
> + *res = true;
>  }
>  
>  /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: constify EDID parsing

== Series Details ==

Series: drm/edid: constify EDID parsing
URL   : https://patchwork.freedesktop.org/series/101787/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c7362ef166c6 drm/edid: don't modify EDID while parsing
4d7e2d1d7ed8 drm/edid: pass a timing pointer to is_display_descriptor()
a720ca2b81fe drm/edid: use struct detailed_timing member access in is_rb()
1c90ada3dd1d drm/edid: use struct detailed_timing member access in gtf2 
functions
-:55: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#55: FILE: drivers/gpu/drm/drm_edid.c:2457:
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);

total: 0 errors, 1 warnings, 0 checks, 98 lines checked
047632ecfcb0 drm/edid: constify struct detailed_timing in lower level parsing
520891b2ea1e drm/edid: constify struct detailed_timing in parsing callbacks
0699bb9a3bd8 drm/edid: constify struct edid passed to detailed blocks
8962d0ea725c drm/edid: constify struct edid passed around in callbacks and 
closure
f4c384d459bc drm/edid: add more general struct edid constness in the interfaces

[Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier

From: Ville Syrjälä 

Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.

To allows us to eventually get accurate numbers for all our
DPLL clock derived state we need to move the DPLL calculation
to hapen much earlier. To that end we hoist it up to the just
after the fastset checks. For now we just do the easy code
motion, and the actual back feeding of the final DPLL clock
into the state will come later.

A slight change here is that now .crtc_compute_clock()
can get called while the shared_dpll is still assigned.
But since .crtc_compute_clock() no longer assignes new
shared_dplls this is perfectly fine.

TODO: I'd actually like to do this before the fastset check
so that if the DPLL state should change we actually do the
modeset. Which I think is what the video aficionados want,
but it might not be what the fans of fastboot want. Not yet
sure how to reconcile those conflicting requirements...

v2: s/return/goto/ in error handling

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +
 drivers/gpu/drm/i915/display/intel_dpll.c| 3 ---
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 1b7bc764498c..f6db0bd2da6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5000,10 +5000,6 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
crtc_state->update_wm_post = true;
 
if (mode_changed) {
-   ret = intel_dpll_crtc_compute_clock(state, crtc);
-   if (ret)
-   return ret;
-
ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
if (ret)
return ret;
@@ -7896,6 +7892,11 @@ static int intel_atomic_check(struct drm_device *dev,
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state)) {
any_ms = true;
+
+   ret = intel_dpll_crtc_compute_clock(state, crtc);
+   if (ret)
+   goto fail;
+
continue;
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 32918e082e9f..7c6e72555b82 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1456,9 +1456,6 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
 
drm_WARN_ON(>drm, !intel_crtc_needs_modeset(crtc_state));
 
-   if (drm_WARN_ON(>drm, crtc_state->shared_dpll))
-   return 0;
-
memset(_state->dpll_hw_state, 0,
   sizeof(crtc_state->dpll_hw_state));
 
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6)
URL   : https://patchwork.freedesktop.org/series/100532/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

Re: [Intel-gfx] [PATCH 2/9] drm/edid: pass a timing pointer to is_display_descriptor()

On Fri, Mar 25, 2022 at 02:25:24PM +0200, Jani Nikula wrote:
> Use struct member access instead of direct offsets to avoid lots of
> casts all over the place.
> 
> Use BUILD_BUG_ON() for sanity check.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/drm_edid.c | 26 +++---
>  1 file changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 1b552fe54f38..48707eef1dc2 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2331,10 +2331,14 @@ struct drm_display_mode *drm_mode_find_dmt(struct 
> drm_device *dev,
>  }
>  EXPORT_SYMBOL(drm_mode_find_dmt);
>  
> -static bool is_display_descriptor(const u8 d[18], u8 tag)
> +static bool is_display_descriptor(const struct detailed_timing *timing, u8 
> type)
>  {
> - return d[0] == 0x00 && d[1] == 0x00 &&
> - d[2] == 0x00 && d[3] == tag;
> + BUILD_BUG_ON(offsetof(typeof(*timing), pixel_clock) != 0);
> + BUILD_BUG_ON(offsetof(typeof(*timing), data.other_data.pad1) != 2);
> + BUILD_BUG_ON(offsetof(typeof(*timing), data.other_data.type) != 3);
> +
> + return timing->pixel_clock == 0 && timing->data.other_data.pad1 == 0 &&

This would probably be less confusing if we moved pixel_clock into
pixel_data and just had matching padding bytes/etc. in other_data.

The names of all structs are also rather weird. We should probably
change them to match the spec terminology a bit more closely:
18 byte descriptor,detailed timing descriptor,display descriptor.
But that's a separate topic.

> + timing->data.other_data.type == type;
>  }
>  
>  static bool is_detailed_timing_descriptor(const u8 d[18])
> @@ -2405,7 +2409,7 @@ is_rb(struct detailed_timing *t, void *data)
>  {
>   u8 *r = (u8 *)t;
>  
> - if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> + if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
>   return;
>  
>   if (r[15] & 0x10)
> @@ -2431,7 +2435,7 @@ find_gtf2(struct detailed_timing *t, void *data)
>  {
>   u8 *r = (u8 *)t;
>  
> - if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> + if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
>   return;
>  
>   if (r[10] == 0x02)
> @@ -2987,7 +2991,7 @@ do_inferred_modes(struct detailed_timing *timing, void 
> *c)
>   struct detailed_non_pixel *data = >data.other_data;
>   struct detailed_data_monitor_range *range = >data.range;
>  
> - if (!is_display_descriptor((const u8 *)timing, 
> EDID_DETAIL_MONITOR_RANGE))
> + if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
>   return;
>  
>   closure->modes += drm_dmt_modes_for_range(closure->connector,
> @@ -3067,7 +3071,7 @@ do_established_modes(struct detailed_timing *timing, 
> void *c)
>  {
>   struct detailed_mode_closure *closure = c;
>  
> - if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
> + if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
>   return;
>  
>   closure->modes += drm_est3_modes(closure->connector, timing);
> @@ -3122,7 +3126,7 @@ do_standard_modes(struct detailed_timing *timing, void 
> *c)
>   struct edid *edid = closure->edid;
>   int i;
>  
> - if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
> + if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
>   return;
>  
>   for (i = 0; i < 6; i++) {
> @@ -3231,7 +3235,7 @@ do_cvt_mode(struct detailed_timing *timing, void *c)
>  {
>   struct detailed_mode_closure *closure = c;
>  
> - if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
> + if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
>   return;
>  
>   closure->modes += drm_cvt_modes(closure->connector, timing);
> @@ -4491,7 +4495,7 @@ drm_parse_hdmi_vsdb_audio(struct drm_connector 
> *connector, const u8 *db)
>  static void
>  monitor_name(struct detailed_timing *t, void *data)
>  {
> - if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
> + if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_NAME))
>   return;
>  
>   *(u8 **)data = t->data.other_data.data.str.str;
> @@ -5226,7 +5230,7 @@ void get_monitor_range(struct detailed_timing *timing,
>   const struct detailed_non_pixel *data = >data.other_data;
>   const struct detailed_data_monitor_range *range = >data.range;
>  
> - if (!is_display_descriptor((const u8 *)timing, 
> EDID_DETAIL_MONITOR_RANGE))
> + if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
>   return;
>  
>   /*
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 1/9] drm/edid: don't modify EDID while parsing

On Fri, Mar 25, 2022 at 02:25:23PM +0200, Jani Nikula wrote:
> We'll want to keep the EDID immutable while parsing. Stop modifying the
> EDID because of the quirks.
> 
> In theory, this does have userspace implications, but the userspace is
> supposed to use the modes exposed via KMS API, not by parsing the EDID
> directly.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/drm_edid.c | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index cc7bd58369df..1b552fe54f38 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2740,9 +2740,9 @@ static struct drm_display_mode 
> *drm_mode_detailed(struct drm_device *dev,
>   return NULL;
>  
>   if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
> - timing->pixel_clock = cpu_to_le16(1088);
> -
> - mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
> + mode->clock = 1088 * 10;
> + else
> + mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
>  
>   mode->hdisplay = hactive;
>   mode->hsync_start = mode->hdisplay + hsync_offset;
> @@ -2763,14 +2763,14 @@ static struct drm_display_mode 
> *drm_mode_detailed(struct drm_device *dev,
>   drm_mode_do_interlace_quirk(mode, pt);
>  
>   if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
> - pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 
> DRM_EDID_PT_VSYNC_POSITIVE;
> + mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
> + } else {
> + mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
> + DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
> + mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
> + DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
>   }
>  
> - mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
> - DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
> - mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
> - DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
> -
>  set_size:
>   mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
>   mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 
> 8;
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention

From: Ville Syrjälä 

Pass the full atomic state+crtc rather than the redundant
crtc+crtc_state pair. We already need the full atomic state
in the hsw+ codepath anyway.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll.c| 83 
 drivers/gpu/drm/i915/display/intel_dpll.h|  4 +-
 3 files changed, 53 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 57d9b065622f..bb1ababe4577 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5001,7 +5001,7 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
 
if (mode_changed && crtc_state->hw.enable &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
-   ret = intel_dpll_crtc_compute_clock(crtc_state);
+   ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 1bd4a05dff7c..1c05ec167046 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -18,7 +18,8 @@
 #include "vlv_sideband.h"
 
 struct intel_dpll_funcs {
-   int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+   int (*crtc_compute_clock)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
 };
 
 struct intel_limit {
@@ -759,8 +760,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock)
 {
-   int refclk = 10;
const struct intel_limit *limit = _limits_bxt;
+   int refclk = 10;
 
return chv_find_best_dpll(limit, crtc_state,
  crtc_state->port_clock, refclk,
@@ -927,12 +928,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state 
*crtc_state,
crtc_state->dpll_hw_state.dpll = dpll;
 }
 
-static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
 {
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_atomic_state *state =
-   to_intel_atomic_state(crtc_state->uapi.state);
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
@@ -1070,12 +1071,12 @@ static void ilk_compute_dpll(struct intel_crtc_state 
*crtc_state,
crtc_state->dpll_hw_state.dpll = dpll;
 }
 
-static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
 {
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_atomic_state *state =
-   to_intel_atomic_state(crtc_state->uapi.state);
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 12;
int ret;
@@ -1167,11 +1168,14 @@ void chv_compute_dpll(struct intel_crtc_state 
*crtc_state)
(crtc_state->pixel_multiplier - 1) << 
DPLL_MD_UDI_MULTIPLIER_SHIFT;
 }
 
-static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int chv_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
 {
-   int refclk = 10;
+   struct drm_i915_private *i915 = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = _limits_chv;
-   struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+   int refclk = 10;
 
memset(_state->dpll_hw_state, 0,
   sizeof(crtc_state->dpll_hw_state));
@@ -1188,11 +1192,14 @@ static int chv_crtc_compute_clock(struct 
intel_crtc_state *crtc_state)
return 0;
 }
 
-static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
 {
-   int refclk = 10;
+

[Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases

From: Ville Syrjälä 

Split the DPLL state computation into a separate function
from the current .get_dplls() which currently serves a dual duty
by also reserving the shared DPLLs.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c |  14 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 291 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 +
 3 files changed, 235 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2ee7255f3c36..32918e082e9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state 
*crtc_state,
 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
-   return 0;
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+   struct intel_encoder *encoder =
+   intel_get_crtc_new_encoder(state, crtc_state);
+
+   if (DISPLAY_VER(dev_priv) < 11 &&
+   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+   return 0;
+
+   return intel_compute_shared_dplls(state, crtc, encoder);
 }
 
 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1140,7 +1150,7 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
ilk_compute_dpll(crtc_state, _state->dpll,
 _state->dpll);
 
-   return 0;
+   return intel_compute_shared_dplls(state, crtc, NULL);
 }
 
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22f55574a35c..d426724d5a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
 struct intel_dpll_mgr {
const struct dpll_info *dpll_info;
 
+   int (*compute_dplls)(struct intel_atomic_state *state,
+struct intel_crtc *crtc,
+struct intel_encoder *encoder);
int (*get_dplls)(struct intel_atomic_state *state,
 struct intel_crtc *crtc,
 struct intel_encoder *encoder);
@@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private 
*dev_priv,
udelay(200);
 }
 
+static int ibx_compute_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc,
+   struct intel_encoder *encoder)
+{
+   return 0;
+}
+
 static int ibx_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
 
 static const struct intel_dpll_mgr pch_pll_mgr = {
.dpll_info = pch_plls,
+   .compute_dplls = ibx_compute_dpll,
.get_dplls = ibx_get_dpll,
.put_dplls = intel_put_dpll,
.dump_hw_state = ibx_dump_hw_state,
@@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
 }
 
-static struct intel_shared_dpll *
-hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
-  struct intel_crtc *crtc)
+static int
+hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
 {
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
-   struct intel_shared_dpll *pll;
-   u32 val;
unsigned int p, n2, r2;
 
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, , , );
 
-   val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
- WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
- WRPLL_DIVIDER_POST(p);
+   crtc_state->dpll_hw_state.wrpll =
+   WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
+   WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+   WRPLL_DIVIDER_POST(p);
 
-   crtc_state->dpll_hw_state.wrpll = val;
+   return 0;
+}
 
-   pll = intel_find_shared_dpll(state, crtc,
-_state->dpll_hw_state,
-BIT(DPLL_ID_WRPLL2) |
-BIT(DPLL_ID_WRPLL1));
+static struct intel_shared_dpll *
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+  struct intel_crtc *crtc)
+{
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
 
-   if (!pll)
-   return NULL;
-
-   return pll;
+   return

[Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll()

From: Ville Syrjälä 

Start splitting the .compute_crtc_clock() into two parts; one
part does the computation, the second part does the shared dpll
assignment. I want to move the actual computation part much earlier
into the compute_config() phase.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c |  4 ++
 drivers/gpu/drm/i915/display/intel_dpll.c| 54 +++-
 drivers/gpu/drm/i915/display/intel_dpll.h|  2 +
 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 7c68bc07c925..1b7bc764498c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5003,6 +5003,10 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
+
+   ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+   if (ret)
+   return ret;
}
 
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index bc59efe18e89..2ee7255f3c36 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,8 @@
 struct intel_dpll_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
  struct intel_crtc *crtc);
+   int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
+   struct intel_crtc *crtc);
 };
 
 struct intel_limit {
@@ -930,6 +932,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state 
*crtc_state,
 
 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
+{
+   return 0;
+}
+
+static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
@@ -964,6 +972,12 @@ static int dg2_crtc_compute_clock(struct 
intel_atomic_state *state,
return intel_mpllb_calc_state(crtc_state, encoder);
 }
 
+static int dg2_crtc_get_shared_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   return 0;
+}
+
 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 {
return dpll->m < factor * dpll->n;
@@ -1087,7 +1101,6 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 12;
-   int ret;
 
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
@@ -1127,6 +1140,21 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
ilk_compute_dpll(crtc_state, _state->dpll,
 _state->dpll);
 
+   return 0;
+}
+
+static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+   int ret;
+
+   /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
+   if (!crtc_state->has_pch_encoder)
+   return 0;
+
ret = intel_reserve_shared_dplls(state, crtc, NULL);
if (ret) {
drm_dbg_kms(_priv->drm,
@@ -1372,14 +1400,17 @@ static int i8xx_crtc_compute_clock(struct 
intel_atomic_state *state,
 
 static const struct intel_dpll_funcs dg2_dpll_funcs = {
.crtc_compute_clock = dg2_crtc_compute_clock,
+   .crtc_get_shared_dpll = dg2_crtc_get_shared_dpll,
 };
 
 static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
+   .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
 };
 
 static const struct intel_dpll_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
+   .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
 };
 
 static const struct intel_dpll_funcs chv_dpll_funcs = {
@@ -1427,6 +1458,27 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
 }
 
+int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   struct drm_i915_private *i915 = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
+   drm_WARN_ON(>drm,

[Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

From: Ville Syrjälä 

Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.

This should also prevent .get_dplls() from seeing a funky port_clock
for DP even in cases where the readout produces a non-standard
clock and we (for some reason) have decided to not fully recompute
the state to remedy the situation.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 17 +
 drivers/gpu/drm/i915/display/intel_dpll.c|  6 ++
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f6db0bd2da6f..41442a1635d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7050,20 +7050,6 @@ intel_crtc_update_active_timings(const struct 
intel_crtc_state *crtc_state)
}
 }
 
-static void intel_modeset_clear_plls(struct intel_atomic_state *state)
-{
-   struct intel_crtc_state *new_crtc_state;
-   struct intel_crtc *crtc;
-   int i;
-
-   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-   if (!intel_crtc_needs_modeset(new_crtc_state))
-   continue;
-
-   intel_release_shared_dplls(state, crtc);
-   }
-}
-
 /*
  * This implements the workaround described in the "notes" section of the mode
  * set sequence documentation. When going from no pipes or single pipe to
@@ -7897,6 +7883,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+   intel_release_shared_dplls(state, crtc);
continue;
}
 
@@ -7944,8 +7931,6 @@ static int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
-
-   intel_modeset_clear_plls(state);
}
 
ret = intel_atomic_check_crtcs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index cbb444a2ba9d..23b3171bd0d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1443,11 +1443,9 @@ int intel_dpll_crtc_get_shared_dpll(struct 
intel_atomic_state *state,
int ret;
 
drm_WARN_ON(>drm, !intel_crtc_needs_modeset(crtc_state));
+   drm_WARN_ON(>drm, !crtc_state->hw.enable && 
crtc_state->shared_dpll);
 
-   if (drm_WARN_ON(>drm, crtc_state->shared_dpll))
-   return 0;
-
-   if (!crtc_state->hw.enable)
+   if (!crtc_state->hw.enable || crtc_state->shared_dpll)
return 0;
 
if (!i915->dpll_funcs->crtc_get_shared_dpll)
-- 
2.34.1

[Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs

From: Ville Syrjälä 

The debugs in lower level DPLL code don't really provide any
useful extra information AFAICS. Better just streamline the
code and just put the necessary debugs (to identify at which
step the modeset failed) into the higher level code. In
addition we'll get the full state dump as well, which should
hopefully have enough information to figure out what went wrong.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 75 +++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++-
 2 files changed, 35 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7c6e72555b82..cbb444a2ba9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
-   int ret;
 
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
 
-   ret = intel_reserve_shared_dplls(state, crtc, encoder);
-   if (ret) {
-   drm_dbg_kms(_priv->drm,
-   "failed to find PLL for pipe %c\n",
-   pipe_name(crtc->pipe));
-   return ret;
-   }
-
-   return 0;
+   return intel_reserve_shared_dplls(state, crtc, encoder);
 }
 
 static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1141,11 +1132,8 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
 
if (!crtc_state->clock_set &&
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-   refclk, NULL, _state->dpll)) {
-   drm_err(_priv->drm,
-   "Couldn't find PLL settings for mode!\n");
+   refclk, NULL, _state->dpll))
return -EINVAL;
-   }
 
ilk_compute_dpll(crtc_state, _state->dpll,
 _state->dpll);
@@ -1156,24 +1144,14 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
 {
-   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
-   int ret;
 
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
return 0;
 
-   ret = intel_reserve_shared_dplls(state, crtc, NULL);
-   if (ret) {
-   drm_dbg_kms(_priv->drm,
-   "failed to find PLL for pipe %c\n",
-   pipe_name(crtc->pipe));
-   return ret;
-   }
-
-   return 0;
+   return intel_reserve_shared_dplls(state, crtc, NULL);
 }
 
 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
@@ -1214,7 +1192,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
 static int chv_crtc_compute_clock(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
-   struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = _limits_chv;
@@ -1222,10 +1199,8 @@ static int chv_crtc_compute_clock(struct 
intel_atomic_state *state,
 
if (!crtc_state->clock_set &&
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-   refclk, NULL, _state->dpll)) {
-   drm_err(>drm, "Couldn't find PLL settings for mode!\n");
+   refclk, NULL, _state->dpll))
return -EINVAL;
-   }
 
chv_compute_dpll(crtc_state);
 
@@ -1235,7 +1210,6 @@ static int chv_crtc_compute_clock(struct 
intel_atomic_state *state,
 static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
-   struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = _limits_vlv;
@@ -1244,7 +1218,6 @@ static int vlv_crtc_compute_clock(struct 
intel_atomic_state *state,
if (!crtc_state->clock_set &&
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, _state->dpll)) {
-   drm_err(>drm,  "Couldn't find PLL settings for mode!\n");

[Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init()

From: Ville Syrjälä 

Stop passing around the drm_device and just pass the
dev_priv instead.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 -
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +--
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 3d2ff258f0a9..986e2e67ef91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9754,7 +9754,7 @@ int intel_modeset_init_nogem(struct drm_i915_private 
*i915)
}
 
intel_plane_possible_crtcs_init(i915);
-   intel_shared_dpll_init(dev);
+   intel_shared_dpll_init(i915);
intel_fdi_pll_freq_update(i915);
 
intel_update_czclk(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1d52796333ab..dc3c889b0aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4078,13 +4078,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
- * @dev: drm device
+ * @dev_priv: i915 device
  *
- * Initialize shared DPLLs for @dev.
+ * Initialize shared DPLLs for @dev_priv.
  */
-void intel_shared_dpll_init(struct drm_device *dev)
+void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
const struct intel_dpll_mgr *dpll_mgr = NULL;
const struct dpll_info *dpll_info;
int i;
@@ -4123,7 +4122,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_info = dpll_mgr->dpll_info;
 
for (i = 0; dpll_info[i].name; i++) {
-   drm_WARN_ON(dev, i != dpll_info[i].id);
+   drm_WARN_ON(_priv->drm, i != dpll_info[i].id);
dev_priv->dpll.shared_dplls[i].info = _info[i];
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 499a43e39123..f7c96a1f13c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -37,7 +37,6 @@
__a > __b ? (__a - __b) : (__b - __a); })
 
 enum tc_port;
-struct drm_device;
 struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc;
@@ -356,7 +355,7 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct drm_device *dev);
+void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
 void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
-- 
2.34.1

[Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock()

From: Ville Syrjälä 

DG2 doesn't currently used the shared_dpll stuff so let's just
split it out from hsw_crtc_compute_clock() entirely.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7960f1d52eaa..bc59efe18e89 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -938,9 +938,6 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state 
*state,
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
 
-   if (IS_DG2(dev_priv))
-   return intel_mpllb_calc_state(crtc_state, encoder);
-
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
@@ -956,6 +953,17 @@ static int hsw_crtc_compute_clock(struct 
intel_atomic_state *state,
return 0;
 }
 
+static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+   struct intel_encoder *encoder =
+   intel_get_crtc_new_encoder(state, crtc_state);
+
+   return intel_mpllb_calc_state(crtc_state, encoder);
+}
+
 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 {
return dpll->m < factor * dpll->n;
@@ -1362,6 +1370,10 @@ static int i8xx_crtc_compute_clock(struct 
intel_atomic_state *state,
return 0;
 }
 
+static const struct intel_dpll_funcs dg2_dpll_funcs = {
+   .crtc_compute_clock = dg2_crtc_compute_clock,
+};
+
 static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
 };
@@ -1418,7 +1430,9 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
 void
 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
 {
-   if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
+   if (IS_DG2(dev_priv))
+   dev_priv->dpll_funcs = _dpll_funcs;
+   else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->dpll_funcs = _dpll_funcs;
-- 
2.34.1

[Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()

From: Ville Syrjälä 

All .crtc_compute_clock() implementations do the same memset() to
clear the dpll_hw_state (since we preserve it across
intel_crtc_prepare_cleared_state()). Move the memset() to the common
wrapper.

Also clear it when we're about disable the pipe. Previously
it looks like we just left the old junk in there.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 24 +++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 
 2 files changed, 3 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 88d78a585304..494a343850e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1081,9 +1081,6 @@ static int ilk_crtc_compute_clock(struct 
intel_atomic_state *state,
int refclk = 12;
int ret;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
return 0;
@@ -1177,9 +1174,6 @@ static int chv_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit = _limits_chv;
int refclk = 10;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (!crtc_state->clock_set &&
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, _state->dpll)) {
@@ -1201,9 +1195,6 @@ static int vlv_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit = _limits_vlv;
int refclk = 10;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (!crtc_state->clock_set &&
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, _state->dpll)) {
@@ -1225,9 +1216,6 @@ static int g4x_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1273,9 +1261,6 @@ static int pnv_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1312,9 +1297,6 @@ static int i9xx_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1351,9 +1333,6 @@ static int i8xx_crtc_compute_clock(struct 
intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 48000;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1430,6 +1409,9 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
 
+   memset(_state->dpll_hw_state, 0,
+  sizeof(crtc_state->dpll_hw_state));
+
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index dc3c889b0aa6..22f55574a35c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1068,9 +1068,6 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_shared_dpll *pll = NULL;
 
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
else if (intel_crtc_has_dp_encoder(crtc_state))
@@ -1595,9 +1592,6 @@ static int skl_ddi_hdmi_pll_dividers(struct 
intel_crtc_state *crtc_state)

[Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe

From: Ville Syrjälä 

Clear the dpll_hw_state when we're about disable the pipe.
Previously it looks like we just left the old junk in there.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 494a343850e7..7960f1d52eaa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1406,12 +1406,12 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
if (drm_WARN_ON(>drm, crtc_state->shared_dpll))
return 0;
 
-   if (!crtc_state->hw.enable)
-   return 0;
-
memset(_state->dpll_hw_state, 0,
   sizeof(crtc_state->dpll_hw_state));
 
+   if (!crtc_state->hw.enable)
+   return 0;
+
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
 }
 
-- 
2.34.1

[Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations

From: Ville Syrjälä 

Start reordering when we do the clock/dpll calculations
during the atomic check. The eventual goals are:
- back feed the actually calculated clock into the crtc state
  so that stuff that depends on it (eg. watermarks) will be
  calculated based on the actual hardware state we're going to use
  rather than the semi-fictional state we started with
- fix the fastset/fastboot stuff to actually require exact
  clock matches. Avoids the current mess where the user asks
  to slightly change the refresh rate (eg. to match video frame
  rate) but the kernel decides to ignore it and do a fastset instead.

Ville Syrjälä (13):
  drm/i915: Make .get_dplls() return int
  drm/i915: Pass dev_priv to intel_shared_dpll_init()
  drm/i915: Remove pointless dpll_funcs checks
  drm/i915: Adjust .crtc_compute_clock() calling convention
  drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
  drm/i915: Move the dpll_hw_state clearing to
intel_dpll_crtc_compute_clock()
  drm/i915: Clear the dpll_hw_state when disabling a pipe
  drm/i915: Split out dg2_crtc_compute_clock()
  drm/i915: Add crtc .crtc_get_shared_dpll()
  drm/i915: Split shared dpll .get_dplls() into compute and get phases
  drm/i915: Do .crtc_compute_clock() earlier
  drm/i915: Clean up DPLL related debugs
  drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

 drivers/gpu/drm/i915/display/intel_display.c  |  33 +-
 drivers/gpu/drm/i915/display/intel_dpll.c | 249 
 drivers/gpu/drm/i915/display/intel_dpll.h |   6 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 531 +++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  12 +-
 5 files changed, 491 insertions(+), 340 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock()

From: Ville Syrjälä 

Move some checks into intel_dpll_crtc_compute_clock() from the
caller. Avoids the caller from having to worry about all this
crap.

We'll also reorder the hw.enable vs. shared_dpll checks since
it makes sense to sanity check that we've cleared out the
old shared_dpll even if the pipe is getting disabled.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c |  3 +--
 drivers/gpu/drm/i915/display/intel_dpll.c| 10 ++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index bb1ababe4577..7c68bc07c925 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4999,8 +4999,7 @@ static int intel_crtc_atomic_check(struct 
intel_atomic_state *state,
mode_changed && !crtc_state->hw.active)
crtc_state->update_wm_post = true;
 
-   if (mode_changed && crtc_state->hw.enable &&
-   !drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
+   if (mode_changed) {
ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 1c05ec167046..88d78a585304 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1419,6 +1419,16 @@ int intel_dpll_crtc_compute_clock(struct 
intel_atomic_state *state,
  struct intel_crtc *crtc)
 {
struct drm_i915_private *i915 = to_i915(state->base.dev);
+   struct intel_crtc_state *crtc_state =
+   intel_atomic_get_new_crtc_state(state, crtc);
+
+   drm_WARN_ON(>drm, !intel_crtc_needs_modeset(crtc_state));
+
+   if (drm_WARN_ON(>drm, crtc_state->shared_dpll))
+   return 0;
+
+   if (!crtc_state->hw.enable)
+   return 0;
 
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
 }
-- 
2.34.1

[Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks

From: Ville Syrjälä 

All platforms have dpll_funcs. Remove the pointless NULL checks.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 986e2e67ef91..57d9b065622f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7053,14 +7053,10 @@ intel_crtc_update_active_timings(const struct 
intel_crtc_state *crtc_state)
 
 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
 {
-   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int i;
 
-   if (!dev_priv->dpll_funcs)
-   return;
-
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
-- 
2.34.1

[Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int

From: Ville Syrjälä 

Get rid of the confusing back and forth between bools and ints
in the .get_dplls() stuff. Just make everything return an int.

Initial conversion done with cocci, with some manual fixups on top:
@find@
identifier func !~ "get_hw_state|_is_|needed";
typedef bool;
parameter list[N] P;
@@
- bool
+ int
 func(P)
{
<...
(
- return true;
+ return 0;
|
- return false;
+ return -EINVAL;
)
...>
}

@@
identifier find.func;
expression list[find.N] E;
expression X;
@@
- if (!func(E))
+ ret = func(E);
+ if (ret)
  {
  ...
- return X;
+ return ret;
  }

@@
identifier find.func;
expression X;
expression list[find.N] E;
@@
- if (!func(E))
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;

@@
identifier find.func;
expression list[find.N] E;
expression O, X;
typedef bool;
bool B;
@@
- B = func(E);
- if (O && !B)
+ if (O) {
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;
+ }

@@
identifier find.func;
expression list[find.N] E;
expression O, X;
@@
- if (O && !func(E))
+ if (O) {
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;
+ }

@@
identifier find.func;
expression list[find.N] E;
expression X;
typedef bool;
bool B;
@@
- B = func(E);
- if (!B)
+ ret = func(E);
+ if (ret)
  {
  ...
- return X;
+ return ret;
  }

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 242 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   6 +-
 3 files changed, 131 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 95b9d327ed4d..1bd4a05dff7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -935,6 +935,7 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state 
*crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
+   int ret;
 
if (IS_DG2(dev_priv))
return intel_mpllb_calc_state(crtc_state, encoder);
@@ -943,11 +944,12 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state 
*crtc_state)
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
 
-   if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
+   ret = intel_reserve_shared_dplls(state, crtc, encoder);
+   if (ret) {
drm_dbg_kms(_priv->drm,
"failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
-   return -EINVAL;
+   return ret;
}
 
return 0;
@@ -1076,6 +1078,7 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state 
*crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
const struct intel_limit *limit;
int refclk = 12;
+   int ret;
 
memset(_state->dpll_hw_state, 0,
   sizeof(crtc_state->dpll_hw_state));
@@ -1118,11 +1121,12 @@ static int ilk_crtc_compute_clock(struct 
intel_crtc_state *crtc_state)
ilk_compute_dpll(crtc_state, _state->dpll,
 _state->dpll);
 
-   if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
+   ret = intel_reserve_shared_dplls(state, crtc, NULL);
+   if (ret) {
drm_dbg_kms(_priv->drm,
"failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
-   return -EINVAL;
+   return ret;
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b7071da4b7e5..1d52796333ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,9 +90,9 @@ struct intel_shared_dpll_funcs {
 struct intel_dpll_mgr {
const struct dpll_info *dpll_info;
 
-   bool (*get_dplls)(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
+   int (*get_dplls)(struct intel_atomic_state *state,
+struct intel_crtc *crtc,
+struct intel_encoder *encoder);
void (*put_dplls)(struct intel_atomic_state *state,
  struct intel_crtc *crtc);
void (*update_active_dpll)(struct intel_atomic_state *state,
@@ -514,9 +514,9 @@ static void ibx_pch_dpll_disable(struct drm_i915_private 
*dev_priv,
udelay(200);
 }
 
-static bool ibx_get_dpll(struct intel_atomic_state *state,
-struct intel_crtc *crtc,
-struct intel_encoder *encoder)
+static int ibx_get_dpll(struct intel_atomic_state *state,
+   struct intel_crtc *crtc,
+   struct intel_encoder *encoder)
 {
struct intel_crtc_state

[Intel-gfx] [PATCH 9/9] drm/edid: add more general struct edid constness in the interfaces

With this, the remaining non-const parts are the ones that actually
modify the EDID, for example to fix corrupt EDID.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 21 +++--
 include/drm/drm_edid.h | 10 +-
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fae6f39897c8..a069c2ddb09d 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2150,7 +2150,7 @@ static u32 edid_extract_panel_id(const struct edid *edid)
 
 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
 {
-   struct edid *edid;
+   const struct edid *edid;
u32 panel_id;
 
edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
@@ -3659,7 +3659,7 @@ static bool drm_valid_hdmi_vic(u8 vic)
 }
 
 static int
-add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
+add_alternate_cea_modes(struct drm_connector *connector, const struct edid 
*edid)
 {
struct drm_device *dev = connector->dev;
struct drm_display_mode *mode, *tmp;
@@ -4340,7 +4340,7 @@ static void drm_parse_y420cmdb_bitmap(struct 
drm_connector *connector,
 }
 
 static int
-add_cea_modes(struct drm_connector *connector, struct edid *edid)
+add_cea_modes(struct drm_connector *connector, const struct edid *edid)
 {
const u8 *cea = drm_find_cea_extension(edid);
const u8 *db, *hdmi = NULL, *video = NULL;
@@ -4546,7 +4546,7 @@ static int get_monitor_name(const struct edid *edid, char 
name[13])
  * @bufsize: The size of the name buffer (should be at least 14 chars.)
  *
  */
-void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
+void drm_edid_get_monitor_name(const struct edid *edid, char *name, int 
bufsize)
 {
int name_length;
char buf[13];
@@ -4580,7 +4580,8 @@ static void clear_eld(struct drm_connector *connector)
  * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
  * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
  */
-static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
+static void drm_edid_to_eld(struct drm_connector *connector,
+   const struct edid *edid)
 {
uint8_t *eld = connector->eld;
const u8 *cea;
@@ -4676,7 +4677,7 @@ static void drm_edid_to_eld(struct drm_connector 
*connector, struct edid *edid)
  *
  * Return: The number of found SADs or negative number on error.
  */
-int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
+int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
 {
int count = 0;
int i, start, end, dbl;
@@ -4738,7 +4739,7 @@ EXPORT_SYMBOL(drm_edid_to_sad);
  * Return: The number of found Speaker Allocation Blocks or negative number on
  * error.
  */
-int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
+int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
 {
int count = 0;
int i, start, end, dbl;
@@ -4833,7 +4834,7 @@ EXPORT_SYMBOL(drm_av_sync_delay);
  *
  * Return: True if the monitor is HDMI, false if not or unknown.
  */
-bool drm_detect_hdmi_monitor(struct edid *edid)
+bool drm_detect_hdmi_monitor(const struct edid *edid)
 {
const u8 *edid_ext;
int i;
@@ -4871,7 +4872,7 @@ EXPORT_SYMBOL(drm_detect_hdmi_monitor);
  *
  * Return: True if the monitor supports audio, false otherwise.
  */
-bool drm_detect_monitor_audio(struct edid *edid)
+bool drm_detect_monitor_audio(const struct edid *edid)
 {
const u8 *edid_ext;
int i, j;
@@ -5538,7 +5539,7 @@ static int add_displayid_detailed_1_modes(struct 
drm_connector *connector,
 }
 
 static int add_displayid_detailed_modes(struct drm_connector *connector,
-   struct edid *edid)
+   const struct edid *edid)
 {
const struct displayid_block *block;
struct displayid_iter iter;
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 144c495b99c4..48b1bf9c315a 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -372,8 +372,8 @@ struct drm_connector;
 struct drm_connector_state;
 struct drm_display_mode;
 
-int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
-int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
+int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads);
+int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);
 int drm_av_sync_delay(struct drm_connector *connector,
  const struct drm_display_mode *mode);
 
@@ -569,8 +569,8 @@ int drm_add_edid_modes(struct drm_connector *connector, 
struct edid *edid);
 int drm_add_override_edid_modes(struct drm_connector *connector);
 
 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
-bool drm_detect_hdmi_monitor(struct edid *edid);
-bool

[Intel-gfx] [PATCH 8/9] drm/edid: constify struct edid passed around in callbacks and closure

Finalize detailed timing parsing constness by making struct edid also
const in callbacks and closure.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 48 +++---
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fad792ef2c79..fae6f39897c8 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -97,7 +97,7 @@ static int oui(u8 first, u8 second, u8 third)
 
 struct detailed_mode_closure {
struct drm_connector *connector;
-   struct edid *edid;
+   const struct edid *edid;
bool preferred;
u32 quirks;
int modes;
@@ -2419,7 +2419,7 @@ is_rb(const struct detailed_timing *timing, void *data)
 
 /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
 static bool
-drm_monitor_supports_rb(struct edid *edid)
+drm_monitor_supports_rb(const struct edid *edid)
 {
if (edid->revision >= 4) {
bool ret = false;
@@ -2447,7 +2447,7 @@ find_gtf2(const struct detailed_timing *timing, void 
*data)
 
 /* Secondary GTF curve kicks in above some break frequency */
 static int
-drm_gtf2_hbreak(struct edid *edid)
+drm_gtf2_hbreak(const struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
@@ -2459,7 +2459,7 @@ drm_gtf2_hbreak(struct edid *edid)
 }
 
 static int
-drm_gtf2_2c(struct edid *edid)
+drm_gtf2_2c(const struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
@@ -2471,7 +2471,7 @@ drm_gtf2_2c(struct edid *edid)
 }
 
 static int
-drm_gtf2_m(struct edid *edid)
+drm_gtf2_m(const struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
@@ -2483,7 +2483,7 @@ drm_gtf2_m(struct edid *edid)
 }
 
 static int
-drm_gtf2_k(struct edid *edid)
+drm_gtf2_k(const struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
@@ -2495,7 +2495,7 @@ drm_gtf2_k(struct edid *edid)
 }
 
 static int
-drm_gtf2_2j(struct edid *edid)
+drm_gtf2_2j(const struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
@@ -2510,7 +2510,7 @@ drm_gtf2_2j(struct edid *edid)
  * standard_timing_level - get std. timing level(CVT/GTF/DMT)
  * @edid: EDID block to scan
  */
-static int standard_timing_level(struct edid *edid)
+static int standard_timing_level(const struct edid *edid)
 {
if (edid->revision >= 2) {
if (edid->revision >= 4 && (edid->features & 
DRM_EDID_FEATURE_DEFAULT_GTF))
@@ -2553,7 +2553,7 @@ static int drm_mode_hsync(const struct drm_display_mode 
*mode)
  * and convert them into a real mode using CVT/GTF/DMT.
  */
 static struct drm_display_mode *
-drm_mode_std(struct drm_connector *connector, struct edid *edid,
+drm_mode_std(struct drm_connector *connector, const struct edid *edid,
 const struct std_timing *t)
 {
struct drm_device *dev = connector->dev;
@@ -2715,7 +2715,7 @@ drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
  * return a new struct drm_display_mode.
  */
 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
- struct edid *edid,
+ const struct edid *edid,
  const struct detailed_timing 
*timing,
  u32 quirks)
 {
@@ -2815,7 +2815,7 @@ static struct drm_display_mode *drm_mode_detailed(struct 
drm_device *dev,
 
 static bool
 mode_in_hsync_range(const struct drm_display_mode *mode,
-   struct edid *edid, const u8 *t)
+   const struct edid *edid, const u8 *t)
 {
int hsync, hmin, hmax;
 
@@ -2832,7 +2832,7 @@ mode_in_hsync_range(const struct drm_display_mode *mode,
 
 static bool
 mode_in_vsync_range(const struct drm_display_mode *mode,
-   struct edid *edid, const u8 *t)
+   const struct edid *edid, const u8 *t)
 {
int vsync, vmin, vmax;
 
@@ -2848,7 +2848,7 @@ mode_in_vsync_range(const struct drm_display_mode *mode,
 }
 
 static u32
-range_pixel_clock(struct edid *edid, const u8 *t)
+range_pixel_clock(const struct edid *edid, const u8 *t)
 {
/* unspecified */
if (t[9] == 0 || t[9] == 255)
@@ -2863,7 +2863,7 @@ range_pixel_clock(struct edid *edid, const u8 *t)
 }
 
 static bool
-mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
+mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
  const struct detailed_timing *timing)
 {
u32 max_clock;
@@ -2909,7 +2909,7 @@ static bool valid_inferred_mode(const struct 
drm_connector *connector,
 }
 
 static int
-drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
+drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid 
*edid,
const struct detailed_timing *timing)
 {
int i,

[Intel-gfx] [PATCH 7/9] drm/edid: constify struct edid passed to detailed blocks

Constify the first level of struct edid in detailed timing parsing. Also
switch to struct edid instead of u8.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 48 ++
 1 file changed, 23 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c006b09066bb..fad792ef2c79 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2349,38 +2349,37 @@ static bool is_detailed_timing_descriptor(const u8 
d[18])
 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
 
 static void
-cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
+cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
 {
int i, n;
u8 d = ext[0x02];
-   u8 *det_base = ext + d;
+   const u8 *det_base = ext + d;
 
if (d < 4 || d > 127)
return;
 
n = (127 - d) / 18;
for (i = 0; i < n; i++)
-   cb((struct detailed_timing *)(det_base + 18 * i), closure);
+   cb((const struct detailed_timing *)(det_base + 18 * i), 
closure);
 }
 
 static void
-vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
+vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
 {
unsigned int i, n = min((int)ext[0x02], 6);
-   u8 *det_base = ext + 5;
+   const u8 *det_base = ext + 5;
 
if (ext[0x01] != 1)
return; /* unknown version */
 
for (i = 0; i < n; i++)
-   cb((struct detailed_timing *)(det_base + 18 * i), closure);
+   cb((const struct detailed_timing *)(det_base + 18 * i), 
closure);
 }
 
 static void
-drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
+drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void 
*closure)
 {
int i;
-   struct edid *edid = (struct edid *)raw_edid;
 
if (edid == NULL)
return;
@@ -2388,8 +2387,8 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb 
*cb, void *closure)
for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
cb(&(edid->detailed_timings[i]), closure);
 
-   for (i = 1; i <= raw_edid[0x7e]; i++) {
-   u8 *ext = raw_edid + (i * EDID_LENGTH);
+   for (i = 1; i <= edid->extensions; i++) {
+   const u8 *ext = (const u8 *)edid + (i * EDID_LENGTH);
 
switch (*ext) {
case CEA_EXT:
@@ -2425,7 +2424,7 @@ drm_monitor_supports_rb(struct edid *edid)
if (edid->revision >= 4) {
bool ret = false;
 
-   drm_for_each_detailed_block((u8 *)edid, is_rb, );
+   drm_for_each_detailed_block(edid, is_rb, );
return ret;
}
 
@@ -2452,7 +2451,7 @@ drm_gtf2_hbreak(struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+   drm_for_each_detailed_block(edid, find_gtf2, );
 
BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
 
@@ -2464,7 +2463,7 @@ drm_gtf2_2c(struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+   drm_for_each_detailed_block(edid, find_gtf2, );
 
BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.c) != 13);
 
@@ -2476,7 +2475,7 @@ drm_gtf2_m(struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+   drm_for_each_detailed_block(edid, find_gtf2, );
 
BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.m) != 14);
 
@@ -2488,7 +2487,7 @@ drm_gtf2_k(struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+   drm_for_each_detailed_block(edid, find_gtf2, );
 
BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.k) != 16);
 
@@ -2500,7 +2499,7 @@ drm_gtf2_2j(struct edid *edid)
 {
const struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+   drm_for_each_detailed_block(edid, find_gtf2, );
 
BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.j) != 17);
 
@@ -3050,8 +3049,7 @@ add_inferred_modes(struct drm_connector *connector, 
struct edid *edid)
};
 
if (version_greater(edid, 1, 0))
-   drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
-   );
+   drm_for_each_detailed_block(edid, do_inferred_modes, );
 
return closure.modes;
 }
@@ -3130,8 +3128,8 @@ add_established_modes(struct drm_connector *connector, 
struct edid *edid)

[Intel-gfx] [PATCH 6/9] drm/edid: constify struct detailed_timing in parsing callbacks

Moving one level higher, constify struct detailed_timing pointers in
callbacks.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 40 --
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 593f151c1155..c006b09066bb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2346,7 +2346,7 @@ static bool is_detailed_timing_descriptor(const u8 d[18])
return d[0] != 0x00 || d[1] != 0x00;
 }
 
-typedef void detailed_cb(struct detailed_timing *timing, void *closure);
+typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
 
 static void
 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
@@ -2405,7 +2405,7 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb 
*cb, void *closure)
 }
 
 static void
-is_rb(struct detailed_timing *timing, void *data)
+is_rb(const struct detailed_timing *timing, void *data)
 {
bool *res = data;
 
@@ -2433,9 +2433,9 @@ drm_monitor_supports_rb(struct edid *edid)
 }
 
 static void
-find_gtf2(struct detailed_timing *timing, void *data)
+find_gtf2(const struct detailed_timing *timing, void *data)
 {
-   struct detailed_timing **res = data;
+   const struct detailed_timing **res = data;
 
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
@@ -2450,7 +2450,7 @@ find_gtf2(struct detailed_timing *timing, void *data)
 static int
 drm_gtf2_hbreak(struct edid *edid)
 {
-   struct detailed_timing *timing = NULL;
+   const struct detailed_timing *timing = NULL;
 
drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
@@ -2462,7 +2462,7 @@ drm_gtf2_hbreak(struct edid *edid)
 static int
 drm_gtf2_2c(struct edid *edid)
 {
-   struct detailed_timing *timing = NULL;
+   const struct detailed_timing *timing = NULL;
 
drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
@@ -2474,7 +2474,7 @@ drm_gtf2_2c(struct edid *edid)
 static int
 drm_gtf2_m(struct edid *edid)
 {
-   struct detailed_timing *timing = NULL;
+   const struct detailed_timing *timing = NULL;
 
drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
@@ -2486,7 +2486,7 @@ drm_gtf2_m(struct edid *edid)
 static int
 drm_gtf2_k(struct edid *edid)
 {
-   struct detailed_timing *timing = NULL;
+   const struct detailed_timing *timing = NULL;
 
drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
@@ -2498,7 +2498,7 @@ drm_gtf2_k(struct edid *edid)
 static int
 drm_gtf2_2j(struct edid *edid)
 {
-   struct detailed_timing *timing = NULL;
+   const struct detailed_timing *timing = NULL;
 
drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
@@ -3004,7 +3004,7 @@ drm_cvt_modes_for_range(struct drm_connector *connector, 
struct edid *edid,
 }
 
 static void
-do_inferred_modes(struct detailed_timing *timing, void *c)
+do_inferred_modes(const struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
const struct detailed_non_pixel *data = >data.other_data;
@@ -3086,7 +3086,7 @@ drm_est3_modes(struct drm_connector *connector, const 
struct detailed_timing *ti
 }
 
 static void
-do_established_modes(struct detailed_timing *timing, void *c)
+do_established_modes(const struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
 
@@ -3137,7 +3137,7 @@ add_established_modes(struct drm_connector *connector, 
struct edid *edid)
 }
 
 static void
-do_standard_modes(struct detailed_timing *timing, void *c)
+do_standard_modes(const struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
const struct detailed_non_pixel *data = >data.other_data;
@@ -3250,7 +3250,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
 }
 
 static void
-do_cvt_mode(struct detailed_timing *timing, void *c)
+do_cvt_mode(const struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
 
@@ -3279,7 +3279,7 @@ add_cvt_modes(struct drm_connector *connector, struct 
edid *edid)
 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
 
 static void
-do_detailed_mode(struct detailed_timing *timing, void *c)
+do_detailed_mode(const struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
struct drm_display_mode *newmode;
@@ -4512,17 +4512,19 @@ drm_parse_hdmi_vsdb_audio(struct drm_connector 
*connector, const u8 *db)
 }
 
 static void
-monitor_name(struct detailed_timing *t, void *data)
+monitor_name(const struct detailed_timing *timing, void *data)
 {
-   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_NAME))
+   const char **res = data;
+
+   if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
return;
 
-   *(u8 **)data = t->data.other_data.data.str.str;
+

[Intel-gfx] [PATCH 4/9] drm/edid: use struct detailed_timing member access in gtf2 functions

Use struct detailed_timing member access instead of direct offsets to
avoid casting.

Use BUILD_BUG_ON() for sanity check.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 57 +-
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5396fa78e864..a9df75cdcc5b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2433,61 +2433,78 @@ drm_monitor_supports_rb(struct edid *edid)
 }
 
 static void
-find_gtf2(struct detailed_timing *t, void *data)
+find_gtf2(struct detailed_timing *timing, void *data)
 {
-   u8 *r = (u8 *)t;
+   struct detailed_timing **res = data;
 
-   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
 
-   if (r[10] == 0x02)
-   *(u8 **)data = r;
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.flags) != 10);
+
+   if (timing->data.other_data.data.range.flags == 0x02)
+   *res = timing;
 }
 
 /* Secondary GTF curve kicks in above some break frequency */
 static int
 drm_gtf2_hbreak(struct edid *edid)
 {
-   u8 *r = NULL;
+   struct detailed_timing *timing = NULL;
+
+   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
-   return r ? (r[12] * 2) : 0;
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
+
+   return timing ? 
timing->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
 }
 
 static int
 drm_gtf2_2c(struct edid *edid)
 {
-   u8 *r = NULL;
+   struct detailed_timing *timing = NULL;
+
+   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.c) != 13);
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
-   return r ? r[13] : 0;
+   return timing ? timing->data.other_data.data.range.formula.gtf2.c : 0;
 }
 
 static int
 drm_gtf2_m(struct edid *edid)
 {
-   u8 *r = NULL;
+   struct detailed_timing *timing = NULL;
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
-   return r ? (r[15] << 8) + r[14] : 0;
+   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.m) != 14);
+
+   return timing ? 
le16_to_cpu(timing->data.other_data.data.range.formula.gtf2.m) : 0;
 }
 
 static int
 drm_gtf2_k(struct edid *edid)
 {
-   u8 *r = NULL;
+   struct detailed_timing *timing = NULL;
+
+   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
-   return r ? r[16] : 0;
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.k) != 16);
+
+   return timing ? timing->data.other_data.data.range.formula.gtf2.k : 0;
 }
 
 static int
 drm_gtf2_2j(struct edid *edid)
 {
-   u8 *r = NULL;
+   struct detailed_timing *timing = NULL;
+
+   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
+
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.gtf2.j) != 17);
 
-   drm_for_each_detailed_block((u8 *)edid, find_gtf2, );
-   return r ? r[17] : 0;
+   return timing ? timing->data.other_data.data.range.formula.gtf2.j : 0;
 }
 
 /**
-- 
2.30.2

[Intel-gfx] [PATCH 5/9] drm/edid: constify struct detailed_timing in lower level parsing

Start constifying the struct detailed_timing pointers being passed
around from bottom up.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 40 +++---
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a9df75cdcc5b..593f151c1155 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2555,7 +2555,7 @@ static int drm_mode_hsync(const struct drm_display_mode 
*mode)
  */
 static struct drm_display_mode *
 drm_mode_std(struct drm_connector *connector, struct edid *edid,
-struct std_timing *t)
+const struct std_timing *t)
 {
struct drm_device *dev = connector->dev;
struct drm_display_mode *m, *mode = NULL;
@@ -2673,7 +2673,7 @@ drm_mode_std(struct drm_connector *connector, struct edid 
*edid,
  */
 static void
 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
-   struct detailed_pixel_timing *pt)
+   const struct detailed_pixel_timing *pt)
 {
int i;
static const struct {
@@ -2717,11 +2717,11 @@ drm_mode_do_interlace_quirk(struct drm_display_mode 
*mode,
  */
 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
  struct edid *edid,
- struct detailed_timing 
*timing,
+ const struct detailed_timing 
*timing,
  u32 quirks)
 {
struct drm_display_mode *mode;
-   struct detailed_pixel_timing *pt = >data.pixel_data;
+   const struct detailed_pixel_timing *pt = >data.pixel_data;
unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
@@ -2816,7 +2816,7 @@ static struct drm_display_mode *drm_mode_detailed(struct 
drm_device *dev,
 
 static bool
 mode_in_hsync_range(const struct drm_display_mode *mode,
-   struct edid *edid, u8 *t)
+   struct edid *edid, const u8 *t)
 {
int hsync, hmin, hmax;
 
@@ -2833,7 +2833,7 @@ mode_in_hsync_range(const struct drm_display_mode *mode,
 
 static bool
 mode_in_vsync_range(const struct drm_display_mode *mode,
-   struct edid *edid, u8 *t)
+   struct edid *edid, const u8 *t)
 {
int vsync, vmin, vmax;
 
@@ -2849,7 +2849,7 @@ mode_in_vsync_range(const struct drm_display_mode *mode,
 }
 
 static u32
-range_pixel_clock(struct edid *edid, u8 *t)
+range_pixel_clock(struct edid *edid, const u8 *t)
 {
/* unspecified */
if (t[9] == 0 || t[9] == 255)
@@ -2865,10 +2865,10 @@ range_pixel_clock(struct edid *edid, u8 *t)
 
 static bool
 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
- struct detailed_timing *timing)
+ const struct detailed_timing *timing)
 {
u32 max_clock;
-   u8 *t = (u8 *)timing;
+   const u8 *t = (const u8 *)timing;
 
if (!mode_in_hsync_range(mode, edid, t))
return false;
@@ -2911,7 +2911,7 @@ static bool valid_inferred_mode(const struct 
drm_connector *connector,
 
 static int
 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
-   struct detailed_timing *timing)
+   const struct detailed_timing *timing)
 {
int i, modes = 0;
struct drm_display_mode *newmode;
@@ -2946,7 +2946,7 @@ void drm_mode_fixup_1366x768(struct drm_display_mode 
*mode)
 
 static int
 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
-   struct detailed_timing *timing)
+   const struct detailed_timing *timing)
 {
int i, modes = 0;
struct drm_display_mode *newmode;
@@ -2975,7 +2975,7 @@ drm_gtf_modes_for_range(struct drm_connector *connector, 
struct edid *edid,
 
 static int
 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
-   struct detailed_timing *timing)
+   const struct detailed_timing *timing)
 {
int i, modes = 0;
struct drm_display_mode *newmode;
@@ -3007,8 +3007,8 @@ static void
 do_inferred_modes(struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
-   struct detailed_non_pixel *data = >data.other_data;
-   struct detailed_data_monitor_range *range = >data.range;
+   const struct detailed_non_pixel *data = >data.other_data;
+   const struct detailed_data_monitor_range *range = >data.range;
 
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
@@ -3057,11 +3057,11 @@ add_inferred_modes(struct drm_connector

[Intel-gfx] [PATCH 3/9] drm/edid: use struct detailed_timing member access in is_rb()

Use struct detailed_timing member access instead of direct offsets to
avoid casting.

Use BUILD_BUG_ON() for sanity check.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 

---

Note: Why can we use range.formula.cvt.flags directly in is_rb() while
gtf2 functions check for range.flags == 0x02 first to ensure it's gtf2?
---
 drivers/gpu/drm/drm_edid.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 48707eef1dc2..5396fa78e864 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2405,15 +2405,17 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb 
*cb, void *closure)
 }
 
 static void
-is_rb(struct detailed_timing *t, void *data)
+is_rb(struct detailed_timing *timing, void *data)
 {
-   u8 *r = (u8 *)t;
+   bool *res = data;
 
-   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
 
-   if (r[15] & 0x10)
-   *(bool *)data = true;
+   BUILD_BUG_ON(offsetof(typeof(*timing), 
data.other_data.data.range.formula.cvt.flags) != 15);
+
+   if (timing->data.other_data.data.range.formula.cvt.flags & 0x10)
+   *res = true;
 }
 
 /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
-- 
2.30.2

[Intel-gfx] [PATCH 2/9] drm/edid: pass a timing pointer to is_display_descriptor()

Use struct member access instead of direct offsets to avoid lots of
casts all over the place.

Use BUILD_BUG_ON() for sanity check.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1b552fe54f38..48707eef1dc2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2331,10 +2331,14 @@ struct drm_display_mode *drm_mode_find_dmt(struct 
drm_device *dev,
 }
 EXPORT_SYMBOL(drm_mode_find_dmt);
 
-static bool is_display_descriptor(const u8 d[18], u8 tag)
+static bool is_display_descriptor(const struct detailed_timing *timing, u8 
type)
 {
-   return d[0] == 0x00 && d[1] == 0x00 &&
-   d[2] == 0x00 && d[3] == tag;
+   BUILD_BUG_ON(offsetof(typeof(*timing), pixel_clock) != 0);
+   BUILD_BUG_ON(offsetof(typeof(*timing), data.other_data.pad1) != 2);
+   BUILD_BUG_ON(offsetof(typeof(*timing), data.other_data.type) != 3);
+
+   return timing->pixel_clock == 0 && timing->data.other_data.pad1 == 0 &&
+   timing->data.other_data.type == type;
 }
 
 static bool is_detailed_timing_descriptor(const u8 d[18])
@@ -2405,7 +2409,7 @@ is_rb(struct detailed_timing *t, void *data)
 {
u8 *r = (u8 *)t;
 
-   if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
return;
 
if (r[15] & 0x10)
@@ -2431,7 +2435,7 @@ find_gtf2(struct detailed_timing *t, void *data)
 {
u8 *r = (u8 *)t;
 
-   if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_RANGE))
return;
 
if (r[10] == 0x02)
@@ -2987,7 +2991,7 @@ do_inferred_modes(struct detailed_timing *timing, void *c)
struct detailed_non_pixel *data = >data.other_data;
struct detailed_data_monitor_range *range = >data.range;
 
-   if (!is_display_descriptor((const u8 *)timing, 
EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
 
closure->modes += drm_dmt_modes_for_range(closure->connector,
@@ -3067,7 +3071,7 @@ do_established_modes(struct detailed_timing *timing, void 
*c)
 {
struct detailed_mode_closure *closure = c;
 
-   if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
+   if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
return;
 
closure->modes += drm_est3_modes(closure->connector, timing);
@@ -3122,7 +3126,7 @@ do_standard_modes(struct detailed_timing *timing, void *c)
struct edid *edid = closure->edid;
int i;
 
-   if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
+   if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
return;
 
for (i = 0; i < 6; i++) {
@@ -3231,7 +3235,7 @@ do_cvt_mode(struct detailed_timing *timing, void *c)
 {
struct detailed_mode_closure *closure = c;
 
-   if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
+   if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
return;
 
closure->modes += drm_cvt_modes(closure->connector, timing);
@@ -4491,7 +4495,7 @@ drm_parse_hdmi_vsdb_audio(struct drm_connector 
*connector, const u8 *db)
 static void
 monitor_name(struct detailed_timing *t, void *data)
 {
-   if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
+   if (!is_display_descriptor(t, EDID_DETAIL_MONITOR_NAME))
return;
 
*(u8 **)data = t->data.other_data.data.str.str;
@@ -5226,7 +5230,7 @@ void get_monitor_range(struct detailed_timing *timing,
const struct detailed_non_pixel *data = >data.other_data;
const struct detailed_data_monitor_range *range = >data.range;
 
-   if (!is_display_descriptor((const u8 *)timing, 
EDID_DETAIL_MONITOR_RANGE))
+   if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
 
/*
-- 
2.30.2

[Intel-gfx] [PATCH 1/9] drm/edid: don't modify EDID while parsing

We'll want to keep the EDID immutable while parsing. Stop modifying the
EDID because of the quirks.

In theory, this does have userspace implications, but the userspace is
supposed to use the modes exposed via KMS API, not by parsing the EDID
directly.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index cc7bd58369df..1b552fe54f38 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2740,9 +2740,9 @@ static struct drm_display_mode *drm_mode_detailed(struct 
drm_device *dev,
return NULL;
 
if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
-   timing->pixel_clock = cpu_to_le16(1088);
-
-   mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
+   mode->clock = 1088 * 10;
+   else
+   mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
 
mode->hdisplay = hactive;
mode->hsync_start = mode->hdisplay + hsync_offset;
@@ -2763,14 +2763,14 @@ static struct drm_display_mode 
*drm_mode_detailed(struct drm_device *dev,
drm_mode_do_interlace_quirk(mode, pt);
 
if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
-   pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 
DRM_EDID_PT_VSYNC_POSITIVE;
+   mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
+   } else {
+   mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+   DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
+   mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+   DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
}
 
-   mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
-   DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
-   mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
-   DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
-
 set_size:
mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 
8;
-- 
2.30.2

[Intel-gfx] [PATCH 0/9] drm/edid: constify EDID parsing

Remove accidental (?) EDID modification while parsing, and constify EDID
in most places during EDID parsing.

In the future I'll want more clarity on who modifies the EDID and where,
and I'll want the compiler to help.

The EDID is still mutable in places that do validity checking and try to
fix it in the process. I'll probably want to split the two into separate
check and fix steps too, but that's for another series.

This is based on current drm-tip, without the CEA iterators work.


BR,
Jani.


Cc: Ville Syrjälä 

Jani Nikula (9):
  drm/edid: don't modify EDID while parsing
  drm/edid: pass a timing pointer to is_display_descriptor()
  drm/edid: use struct detailed_timing member access in is_rb()
  drm/edid: use struct detailed_timing member access in gtf2 functions
  drm/edid: constify struct detailed_timing in lower level parsing
  drm/edid: constify struct detailed_timing in parsing callbacks
  drm/edid: constify struct edid passed to detailed blocks
  drm/edid: constify struct edid passed around in callbacks and closure
  drm/edid: add more general struct edid constness in the interfaces

 drivers/gpu/drm/drm_edid.c | 272 -
 include/drm/drm_edid.h |  10 +-
 2 files changed, 153 insertions(+), 129 deletions(-)

-- 
2.30.2

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details ==

Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL   : https://patchwork.freedesktop.org/series/101781/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22680


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22680 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22680, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/index.html

Participating hosts (45 -> 40)
--

  Additional (2): bat-adlp-4 fi-pnv-d510 
  Missing(7): shard-tglu fi-bsw-cyan fi-hsw-4770 shard-rkl shard-dg1 
bat-jsl-2 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22680:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/bat-adlp-4/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-2}:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/bat-rpls-2/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_22680 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-dg1-6:  [PASS][3] -> [FAIL][4] ([i915#5200])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-dg1-6/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/bat-dg1-6/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#5341])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][7] ([i915#5127]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][9] ([i915#4391]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_module_l...@reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/bat-rpls-2/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [INCOMPLETE][11] ([i915#5414]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u:   [DMESG-WARN][13] ([i915#295] / [i915#5341]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u:   [DMESG-WARN][15] ([i915#295]) -> [PASS][16] +10 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22680/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#295]:

Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header

On Fri, 25 Mar 2022, Tvrtko Ursulin  wrote:
> On 24/03/2022 18:57, Jani Nikula wrote:
>> On Thu, 24 Mar 2022, Tvrtko Ursulin  wrote:
>>> On 24/03/2022 11:57, Jani Nikula wrote:
 On Thu, 24 Mar 2022, Tvrtko Ursulin  wrote:
> On 24/03/2022 09:31, Jani Nikula wrote:
>> On Tue, 22 Mar 2022, Tvrtko Ursulin  
>> wrote:
>>> From: Tvrtko Ursulin 
>>>
>>> ...
>>>
>>> Signed-off-by: Tvrtko Ursulin 
>>> Cc: Jani Nikula 
>>> Cc: Lucas De Marchi 
>>> ---
>>> Typed up how I see it - bash away.
>>
>> So is intel_vtd_active() so performance critical that it needs to be
>> inline?
>>
>> We're passing struct drm_i915_private * everywhere we can, and it just
>> feels silly to use struct drm_device * to avoid the include.
>>
>> Static inlines considered harmful. :p
>
> Same as it is ;), and gee, who was it that he said he was just trying to
> declutter i915_drv.h.. ;p

 Not at the cost of clarity elsewhere!
>>>
>>> To be clear now you oppose intel_vtd_active taking struct device? I
>>> thought you expressed general agreement when I presented the idea in the
>>> previous thread.
>>>
>>> I don't mind hugely to go either way, but I also don't see how taking
>>> struct device makes anything unclear. (I only think
>>> intel_vtd_run_as_guest is really wrong in this story but that's old news.)
>>>
>>> And if I make it take i915 then I would want to name it i915_vtd_active
>>> as well. But then you wouldn't like that.
>>>
>>> Should we just stuff all this into i915_utils for now, as I think Lucas
>>> suggested? Static inline or not, I don't care.
>> 
>> Just general grumpiness.
>> 
>> Acked-by: Jani Nikula 
>
> No worries. Ack is for this version or with i915_ prefixes in 
> i915_utils.h/c?

Both. Either. ;)

>
> Regards,
>
> Tvrtko

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details ==

Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL   : https://patchwork.freedesktop.org/series/101781/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details ==

Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL   : https://patchwork.freedesktop.org/series/101781/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details ==

Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)
URL   : https://patchwork.freedesktop.org/series/101781/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e3f9a29e30e4 drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB
-:11: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by 
Signed-off-by:
#11: 
Co-developed-by: Jordan Justen 
Cc: Jon Bloomfield 
total: 0 errors, 1 warnings, 0 checks, 25 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix one mem leak in mmap_offset_attach() (rev5)

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5)
URL   : https://patchwork.freedesktop.org/series/100532/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22679


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22679 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22679, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/index.html

Participating hosts (44 -> 41)
--

  Additional (1): bat-adlp-4 
  Missing(4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22679:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/bat-adlp-4/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22679 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#1436] / 
[i915#2722] / [i915#4312])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [DMESG-WARN][5] ([i915#4391]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_module_l...@reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/bat-rpls-2/igt@i915_module_l...@reload.html

  * igt@kms_busy@basic@flip:
- {bat-adlp-6}:   [DMESG-WARN][7] ([i915#3576]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-adlp-6/igt@kms_busy@ba...@flip.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/bat-adlp-6/igt@kms_busy@ba...@flip.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u:   [DMESG-WARN][9] ([i915#295] / [i915#5341]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u:   [DMESG-WARN][11] ([i915#295]) -> [PASS][12] +10 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339
  [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
  [i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342
  [i915#5401]: https://gitlab.freedesktop.org/drm/intel/issues/5401
  [i915#5414]: https://gitlab.freedesktop.org/drm/intel/issues/5414


Build changes
-

  * Linux: CI_DRM_11403 -> Patchwork_22679

  CI-20190529: 20190529
  CI_DRM_11403: 76ccfdacc3c78b22c90127356a2d19241f452208 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6392: 5a78ea9ff9c0a77bec5b094bf7e9d82c9848702b @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22679: 7045673f0005a3dbfa21d4f985ca9c8f017775d7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7045673f0005 drm/i915: fix one mem leak in mmap_offset_attach()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22679/index.html

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix one mem leak in mmap_offset_attach() (rev5)

== Series Details ==

Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5)
URL   : https://patchwork.freedesktop.org/series/100532/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

Re: [Intel-gfx] [PATCH] drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

2022-03-25 Thread Tvrtko Ursulin




On 25/03/2022 09:53, Daniel Vetter wrote:

On Fri, Mar 25, 2022 at 09:49:16AM +, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

UAPI with absolutely no documentation should not have been added -
clarify blob format and content will be described externally.

Fixes: 78e1fb3112c0 ("drm/i915/uapi: Add query for hwconfig blob")
Signed-off-by: Tvrtko Ursulin 
Co-developed-by: Jordan Justen 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: John Harrison 
Cc: Jon Ewins 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  include/uapi/drm/i915_drm.h | 13 +
  1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 071ffd9d51f1..8d0719bee8fc 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2683,6 +2683,9 @@ struct drm_i915_perf_oa_config {
   *
   * The behaviour is determined by the @query_id. Note that exactly what
   * @data_ptr is also depends on the specific @query_id.
+ *
+ * For specific queries see:
+ *  * `GuC HWCONFIG blob uAPI`_


I'd put this into the @query_id section, and then make it an item list
with the #define as the label, so that it becomes tidy and can neatly
iterate them all.

Anyway we can bikeshed this all more in a follow-up.

Reviewed-by: Daniel Vetter 


Thanks, yes I wanted to do the minimal thing to close the gap.

   */
  struct drm_i915_query_item {
/** @query_id: The id for this query */
@@ -3135,6 +3138,16 @@ struct drm_i915_query_memory_regions {
struct drm_i915_memory_region_info regions[];
  };
  
+/**

+ * DOC: GuC HWCONFIG blob uAPI
+ *
+ * The GuC produces a blob with information about the current device.
+ * i915 reads this blob from GuC and makes it available via this uAPI.
+ *
+ * The format and meading of the blob content are documented in the


Meading? I will fix that up while merging.

Regards,

Tvrtko


+ * Programmer's Reference Manual.
+ */
+
  /**
   * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
   * extension support using struct i915_user_extension.
--
2.32.0

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB