== Series Details ==
Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during
loading/disabling the firmware (rev2)
URL : https://patchwork.freedesktop.org/series/106767/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each
From: Matt Roper
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be
== Series Details ==
Series: Random assortment of (mostly) GuC related patches (rev3)
URL : https://patchwork.freedesktop.org/series/106272/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106272v3
Summary
== Series Details ==
Series: Random assortment of (mostly) GuC related patches (rev3)
URL : https://patchwork.freedesktop.org/series/106272/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Random assortment of (mostly) GuC related patches (rev3)
URL : https://patchwork.freedesktop.org/series/106272/
State : warning
== Summary ==
Error: dim checkpatch failed
fe6417b35380 drm/i915/guc: Route semaphores to GuC for Gen12+
383e87c640b2 drm/i915/guc: Fix
== Series Details ==
Series: Fixes and improvements to GuC logging and error capture
URL : https://patchwork.freedesktop.org/series/106789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106789v1
Summary
On 7/27/2022 19:42, john.c.harri...@intel.com wrote:
From: Matthew Brost
The GuC needs a copy of a golden context for implementing watchdog
resets (aka media resets). This context is larger on newer platforms.
So adjust the size being allocated/copied accordingly.
Signed-off-by: Matthew Brost
On 7/27/2022 19:42, john.c.harri...@intel.com wrote:
From: Matthew Brost
Having semaphores results in different behavior when a dependent request
is cancelled. In the case of semaphores the request could be on the HW
and complete successfully while without the request is held in the
driver and
From: Matthew Brost
The GuC needs a copy of a golden context for implementing watchdog
resets (aka media resets). This context is larger on newer platforms.
So adjust the size being allocated/copied accordingly.
Signed-off-by: Matthew Brost
Signed-off-by: John Harrison
---
From: Matthew Brost
Having semaphores results in different behavior when a dependent request
is cancelled. In the case of semaphores the request could be on the HW
and complete successfully while without the request is held in the
driver and the error from the dependent request is propagated.
From: John Harrison
It is no longer guaranteed that there will always be an RCS engine.
So, use the helper function for finding the first available engine that
can be used for general purpose selftets.
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
From: Michał Winiarski
In GuC submission mode, there is an option to use auto-switch out
semaphores and have GuC auto-switch in a waiting context. This
requires routing the semaphore interrupt to GuC.
Signed-off-by: Michał Winiarski
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
From: John Harrison
When the KMD sends a CLIENT_RESET request to GuC (as part of the
suspend sequence), GuC will mark the CTB buffer as 'UNUSED'. If the
KMD then checked the CTB queue, it would see a non-zero status value
and report the buffer as corrupted.
Technically, no G2H messages should
From: Rahul Kumar Singh
Add a test to check that the hangcheck will recover from a submission
hang in the GuC.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
.../drm/i915/gt/uc/selftest_guc_hangcheck.c | 159
From: John Harrison
Pushing a bunch of patches which had gotten forgotten about.
Signed-off-by: John Harrison
John Harrison (2):
drm/i915/selftest: Cope with not having an RCS engine
drm/i915/guc: Don't abort on CTB_UNUSED status
Matthew Brost (2):
drm/i915/guc: Fix issues with
== Series Details ==
Series: Fixes and improvements to GuC logging and error capture
URL : https://patchwork.freedesktop.org/series/106789/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Fixes and improvements to GuC logging and error capture
URL : https://patchwork.freedesktop.org/series/106789/
State : warning
== Summary ==
Error: dim checkpatch failed
77f455e72ebc drm/i915/guc: Add a helper for log buffer size
f49ac6e6709a drm/i915/guc: Fix
From: John Harrison
There was a size check to warn if the GuC error state capture buffer
allocation would be too small to fit a reasonable amount of capture
data for the current platform. Unfortunately, the test was done too
early in the boot sequence and was actually testing 'if(-ENODEV >
From: John Harrison
It is useful to be able to match GuC events to kernel events when
looking at the GuC log. That requires being able to convert GuC
timestamps to kernel time. So, when dumping error captures and/or GuC
logs, include a stamp in both time zones plus the clock frequency.
From: John Harrison
The GuC log buffer sizes had to be configured statically at compile
time. This can be quite troublesome when needing to get larger logs
out of a released driver. So re-organise the code to allow a boot time
module parameter override.
Signed-off-by: John Harrison
---
From: John Harrison
Some debug code got left in when the GuC based register save for error
capture was added. Remove that.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 67 ---
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git
From: John Harrison
Fix bugs and improve the usability/effectiveness of GuC logging and
GuC related error captures.
Signed-off-by: John Harrison
Alan Previn (1):
drm/i915/guc: Add a helper for log buffer size
Chris Wilson (1):
drm/i915/guc: Use streaming loads to speed up dumping the
From: Chris Wilson
Use a temporary page and mempy_from_wc to reduce the time it takes to
dump the guc log to debugfs.
Signed-off-by: Chris Wilson
Signed-off-by: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 24 --
1 file
From: John Harrison
When debugging GuC communication issues, it is useful to have the CTB
info available. So add the state and buffer contents to the error
capture log.
Also, add a sub-structure for the GuC specific error capture info as
it is now becoming numerous.
Signed-off-by: John
From: Alan Previn
Add a helper to get GuC log buffer size.
Signed-off-by: Alan Previn
Signed-off-by: John Harrison
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 49 --
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git
On 7/27/2022 18:50, Ceraolo Spurio, Daniele wrote:
On 7/27/2022 6:44 PM, John Harrison wrote:
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
== Series Details ==
Series: Initial Meteorlake Support
URL : https://patchwork.freedesktop.org/series/106786/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
On 7/27/2022 6:44 PM, John Harrison wrote:
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just
On 7/26/2022 13:51, Nerlige Ramappa, Umesh wrote:
The worker is canceled in gt_park path, but earlier it was assumed that
gt_park path cannot sleep and the cancel is asynchronous. This caused a
race with suspend flow where the worker runs after suspend and causes an
unclaimed register access
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
>From spec we have registers GPIO_CTL[1-5] mapped to combo phys and
GPIO_CTL[9-14] are mapped to TC ports.
BSpec: 49306
Original Author: Brian J Lovin
Signed-off-by: Radhakrishna Sripada
---
Meteorlake uses a similar DBUF programming as ADL-P.
Reuse the call flow for meteorlake.
Bspec: 49255
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Madhumitha Tolakanahalli Pradeep
In Display version 14, Transcoder Chicken Registers are moved from DPRZ to DRPOS
to reduce register signal crossings for Unit Interface Optimization.
This patch modifies the CHICKEN_TRANS macro to add a DISPLAY_VER check for
calculating the correct
Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
instead of GT driver mailbox.
Bspec: 64608
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_pm.c | 105
The initialization sequence for Meteorlake reuses the sequence for
icelake for most parts. Some changes viz. reset PICA handshake
are added.
Bspec: 49189
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
From: José Roberto de Souza
The GMD step field do not properly match the current stepping convention
that we use(STEP_A0, STEP_A1, STEP_B0...).
One platform could have { arch = 12, rel = 70, step = 1 } and the
actual stepping is STEP_B0 but without the translation of the step
field would mean
From: Madhumitha Tolakanahalli Pradeep
Adding support to load DMC v2.08 on MTL.
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_dmc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
From: Imre Deak
Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just
follows the ADL_P one.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_bios.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
The PCI Id's and platform definition are posted earlier.
This series adds handful of early enablement patches including
support for display power wells, VBT and AUX Channel mapping,
PCH and gmbus support, dbus, mbus, sagv and memory bandwidth support.
This series also add the support for a new
From: Imre Deak
Add support for display power wells on MTL. The differences from D13:
- The AUX HW block is moved to the PICA block, where the registers are on
an always-on power well and the functionality needs to be powered on/off
via the AUX_CH_CTL register: [1], [2]
- The DDI IO power
No need to update mask value/restrict because
"Pcode only wants to use GV bandwidth value, not the mask value."
for Display version greater than 14.
Bspec: 646365
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_pm.c | 18
From: Matt Roper
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be
From: José Roberto de Souza
Display version 14 also supports MBUS joining just like ADL-P
and also it don't need MBUS initialization, so extending ADL-P
code paths to display version 14 and higher.
Bspec: 49213
Signed-off-by: José Roberto de Souza
---
From: Matt Roper
Previously only dgfx platforms had a 4MB MMIO range, but starting with
MTL we now use the larger range for all platforms.
Bspec: 63834, 63830
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_uncore.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
Like ADL_P, Meteorlake has different memory characteristics from
past platforms. Update the values used by our memory bandwidth
calculations accordingly.
Bspec: 64631
Cc: Matt Roper
Cc: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
---
Display version 14 platforms has different credits values compared to ADL-P.
Update the credits based on pipe usage.
Bspec: 49213
Cc: Jose Roberto de Souza
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
---
From: Anusha Srivatsa
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC. Patch also adds
DMC debug register for MTL.
BSpec: 49788
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 8
1 file changed, 4 insertions(+), 4
From: Imre Deak
On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
changed wrt. previous platforms, adjust the code accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
From: Anusha Srivatsa
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
bxt_get_cdclk() is not properly calculating HW clock for MTL, because
the squash formula is only
From: Clint Taylor
MTL has a fixed rawclk of 38400Mhz. Register does not need to be
reprogrammed.
Bspec: 49304
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
From: Matt Roper
The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.
For render/compute engines, the part of the
Add support for Meteorpoint(MTP) PCH used with Meteorlake.
Cc: Matt Roper
Cc: Anusha Srivatsa
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_pch.c | 9 -
drivers/gpu/drm/i915/intel_pch.h | 4
2 files changed, 12 insertions(+), 1
>From Meteorlake, Latency Level, SAGV bloack time are read from
LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
and QGV information are also tob read from Mem SS registers.
Bspec: 49324, 64636
Cc: Matt Roper
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de
From: Matt Roper
Unlike the Xe_HP platforms, MTL only has a single CCS engine; the
quad-based engine masking logic does not apply to this platform (or
presumably any future platforms that only have 0 or 1 CCS).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1
The following changes since commit 150864a4d73e8c448eb1e2c68e65f07635fe1a66:
amdgpu partially revert "amdgpu: update beige goby to release 22.20"
(2022-07-25 14:16:04 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_guc_v70.4.1
for you to
== Series Details ==
Series: drm/i915/guc: Don't send policy update for child contexts.
URL : https://patchwork.freedesktop.org/series/106783/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106783v1
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any functional consequences,
because the GuC just drops it and logs an error; since we were trying
to
== Series Details ==
Series: Move CDCLK checks to atomic check phase
URL : https://patchwork.freedesktop.org/series/106782/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106782v1
Summary
---
== Series Details ==
Series: Move CDCLK checks to atomic check phase
URL : https://patchwork.freedesktop.org/series/106782/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Move CDCLK checks to atomic check phase
URL : https://patchwork.freedesktop.org/series/106782/
State : warning
== Summary ==
Error: dim checkpatch failed
b31629d56cc7 drm/i915/display: Add CDCLK actions to intel_cdclk_state
a77796ff5290 drm/i915/display:
Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.
v2: Add intel_cdclk_modeset() similar to
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++---
1 file changed, 11
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++--
1 file changed, 11
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
The intention is to check for squashing, crawling conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate this.
Cc:
The intention is to check for squashing, crawling conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate this.
Anusha
> -Original Message-
> From: Auld, Matthew
> Sent: Wednesday, July 27, 2022 10:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Thomas Hellström
> ; C,
> Ramalingam
> Subject: [PATCH] drm/i915/ttm: don't leak the ccs state
>
> The kernel only manages
== Series Details ==
Series: drm/i915/ttm: don't leak the ccs state
URL : https://patchwork.freedesktop.org/series/106765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946_full -> Patchwork_106765v1_full
Summary
---
== Series Details ==
Series: Bump DG2 DMC firmware to v2.07 (rev2)
URL : https://patchwork.freedesktop.org/series/106773/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106773v2
Summary
---
Hi Nirmoy,
On Wed, Jul 27, 2022 at 07:40:23PM +0200, Nirmoy Das wrote:
> From: Chris Wilson
>
> We report object allocation failures to userspace with ENOMEM, yet we
> still show the memory warning after failing to shrink device allocated
> pages. While this warning is similar to other system
Hi Nirmoy,
On Wed, Jul 27, 2022 at 07:33:06PM +0200, Nirmoy Das wrote:
> PCI bar resize only works with 64 bit BAR so disable
> this on 32-bit machine and resolve below compilation error:
>
> drivers/gpu/drm/i915/gt/intel_region_lmem.c:94:23: error: result of
> comparison of constant 4294967296
== Series Details ==
Series: drm/i915: Suppress oom warning for shmemfs object allocation failure
(rev4)
URL : https://patchwork.freedesktop.org/series/106528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106528v4
== Series Details ==
Series: drm/i915: Suppress oom warning for shmemfs object allocation failure
(rev4)
URL : https://patchwork.freedesktop.org/series/106528/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/i915: disable pci resize on 32-bit machine (rev2)
URL : https://patchwork.freedesktop.org/series/106708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106708v2
Summary
== Series Details ==
Series: drm/i915: stop using swiotlb (rev6)
URL : https://patchwork.freedesktop.org/series/106589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106589v6
Summary
---
On Tue, Jul 26, 2022 at 09:44:38AM -0700, Srivatsa, Anusha wrote:
> Thanks Tvrtko :)
> @Roper, Matthew D Did you have any other feedback on this patch?
Nope, looks fine to me. Thanks.
Reviewed-by: Matt Roper
>
> Anusha
>
> > -Original Message-
> > From: Tvrtko Ursulin
> > Sent:
== Series Details ==
Series: drm/i915: stop using swiotlb (rev6)
URL : https://patchwork.freedesktop.org/series/106589/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during
loading/disabling the firmware
URL : https://patchwork.freedesktop.org/series/106767/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106767v1
The following changes since commit 150864a4d73e8c448eb1e2c68e65f07635fe1a66:
amdgpu partially revert "amdgpu: update beige goby to release 22.20"
(2022-07-25 14:16:04 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_dmc_2_07
for you to
The release notes mention that DMC v2.07 has a workaround
for MMIO hang issue when DC States are enabled.
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
== Series Details ==
Series: series starting with [1/2] drm/i915/d12+: Disable DMC handlers during
loading/disabling the firmware
URL : https://patchwork.freedesktop.org/series/106767/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
== Series Details ==
Series: drm/i915/ttm: don't leak the ccs state
URL : https://patchwork.freedesktop.org/series/106765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106765v1
Summary
---
From: Chris Wilson
We report object allocation failures to userspace with ENOMEM, yet we
still show the memory warning after failing to shrink device allocated
pages. While this warning is similar to other system page allocation
failures, it is superfluous to the ENOMEM provided directly to
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine and resolve below compilation error:
drivers/gpu/drm/i915/gt/intel_region_lmem.c:94:23: error: result of
comparison of constant 4294967296 with expression of type
'resource_size_t' (aka 'unsigned int') is always false
On 7/27/2022 6:58 PM, Matthew Auld wrote:
On 26/07/2022 09:32, Nirmoy Das wrote:
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine.
Maybe also mention somewhere that this is just to fix a compiler
warning with the 0x1ull being out-of-range with
On 26/07/2022 09:32, Nirmoy Das wrote:
PCI bar resize only works with 64 bit BAR so disable
this on 32-bit machine.
Maybe also mention somewhere that this is just to fix a compiler warning
with the 0x1ull being out-of-range with resource_size_t on 32bit?
Acked-by: Matthew Auld
Add a workaround making sure that PIPEDMC-A/B is enabled when the
firmware needs these on D13 platforms to save/restore the registers
backed by the PW_1 and PW_A power wells.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
Disable the DMC event handlers before loading the firmware and after
uninitializing the display, to make sure the firmware is inactive. This
matches the Bspec "Sequences for Display C5 and C6" page for GEN12+.
Add a TODO comment for doing the same on pre-GEN12 platforms.
Signed-off-by: Imre Deak
The kernel only manages the ccs state with lmem-only objects, however
the kernel should still take care not to leak the CCS state from the
previous user.
Fixes: 48760ffe923a ("drm/i915/gt: Clear compress metadata for Flat-ccs
objects")
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc:
== Series Details ==
Series: drm/i915: reduce TLB performance regressions
URL : https://patchwork.freedesktop.org/series/106758/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11946_full -> Patchwork_106758v1_full
Summary
Hi Arunpravin,
Às 02:30 de 27/07/22, Arunpravin Paneer Selvam escreveu:
> Check the bo->resource value before accessing the resource
> mem_type.
>
> v2: Fix commit description unwrapped warning
>
>
> [ 40.191227][ T184] general protection fault, probably for non-canonical
> address
Hi Mauro,
I think there are still some unanswered questions from Tvrtko on
this patch, am I right?
Andi
On Wed, Jul 27, 2022 at 02:29:55PM +0200, Mauro Carvalho Chehab wrote:
> From: Chris Wilson
>
> Invalidate TLB in batches, in order to reduce performance regressions.
>
> Currently, every
Hi Mauro,
> TLB cache invalidation can happen on two different situations:
>
> 1. synchronously, at __vma_put_pages();
> 2. asynchronously.
>
> On the first case, TLB cache invalidation happens inside
> __vma_put_pages(). So, no need to do it later on.
>
> However, on the second case, the
Hi Mauro,
> Add a kernel-doc markup to document this new macro.
>
> Reviewed-by: Tvrtko Ursulin
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Andi Shyti
Andi
== Series Details ==
Series: drm/i915: reduce TLB performance regressions
URL : https://patchwork.freedesktop.org/series/106758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11946 -> Patchwork_106758v1
Summary
---
== Series Details ==
Series: drm/i915: reduce TLB performance regressions
URL : https://patchwork.freedesktop.org/series/106758/
State : warning
== Summary ==
Error: dim checkpatch failed
735755e9d5d5 drm/i915/gt: Ignore TLB invalidations on idle engines
-:138: CHECK:MACRO_ARG_REUSE: Macro
On 27/07/2022 12:48, Mauro Carvalho Chehab wrote:
On Wed, 20 Jul 2022 11:49:59 +0100
Tvrtko Ursulin wrote:
On 20/07/2022 08:13, Mauro Carvalho Chehab wrote:
On Mon, 18 Jul 2022 14:52:05 +0100
Tvrtko Ursulin wrote:
On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
From: Chris Wilson
From: Chris Wilson
Check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not needed, thus reducing the
performance regression impact due to it.
This becomes more significant with GuC, as it
From: Chris Wilson
Invalidate TLB in batches, in order to reduce performance regressions.
Currently, every caller performs a full barrier around a TLB
invalidation, ignoring all other invalidations that may have already
removed their PTEs from the cache. As this is a synchronous operation
and
Doing TLB invalidation cause performance regressions, like:
[424.370996] i915 :00:02.0: [drm] *ERROR* rcs0 TLB invalidation did
not complete in 4ms!
As reported at:
https://gitlab.freedesktop.org/drm/intel/-/issues/6424
as this is an expensive operation. So, reduce the need
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