Re: [Intel-gfx] [PATCH] ALSA: hda/hdmi: disable KAE for Intel DG2
On Thu, 13 Apr 2023 21:11:53 +0200,
Kai Vehmanen wrote:
>
> Use of keep-alive (KAE) has resulted in loss of audio on some A750/770
> cards as the transition from keep-alive to stream playback is not
> working as expected. As there is limited benefit of the new KAE mode
> on discrete cards, revert back to older silent-stream implementation
> on these systems.
>
> Cc: sta...@vger.kernel.org
> Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and
> DG2")
> Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8307
> Signed-off-by: Kai Vehmanen
Thanks, applied.
Takashi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Avoid out-of-bounds access when loading HuC
== Series Details ==
Series: drm/i915/gt: Avoid out-of-bounds access when loading HuC
URL : https://patchwork.freedesktop.org/series/116460/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13004_full -> Patchwork_116460v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 8)
--
Additional (1): shard-rkl0
Known issues
Here are the changes found in Patchwork_116460v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pipe_stress@stress-xrgb-ytiled:
- shard-apl: NOTRUN -> [FAIL][3] ([i915#7036])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl1/igt@i915_pipe_str...@stress-xrgb-ytiled.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +2
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#72])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +7 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk4/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271]) +51 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl1/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0...@pipe-a-dp-1.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl1/igt@kms_psr2_su@page_flip-nv12.html
Possible fixes
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][14] ([i915#2846]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk6/igt@gem_exec_f...@basic-deadline.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk1/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}:[FAIL][16] ([i915#2842]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-apl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-glk: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-glk:
[Intel-gfx] ✓ Fi.CI.IGT: success for ALSA: hda/hdmi: disable KAE for Intel DG2
== Series Details ==
Series: ALSA: hda/hdmi: disable KAE for Intel DG2
URL : https://patchwork.freedesktop.org/series/116456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13004_full -> Patchwork_116456v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116456v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][1] -> [ABORT][2] ([i915#8211] / [i915#8234])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-apl7/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#5566])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-apl4/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#72])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][11] -> [ABORT][12] ([i915#180])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-apl3/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +7 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-glk4/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_plane_lowres@tiling-4:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-apl1/igt@kms_plane_low...@tiling-4.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][15] ([i915#7742]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_eio@hibernate:
- {shard-dg1}:[ABORT][17] ([i915#7975]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-dg1-14/igt@gem_...@hibernate.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-dg1-16/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][19] ([i915#2846]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-glk6/igt@gem_exec_f...@basic-deadline.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-glk3/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}:[FAIL][21] ([i915#2842]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][23] ([i915#2842]) -> [PASS][24]
[23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add Support for C10 phy (rev4)
== Series Details == Series: drm/i915/mtl: Add Support for C10 phy (rev4) URL : https://patchwork.freedesktop.org/series/116191/ State : success == Summary == CI Bug Log - changes from CI_DRM_13005 -> Patchwork_116191v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/index.html Participating hosts (37 -> 36) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_116191v4 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334] / [i915#7872]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][5] ([i915#6367] / [i915#7913] / [i915#7996]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-2/igt@i915_selftest@l...@slpc.html - bat-rpls-1: [PASS][6] -> [DMESG-FAIL][7] ([i915#6367] / [i915#7996]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-1/igt@i915_selftest@l...@slpc.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_selftest@live@workarounds: - bat-rplp-1: [PASS][8] -> [INCOMPLETE][9] ([i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rplp-1/igt@i915_selftest@l...@workarounds.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rplp-1/igt@i915_selftest@l...@workarounds.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-2: NOTRUN -> [SKIP][10] ([i915#7828]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#7828]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1: - bat-dg2-8: [PASS][12] -> [FAIL][13] ([i915#7932]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#1845]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@i915_pm_rps@basic-api: - bat-dg1-5: [FAIL][15] ([i915#8308]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg1-5/igt@i915_pm_...@basic-api.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-dg1-5/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [INCOMPLETE][17] ([i915#7609] / [i915#7913]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@mman: - bat-rpls-2: [TIMEOUT][19] ([i915#6794]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-2/igt@i915_selftest@l...@mman.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-2: [ABORT][21] ([i915#6687] / [i915#7978]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116191v4/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Support for C10 phy (rev4)
== Series Details == Series: drm/i915/mtl: Add Support for C10 phy (rev4) URL : https://patchwork.freedesktop.org/series/116191/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 phy (rev4)
== Series Details == Series: drm/i915/mtl: Add Support for C10 phy (rev4) URL : https://patchwork.freedesktop.org/series/116191/ State : warning == Summary == Error: dim checkpatch failed 82a3f0bc865f drm/i915/mtl: Add DP rates c39006db21f7 drm/i915/mtl: Create separate reg file for PICA registers Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:19: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #19: new file mode 100644 -:39: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:16: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ -:40: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:17: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ -:41: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #41: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:18: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ -:42: WARNING:LONG_LINE: line length of 133 exceeds 100 columns #42: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:19: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) -:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #45: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:22: +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) -:46: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #46: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:23: +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) -:47: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #47: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:24: +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) -:49: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #49: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:26: +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) -:52: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #52: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:29: +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) -:54: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #54: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:31: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ -:55: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #55: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:32: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ -:56: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #56: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:33: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ -:57: WARNING:LONG_LINE: line length of 137 exceeds 100 columns #57: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:34: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) -:63: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:40: +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) -:81: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #81: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:58: + _XELPDP_PORT_BUF_CTL1_LN0_A, \ -:82: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #82: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59: + _XELPDP_PORT_BUF_CTL1_LN0_B, \ -:83: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #83: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:60: + _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ -:84: WARNING:LONG_LINE: line length of 114 exceeds 100 columns #84: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:61: +
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Make intel_mpllb_state_verify() safer
== Series Details == Series: series starting with [1/2] drm/i915: Make intel_mpllb_state_verify() safer URL : https://patchwork.freedesktop.org/series/116461/ State : success == Summary == CI Bug Log - changes from CI_DRM_13005 -> Patchwork_116461v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_116461v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@migrate: - bat-dg2-11: NOTRUN -> [DMESG-WARN][3] ([i915#7699]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][4] ([i915#6367] / [i915#7913]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#7828]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#5354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1: - bat-dg2-8: [PASS][8] -> [FAIL][9] ([i915#7932]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-2: NOTRUN -> [SKIP][10] ([i915#1845]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@i915_pm_rps@basic-api: - bat-dg1-5: [FAIL][11] ([i915#8308]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg1-5/igt@i915_pm_...@basic-api.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg1-5/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [INCOMPLETE][13] ([i915#7609] / [i915#7913]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@mman: - bat-rpls-2: [TIMEOUT][15] ([i915#6794]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-2/igt@i915_selftest@l...@mman.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-2: [ABORT][17] ([i915#6687] / [i915#7978]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13005/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116461v1/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#8308]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Make intel_mpllb_state_verify() safer
== Series Details == Series: series starting with [1/2] drm/i915: Make intel_mpllb_state_verify() safer URL : https://patchwork.freedesktop.org/series/116461/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: hide mkwrite_device_info() better (rev3)
== Series Details ==
Series: drm/i915: hide mkwrite_device_info() better (rev3)
URL : https://patchwork.freedesktop.org/series/113017/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13003_full -> Patchwork_113017v3_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_113017v3_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][1] -> [ABORT][2] ([i915#8211])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-glk8/igt@gem_barrier_race@remote-requ...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk5/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][5] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271]) +42 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@kms_big...@x-tiled-64bpp-rotate-90.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][11] -> [ABORT][12] ([i915#180])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-apl1/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-apl3/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk1/igt@kms_vbl...@pipe-d-wait-idle.html
Possible fixes
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][14] ([i915#6268]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-tglu-5/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}:[FAIL][16] ([i915#2842]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-rkl-6/igt@gem_exec_fair@basic-n...@vecs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-rkl-2/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}:[SKIP][20] ([i915#1397]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-rkl-4/igt@i915_pm_...@dpms-lpsp.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/shard-rkl-7/igt@i915_pm_...@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}:[SKIP][22] ([i915#1397]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-dg1-16/igt@i915_pm_...@modeset-lpsp-stress.html
[23]:
[Intel-gfx] [PATCH i-g-t 4/4] HAX: tests/i915: Try out the SLPC IGT tests
Trying out for CI. Do not review. Signed-off-by: Vinay Belgaumkar --- tests/intel-ci/fast-feedback.testlist | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index d9fcb62d..653668dd 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -139,6 +139,8 @@ igt@prime_self_import@basic-with_fd_dup igt@prime_self_import@basic-with_one_bo igt@prime_self_import@basic-with_one_bo_two_files igt@prime_self_import@basic-with_two_bos +igt@i915_pm_freq_api@freq-basic-api +igt@i915_pm_freq_api@freq-reset igt@prime_vgem@basic-fence-flip igt@prime_vgem@basic-fence-mmap igt@prime_vgem@basic-fence-read -- 2.38.1
[Intel-gfx] [PATCH i-g-t 3/4] i915_pm_freq_api: Add some basic SLPC igt tests
Validate basic api for GT freq control. Also test
interaction with GT reset. We skip rps tests with
SLPC enabled, this will re-introduce some coverage.
SLPC selftests are already covering some other workload
related scenarios.
v2: Rename test (Rodrigo)
v3: Review comments (Ashutosh)
v4: Skip when SLPC is disabled. Check for enable_guc is
not sufficient as kernel config may have it but the
platform doesn't actually support it.
v5: Use the updated SLPC helper
Reviewed-by: Ashutosh Dixit
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 152 ++
tests/meson.build | 1 +
2 files changed, 153 insertions(+)
create mode 100644 tests/i915/i915_pm_freq_api.c
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
new file mode 100644
index ..d42b3a2b
--- /dev/null
+++ b/tests/i915/i915_pm_freq_api.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h"
+#include "i915/gem.h"
+#include "igt_sysfs.h"
+#include "igt.h"
+
+IGT_TEST_DESCRIPTION("Test SLPC freq API");
+/*
+ * Too many intermediate components and steps before freq is adjusted
+ * Specially if workload is under execution, so let's wait 100 ms.
+ */
+#define ACT_FREQ_LATENCY_US 10
+
+static uint32_t get_freq(int dirfd, uint8_t id)
+{
+ uint32_t val;
+
+ igt_assert(igt_sysfs_rps_scanf(dirfd, id, "%u", ) == 1);
+
+ return val;
+}
+
+static int set_freq(int dirfd, uint8_t id, uint32_t val)
+{
+ return igt_sysfs_rps_printf(dirfd, id, "%u", val);
+}
+
+static void test_freq_basic_api(int dirfd, int gt)
+{
+ uint32_t rpn, rp0, rpe;
+
+ /* Save frequencies */
+ rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ rp0 = get_freq(dirfd, RPS_RP0_FREQ_MHZ);
+ rpe = get_freq(dirfd, RPS_RP1_FREQ_MHZ);
+ igt_info("System min freq: %dMHz; max freq: %dMHz\n", rpn, rp0);
+
+ /*
+* Negative bound tests
+* RPn is the floor
+* RP0 is the ceiling
+*/
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn - 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0 + 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn - 1) < 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0 + 1) < 0);
+
+ /* Assert min requests are respected from rp0 to rpn */
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rp0) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rp0);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpe) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpe);
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+
+ /* Assert max requests are respected from rpn to rp0 */
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpe) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpe);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rp0) > 0);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rp0);
+
+}
+
+static void test_reset(int i915, int dirfd, int gt)
+{
+ uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ int fd;
+
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
+ usleep(ACT_FREQ_LATENCY_US);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+
+ /* Manually trigger a GT reset */
+ fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
+ igt_require(fd >= 0);
+ igt_ignore_warn(write(fd, "1\n", 2));
+ close(fd);
+
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+}
+
+igt_main
+{
+ int i915 = -1;
+ uint32_t *stash_min, *stash_max;
+
+ igt_fixture {
+ int num_gts, dirfd, gt;
+
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ /* i915_pm_rps already covers execlist path */
+ igt_skip_on_f(!i915_is_slpc_enabled(i915, 0),
+ "This test is supported only with SLPC
enabled\n");
+
+ num_gts = igt_sysfs_get_num_gt(i915);
+ stash_min = (uint32_t*)malloc(sizeof(uint32_t) * num_gts);
+ stash_max = (uint32_t*)malloc(sizeof(uint32_t) * num_gts);
+
+ /* Save curr min and max across GTs */
+ for_each_sysfs_gt_dirfd(i915, dirfd, gt) {
+ stash_min[gt] = get_freq(dirfd, RPS_MIN_FREQ_MHZ);
+ stash_max[gt] = get_freq(dirfd, RPS_MAX_FREQ_MHZ);
+ }
+ }
+
+
[Intel-gfx] [PATCH i-g-t 2/4] lib: Make SLPC helper function per GT
Use default of 0 where GT id is not being used.
Signed-off-by: Vinay Belgaumkar
---
lib/igt_pm.c | 20 ++--
lib/igt_pm.h | 2 +-
tests/i915/i915_pm_rps.c | 6 +++---
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 704acf7d..8ca7c181 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -1329,21 +1329,21 @@ void igt_pm_print_pci_card_runtime_status(void)
}
}
-bool i915_is_slpc_enabled(int fd)
+bool i915_is_slpc_enabled(int drm_fd, int gt)
{
- int debugfs_fd = igt_debugfs_dir(fd);
- char buf[4096] = {};
- int len;
+ int debugfs_fd;
+ char buf[256] = {};
+
+ debugfs_fd = igt_debugfs_gt_open(drm_fd, gt, "uc/guc_slpc_info",
O_RDONLY);
- igt_require(debugfs_fd != -1);
+ /* if guc_slpc_info not present then return false */
+ if (debugfs_fd < 0)
+ return false;
+ read(debugfs_fd, buf, sizeof(buf)-1);
- len = igt_debugfs_simple_read(debugfs_fd, "gt/uc/guc_slpc_info", buf,
sizeof(buf));
close(debugfs_fd);
- if (len < 0)
- return false;
- else
- return strstr(buf, "SLPC state: running");
+ return strstr(buf, "SLPC state: running");
}
int igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev)
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index d0d6d673..1b054dce 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -84,7 +84,7 @@ void igt_pm_set_d3cold_allowed(struct igt_device_card *card,
const char *val);
void igt_pm_setup_pci_card_runtime_pm(struct pci_device *pci_dev);
void igt_pm_restore_pci_card_runtime_pm(void);
void igt_pm_print_pci_card_runtime_status(void);
-bool i915_is_slpc_enabled(int fd);
+bool i915_is_slpc_enabled(int fd, int gt);
int igt_pm_get_runtime_suspended_time(struct pci_device *pci_dev);
int igt_pm_get_runtime_usage(struct pci_device *pci_dev);
diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
index d4ee2d58..85dae449 100644
--- a/tests/i915/i915_pm_rps.c
+++ b/tests/i915/i915_pm_rps.c
@@ -916,21 +916,21 @@ igt_main
}
igt_subtest("basic-api") {
- igt_skip_on_f(i915_is_slpc_enabled(drm_fd),
+ igt_skip_on_f(i915_is_slpc_enabled(drm_fd, 0),
"This subtest is not supported when SLPC is
enabled\n");
min_max_config(basic_check, false);
}
/* Verify the constraints, check if we can reach idle */
igt_subtest("min-max-config-idle") {
- igt_skip_on_f(i915_is_slpc_enabled(drm_fd),
+ igt_skip_on_f(i915_is_slpc_enabled(drm_fd, 0),
"This subtest is not supported when SLPC is
enabled\n");
min_max_config(idle_check, true);
}
/* Verify the constraints with high load, check if we can reach max */
igt_subtest("min-max-config-loaded") {
- igt_skip_on_f(i915_is_slpc_enabled(drm_fd),
+ igt_skip_on_f(i915_is_slpc_enabled(drm_fd, 0),
"This subtest is not supported when SLPC is
enabled\n");
load_helper_run(HIGH);
min_max_config(loaded_check, false);
--
2.38.1
[Intel-gfx] [PATCH i-g-t 1/4] lib/debugfs: Add per GT debugfs helpers
These can be used to open per-gt debugfs files.
Reviewed-by: Ashutosh Dixit
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
---
lib/igt_debugfs.c | 60 +++
lib/igt_debugfs.h | 4
2 files changed, 64 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 05889bbe..afde2da6 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -217,6 +217,37 @@ int igt_debugfs_dir(int device)
return open(path, O_RDONLY);
}
+/**
+ * igt_debugfs_gt_dir:
+ * @device: fd of the device
+ * @gt: GT instance number
+ *
+ * This opens the debugfs directory corresponding to device for use
+ * with igt_sysfs_get() and related functions.
+ *
+ * Returns:
+ * The directory fd, or -1 on failure.
+ */
+int igt_debugfs_gt_dir(int device, unsigned int gt)
+{
+ int debugfs_gt_dir_fd;
+ char path[PATH_MAX];
+ char gtpath[16];
+ int ret;
+
+ if (!igt_debugfs_path(device, path, sizeof(path)))
+ return -1;
+
+ ret = snprintf(gtpath, sizeof(gtpath), "/gt%u", gt);
+ igt_assert(ret < sizeof(gtpath));
+ strncat(path, gtpath, sizeof(path) - 1);
+
+ debugfs_gt_dir_fd = open(path, O_RDONLY);
+ igt_debug_on_f(debugfs_gt_dir_fd < 0, "path: %s\n", path);
+
+ return debugfs_gt_dir_fd;
+}
+
/**
* igt_debugfs_connector_dir:
* @device: fd of the device
@@ -313,6 +344,35 @@ bool igt_debugfs_exists(int device, const char *filename,
int mode)
return false;
}
+/**
+ * igt_debugfs_gt_open:
+ * @device: open i915 drm fd
+ * @gt: gt instance number
+ * @filename: name of the debugfs node to open
+ * @mode: mode bits as used by open()
+ *
+ * This opens a debugfs file as a Unix file descriptor. The filename should be
+ * relative to the drm device's root, i.e. without "drm/$minor".
+ *
+ * Returns:
+ * The Unix file descriptor for the debugfs file or -1 if that didn't work out.
+ */
+int
+igt_debugfs_gt_open(int device, unsigned int gt, const char *filename, int
mode)
+{
+ int dir, ret;
+
+ dir = igt_debugfs_gt_dir(device, gt);
+ if (dir < 0)
+ return dir;
+
+ ret = openat(dir, filename, mode);
+
+ close(dir);
+
+ return ret;
+}
+
/**
* igt_debugfs_simple_read:
* @dir: fd of the debugfs directory
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index 4824344a..3e6194ad 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -45,6 +45,10 @@ void __igt_debugfs_write(int fd, const char *filename, const
char *buf, int size
int igt_debugfs_simple_read(int dir, const char *filename, char *buf, int
size);
bool igt_debugfs_search(int fd, const char *filename, const char *substring);
+int igt_debugfs_gt_dir(int device, unsigned int gt);
+int igt_debugfs_gt_open(int device, unsigned int gt, const char *filename,
+ int mode);
+
/**
* igt_debugfs_read:
* @filename: name of the debugfs file
--
2.38.1
[Intel-gfx] [PATCH v5 i-g-t 0/4] tests/slpc: Add basic IGT test
Borrow some subtests from xe_guc_pc. Also add per GT debugfs helpers. v3: Review comments and add HAX patch v4: Modify the condition for skipping the test v5: Update the SLPC helper to per GT Signed-off-by: Vinay Belgaumkar Vinay Belgaumkar (4): lib/debugfs: Add per GT debugfs helpers lib: Make SLPC helper function per GT i915_pm_freq_api: Add some basic SLPC igt tests HAX: tests/i915: Try out the SLPC IGT tests lib/igt_debugfs.c | 60 ++ lib/igt_debugfs.h | 4 + lib/igt_pm.c | 20 ++-- lib/igt_pm.h | 2 +- tests/i915/i915_pm_freq_api.c | 152 ++ tests/i915/i915_pm_rps.c | 6 +- tests/intel-ci/fast-feedback.testlist | 2 + tests/meson.build | 1 + 8 files changed, 233 insertions(+), 14 deletions(-) create mode 100644 tests/i915/i915_pm_freq_api.c -- 2.38.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Avoid out-of-bounds access when loading HuC
== Series Details == Series: drm/i915/gt: Avoid out-of-bounds access when loading HuC URL : https://patchwork.freedesktop.org/series/116460/ State : success == Summary == CI Bug Log - changes from CI_DRM_13004 -> Patchwork_116460v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/index.html Participating hosts (35 -> 34) -- Additional (1): bat-rpls-2 Missing(2): bat-mtlp-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_116460v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@slpc: - bat-adln-1: NOTRUN -> [DMESG-FAIL][6] ([i915#6997]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-adln-1/igt@i915_selftest@l...@slpc.html * igt@i915_selftest@live@workarounds: - bat-rpls-2: NOTRUN -> [INCOMPLETE][7] ([i915#4983] / [i915#7913]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@i915_selftest@l...@workarounds.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#1845]) +14 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_b...@basic.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#7828]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adln-1: NOTRUN -> [SKIP][10] ([i915#7828]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-adln-1/igt@kms_chamelium_...@common-hpd-after-suspend.html - fi-bsw-n3050: NOTRUN -> [SKIP][11] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/fi-bsw-n3050/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-rpls-1: NOTRUN -> [SKIP][12] ([i915#7828]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_flip@basic-flip-vs-dpms: - bat-rpls-2: NOTRUN -> [SKIP][13] ([i915#3637]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-rpls-2: NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#1849]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [PASS][16] -> [FAIL][17] ([i915#7932]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-1: NOTRUN -> [SKIP][18] ([i915#1845]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html * igt@kms_psr@sprite_plane_onoff: - bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#1072]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116460v1/bat-rpls-2/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rpls-2: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Avoid out-of-bounds access when loading HuC
== Series Details == Series: drm/i915/gt: Avoid out-of-bounds access when loading HuC URL : https://patchwork.freedesktop.org/series/116460/ State : warning == Summary == Error: dim checkpatch failed 3145aadb2876 drm/i915/gt: Avoid out-of-bounds access when loading HuC -:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #17: [drm] *ERROR* GT0: HuC firmware i915/dg2_huc_gsc.bin: fetch failed -ENODATA total: 0 errors, 1 warnings, 0 checks, 36 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda/hdmi: disable KAE for Intel DG2
== Series Details == Series: ALSA: hda/hdmi: disable KAE for Intel DG2 URL : https://patchwork.freedesktop.org/series/116456/ State : success == Summary == CI Bug Log - changes from CI_DRM_13004 -> Patchwork_116456v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/index.html Participating hosts (35 -> 35) -- Additional (2): fi-kbl-soraka bat-rpls-2 Missing(2): bat-mtlp-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_116456v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@dmabuf@all-tests@dma_fence: - bat-dg2-8: [PASS][2] -> [DMESG-FAIL][3] ([i915#8189]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/bat-dg2-8/igt@dmabuf@all-tests@dma_fence.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-dg2-8/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - bat-dg2-8: [PASS][4] -> [ABORT][5] ([i915#7699]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/bat-dg2-8/igt@dmabuf@all-te...@sanitycheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-dg2-8/igt@dmabuf@all-te...@sanitycheck.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#2582]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@fb...@read.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][10] ([i915#3282]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][11] ([i915#7561]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#5334] / [i915#7872]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][13] ([i915#4258]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][14] ([i915#1886]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][15] -> [DMESG-WARN][16] ([i915#7699]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/bat-dg2-11/igt@i915_selftest@l...@migrate.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@mman: - bat-rpls-1: [PASS][17] -> [TIMEOUT][18] ([i915#6794]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13004/bat-rpls-1/igt@i915_selftest@l...@mman.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][19] ([i915#6367] / [i915#7913] / [i915#7996]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html - bat-adln-1: NOTRUN -> [DMESG-FAIL][20] ([i915#6997]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-adln-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-2: NOTRUN -> [ABORT][21] ([i915#6687] / [i915#7978]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116456v1/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][22]
Re: [Intel-gfx] [PATCH] drm/i915/gt: Avoid out-of-bounds access when loading HuC
On 4/13/2023 1:03 PM, Lucas De Marchi wrote:
When HuC is loaded by GSC, there is no header definition for the kernel
to look at and firmware is just handed to GSC. However when reading the
version, it should still check the size of the blob to guarantee it's not
incurring into out-of-bounds array access.
If firmware is smaller than expected, the following message is now
printed:
# echo boom > /lib/firmware/i915/dg2_huc_gsc.bin
# dmesg | grep -i huc
[drm] GT0: HuC firmware i915/dg2_huc_gsc.bin: invalid size: 5 < 184
[drm] *ERROR* GT0: HuC firmware i915/dg2_huc_gsc.bin: fetch failed
-ENODATA
...
Even without this change the size, header and signature are still
checked by GSC when loading, so this only avoids the out-of-bounds array
access.
Fixes: a7b516bd981f ("drm/i915/huc: Add fetch support for gsc-loaded HuC
binary")
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Lucas De Marchi
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 1ac6f9f340e3..a82a53dbbc86 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -489,12 +489,25 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw, int e)
}
}
-static int check_gsc_manifest(const struct firmware *fw,
+static int check_gsc_manifest(struct intel_gt *gt,
+ const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
u32 *dw = (u32 *)fw->data;
- u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
- u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
+ u32 version_hi, version_lo;
+ size_t min_size;
+
+ /* Check the size of the blob before examining buffer contents */
+ min_size = sizeof(u32) * (HUC_GSC_VERSION_LO_DW + 1);
+ if (unlikely(fw->size < min_size)) {
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type),
uc_fw->file_selected.path,
+ fw->size, min_size);
+ return -ENODATA;
+ }
+
+ version_hi = dw[HUC_GSC_VERSION_HI_DW];
+ version_lo = dw[HUC_GSC_VERSION_LO_DW];
uc_fw->file_selected.ver.major = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK, version_hi);
uc_fw->file_selected.ver.minor = FIELD_GET(HUC_GSC_MINOR_VER_HI_MASK,
version_hi);
@@ -665,7 +678,7 @@ static int check_fw_header(struct intel_gt *gt,
return 0;
if (uc_fw->loaded_via_gsc)
- err = check_gsc_manifest(fw, uc_fw);
+ err = check_gsc_manifest(gt, fw, uc_fw);
else
err = check_ccs_header(gt, fw, uc_fw);
if (err)
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/aux: clean up aux name initialization
== Series Details ==
Series: drm/i915/aux: clean up aux name initialization
URL : https://patchwork.freedesktop.org/series/116436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13003_full -> Patchwork_116436v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116436v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@smoketest:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#5099])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-apl1/igt@gem_ctx_persiste...@smoketest.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-apl2/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-glk1/igt@gem_exec_f...@basic-deadline.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][5] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk1/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-apl4/igt@gem_lmem_swapp...@smem-oom.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][8] ([i915#3318])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-apl4/igt@gem_userptr_bl...@vma-merge.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-0:
- shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-snb5/igt@kms_big...@x-tiled-16bpp-rotate-0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-snb2/igt@kms_big...@x-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +42 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk1/igt@kms_big...@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271]) +26 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-apl4/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-snb2/igt@kms_plane_scal...@planes-upscale-20x20.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-glk1/igt@kms_vbl...@pipe-d-wait-idle.html
Possible fixes
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][16] ([i915#6268]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}:[FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-rkl-6/igt@gem_exec_fair@basic-n...@vecs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-rkl-4/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [ABORT][20] ([i915#5566]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/shard-apl3/igt@gen9_exec_pa...@allowed-single.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/shard-apl4/igt@gen9_exec_pa...@allowed-single.html
*
[Intel-gfx] [PATCH 3/9] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak (v4)
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1207 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 34 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 49 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
.../drm/i915/display/intel_display_types.h| 13 +
drivers/gpu/drm/i915/display/intel_dpll.c | 33 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c |2 +-
.../drm/i915/display/intel_modeset_verify.c |2 +
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
11 files changed, 1412 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 97b0d4ae221a..4ee3b5850dd0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -298,6 +298,7 @@ i915-y += \
display/icl_dsi.o \
display/intel_backlight.o \
display/intel_crt.o \
+ display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
new file mode 100644
index ..9ab1e686a40b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -0,0 +1,1207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "i915_reg.h"
+#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_panel.h"
+#include "intel_psr.h"
+#include "intel_tc.h"
+
+#define MB_WRITE_COMMITTED true
+#define MB_WRITE_UNCOMMITTEDfalse
+
+#define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
+ for ((__lane) = 0; (__lane) < 2; (__lane)++) \
+ for_each_if((__lane_mask) & BIT(__lane))
+
+#define INTEL_CX0_LANE0BIT(0)
+#define INTEL_CX0_LANE1BIT(1)
+#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
+
+bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
+{
+ if (IS_METEORLAKE(i915) && (phy < PHY_C))
+ return true;
+
+ return false;
+}
+
+static int lane_mask_to_lane(u8 lane_mask)
+{
+ if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
+ hweight8(lane_mask) != 1))
+ return 0;
+
+ return ilog2(lane_mask);
+}
+
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(>drm, !enabled);
+}
+
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR
[Intel-gfx] [PATCH 8/9] drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
From: Ankit Nautiyal
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
v2:
- Added fixes from Clint's Add HDMI implementation changes.
- Modified commit message.
v3:
- Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
of TRANS_DDI_FUNC_CTL_*. (Gustavo)
Cc: Taylor, Clinton A
Signed-off-by: Ankit Nautiyal
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c0283829823f..ea012d7f378f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -541,6 +541,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder
*encoder,
temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
@@ -3157,6 +3159,10 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
if (has_buf_trans_select(dev_priv))
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
+ /* e. Enable D2D Link for C10/C20 Phy */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ mtl_ddi_enable_d2d(encoder);
+
encoder->set_signal_levels(encoder, crtc_state);
/* Display WA #1143: skl,kbl,cfl */
@@ -3202,12 +3208,30 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
*
* On ADL_P the PHY link rate and lane count must be programmed but
* these are both 0 for HDMI.
+*
+* But MTL onwards HDMI2.1 is supported and in TMDS mode this
+* is filled with lane count, already set in the crtc_state.
+* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
- if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
+ u32 port_buf = 0;
+
+ port_buf |= XELPDP_PORT_WIDTH(lane_count);
+
+ if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
+ port_buf |= XELPDP_PORT_REVERSAL;
+
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
port_buf);
+
+ buf_ctl |= DDI_PORT_WIDTH(lane_count);
+ } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(_priv->drm,
!intel_tc_port_in_legacy_mode(dig_port));
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
+
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3668,7 +3692,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder
*encoder,
fallthrough;
case TRANS_DDI_MODE_SELECT_DVI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
- pipe_config->lane_count = 4;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ pipe_config->lane_count =
+ ((temp & DDI_PORT_WIDTH_MASK) >>
DDI_PORT_WIDTH_SHIFT) + 1;
+ else
+ pipe_config->lane_count = 4;
break;
case TRANS_DDI_MODE_SELECT_DP_SST:
if (encoder->type == INTEL_OUTPUT_EDP)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df29ab301326..f472baf242dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5596,6 +5596,8 @@ enum skl_power_gate {
#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
+#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define TRANS_DDI_PORT_WIDTH(width)
REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
--
2.34.1
[Intel-gfx] [PATCH 4/9] drm/i915/mtl: Add vswing programming for C10 phys
From: Mika Kahola
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
v4: Add vboost termination ctl programming(Imre)
Fix tx llogic and other nits
Restrict C10 vdr ctl register access for C10 phy(RK)
v5: Program vboots, termination ctl for both lanes(Imre)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak (v3)
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 102 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 14 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c| 31 +-
5 files changed, 143 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9ab1e686a40b..5ffd661fa507 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,6 +6,8 @@
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
@@ -292,6 +294,97 @@ static void intel_cx0_rmw(struct drm_i915_private *i915,
enum port port,
__intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
}
+static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state
*crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+ (crtc_state->port_clock == 54 ||
+crtc_state->port_clock == 81))
+ return 5;
+ else
+ return 4;
+ } else {
+ return 5;
+ }
+}
+
+static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+ (crtc_state->port_clock == 54 ||
+crtc_state->port_clock == 81))
+ return 5;
+ else
+ return 2;
+ } else {
+ return 6;
+ }
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_ddi_buf_trans *trans;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, _entries);
+ if (drm_WARN_ON_ONCE(>drm, !trans)) {
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+ return;
+ }
+
+ if (intel_is_c10phy(i915, phy)) {
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CMN(3),
+ C10_CMN3_TXVBOOST_MASK,
+
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
+ MB_WRITE_UNCOMMITTED);
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_TX(1),
+ C10_TX1_TERMCTL_MASK,
+
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
+ MB_WRITE_COMMITTED);
+ }
+
+ for (ln = 0; ln < crtc_state->lane_count; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2;
+
+ intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+ C10_PHY_OVRD_LEVEL_MASK,
+
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+ C10_PHY_OVRD_LEVEL_MASK,
+
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
+ MB_WRITE_COMMITTED);
+
[Intel-gfx] [PATCH 2/9] drm/i915/mtl: Create separate reg file for PICA registers
From: Mika Kahola Create a separate file to store registers for PICA chips C10 and C20. v2: Rename file (Jani) v3: Use _PICK_EVEN_2RANGES() macro (Lucas) Coding style fixed (Lucas) v4: Redefine macros (Imre) Reviewed-by: Vinod Govindapillai (v3) Signed-off-by: Radhakrishna Sripada Signed-off-by: Mika Kahola --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 133 ++ 1 file changed, 133 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h new file mode 100644 index ..27723c1a93d9 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_CX0_PHY_REGS_H__ +#define __INTEL_CX0_PHY_REGS_H__ + +#include "i915_reg_defs.h" + +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) +#define XELPDP_PORT_M2P_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) +#define XELPDP_PORT_M2P_TRANSACTION_RESETREG_BIT(15) +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK0x5 +#define XELPDP_PORT_P2M_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) +#define XELPDP_PORT_P2M_ERROR_SETREG_BIT(15) + +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1 +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US100 +#define XELPDP_PORT_RESET_END_TIMEOUT 15 +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US1 + +#define _XELPDP_PORT_BUF_CTL1_LN0_A0x64004 +#define _XELPDP_PORT_BUF_CTL1_LN0_B0x64104 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC10x16F200 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC20x16F400 +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_BUF_CTL1_LN0_A, \ + _XELPDP_PORT_BUF_CTL1_LN0_B, \ +
[Intel-gfx] [PATCH 7/9] drm/i915/mtl: Add C10 phy programming for HDMI
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can, and also add some logic to hdmi_port_clock_valid() to filter the
modelist to just the modes we can actually support with these link
rates.
Hopefully we'll have a proper / non-encumbered algorithm to calculate
these registers by the time we upstream and we'll be able to replace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Remove the extra hdmi clock check pruning.
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-6-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 610 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
4 files changed, 614 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5ffd661fa507..d46ff3401e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -647,6 +647,603 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
+ .clock = 25200,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xB2,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0x8F,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
+ .clock = 27000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xC0,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x80,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0xCF,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
+ .clock = 74250,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xB,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
+ .clock = 148500,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xA,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
+ .clock = 594000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x8,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+/* Precomputed C10 HDMI PLL tables */
+static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
+ .clock = 27027,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4]
= 0x00,
+ .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9]
= 0xFF,
+ .pll[10] =
[Intel-gfx] [PATCH 9/9] drm/i915/mtl: Initial DDI port setup
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Reviewed-by: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0334565cec82..2d4215862ed3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7801,7 +7801,11 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.34.1
[Intel-gfx] [PATCH 6/9] drm/i915/mtl/display: Implement DisplayPort sequences
From: José Roberto de Souza
The differences between MTL and TGL DP sequences are big enough to
MTL have its own functions.
Also it is much easier to follow MTL sequences against spec with
its own functions.
One change worthy to mention is the move of
'intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain)'.
This call is not necessary for MTL but we have _put() counter part in
intel_ddi_post_disable_dp() that needs to balanced.
We could add a display version check on it but instead here it is
moving it to intel_ddi_pre_enable_dp() so it is executed for all
platforms in a single place and this will not cause any harm in MTL
and newer platforms.
v2:
- Fix logic to wait for buf idle.
- Use the right register to wait for ddi active.(RK)
v3:
- Increase wait timeout for ddi buf active (Mika)
v4:
- Increase idle timeout for ddi buf idle (Mika)
v5: use rmw in mtl_disable_ddi_buf. Donot clear
link training mask(Imre)
BSpec: 65448 65505
Cc: Matt Roper
Cc: Satyeshwar Singh
Cc: Clint Taylor
Cc: Ankit Nautiyal
Cc: Imre Deak
Signed-off-by: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 +
drivers/gpu/drm/i915/display/intel_ddi.c | 344 +-
drivers/gpu/drm/i915/i915_reg.h | 5 +
3 files changed, 345 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 9cfa7f508c90..fe2e3edef69b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -59,8 +59,16 @@
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2))
+#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
#define XELPDP_PORT_BUF_SOC_PHY_READYREG_BIT(24)
+#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
+#define XELPDP_PORT_BUF_PORT_DATA_10BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
+#define XELPDP_PORT_BUF_PORT_DATA_20BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
+#define XELPDP_PORT_BUF_PORT_DATA_40BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
#define XELPDP_PORT_REVERSAL REG_BIT(16)
+#define XELPDP_PORT_BUF_IO_SELECT_TBTREG_BIT(11)
+#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
#define XELPDP_TCSS_POWER_REQUESTREG_BIT(5)
#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 21a86cb7b2dc..c0283829823f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -40,6 +40,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@@ -169,6 +170,18 @@ static void hsw_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
trans->entries[level].hsw.trans2);
}
+static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port
port)
+{
+ int ret;
+
+ /* FIXME: find out why Bspec's 100us timeout is too short */
+ ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+ XELPDP_PORT_BUF_PHY_IDLE), 1);
+ if (ret)
+ drm_err(>drm, "Timeout waiting for DDI BUF %c to get
idle\n",
+ port_name(port));
+}
+
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -196,7 +209,9 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
return;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ timeout_us = 1;
+ } else if (IS_DG2(dev_priv)) {
timeout_us = 1200;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_tc(dev_priv, phy))
@@ -207,8 +222,12 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
timeout_us = 500;
}
- ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
- DDI_BUF_IS_IDLE), timeout_us, 10, 10);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ ret
[Intel-gfx] [PATCH 5/9] drm/i915/mtl: MTL PICA hotplug detection
From: Mika Kahola
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Reviewed-by: Imre Deak
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 237 +++-
drivers/gpu/drm/i915/i915_reg.h | 31 -
2 files changed, 261 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d24bdea65a3d..b4dd6a5a536f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -162,6 +162,13 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) |
GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
};
+static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
+ [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
+};
+
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
@@ -182,6 +189,15 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
};
+static const u32 hpd_mtp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct intel_hotplug *hpd = _priv->display.hotplug;
@@ -195,7 +211,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
return;
}
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ hpd->hpd = hpd_xelpdp;
+ else if (DISPLAY_VER(dev_priv) >= 11)
hpd->hpd = hpd_gen11;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
hpd->hpd = hpd_bxt;
@@ -214,6 +232,8 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+ hpd->pch_hpd = hpd_mtp;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
@@ -1559,6 +1579,44 @@ static void cpt_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
cpt_serr_int_handler(dev_priv);
}
+static void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
+{
+ enum hpd_pin pin;
+ u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK |
XELPDP_TBT_HOTPLUG_MASK);
+ u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
+ u32 pin_mask = 0, long_mask = 0;
+
+ for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
+ u32 val;
+
+ if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
+ continue;
+
+ pin_mask |= BIT(pin);
+
+ val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
+ intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
+
+ if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT |
XELPDP_TBT_HPD_LONG_DETECT))
+ long_mask |= BIT(pin);
+ }
+
+ if (pin_mask) {
+ drm_dbg(>drm,
+ "pica hotplug event received, stat 0x%08x, pins 0x%08x,
long 0x%08x\n",
+ hotplug_trigger, pin_mask, long_mask);
+
+ intel_hpd_irq_handler(i915, pin_mask, long_mask);
+ }
+
+ if (trigger_aux)
+ dp_aux_irq_handler(i915);
+
+ if (!pin_mask && !trigger_aux)
+ drm_err(>drm,
+ "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
+}
+
static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
[Intel-gfx] [PATCH 1/9] drm/i915/mtl: Add DP rates
From: Mika Kahola
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 48d43f7f0c58..db7b6eaf8c85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 81;
}
+static int mtl_max_source_rate(struct intel_dp *intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ? 675000 : 81;
+}
+
static int vbt_max_link_rate(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
@@ -444,6 +449,10 @@ static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
+ static const int mtl_rates[] = {
+ 162000, 216000, 243000, 27, 324000, 432000, 54, 675000,
+ 81,
+ };
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
100, 135,
@@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ source_rates = mtl_rates;
+ size = ARRAY_SIZE(mtl_rates);
+ max_rate = mtl_max_source_rate(intel_dp);
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
--
2.34.1
[Intel-gfx] [PATCH 0/9] drm/i915/mtl: Add Support for C10 phy
Ignore the previous rev as the individual files got mixed with older series. Resending to avoid confusion. Apologies for the spam. This is a new rev for the series with the same title posted by Mika Kahola at [1]. Reusing the commit message from the series to preserve the version history. Phy programming support for C10 phy. This is the first part of the series that adds support for PICA phy. Later stage the support for C20 phy is added. This series gets the eDP going. v2: Register refinitions in intel_cx0_phy_regs.h file (Jani) v3: Add waits for between message bus writes (Imre) General cleanups and macro definitions (Imre) v4: Several nitpicks across patches(Imre) s/dev_priv/i915/,s/intel_c10mpllb_state/intel_c10pll_state/ Push the output init patch later Add teh HDMI definition patch. v5: Minor HDMI cleanup Program vboost and txterctl for both lanes in vswing patch. Fix the definition for mtl_crtc_compute_clock. Use rmw in mtl_disable_ddi_buf for DP sequences patch. Note that patches 1-6, 9 are required to boot with edp/native DP. Patches 7, 8 add the HDMI functionality. Signed-off-by: Mika Kahola Signed-off-by: Radhakrishna Sripada [1] https://patchwork.freedesktop.org/series/116191/ Ankit Nautiyal (1): drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI Clint Taylor (1): drm/i915/mtl: Initial DDI port setup José Roberto de Souza (1): drm/i915/mtl/display: Implement DisplayPort sequences Mika Kahola (4): drm/i915/mtl: Add DP rates drm/i915/mtl: Create separate reg file for PICA registers drm/i915/mtl: Add vswing programming for C10 phys drm/i915/mtl: MTL PICA hotplug detection Radhakrishna Sripada (2): drm/i915/mtl: Add Support for C10 PHY message bus and pll programming drm/i915/mtl: Add C10 phy programming for HDMI drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1903 + drivers/gpu/drm/i915/display/intel_cx0_phy.h | 37 + .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 180 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 402 +++- .../drm/i915/display/intel_ddi_buf_trans.c| 31 +- drivers/gpu/drm/i915/display/intel_display.c |6 +- .../drm/i915/display/intel_display_types.h| 13 + drivers/gpu/drm/i915/display/intel_dp.c | 15 +- drivers/gpu/drm/i915/display/intel_dpll.c | 33 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c |2 +- drivers/gpu/drm/i915/display/intel_hdmi.c |5 +- .../drm/i915/display/intel_modeset_verify.c |2 + drivers/gpu/drm/i915/i915_irq.c | 237 +- drivers/gpu/drm/i915/i915_reg.h | 43 +- drivers/gpu/drm/i915/i915_reg_defs.h | 57 + 16 files changed, 2938 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h -- 2.34.1
[Intel-gfx] [PATCH 8/9] drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
From: Ankit Nautiyal
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
v2:
- Added fixes from Clint's Add HDMI implementation changes.
- Modified commit message.
v3:
- Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
of TRANS_DDI_FUNC_CTL_*. (Gustavo)
Cc: Taylor, Clinton A
Signed-off-by: Ankit Nautiyal
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c0283829823f..ea012d7f378f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -541,6 +541,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder
*encoder,
temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
@@ -3157,6 +3159,10 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
if (has_buf_trans_select(dev_priv))
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
+ /* e. Enable D2D Link for C10/C20 Phy */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ mtl_ddi_enable_d2d(encoder);
+
encoder->set_signal_levels(encoder, crtc_state);
/* Display WA #1143: skl,kbl,cfl */
@@ -3202,12 +3208,30 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
*
* On ADL_P the PHY link rate and lane count must be programmed but
* these are both 0 for HDMI.
+*
+* But MTL onwards HDMI2.1 is supported and in TMDS mode this
+* is filled with lane count, already set in the crtc_state.
+* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
- if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
+ u32 port_buf = 0;
+
+ port_buf |= XELPDP_PORT_WIDTH(lane_count);
+
+ if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
+ port_buf |= XELPDP_PORT_REVERSAL;
+
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
port_buf);
+
+ buf_ctl |= DDI_PORT_WIDTH(lane_count);
+ } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(_priv->drm,
!intel_tc_port_in_legacy_mode(dig_port));
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
+
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3668,7 +3692,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder
*encoder,
fallthrough;
case TRANS_DDI_MODE_SELECT_DVI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
- pipe_config->lane_count = 4;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ pipe_config->lane_count =
+ ((temp & DDI_PORT_WIDTH_MASK) >>
DDI_PORT_WIDTH_SHIFT) + 1;
+ else
+ pipe_config->lane_count = 4;
break;
case TRANS_DDI_MODE_SELECT_DP_SST:
if (encoder->type == INTEL_OUTPUT_EDP)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df29ab301326..f472baf242dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5596,6 +5596,8 @@ enum skl_power_gate {
#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
+#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define TRANS_DDI_PORT_WIDTH(width)
REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
--
2.34.1
[Intel-gfx] [PATCH 8/9] drm/i915/mtl: Add C10 phy programming for HDMI
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can, and also add some logic to hdmi_port_clock_valid() to filter the
modelist to just the modes we can actually support with these link
rates.
Hopefully we'll have a proper / non-encumbered algorithm to calculate
these registers by the time we upstream and we'll be able to replace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-6-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 648 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
4 files changed, 652 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ca7626eadd7c..cacd51098290 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -647,6 +647,630 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
+ .clock = 25200,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xB2,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0x8F,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
+ .clock = 27000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xC0,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x80,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0xCF,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
+ .clock = 74250,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xB,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
+ .clock = 148500,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xA,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
+ .clock = 594000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x8,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+/* Precomputed C10 HDMI PLL tables */
+static const struct intel_c10pll_state mtl_c10_hdmi_25175 = {
+ .clock = 25175,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34,
+ .pll[1] = 0x00,
+ .pll[2] = 0xB0,
+ .pll[3] = 0x00,
+ .pll[4] = 0x00,
+ .pll[5] = 0x00,
+ .pll[6] = 0x00,
+ .pll[7] = 0x00,
+ .pll[8] = 0x20,
+ .pll[9] = 0xFF,
+
[Intel-gfx] [PATCH 7/9] drm/i915/mtl: Initial DDI port setup
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Reviewed-by: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 27b47680573a..1fec49c5d23a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7791,7 +7791,11 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.34.1
[Intel-gfx] [PATCH 5/9] drm/i915/mtl: MTL PICA hotplug detection
From: Mika Kahola
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Reviewed-by: Imre Deak
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 237 +++-
drivers/gpu/drm/i915/i915_reg.h | 31 -
2 files changed, 261 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d24bdea65a3d..b4dd6a5a536f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -162,6 +162,13 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) |
GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
};
+static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
+ [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) |
XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
+};
+
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
@@ -182,6 +189,15 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
};
+static const u32 hpd_mtp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct intel_hotplug *hpd = _priv->display.hotplug;
@@ -195,7 +211,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
return;
}
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ hpd->hpd = hpd_xelpdp;
+ else if (DISPLAY_VER(dev_priv) >= 11)
hpd->hpd = hpd_gen11;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
hpd->hpd = hpd_bxt;
@@ -214,6 +232,8 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+ hpd->pch_hpd = hpd_mtp;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
@@ -1559,6 +1579,44 @@ static void cpt_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
cpt_serr_int_handler(dev_priv);
}
+static void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
+{
+ enum hpd_pin pin;
+ u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK |
XELPDP_TBT_HOTPLUG_MASK);
+ u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
+ u32 pin_mask = 0, long_mask = 0;
+
+ for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
+ u32 val;
+
+ if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
+ continue;
+
+ pin_mask |= BIT(pin);
+
+ val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
+ intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
+
+ if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT |
XELPDP_TBT_HPD_LONG_DETECT))
+ long_mask |= BIT(pin);
+ }
+
+ if (pin_mask) {
+ drm_dbg(>drm,
+ "pica hotplug event received, stat 0x%08x, pins 0x%08x,
long 0x%08x\n",
+ hotplug_trigger, pin_mask, long_mask);
+
+ intel_hpd_irq_handler(i915, pin_mask, long_mask);
+ }
+
+ if (trigger_aux)
+ dp_aux_irq_handler(i915);
+
+ if (!pin_mask && !trigger_aux)
+ drm_err(>drm,
+ "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
+}
+
static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
[Intel-gfx] [PATCH 7/9] drm/i915/mtl: Add C10 phy programming for HDMI
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can, and also add some logic to hdmi_port_clock_valid() to filter the
modelist to just the modes we can actually support with these link
rates.
Hopefully we'll have a proper / non-encumbered algorithm to calculate
these registers by the time we upstream and we'll be able to replace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Remove the extra hdmi clock check pruning.
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-6-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 610 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
4 files changed, 614 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5ffd661fa507..d46ff3401e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -647,6 +647,603 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
+ .clock = 25200,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xB2,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0x8F,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
+ .clock = 27000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xC0,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x80,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0xCF,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
+ .clock = 74250,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xB,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
+ .clock = 148500,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xA,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
+ .clock = 594000,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x8,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+/* Precomputed C10 HDMI PLL tables */
+static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
+ .clock = 27027,
+ .tx = 0x10,
+ .cmn = 0x1,
+ .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4]
= 0x00,
+ .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9]
= 0xFF,
+ .pll[10] =
[Intel-gfx] [PATCH 9/9] drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
From: Ankit Nautiyal
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
v2:
- Added fixes from Clint's Add HDMI implementation changes.
- Modified commit message.
v3:
- Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
of TRANS_DDI_FUNC_CTL_*. (Gustavo)
Cc: Taylor, Clinton A
Signed-off-by: Ankit Nautiyal
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9df3da46fdca..c5d210a6fb94 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -541,6 +541,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder
*encoder,
temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
@@ -3158,6 +3160,10 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
if (has_buf_trans_select(dev_priv))
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
+ /* e. Enable D2D Link for C10/C20 Phy */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ mtl_ddi_enable_d2d(encoder);
+
encoder->set_signal_levels(encoder, crtc_state);
/* Display WA #1143: skl,kbl,cfl */
@@ -3203,12 +3209,30 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
*
* On ADL_P the PHY link rate and lane count must be programmed but
* these are both 0 for HDMI.
+*
+* But MTL onwards HDMI2.1 is supported and in TMDS mode this
+* is filled with lane count, already set in the crtc_state.
+* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
- if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
+ u32 port_buf = 0;
+
+ port_buf |= XELPDP_PORT_WIDTH(lane_count);
+
+ if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
+ port_buf |= XELPDP_PORT_REVERSAL;
+
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
port_buf);
+
+ buf_ctl |= DDI_PORT_WIDTH(lane_count);
+ } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(_priv->drm,
!intel_tc_port_in_legacy_mode(dig_port));
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
+
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3669,7 +3693,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder
*encoder,
fallthrough;
case TRANS_DDI_MODE_SELECT_DVI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
- pipe_config->lane_count = 4;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ pipe_config->lane_count =
+ ((temp & DDI_PORT_WIDTH_MASK) >>
DDI_PORT_WIDTH_SHIFT) + 1;
+ else
+ pipe_config->lane_count = 4;
break;
case TRANS_DDI_MODE_SELECT_DP_SST:
if (encoder->type == INTEL_OUTPUT_EDP)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d917353d4161..2f0371f8bcf0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5596,6 +5596,8 @@ enum skl_power_gate {
#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
+#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define TRANS_DDI_PORT_WIDTH(width)
REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
--
2.34.1
[Intel-gfx] [PATCH 9/9] drm/i915/mtl: Initial DDI port setup
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Reviewed-by: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0334565cec82..2d4215862ed3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7801,7 +7801,11 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.34.1
[Intel-gfx] [PATCH 6/9] drm/i915/mtl/display: Implement DisplayPort sequences
From: José Roberto de Souza
The differences between MTL and TGL DP sequences are big enough to
MTL have its own functions.
Also it is much easier to follow MTL sequences against spec with
its own functions.
One change worthy to mention is the move of
'intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain)'.
This call is not necessary for MTL but we have _put() counter part in
intel_ddi_post_disable_dp() that needs to balanced.
We could add a display version check on it but instead here it is
moving it to intel_ddi_pre_enable_dp() so it is executed for all
platforms in a single place and this will not cause any harm in MTL
and newer platforms.
v2:
- Fix logic to wait for buf idle.
- Use the right register to wait for ddi active.(RK)
v3:
- Increase wait timeout for ddi buf active (Mika)
v4:
- Increase idle timeout for ddi buf idle (Mika)
v5: use rmw in mtl_disable_ddi_buf. Donot clear
link training mask(Imre)
BSpec: 65448 65505
Cc: Matt Roper
Cc: Satyeshwar Singh
Cc: Clint Taylor
Cc: Ankit Nautiyal
Cc: Imre Deak
Signed-off-by: Radhakrishna Sripada
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 +
drivers/gpu/drm/i915/display/intel_ddi.c | 344 +-
drivers/gpu/drm/i915/i915_reg.h | 5 +
3 files changed, 345 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 9cfa7f508c90..fe2e3edef69b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -59,8 +59,16 @@
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2))
+#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
#define XELPDP_PORT_BUF_SOC_PHY_READYREG_BIT(24)
+#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
+#define XELPDP_PORT_BUF_PORT_DATA_10BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
+#define XELPDP_PORT_BUF_PORT_DATA_20BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
+#define XELPDP_PORT_BUF_PORT_DATA_40BIT
REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
#define XELPDP_PORT_REVERSAL REG_BIT(16)
+#define XELPDP_PORT_BUF_IO_SELECT_TBTREG_BIT(11)
+#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
#define XELPDP_TCSS_POWER_REQUESTREG_BIT(5)
#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 21a86cb7b2dc..c0283829823f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -40,6 +40,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@@ -169,6 +170,18 @@ static void hsw_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
trans->entries[level].hsw.trans2);
}
+static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port
port)
+{
+ int ret;
+
+ /* FIXME: find out why Bspec's 100us timeout is too short */
+ ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+ XELPDP_PORT_BUF_PHY_IDLE), 1);
+ if (ret)
+ drm_err(>drm, "Timeout waiting for DDI BUF %c to get
idle\n",
+ port_name(port));
+}
+
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -196,7 +209,9 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
return;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ timeout_us = 1;
+ } else if (IS_DG2(dev_priv)) {
timeout_us = 1200;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_tc(dev_priv, phy))
@@ -207,8 +222,12 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
timeout_us = 500;
}
- ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
- DDI_BUF_IS_IDLE), timeout_us, 10, 10);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ ret
[Intel-gfx] [PATCH 4/9] drm/i915/mtl: Add vswing programming for C10 phys
From: Mika Kahola
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
v4: Add vboost termination ctl programming(Imre)
Fix tx llogic and other nits
Restrict C10 vdr ctl register access for C10 phy(RK)
v5: Program vboots, termination ctl for both lanes(Imre)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak (v3)
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 102 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 14 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c| 31 +-
5 files changed, 143 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9ab1e686a40b..5ffd661fa507 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,6 +6,8 @@
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
@@ -292,6 +294,97 @@ static void intel_cx0_rmw(struct drm_i915_private *i915,
enum port port,
__intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
}
+static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state
*crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+ (crtc_state->port_clock == 54 ||
+crtc_state->port_clock == 81))
+ return 5;
+ else
+ return 4;
+ } else {
+ return 5;
+ }
+}
+
+static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+ (crtc_state->port_clock == 54 ||
+crtc_state->port_clock == 81))
+ return 5;
+ else
+ return 2;
+ } else {
+ return 6;
+ }
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_ddi_buf_trans *trans;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, _entries);
+ if (drm_WARN_ON_ONCE(>drm, !trans)) {
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+ return;
+ }
+
+ if (intel_is_c10phy(i915, phy)) {
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CMN(3),
+ C10_CMN3_TXVBOOST_MASK,
+
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
+ MB_WRITE_UNCOMMITTED);
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_TX(1),
+ C10_TX1_TERMCTL_MASK,
+
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
+ MB_WRITE_COMMITTED);
+ }
+
+ for (ln = 0; ln < crtc_state->lane_count; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2;
+
+ intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+ C10_PHY_OVRD_LEVEL_MASK,
+
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+ C10_PHY_OVRD_LEVEL_MASK,
+
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
+ MB_WRITE_COMMITTED);
+
[Intel-gfx] [PATCH 1/9] drm/i915/mtl: Add DP rates
From: Mika Kahola
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 48d43f7f0c58..db7b6eaf8c85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 81;
}
+static int mtl_max_source_rate(struct intel_dp *intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ? 675000 : 81;
+}
+
static int vbt_max_link_rate(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
@@ -444,6 +449,10 @@ static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
+ static const int mtl_rates[] = {
+ 162000, 216000, 243000, 27, 324000, 432000, 54, 675000,
+ 81,
+ };
static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81,
100, 135,
@@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ source_rates = mtl_rates;
+ size = ARRAY_SIZE(mtl_rates);
+ max_rate = mtl_max_source_rate(intel_dp);
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
--
2.34.1
[Intel-gfx] [PATCH 3/9] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak (v4)
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1207 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 34 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 49 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
.../drm/i915/display/intel_display_types.h| 13 +
drivers/gpu/drm/i915/display/intel_dpll.c | 33 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c |2 +-
.../drm/i915/display/intel_modeset_verify.c |2 +
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
11 files changed, 1412 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 97b0d4ae221a..4ee3b5850dd0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -298,6 +298,7 @@ i915-y += \
display/icl_dsi.o \
display/intel_backlight.o \
display/intel_crt.o \
+ display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
new file mode 100644
index ..9ab1e686a40b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -0,0 +1,1207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "i915_reg.h"
+#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_panel.h"
+#include "intel_psr.h"
+#include "intel_tc.h"
+
+#define MB_WRITE_COMMITTED true
+#define MB_WRITE_UNCOMMITTEDfalse
+
+#define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
+ for ((__lane) = 0; (__lane) < 2; (__lane)++) \
+ for_each_if((__lane_mask) & BIT(__lane))
+
+#define INTEL_CX0_LANE0BIT(0)
+#define INTEL_CX0_LANE1BIT(1)
+#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
+
+bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
+{
+ if (IS_METEORLAKE(i915) && (phy < PHY_C))
+ return true;
+
+ return false;
+}
+
+static int lane_mask_to_lane(u8 lane_mask)
+{
+ if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
+ hweight8(lane_mask) != 1))
+ return 0;
+
+ return ilog2(lane_mask);
+}
+
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(>drm, !enabled);
+}
+
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR
[Intel-gfx] [PATCH 2/9] drm/i915/mtl: Create separate reg file for PICA registers
From: Mika Kahola Create a separate file to store registers for PICA chips C10 and C20. v2: Rename file (Jani) v3: Use _PICK_EVEN_2RANGES() macro (Lucas) Coding style fixed (Lucas) v4: Redefine macros (Imre) Reviewed-by: Vinod Govindapillai (v3) Signed-off-by: Radhakrishna Sripada Signed-off-by: Mika Kahola --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 133 ++ 1 file changed, 133 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h new file mode 100644 index ..27723c1a93d9 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_CX0_PHY_REGS_H__ +#define __INTEL_CX0_PHY_REGS_H__ + +#include "i915_reg_defs.h" + +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) +#define XELPDP_PORT_M2P_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) +#define XELPDP_PORT_M2P_TRANSACTION_RESETREG_BIT(15) +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK0x5 +#define XELPDP_PORT_P2M_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) +#define XELPDP_PORT_P2M_ERROR_SETREG_BIT(15) + +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1 +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US100 +#define XELPDP_PORT_RESET_END_TIMEOUT 15 +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US1 + +#define _XELPDP_PORT_BUF_CTL1_LN0_A0x64004 +#define _XELPDP_PORT_BUF_CTL1_LN0_B0x64104 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC10x16F200 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC20x16F400 +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_BUF_CTL1_LN0_A, \ + _XELPDP_PORT_BUF_CTL1_LN0_B, \ +
[Intel-gfx] [PATCH 0/9] drm/i915/mtl: Add Support for C10 phy
This is a new rev for the series with the same title posted by Mika Kahola at [1]. Reusing the commit message from the series to preserve the version history. Phy programming support for C10 phy. This is the first part of the series that adds support for PICA phy. Later stage the support for C20 phy is added. This series gets the eDP going. v2: Register refinitions in intel_cx0_phy_regs.h file (Jani) v3: Add waits for between message bus writes (Imre) General cleanups and macro definitions (Imre) v4: Several nitpicks across patches(Imre) s/dev_priv/i915/,s/intel_c10mpllb_state/intel_c10pll_state/ Push the output init patch later Add teh HDMI definition patch. v5: Minor HDMI cleanup Program vboost and txterctl for both lanes in vswing patch. Fix the definition for mtl_crtc_compute_clock. Use rmw in mtl_disable_ddi_buf for DP sequences patch. Note that patches 1-6, 9 are required to boot with edp/native DP. Patches 7, 8 add the HDMI functionality. Signed-off-by: Mika Kahola Signed-off-by: Radhakrishna Sripada [1] https://patchwork.freedesktop.org/series/116191/ Ankit Nautiyal (1): drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI Clint Taylor (1): drm/i915/mtl: Initial DDI port setup José Roberto de Souza (1): drm/i915/mtl/display: Implement DisplayPort sequences Mika Kahola (4): drm/i915/mtl: Add DP rates drm/i915/mtl: Create separate reg file for PICA registers drm/i915/mtl: Add vswing programming for C10 phys drm/i915/mtl: MTL PICA hotplug detection Radhakrishna Sripada (2): drm/i915/mtl: Add Support for C10 PHY message bus and pll programming drm/i915/mtl: Add C10 phy programming for HDMI drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1903 + drivers/gpu/drm/i915/display/intel_cx0_phy.h | 37 + .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 180 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 402 +++- .../drm/i915/display/intel_ddi_buf_trans.c| 31 +- drivers/gpu/drm/i915/display/intel_display.c |6 +- .../drm/i915/display/intel_display_types.h| 13 + drivers/gpu/drm/i915/display/intel_dp.c | 15 +- drivers/gpu/drm/i915/display/intel_dpll.c | 33 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c |2 +- drivers/gpu/drm/i915/display/intel_hdmi.c |5 +- .../drm/i915/display/intel_modeset_verify.c |2 + drivers/gpu/drm/i915/i915_irq.c | 237 +- drivers/gpu/drm/i915/i915_reg.h | 43 +- drivers/gpu/drm/i915/i915_reg_defs.h | 57 + 16 files changed, 2938 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h -- 2.34.1
Re: [Intel-gfx] [PATCH 2/2] drm/nouveau: constify pointers to hwmon_channel_info
Reviewed-by: Lyude Paul
On Fri, 2023-04-07 at 17:00 +0200, Krzysztof Kozlowski wrote:
> Statically allocated array of pointed to hwmon_channel_info can be made
> const for safety.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> This depends on hwmon core patch:
> https://lore.kernel.org/all/20230406203103.3011503-2-krzysztof.kozlow...@linaro.org/
>
> Therefore I propose this should also go via hwmon tree.
>
> Cc: Jean Delvare
> Cc: Guenter Roeck
> Cc: linux-hw...@vger.kernel.org
> ---
> drivers/gpu/drm/nouveau/nouveau_hwmon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
> b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
> index e844be49e11e..db30a4c2cd4d 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
> @@ -211,7 +211,7 @@ static const struct attribute_group
> temp1_auto_point_sensor_group = {
>
> #define N_ATTR_GROUPS 3
>
> -static const struct hwmon_channel_info *nouveau_info[] = {
> +static const struct hwmon_channel_info * const nouveau_info[] = {
> HWMON_CHANNEL_INFO(chip,
> HWMON_C_UPDATE_INTERVAL),
> HWMON_CHANNEL_INFO(temp,
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache at BO creation
> Subject: Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache at BO > creation > > On 2023-04-05 13:26:43, Jordan Justen wrote: >> On 2023-04-05 00:45:24, Lionel Landwerlin wrote: >>> On 04/04/2023 19:04, Yang, Fei wrote: > Subject: Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set > cache at BO creation > > Just like the protected content uAPI, there is no way for > userspace to tell this feature is available other than trying using it. > > Given the issues with protected content, is it not thing we could want to > add? Sorry I'm not aware of the issues with protected content, could you elaborate? There was a long discussion on teams uAPI channel, could you comment there if any concerns? >>> >>> We wanted to have a getparam to detect protected support and were >>> told to detect it by trying to create a context with it. >>> >> >> An extensions system where the detection mechanism is "just try it", >> and assume it's not supported if it fails. ?? >> > > I guess no one wants to discuss the issues with this so-called detection > mechanism for i915 extensions. (Just try it and if it fails, it must not be supported.) > > I wonder how many ioctls we will be making a couple years down the road > just to see what the kernel supports. > > Maybe we'll get more fun 8 second timeouts to deal with. Maybe these probing > ioctls failing or succeeding will alter the kmd's state in some unexpected > way. For this SET_PAT extension, I can assure you there is no 8 second wait :) This is definitely a non-blocking call. > It'll also be fun to debug cases where the driver is not starting up with the > noise of a bunch of probing ioctls flying by. > > I thought about suggesting at least something like > I915_PARAM_CMD_PARSER_VERSION, > but I don't know if that could have prevented this 8 second timeout for > creating > a protected content context. Maybe it's better than nothing though. > > Of course, there was also the vague idea I threw out below for getting a list > of > supported extentions. The detection mechanism itself is an uAPI change, I don't think it's a good idea to combine that with this SET_PAT extension patch. I suggest we start a discussion in the "i915 uAPI changes" teams channel just like how we sorted out a solution for this setting cache policy issue. Would that work? https://teams.microsoft.com/l/channel/19%3af1767bda6734476ba0a9c7d147b928d1%40thread.skype/i915%2520uAPI%2520changes?groupId=379f3ae1-d138-4205-bb65-d4c7d38cb481=46c98d88-e344-4ed4-8496-4ed7712e255d -Fei > -Jordan > >> >> This seem likely to get more and more problematic as a detection >> mechanism as more extensions are added. >> >> > >> > Now it appears trying to create a protected context can block for >> > several seconds. >> > >> > Since we have to report capabilities to the user even before it >> > creates protected contexts, any app is at risk of blocking. >> > >> >> This failure path is not causing any re-thinking about using this as >> the extension detection mechanism? >> >> Doesn't the ioctl# + input-struct-size + u64-extension# identify the >> extension such that the kernel could indicate if it is supported or >> not. (Or, perhaps return an array of the supported extensions so the >> umd doesn't have to potentially make many ioctls for each extension of >> interest.) >> >> -Jordan
Re: [Intel-gfx] [PATCH 8/9] drm/i915/mtl: Add C10 phy programming for HDMI
> -Original Message-
> From: Deak, Imre
> Sent: Thursday, April 13, 2023 9:37 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 8/9] drm/i915/mtl: Add C10 phy programming for HDMI
>
> On Wed, Apr 12, 2023 at 03:49:24PM -0700, Radhakrishna Sripada wrote:
> > [...]
> > +/* Precomputed C10 HDMI PLL tables */
> > +static const struct intel_c10pll_state mtl_c10_hdmi_25175 = {
> > + .clock = 25175,
> > + .tx = 0x10,
> > + .cmn = 0x1,
> > + .pll[0] = 0x34,
> > + .pll[1] = 0x00,
> > + .pll[2] = 0xB0,
> > + .pll[3] = 0x00,
> > + .pll[4] = 0x00,
> > + .pll[5] = 0x00,
> > + .pll[6] = 0x00,
> > + .pll[7] = 0x00,
> > + .pll[8] = 0x20,
> > + .pll[9] = 0xFF,
> > + .pll[10] = 0xFF,
> > + .pll[11] = 0x55,
> > + .pll[12] = 0xE5,
> > + .pll[13] = 0x55,
> > + .pll[14] = 0x55,
> > + .pll[15] = 0x0D,
> > + .pll[16] = 0x09,
> > + .pll[17] = 0x8F,
> > + .pll[18] = 0x84,
> > + .pll[19] = 0x23,
> > +};
>
> Something off with the above table,
> intel_c10pll_calc_port_clock() calculates 25200 clock rate for it. So
> either .clock above needs to be the same rate, or the PLL params need to
> be corrected for the 25175 rate.
We do have a pre-computed table for 25200 clock which has different values.
Do we skip this clock for now?
-RK
>
> > [...]
> > @@ -690,9 +1315,20 @@ static void intel_c10pll_update_pll(struct
> intel_crtc_state *crtc_state,
> > static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> >struct intel_encoder *encoder)
> > {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > const struct intel_c10pll_state * const *tables;
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > int i;
> >
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> > + if (intel_c10_phy_check_hdmi_link_rate(crtc_state->port_clock)
> > + != MODE_OK) {
> > + drm_dbg_kms(>drm, "Can't support HDMI link
> rate %d on phy %c.\n",
> > + crtc_state->port_clock, phy_name(phy));
> > + return -EINVAL;
> > + }
> > + }
>
> The above check is not needed, covered already by the loop later in
> the function.
>
> > +
> > tables = intel_c10pll_tables_get(crtc_state, encoder);
> > if (!tables)
> > return -EINVAL;
[Intel-gfx] [PATCH 2/2] drm/i915: Make intel_get_crtc_new_encoder() less oopsy
From: Ville Syrjälä The point of the WARN was to print something, not oops straight up. Currently that is precisely what happens if we can't find the connector for the crtc in the atomic state. Get the dev pointer from the atomic state instead of the potentially NULL encoder to avoid that. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0334565cec82..5208b07505b2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -959,7 +959,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state, num_encoders++; } - drm_WARN(encoder->base.dev, num_encoders != 1, + drm_WARN(state->base.dev, num_encoders != 1, "%d encoders for pipe %c\n", num_encoders, pipe_name(master_crtc->pipe)); -- 2.39.2
[Intel-gfx] [PATCH 1/2] drm/i915: Make intel_mpllb_state_verify() safer
From: Ville Syrjälä intel_mpllb_state_verify() blows up if you call it for a non-modeset/fastset commit on account of the relevant connector not being part of the overall atomic state. Currently the state checker only runs for modeset/fastset commits, but for testing purposes it is sometimes desirable to run it for other commits too. Check for modeset/fastset in intel_mpllb_state_verify() itself to make this safe. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_snps_phy.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 1cfb94b5cedb..4efc79d47e43 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -2007,6 +2007,10 @@ void intel_mpllb_state_verify(struct intel_atomic_state *state, if (!new_crtc_state->hw.active) return; + if (!intel_crtc_needs_modeset(new_crtc_state) && + !intel_crtc_needs_fastset(new_crtc_state)) + return; + encoder = intel_get_crtc_new_encoder(state, new_crtc_state); intel_mpllb_readout_hw_state(encoder, _hw_state); -- 2.39.2
[Intel-gfx] [PATCH] drm/i915/gt: Avoid out-of-bounds access when loading HuC
When HuC is loaded by GSC, there is no header definition for the kernel
to look at and firmware is just handed to GSC. However when reading the
version, it should still check the size of the blob to guarantee it's not
incurring into out-of-bounds array access.
If firmware is smaller than expected, the following message is now
printed:
# echo boom > /lib/firmware/i915/dg2_huc_gsc.bin
# dmesg | grep -i huc
[drm] GT0: HuC firmware i915/dg2_huc_gsc.bin: invalid size: 5 < 184
[drm] *ERROR* GT0: HuC firmware i915/dg2_huc_gsc.bin: fetch failed
-ENODATA
...
Even without this change the size, header and signature are still
checked by GSC when loading, so this only avoids the out-of-bounds array
access.
Fixes: a7b516bd981f ("drm/i915/huc: Add fetch support for gsc-loaded HuC
binary")
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 1ac6f9f340e3..a82a53dbbc86 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -489,12 +489,25 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw, int e)
}
}
-static int check_gsc_manifest(const struct firmware *fw,
+static int check_gsc_manifest(struct intel_gt *gt,
+ const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
u32 *dw = (u32 *)fw->data;
- u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
- u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
+ u32 version_hi, version_lo;
+ size_t min_size;
+
+ /* Check the size of the blob before examining buffer contents */
+ min_size = sizeof(u32) * (HUC_GSC_VERSION_LO_DW + 1);
+ if (unlikely(fw->size < min_size)) {
+ gt_warn(gt, "%s firmware %s: invalid size: %zu < %zu\n",
+ intel_uc_fw_type_repr(uc_fw->type),
uc_fw->file_selected.path,
+ fw->size, min_size);
+ return -ENODATA;
+ }
+
+ version_hi = dw[HUC_GSC_VERSION_HI_DW];
+ version_lo = dw[HUC_GSC_VERSION_LO_DW];
uc_fw->file_selected.ver.major = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK,
version_hi);
uc_fw->file_selected.ver.minor = FIELD_GET(HUC_GSC_MINOR_VER_HI_MASK,
version_hi);
@@ -665,7 +678,7 @@ static int check_fw_header(struct intel_gt *gt,
return 0;
if (uc_fw->loaded_via_gsc)
- err = check_gsc_manifest(fw, uc_fw);
+ err = check_gsc_manifest(gt, fw, uc_fw);
else
err = check_ccs_header(gt, fw, uc_fw);
if (err)
--
2.39.0
Re: [Intel-gfx] [PULL] drm-misc-fixes
On Thu, Apr 13, 2023 at 08:42:33PM +0200, Thomas Zimmermann wrote: > Hi Dave and Daniel, > > this is the PR for drm-misc-fixes for this week. > > Best regards > Thomas > > drm-misc-fixes-2023-04-13: > Short summary of fixes pull: > > * armada: Fix double free > * fb: Clear FB_ACTIVATE_KD_TEXT in ioctl > * nouveau: Add missing callbacks > * scheduler: Fix use-after-free error > The following changes since commit 09a9639e56c01c7a00d6c0ca63f4c7c41abe075d: > > Linux 6.3-rc6 (2023-04-09 11:15:57 -0700) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2023-04-13 Pulled, thanks > > for you to fetch changes up to 5603effb8295ada8419408d038a34ca89d658229: > > Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes > (2023-04-12 12:01:32 +0200) > > > Short summary of fixes pull: > > * armada: Fix double free > * fb: Clear FB_ACTIVATE_KD_TEXT in ioctl > * nouveau: Add missing callbacks > * scheduler: Fix use-after-free error > > > Asahi Lina (1): > drm/scheduler: Fix UAF race in drm_sched_entity_push_job() > > Christophe JAILLET (1): > drm/armada: Fix a potential double free in an error handling path > > Daniel Vetter (1): > fbmem: Reject FB_ACTIVATE_KD_TEXT from userspace > > Karol Herbst (1): > drm/nouveau/fb: add missing sysmen flush callbacks > > Maarten Lankhorst (1): > Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes > > drivers/gpu/drm/armada/armada_drv.c| 1 - > drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c | 1 + > drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c | 1 + > drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c | 1 + > drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c | 1 + > drivers/gpu/drm/scheduler/sched_entity.c | 11 +-- > drivers/video/fbdev/core/fbmem.c | 2 ++ > 7 files changed, 15 insertions(+), 3 deletions(-) > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] [PATCH] ALSA: hda/hdmi: disable KAE for Intel DG2
Use of keep-alive (KAE) has resulted in loss of audio on some A750/770
cards as the transition from keep-alive to stream playback is not
working as expected. As there is limited benefit of the new KAE mode
on discrete cards, revert back to older silent-stream implementation
on these systems.
Cc: sta...@vger.kernel.org
Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8307
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 4ffa3a59f419..5c6980394dce 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -4604,7 +4604,7 @@ HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI",
patch_i915_tgl_hdmi),
HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
-HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI",patch_i915_adlp_hdmi),
+HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI",patch_i915_tgl_hdmi),
HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI",patch_i915_icl_hdmi),
HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
base-commit: be6247640eea9d9b0ff15607fab7a12f40974985
--
2.40.0
Re: [Intel-gfx] [PATCH 04/10] drm/i915/display: rename intel_modeset_probe_defer() -> intel_display_driver_probe_defer()
On Thu, Apr 13, 2023 at 12:47:30PM +0300, Jani Nikula wrote: Follow the usual naming conventions. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_driver.c | 2 +- drivers/gpu/drm/i915/display/intel_display_driver.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 1386f2001613..882a2586aba4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -21,7 +21,7 @@ #include "intel_fbdev.h" #include "intel_opregion.h" -bool intel_modeset_probe_defer(struct pci_dev *pdev) +bool intel_display_driver_probe_defer(struct pci_dev *pdev) thanks much Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v10 00/23] drm/i915/vm_bind: Add VM_BIND functionality
On Tue, Jan 17, 2023 at 11:15:46PM -0800, Niranjana Vishwanathapura wrote: DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer objects (BOs) or sections of a BOs at specified GPU virtual addresses on a specified address space (VM). Multiple mappings can map to the same physical pages of an object (aliasing). These mappings (also referred to as persistent mappings) will be persistent across multiple GPU submissions (execbuf calls) issued by the UMD, without user having to provide a list of all required mappings during each submission (as required by older execbuf mode). This patch series support VM_BIND version 1, as described by the param I915_PARAM_VM_BIND_VERSION. Add new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. The new execbuf3 ioctl will not have any execlist support and all the legacy support like relocations etc., are removed. NOTEs: * It is based on below VM_BIND design+uapi rfc. Documentation/gpu/rfc/i915_vm_bind.rst * The IGT RFC series is posted as, [PATCH i-g-t v10 0/19] vm_bind: Add VM_BIND validation support v2: Address various review comments v3: Address review comments and other fixes v4: Remove vm_unbind out fence uapi which is not supported yet, replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() v5: Render kernel-doc, use PIN_NOEVICT, limit vm_bind support to non-recoverable faults v6: Rebased, minor fixes, add reserved fields to drm_i915_gem_vm_bind, add new patch for async vm_unbind support v7: Rebased, minor cleanups as per review feedback v8: Rebased, add capture support v9: Address capture support feedback from v8 v10: Properly handle vma->resource for mappings with capture request Test-with: 20230118071350.17498-1-niranjana.vishwanathap...@intel.com Signed-off-by: Niranjana Vishwanathapura Hi, It has become clear that we have a long way towards fully featured implementation of VM_BIND in i915. Examples of the many challenges include integration with display, integration with userspace drivers, a rewrite of all the i915 IGTs to support execbuf3, alignment with DRM GPU VA manager[1] etc. We are stopping further VM_BIND upstreaming efforts in i915 so we can accelerate the merge plan for the new drm/xe driver[2] which has been designed for VM_BIND from the beginning. Since we are not proceeding further with this i915 VM_BIND patch series, the MTL support needed for setting the MOCS and PAT settings in an immutable way at buffer creation time has been posted in a separate series[3] under review. Thanks for all your feedback on this series which is much appreciated. Regards, Niranjana [1] https://www.spinics.net/lists/nouveau/msg11069.html [2] https://www.spinics.net/lists/dri-devel/msg390882.html [3] https://patchwork.freedesktop.org/series/115980/ Niranjana Vishwanathapura (23): drm/i915/vm_bind: Expose vm lookup function drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() drm/i915/vm_bind: Expose i915_gem_object_max_page_size() drm/i915/vm_bind: Support partially mapped vma resource drm/i915/vm_bind: Add support to create persistent vma drm/i915/vm_bind: Implement bind and unbind of object drm/i915/vm_bind: Support for VM private BOs drm/i915/vm_bind: Add support to handle object evictions drm/i915/vm_bind: Support persistent vma activeness tracking drm/i915/vm_bind: Add out fence support drm/i915/vm_bind: Abstract out common execbuf functions drm/i915/vm_bind: Use common execbuf functions in execbuf path drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl drm/i915/vm_bind: Update i915_vma_verify_bind_complete() drm/i915/vm_bind: Expose i915_request_await_bind() drm/i915/vm_bind: Handle persistent vmas in execbuf3 drm/i915/vm_bind: userptr dma-resv changes drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode drm/i915/vm_bind: Render VM_BIND documentation drm/i915/vm_bind: Async vm_unbind support drm/i915/vm_bind: Properly build persistent map sg table drm/i915/vm_bind: Support capture of persistent mappings Documentation/gpu/i915.rst| 78 +- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 43 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 17 + drivers/gpu/drm/i915/gem/i915_gem_create.c| 72 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 6 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 522 +-- .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 872 ++ .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++ .../drm/i915/gem/i915_gem_execbuffer_common.h | 76 ++ drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 + drivers/gpu/drm/i915/gem/i915_gem_object.c| 3 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: CTM stuff mostly (rev3)
== Series Details == Series: drm/i915: CTM stuff mostly (rev3) URL : https://patchwork.freedesktop.org/series/116345/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13003 -> Patchwork_116345v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_116345v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_116345v3, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/index.html Participating hosts (36 -> 36) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_116345v3: ### IGT changes ### Possible regressions * igt@kms_color@ctm-red-to-blue@pipe-a (NEW): - bat-dg2-11: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-11/igt@kms_color@ctm-red-to-b...@pipe-a.html - bat-dg2-8: NOTRUN -> [ABORT][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-8/igt@kms_color@ctm-red-to-b...@pipe-a.html - bat-dg2-9: NOTRUN -> [ABORT][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-9/igt@kms_color@ctm-red-to-b...@pipe-a.html New tests - New tests have been introduced between CI_DRM_13003 and Patchwork_116345v3: ### New IGT tests (37) ### * igt@kms_color@ctm-0-25@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-25@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-25@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-25@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-50@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-50@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-50@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-50@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-75@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-75@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-75@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-0-75@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-blue-to-red@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-blue-to-red@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-blue-to-red@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-blue-to-red@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-green-to-red@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-green-to-red@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-green-to-red@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-green-to-red@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-max@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-max@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-max@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-max@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-negative@pipe-a: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-negative@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-negative@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-negative@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-red-to-blue@pipe-a: - Statuses : 3 abort(s) 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-red-to-blue@pipe-b: - Statuses : 20 pass(s) 9 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-red-to-blue@pipe-c: - Statuses : 20 pass(s) 6 skip(s) - Exec time: [0.0] s * igt@kms_color@ctm-red-to-blue@pipe-d: - Statuses : 5 pass(s) 1 skip(s) - Exec time: [0.0] s *
Re: [Intel-gfx] [PULL] drm-intel-next-fixes
On Thu, Apr 13, 2023 at 03:12:19PM +0300, Joonas Lahtinen wrote: > Hi Dave & Daniel, > > Just one Cc:stable fix for indirect sampler state this week on > drm-intel-next-fixes. > > Regards, Joonas > > *** > > drm-intel-next-fixes-2023-04-13: > > Short summary of fixes pull (less than what git shortlog provides): > > Just one Cc:stable fix for sampler indirect state in bindless heap. > > The following changes since commit 55bf14961db9da61220e6f04bc9919c94b1a6585: > > Merge tag 'mediatek-drm-next-6.4' of > https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into > drm-next (2023-04-11 12:28:10 +0200) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/drm-intel-next-fixes-2023-04-13 Pulled, thanks. > > for you to fetch changes up to 81900e3a37750d8c6ad705045310e002f6dd0356: > > drm/i915: disable sampler indirect state in bindless heap (2023-04-12 > 11:36:09 +0300) > > > Short summary of fixes pull (less than what git shortlog provides): > > Just one Cc:stable fix for sampler indirect state in bindless heap. > > > Lionel Landwerlin (1): > drm/i915: disable sampler indirect state in bindless heap > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++ > 2 files changed, 20 insertions(+) -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, this is the PR for drm-misc-fixes for this week. Best regards Thomas drm-misc-fixes-2023-04-13: Short summary of fixes pull: * armada: Fix double free * fb: Clear FB_ACTIVATE_KD_TEXT in ioctl * nouveau: Add missing callbacks * scheduler: Fix use-after-free error The following changes since commit 09a9639e56c01c7a00d6c0ca63f4c7c41abe075d: Linux 6.3-rc6 (2023-04-09 11:15:57 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2023-04-13 for you to fetch changes up to 5603effb8295ada8419408d038a34ca89d658229: Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes (2023-04-12 12:01:32 +0200) Short summary of fixes pull: * armada: Fix double free * fb: Clear FB_ACTIVATE_KD_TEXT in ioctl * nouveau: Add missing callbacks * scheduler: Fix use-after-free error Asahi Lina (1): drm/scheduler: Fix UAF race in drm_sched_entity_push_job() Christophe JAILLET (1): drm/armada: Fix a potential double free in an error handling path Daniel Vetter (1): fbmem: Reject FB_ACTIVATE_KD_TEXT from userspace Karol Herbst (1): drm/nouveau/fb: add missing sysmen flush callbacks Maarten Lankhorst (1): Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes drivers/gpu/drm/armada/armada_drv.c| 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c | 1 + drivers/gpu/drm/scheduler/sched_entity.c | 11 +-- drivers/video/fbdev/core/fbmem.c | 2 ++ 7 files changed, 15 insertions(+), 3 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/debugfs: New debugfs for display clock frequencies (rev2)
== Series Details ==
Series: drm/i915/debugfs: New debugfs for display clock frequencies (rev2)
URL : https://patchwork.freedesktop.org/series/116372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13002_full -> Patchwork_116372v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116372v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#5566])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-apl7/igt@gen9_exec_pa...@allowed-single.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-apl7/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-apl6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk2/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#2346]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-apl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#79])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +40 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk4/igt@kms_frontbuffer_track...@psr-1p-pri-indfb-multidraw.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][14] ([i915#7742]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl}:[FAIL][16] ([i915#2842]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-rkl-2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-rkl-6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][18] ([i915#5566]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-glk7/igt@gen9_exec_pa...@allowed-single.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116372v2/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][20] ([i915#2346]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13002/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[21]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: CTM stuff mostly (rev3)
== Series Details == Series: drm/i915: CTM stuff mostly (rev3) URL : https://patchwork.freedesktop.org/series/116345/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev3)
== Series Details == Series: drm/i915: CTM stuff mostly (rev3) URL : https://patchwork.freedesktop.org/series/116345/ State : warning == Summary == Error: dim checkpatch failed 78b5c06e6a08 drm/uapi: Document CTM matrix better 040d34333d15 drm/i915: Expose crtc CTM property on ilk/snb 025b0a294b12 drm/i915: Fix CHV CGM CSC coefficient sign handling 4c183dda16bc drm/i915: Always enable CGM CSC on CHV 9b4ab15ce12b drm/i915: Implement CTM property support for VLV -:10: WARNING:REPEATED_WORD: Possible repeated word: 'is' #10: What it is is a 3x3 matrix similar to the later CHV CGM total: 0 errors, 1 warnings, 0 checks, 310 lines checked 28846b2d788c drm/i915: No 10bit gamma on desktop gen3 parts deec600a1da5 drm/i915: Do state check for color management changes
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: hide mkwrite_device_info() better (rev3)
== Series Details == Series: drm/i915: hide mkwrite_device_info() better (rev3) URL : https://patchwork.freedesktop.org/series/113017/ State : success == Summary == CI Bug Log - changes from CI_DRM_13003 -> Patchwork_113017v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/index.html Participating hosts (36 -> 35) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_113017v3 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][1] -> [DMESG-WARN][2] ([i915#7699]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-11/igt@i915_selftest@l...@migrate.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][3] ([i915#6367] / [i915#7913] / [i915#7996]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#7828]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-adlp-9: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-adlp-9/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-rpls-1: NOTRUN -> [SKIP][6] ([i915#7828]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1: - bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#5354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-1: NOTRUN -> [SKIP][11] ([i915#1845]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html - bat-rpls-2: NOTRUN -> [SKIP][12] ([i915#1845]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [ABORT][13] ([i915#6687] / [i915#7978]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@reset: - bat-rpls-2: [ABORT][15] ([i915#4983] / [i915#7913] / [i915#7981]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-2/igt@i915_selftest@l...@reset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][17] ([i915#6367]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-1/igt@i915_selftest@l...@slpc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_selftest@live@uncore: - bat-adlp-9: [ABORT][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-adlp-9/igt@i915_selftest@l...@uncore.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-adlp-9/igt@i915_selftest@l...@uncore.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1: - bat-dg2-8: [FAIL][21] ([i915#7932]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113017v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html [i915#1845]:
Re: [Intel-gfx] [PATCH v3 12/12] vfio/pci: Report dev_id in VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
On Thu, 13 Apr 2023 08:50:45 -0300
Jason Gunthorpe wrote:
> On Thu, Apr 13, 2023 at 08:25:52AM +, Tian, Kevin wrote:
> > > From: Jason Gunthorpe
> > > Sent: Thursday, April 13, 2023 4:07 AM
> > >
> > >
> > > > in which case we need c) a way to
> > > > report the overall set of affected devices regardless of ownership in
> > > > support of 4), BDF?
> > >
> > > Yes, continue to use INFO unmodified.
> > >
> > > > Are we back to replacing group-ids with dev-ids in the INFO structure,
> > > > where an invalid dev-id either indicates an affected device with
> > > > implied ownership (ok) or a gap in ownership (bad) and a flag somewhere
> > > > is meant to indicate the overall disposition based on the availability
> > > > of reset?
> > >
> > > As you explore in the following this gets ugly. I prefer to keep INFO
> > > unchanged and add INFO2.
> > >
> >
> > INFO needs a change when VFIO_GROUP is disabled. Now it assumes
> > a valid iommu group always exists:
> >
> > vfio_pci_fill_devs()
> > {
> > ...
> > iommu_group = iommu_group_get(>dev);
> > if (!iommu_group)
> > return -EPERM; /* Cannot reset non-isolated devices */
> > ...
> > }
>
> This can still work in a ugly way. With a INFO2 the only purpose of
> INFO would be debugging, so if someone uses no-iommu, with hotreset
> and misconfigures it then the only downside is they don't get the
> debugging print. But we know of nothing that uses this combination
> anyhow..
>
> > with that plus BDF cap, I'm curious what is the actual purpose of
> > INFO2 or why cannot requirement#3 reuse the information collected
> > via existing INFO?
>
> It can - it is just more complicated for userspace to do it, it has to
> extract and match the BDFs and then run some algorithm to determine if
> the opened devices cover the right set of devices in the reset group,
> and it has to have some special code for no-iommu.
>
> VS info2 would return the dev_id's and a single yes/no if the right
> set is present. Kernel runs the algorithm instead of userspace, it
> seems more abstract this way.
>
> Also, if we make iommufd return a 'ioas dev_id group' as well it
> composes nicely that userspace just needs one translation from dev_id.
IIUC, the semantics we're proposing is that an INFO2 ioctl would return
success or failure indicating whether the user has sufficient ownership
of the affected devices, and in the success case returns an array of
affected dev-ids within the user's iommufd_ctx. Unopened, affected
devices, are not reported via INFO2, and unopened, affected devices
outside the user's scope of ownership (ie. outside the owned IOMMU
group) will generate a failure condition.
As for the INFO ioctl, it's described as unchanged, which does raise
the question of what is reported for IOMMU groups and how does the
value there coherently relate to anything else in the cdev-exclusive
vfio API...
We had already iterated a proposal where the group-id is replaced with
a dev-id in the existing ioctl and a flag indicates when the return
value is a dev-id vs group-id. This had a gap that userspace cannot
determine if a reset is available given this information since un-owned
devices report an invalid dev-id and userspace can't know if it has
implicit ownership.
It seems cleaner to me though that we would could still re-use INFO in
a similar way, simply defining a new flag bit which is valid only in
the case of returning dev-ids and indicates if the reset is available.
Therefore in one ioctl, userspace knows if hot-reset is available
(based on a kernel determination) and can pull valid dev-ids from the
array to associate affected, owned devices, and still has the
equivalent information to know that one or more of the devices listed
with an invalid dev-id are preventing the hot-reset from being
available.
Is that an option? Thanks,
Alex
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: hide mkwrite_device_info() better (rev3)
== Series Details == Series: drm/i915: hide mkwrite_device_info() better (rev3) URL : https://patchwork.freedesktop.org/series/113017/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: hide mkwrite_device_info() better (rev3)
== Series Details == Series: drm/i915: hide mkwrite_device_info() better (rev3) URL : https://patchwork.freedesktop.org/series/113017/ State : warning == Summary == Error: dim checkpatch failed 33d6eac19e2e drm/i915: hide mkwrite_device_info() better -:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #21: [1] https://lore.kernel.org/r/a0422f0a8ac055f65b7922bcd3119b180a41e79e.1655712106.git.jani.nik...@intel.com total: 0 errors, 1 warnings, 0 checks, 84 lines checked
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use min() instead of hand rolling it
Hi Ville > -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: 04 April 2023 23:25 > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Use min() instead of hand rolling > it > > From: Ville Syrjälä > > Most places in the vblank code use min() to clamp scanline counters below > vtotal. But we missed one in the gen3/4 pixel counter based codepath. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_vblank.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c > b/drivers/gpu/drm/i915/display/intel_vblank.c > index f8bf9810527d..136393d99298 100644 > --- a/drivers/gpu/drm/i915/display/intel_vblank.c > +++ b/drivers/gpu/drm/i915/display/intel_vblank.c > @@ -340,8 +340,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc > *_crtc, >* matches how the scanline counter based position works > since >* the scanline counter doesn't count the two half lines. >*/ > - if (position >= vtotal) > - position = vtotal - 1; > + position = min(position, vtotal - 1); changes LGTM. Thanks Reviewed-by: Mitul Golani > > /* >* Start of vblank interrupt is triggered at start of hsync, > -- > 2.39.2
Re: [Intel-gfx] [PATCH v4 08/12] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
Hi,
> Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
>
Looks Good to me
Reviewed-by: Suraj Kandpal
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 438
> +++
> include/drm/display/drm_dsc_helper.h | 2 +
> 2 files changed, 440 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index aec6f8c201af..65e810a54257 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -740,6 +740,438 @@ static const struct rc_parameters_data
> rc_parameters_1_2_444[] = {
> { /* sentinel */ }
> };
>
> +static const struct rc_parameters_data rc_parameters_1_2_422[] = {
> + {
> + .bpp = DSC_BPP(6), .bpc = 8,
> + { 512, 15, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11,
> -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(6), .bpc = 10,
> + { 512, 15, 6144, 7, 16, 15, 15, {
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15,
> -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(6), .bpc = 12,
> + { 512, 15, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(6), .bpc = 14,
> + { 512, 15, 6144, 15, 24, 23, 23, {
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2
> },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15,
> 20, -8 },
> + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> + { 24, 25, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(6), .bpc = 16,
> + { 512, 15, 6144, 19, 28, 27, 27, {
> + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2
> },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19,
> 24, -8 },
> + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> + { 28, 29, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(7), .bpc = 8,
> + { 410, 15, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10,
> -10 },
> + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(7), .bpc = 10,
> + { 410, 15, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14,
> -10 },
> + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(7), .bpc = 12,
> + { 410, 15, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2
> },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> + { 19, 20, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(7), .bpc = 14,
> + { 410, 15, 5632, 15, 24, 23, 23, {
> + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2
>
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Evade transcoder's vblank when doing seamless M/N changes
Hi Ville,
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 04 April 2023 23:25
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Evade transcoder's vblank when
> doing seamless M/N changes
>
> From: Ville Syrjälä
>
> The transcoder M/N values are double buffered on the transcoder's
> undelayed vblank. So when doing seamless M/N fastsets we need to evade
> also that.
>
> Not that currently the pipe's delayed vblank == transcoder's undelayed
> vblank, so this is still a nop change. But in the future when we may have to
> delay the pipe's vblank to create a register programming window
> ("window2") for the DSB.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index ed45a6934854..f3b836829296 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -510,6 +510,13 @@ void intel_pipe_update_start(struct intel_crtc_state
> *new_crtc_state)
>
> VBLANK_EVASION_TIME_US);
> max = vblank_start - 1;
>
> + /*
> + * M/N is double buffered on the transcoder's undelayed vblank,
> + * so with seamless M/N we must evade both vblanks.
> + */
> + if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> + min -= adjusted_mode->crtc_vblank_start -
> +adjusted_mode->crtc_vdisplay;
> +
changes LGTM.
Thanks
Reviewed-by: Mitul Golani > if (min <= 0 || max <= 0)
> goto irq_disable;
>
> --
> 2.39.2
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Allow arbitrary refresh rates with VRR eDP panels
Hi Ville,
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 04 April 2023 23:24
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Allow arbitrary refresh rates with
> VRR eDP panels
>
> From: Ville Syrjälä
>
> If the panel supports VRR it must be capable of accepting timings with
> arbitrary vblank length, within the valid VRR range. Use that fact to allow
> the
> user to request any refresh rate they like. We simply pick the next highest
> fixed mode from our list, and adjust the vblank to get the desired refresh
> rate in the end.
>
> Of course currently everything to do with the vrefresh is using 1Hz precision,
> so might not be exact. But we can improve that in the future by just upping
> our vrefresh precision.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 80 ++
> 1 file changed, 66 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index ce2a34a25211..9acdd68b2dbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -42,6 +42,7 @@
> #include "intel_lvds_regs.h"
> #include "intel_panel.h"
> #include "intel_quirks.h"
> +#include "intel_vrr.h"
>
> bool intel_panel_use_ssc(struct drm_i915_private *i915) { @@ -58,6 +59,38
> @@ intel_panel_preferred_fixed_mode(struct intel_connector *connector)
> struct drm_display_mode, head);
> }
>
> +static bool is_in_vrr_range(struct intel_connector *connector, int
> +vrefresh) {
> + const struct drm_display_info *info =
> >base.display_info;
> +
> + return intel_vrr_is_capable(connector) &&
> + vrefresh >= info->monitor_range.min_vfreq &&
> + vrefresh <= info->monitor_range.max_vfreq; }
> +
> +static bool is_best_fixed_mode(struct intel_connector *connector,
> +int vrefresh, int fixed_mode_vrefresh,
> +const struct drm_display_mode *best_mode) {
> + /* we want to always return something */
> + if (!best_mode)
> + return true;
> +
> + /*
> + * With VRR always pick a mode with equal/higher than requested
> + * vrefresh, which we can then reduce to match the requested
> + * vrefresh by extending the vblank length.
> + */
> + if (is_in_vrr_range(connector, vrefresh) &&
> + is_in_vrr_range(connector, fixed_mode_vrefresh) &&
> + fixed_mode_vrefresh < vrefresh)
> + return false;
> +
> + /* pick the fixed_mode that is closest in terms of vrefresh */
> + return abs(fixed_mode_vrefresh - vrefresh) <
> + abs(drm_mode_vrefresh(best_mode) - vrefresh); }
> +
> const struct drm_display_mode *
> intel_panel_fixed_mode(struct intel_connector *connector,
> const struct drm_display_mode *mode) @@ -65,11
> +98,11 @@ intel_panel_fixed_mode(struct intel_connector *connector,
> const struct drm_display_mode *fixed_mode, *best_mode = NULL;
> int vrefresh = drm_mode_vrefresh(mode);
>
> - /* pick the fixed_mode that is closest in terms of vrefresh */
> list_for_each_entry(fixed_mode, >panel.fixed_modes,
> head) {
> - if (!best_mode ||
> - abs(drm_mode_vrefresh(fixed_mode) - vrefresh) <
> - abs(drm_mode_vrefresh(best_mode) - vrefresh))
> + int fixed_mode_vrefresh =
> drm_mode_vrefresh(fixed_mode);
> +
> + if (is_best_fixed_mode(connector, vrefresh,
> +fixed_mode_vrefresh, best_mode))
> best_mode = fixed_mode;
> }
>
> @@ -178,27 +211,46 @@ int intel_panel_compute_config(struct
> intel_connector *connector, {
> const struct drm_display_mode *fixed_mode =
> intel_panel_fixed_mode(connector, adjusted_mode);
> + int vrefresh, fixed_mode_vrefresh;
> + bool is_vrr;
>
> if (!fixed_mode)
> return 0;
>
> + vrefresh = drm_mode_vrefresh(adjusted_mode);
> + fixed_mode_vrefresh = drm_mode_vrefresh(fixed_mode);
> +
> /*
> - * We don't want to lie too much to the user about the refresh
> - * rate they're going to get. But we have to allow a bit of latitude
> - * for Xorg since it likes to automagically cook up modes with slightly
> - * off refresh rates.
> + * Assume that we shouldn't muck about with the
> + * timings if they don't land in the VRR range.
>*/
> - if (abs(drm_mode_vrefresh(adjusted_mode) -
> drm_mode_vrefresh(fixed_mode)) > 1) {
> - drm_dbg_kms(connector->base.dev,
> - "[CONNECTOR:%d:%s] Requested mode vrefresh
> (%d Hz) does not match fixed mode vrefresh (%d Hz)\n",
> - connector->base.base.id, connector->base.name,
> -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/aux: clean up aux name initialization
== Series Details == Series: drm/i915/aux: clean up aux name initialization URL : https://patchwork.freedesktop.org/series/116436/ State : success == Summary == CI Bug Log - changes from CI_DRM_13003 -> Patchwork_116436v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/index.html Participating hosts (36 -> 36) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_116436v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html - fi-apl-guc: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adlp-9: NOTRUN -> [SKIP][8] ([i915#7828]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/bat-adlp-9/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1: - bat-dg2-8: [PASS][9] -> [FAIL][10] ([i915#7932]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html Possible fixes * igt@i915_selftest@live@uncore: - bat-adlp-9: [ABORT][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-adlp-9/igt@i915_selftest@l...@uncore.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/bat-adlp-9/igt@i915_selftest@l...@uncore.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][13] ([i915#6367]) -> [DMESG-FAIL][14] ([i915#6367] / [i915#7996]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-1/igt@i915_selftest@l...@slpc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 Build changes - * Linux: CI_DRM_13003 -> Patchwork_116436v1 CI-20190529: 20190529 CI_DRM_13003: 9452fe4b47da924d60188cd39d263e5a980db5df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7254: 7fab01340a3f360abacd7914015be1ad485363d7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116436v1: 9452fe4b47da924d60188cd39d263e5a980db5df @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits a01481818bdf drm/i915/aux: clean up aux name initialization == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116436v1/index.html
Re: [Intel-gfx] [PATCH 10/10] drm/i915/display: add intel_display_driver_early_probe()
Quoting Jani Nikula (2023-04-13 06:47:36)
> Add intel_display_driver_early_probe() as the early probe call to
> replace intel_init_display_hooks(). The latter will be "demoted" to
> setting up hooks in intel_display.c only.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 ---
> .../gpu/drm/i915/display/intel_display_driver.c| 14 ++
> .../gpu/drm/i915/display/intel_display_driver.h| 1 +
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> 4 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9eb9898885bb..afc5bc38d006 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8005,15 +8005,6 @@ static const struct intel_display_funcs
> i9xx_display_funcs = {
> */
> void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> {
> - if (!HAS_DISPLAY(dev_priv))
> - return;
> -
> - intel_color_init_hooks(dev_priv);
> - intel_init_cdclk_hooks(dev_priv);
> - intel_audio_hooks_init(dev_priv);
> -
> - intel_dpll_init_clock_hook(dev_priv);
> -
> if (DISPLAY_VER(dev_priv) >= 9) {
> dev_priv->display.funcs.display = _display_funcs;
> } else if (HAS_DDI(dev_priv)) {
> @@ -8026,8 +8017,6 @@ void intel_init_display_hooks(struct drm_i915_private
> *dev_priv)
> } else {
> dev_priv->display.funcs.display = _display_funcs;
> }
> -
> - intel_fdi_init_hook(dev_priv);
> }
>
> int intel_initial_commit(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index d20a279fdf51..b3dbfe2a892e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -32,6 +32,7 @@
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> #include "intel_dp.h"
> +#include "intel_dpll.h"
> #include "intel_dpll_mgr.h"
> #include "intel_fb.h"
> #include "intel_fbc.h"
> @@ -169,6 +170,19 @@ static void intel_plane_possible_crtcs_init(struct
> drm_i915_private *dev_priv)
> }
> }
>
> +void intel_display_driver_early_probe(struct drm_i915_private *i915)
> +{
> + if (!HAS_DISPLAY(i915))
> + return;
> +
> + intel_color_init_hooks(i915);
> + intel_init_cdclk_hooks(i915);
> + intel_audio_hooks_init(i915);
> + intel_dpll_init_clock_hook(i915);
> + intel_init_display_hooks(i915);
> + intel_fdi_init_hook(i915);
> +}
> +
> /* part #1: call before irq install */
> int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h
> b/drivers/gpu/drm/i915/display/intel_display_driver.h
> index 84e7977f265a..c276a58ee329 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> @@ -15,6 +15,7 @@ struct pci_dev;
>
> bool intel_display_driver_probe_defer(struct pci_dev *pdev);
> void intel_display_driver_init_hw(struct drm_i915_private *i915);
> +void intel_display_driver_early_probe(struct drm_i915_private *i915);
> int intel_display_driver_probe_noirq(struct drm_i915_private *i915);
> int intel_display_driver_probe_nogem(struct drm_i915_private *i915);
> int intel_display_driver_probe(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index 082393ea3833..8a0a893443b4 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -252,7 +252,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> intel_detect_pch(dev_priv);
>
> intel_irq_init(dev_priv);
> - intel_init_display_hooks(dev_priv);
> + intel_display_driver_early_probe(dev_priv);
> intel_clock_gating_hooks_init(dev_priv);
>
> intel_detect_preproduction_hw(dev_priv);
> --
> 2.39.2
>
Re: [Intel-gfx] [PATCH 09/10] drm/i915/display: rename intel_display_driver_suspend/resume functions
Quoting Jani Nikula (2023-04-13 06:47:35)
> Follow the usual naming conventions. Switch to i915 arguments and naming
> while at it.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> .../drm/i915/display/intel_display_driver.c | 24 +--
> .../drm/i915/display/intel_display_driver.h | 11 -
> .../drm/i915/display/intel_display_reset.c| 2 +-
> drivers/gpu/drm/i915/i915_driver.c| 6 ++---
> 4 files changed, 20 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index eb03b0a87d5a..d20a279fdf51 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -471,29 +471,28 @@ void intel_display_driver_unregister(struct
> drm_i915_private *i915)
> * turn all crtc's off, but do not adjust state
> * This has to be paired with a call to intel_modeset_setup_hw_state.
> */
> -int intel_display_suspend(struct drm_device *dev)
> +int intel_display_driver_suspend(struct drm_i915_private *i915)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_atomic_state *state;
> int ret;
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(i915))
> return 0;
>
> - state = drm_atomic_helper_suspend(dev);
> + state = drm_atomic_helper_suspend(>drm);
> ret = PTR_ERR_OR_ZERO(state);
> if (ret)
> - drm_err(_priv->drm, "Suspending crtc's failed with %i\n",
> + drm_err(>drm, "Suspending crtc's failed with %i\n",
> ret);
> else
> - dev_priv->display.restore.modeset_state = state;
> + i915->display.restore.modeset_state = state;
> return ret;
> }
>
> int
> -__intel_display_resume(struct drm_i915_private *i915,
> - struct drm_atomic_state *state,
> - struct drm_modeset_acquire_ctx *ctx)
> +__intel_display_driver_resume(struct drm_i915_private *i915,
> +struct drm_atomic_state *state,
> +struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_crtc_state *crtc_state;
> struct drm_crtc *crtc;
> @@ -530,9 +529,8 @@ __intel_display_resume(struct drm_i915_private *i915,
> return ret;
> }
>
> -void intel_display_resume(struct drm_device *dev)
> +void intel_display_driver_resume(struct drm_i915_private *i915)
> {
> - struct drm_i915_private *i915 = to_i915(dev);
> struct drm_atomic_state *state = i915->display.restore.modeset_state;
> struct drm_modeset_acquire_ctx ctx;
> int ret;
> @@ -547,7 +545,7 @@ void intel_display_resume(struct drm_device *dev)
> drm_modeset_acquire_init(, 0);
>
> while (1) {
> - ret = drm_modeset_lock_all_ctx(dev, );
> + ret = drm_modeset_lock_all_ctx(>drm, );
> if (ret != -EDEADLK)
> break;
>
> @@ -555,7 +553,7 @@ void intel_display_resume(struct drm_device *dev)
> }
>
> if (!ret)
> - ret = __intel_display_resume(i915, state, );
> + ret = __intel_display_driver_resume(i915, state, );
>
> skl_watermark_ipc_update(i915);
> drm_modeset_drop_locks();
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h
> b/drivers/gpu/drm/i915/display/intel_display_driver.h
> index 7b5ff4309dec..84e7977f265a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> @@ -9,7 +9,6 @@
> #include
>
> struct drm_atomic_state;
> -struct drm_device;
> struct drm_i915_private;
> struct drm_modeset_acquire_ctx;
> struct pci_dev;
> @@ -24,13 +23,13 @@ void intel_display_driver_remove(struct drm_i915_private
> *i915);
> void intel_display_driver_remove_noirq(struct drm_i915_private *i915);
> void intel_display_driver_remove_nogem(struct drm_i915_private *i915);
> void intel_display_driver_unregister(struct drm_i915_private *i915);
> -int intel_display_suspend(struct drm_device *dev);
> -void intel_display_resume(struct drm_device *dev);
> +int intel_display_driver_suspend(struct drm_i915_private *i915);
> +void intel_display_driver_resume(struct drm_i915_private *i915);
>
> /* interface for intel_display_reset.c */
> -int __intel_display_resume(struct drm_i915_private *i915,
> - struct drm_atomic_state *state,
> - struct drm_modeset_acquire_ctx *ctx);
> +int __intel_display_driver_resume(struct drm_i915_private *i915,
> +struct drm_atomic_state *state,
> +struct drm_modeset_acquire_ctx *ctx);
>
> #endif /* __INTEL_DISPLAY_DRIVER_H__ */
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c
> b/drivers/gpu/drm/i915/display/intel_display_reset.c
> index 166aa0cab1fc..17178d5d7788
Re: [Intel-gfx] [PATCH 08/10] drm/i915/display: move display suspend/resume to intel_display_driver.[ch]
Quoting Jani Nikula (2023-04-13 06:47:34)
> High level display functionality only called from driver top level code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 102 --
> drivers/gpu/drm/i915/display/intel_display.h | 8 --
> .../drm/i915/display/intel_display_driver.c | 101 +
> .../drm/i915/display/intel_display_driver.h | 10 ++
> 4 files changed, 111 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e89e9473a744..9eb9898885bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -693,46 +693,6 @@ intel_plane_fence_y_offset(const struct
> intel_plane_state *plane_state)
> return y;
> }
>
> -int
> -__intel_display_resume(struct drm_i915_private *i915,
> - struct drm_atomic_state *state,
> - struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct drm_crtc_state *crtc_state;
> - struct drm_crtc *crtc;
> - int ret, i;
> -
> - intel_modeset_setup_hw_state(i915, ctx);
> - intel_vga_redisable(i915);
> -
> - if (!state)
> - return 0;
> -
> - /*
> - * We've duplicated the state, pointers to the old state are invalid.
> - *
> - * Don't attempt to use the old state until we commit the duplicated state.
> - */
> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - /*
> - * Force recalculation even if we restore
> - * current state. With fast modeset this may not result
> - * in a modeset when the state is compatible.
> - */
> - crtc_state->mode_changed = true;
> - }
> -
> - /* ignore any reset values/BIOS leftovers in the WM registers */
> - if (!HAS_GMCH(i915))
> - to_intel_atomic_state(state)->skip_intermediate_wm = true;
> -
> - ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
> -
> - drm_WARN_ON(>drm, ret == -EDEADLK);
> -
> - return ret;
> -}
> -
> static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -2104,30 +2064,6 @@ static void i9xx_crtc_disable(struct
> intel_atomic_state *state,
> i830_enable_pipe(dev_priv, pipe);
> }
>
> -
> -/*
> - * turn all crtc's off, but do not adjust state
> - * This has to be paired with a call to intel_modeset_setup_hw_state.
> - */
> -int intel_display_suspend(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state;
> - int ret;
> -
> - if (!HAS_DISPLAY(dev_priv))
> - return 0;
> -
> - state = drm_atomic_helper_suspend(dev);
> - ret = PTR_ERR_OR_ZERO(state);
> - if (ret)
> - drm_err(_priv->drm, "Suspending crtc's failed with %i\n",
> - ret);
> - else
> - dev_priv->display.restore.modeset_state = state;
> - return ret;
> -}
> -
> void intel_encoder_destroy(struct drm_encoder *encoder)
> {
> struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
> @@ -8280,44 +8216,6 @@ void i830_disable_pipe(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> intel_de_posting_read(dev_priv, DPLL(pipe));
> }
>
> -void intel_display_resume(struct drm_device *dev)
> -{
> - struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_atomic_state *state = i915->display.restore.modeset_state;
> - struct drm_modeset_acquire_ctx ctx;
> - int ret;
> -
> - if (!HAS_DISPLAY(i915))
> - return;
> -
> - i915->display.restore.modeset_state = NULL;
> - if (state)
> - state->acquire_ctx =
> -
> - drm_modeset_acquire_init(, 0);
> -
> - while (1) {
> - ret = drm_modeset_lock_all_ctx(dev, );
> - if (ret != -EDEADLK)
> - break;
> -
> - drm_modeset_backoff();
> - }
> -
> - if (!ret)
> - ret = __intel_display_resume(i915, state, );
> -
> - skl_watermark_ipc_update(i915);
> - drm_modeset_drop_locks();
> - drm_modeset_acquire_fini();
> -
> - if (ret)
> - drm_err(>drm,
> - "Restoring old state failed with %i\n", ret);
> - if (state)
> - drm_atomic_state_put(state);
> -}
> -
> void intel_hpd_poll_fini(struct drm_i915_private *i915)
> {
> struct intel_connector *connector;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index e5bf8ef8e06b..c7b1e220e84d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -438,7 +438,6 @@ void intel_add_fb_offsets(int *x, int *y,
> unsigned int intel_rotation_info_size(const struct intel_rotation_info
> *rot_info);
> unsigned int intel_remapped_info_size(const struct intel_remapped_info
> *rem_info);
> bool
Re: [Intel-gfx] [PATCH 07/10] drm/i915/display: add intel_display_reset.[ch]
Quoting Jani Nikula (2023-04-13 06:47:33)
> Split out the display reset functionality to a separate file to
> declutter intel_display.c. Rename the functions accordingly. The minor
> downside is having to expose __intel_display_resume().
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 123 +---
> drivers/gpu/drm/i915/display/intel_display.h | 8 +-
> .../drm/i915/display/intel_display_reset.c| 135 ++
> .../drm/i915/display/intel_display_reset.h| 14 ++
> drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-
> 6 files changed, 160 insertions(+), 127 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_reset.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_reset.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 91f0c214ef28..39e22cf85e55 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -241,6 +241,7 @@ i915-y += \
> display/intel_display_power.o \
> display/intel_display_power_map.o \
> display/intel_display_power_well.o \
> + display/intel_display_reset.o \
> display/intel_display_rps.o \
> display/intel_dmc.o \
> display/intel_dpio_phy.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f425e5ed155b..e89e9473a744 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -693,7 +693,7 @@ intel_plane_fence_y_offset(const struct intel_plane_state
> *plane_state)
> return y;
> }
>
> -static int
> +int
> __intel_display_resume(struct drm_i915_private *i915,
>struct drm_atomic_state *state,
>struct drm_modeset_acquire_ctx *ctx)
> @@ -733,127 +733,6 @@ __intel_display_resume(struct drm_i915_private *i915,
> return ret;
> }
>
> -static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
> -{
> - return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
> - intel_has_gpu_reset(to_gt(dev_priv)));
> -}
> -
> -void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
> -{
> - struct drm_modeset_acquire_ctx *ctx = _priv->display.restore.reset_ctx;
> - struct drm_atomic_state *state;
> - int ret;
> -
> - if (!HAS_DISPLAY(dev_priv))
> - return;
> -
> - /* reset doesn't touch the display */
> - if (!dev_priv->params.force_reset_modeset_test &&
> - !gpu_reset_clobbers_display(dev_priv))
> - return;
> -
> - /* We have a modeset vs reset deadlock, defensively unbreak it. */
> - set_bit(I915_RESET_MODESET, _gt(dev_priv)->reset.flags);
> - smp_mb__after_atomic();
> - wake_up_bit(_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
> -
> - if (atomic_read(_priv->gpu_error.pending_fb_pin)) {
> - drm_dbg_kms(_priv->drm,
> - "Modeset potentially stuck, unbreaking through
> wedging\n");
> - intel_gt_set_wedged(to_gt(dev_priv));
> - }
> -
> - /*
> - * Need mode_config.mutex so that we don't
> - * trample ongoing ->detect() and whatnot.
> - */
> - mutex_lock(_priv->drm.mode_config.mutex);
> - drm_modeset_acquire_init(ctx, 0);
> - while (1) {
> - ret = drm_modeset_lock_all_ctx(_priv->drm, ctx);
> - if (ret != -EDEADLK)
> - break;
> -
> - drm_modeset_backoff(ctx);
> - }
> - /*
> - * Disabling the crtcs gracefully seems nicer. Also the
> - * g33 docs say we should at least disable all the planes.
> - */
> - state = drm_atomic_helper_duplicate_state(_priv->drm, ctx);
> - if (IS_ERR(state)) {
> - ret = PTR_ERR(state);
> - drm_err(_priv->drm, "Duplicating state failed with %i\n",
> - ret);
> - return;
> - }
> -
> - ret = drm_atomic_helper_disable_all(_priv->drm, ctx);
> - if (ret) {
> - drm_err(_priv->drm, "Suspending crtc's failed with %i\n",
> - ret);
> - drm_atomic_state_put(state);
> - return;
> - }
> -
> - dev_priv->display.restore.modeset_state = state;
> - state->acquire_ctx = ctx;
> -}
> -
> -void intel_display_finish_reset(struct drm_i915_private *i915)
> -{
> - struct drm_modeset_acquire_ctx *ctx = >display.restore.reset_ctx;
> - struct drm_atomic_state *state;
> - int ret;
> -
> - if (!HAS_DISPLAY(i915))
> - return;
> -
> - /* reset doesn't touch the display */
> - if (!test_bit(I915_RESET_MODESET, _gt(i915)->reset.flags))
> - return;
> -
> - state = fetch_and_zero(>display.restore.modeset_state);
> - if (!state)
> - goto unlock;
> -
> - /* reset doesn't touch the display */
> - if (!gpu_reset_clobbers_display(i915)) {
> - /* for testing only restore the display */
> - ret =
Re: [Intel-gfx] [PATCH 04/10] drm/i915/display: rename intel_modeset_probe_defer() -> intel_display_driver_probe_defer()
Quoting Jani Nikula (2023-04-13 06:47:30)
> Follow the usual naming conventions.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_display_driver.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_driver.h | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 1386f2001613..882a2586aba4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -21,7 +21,7 @@
> #include "intel_fbdev.h"
> #include "intel_opregion.h"
>
> -bool intel_modeset_probe_defer(struct pci_dev *pdev)
> +bool intel_display_driver_probe_defer(struct pci_dev *pdev)
> {
> struct drm_privacy_screen *privacy_screen;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h
> b/drivers/gpu/drm/i915/display/intel_display_driver.h
> index 4c18792fcafd..744117b04ed4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> @@ -11,7 +11,7 @@
> struct drm_i915_private;
> struct pci_dev;
>
> -bool intel_modeset_probe_defer(struct pci_dev *pdev);
> +bool intel_display_driver_probe_defer(struct pci_dev *pdev);
> void intel_display_driver_register(struct drm_i915_private *i915);
> void intel_display_driver_unregister(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bda5caa33f12..d64e074d7457 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1355,7 +1355,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const
> struct pci_device_id *ent)
> return -ENXIO;
>
> /* Detect if we need to wait for other drivers early on */
> - if (intel_modeset_probe_defer(pdev))
> + if (intel_display_driver_probe_defer(pdev))
> return -EPROBE_DEFER;
>
> err = i915_driver_probe(pdev, ent);
> --
> 2.39.2
>
Re: [Intel-gfx] [PATCH 03/10] drm/i915/display: move intel_modeset_probe_defer() to intel_display_driver.[ch]
Quoting Jani Nikula (2023-04-13 06:47:29)
> High level display functionality only called from driver top level code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 23 ---
> drivers/gpu/drm/i915/display/intel_display.h | 1 -
> .../drm/i915/display/intel_display_driver.c | 23 +++
> .../drm/i915/display/intel_display_driver.h | 4
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> 5 files changed, 28 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7c66b9ce0db5..dfec17bb3a7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -31,7 +31,6 @@
> #include
> #include
> #include
> -#include
>
> #include
> #include
> @@ -40,7 +39,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
>
> @@ -8810,27 +8808,6 @@ void intel_modeset_driver_remove_nogem(struct
> drm_i915_private *i915)
> intel_bios_driver_remove(i915);
> }
>
> -bool intel_modeset_probe_defer(struct pci_dev *pdev)
> -{
> - struct drm_privacy_screen *privacy_screen;
> -
> - /*
> - * apple-gmux is needed on dual GPU MacBook Pro
> - * to probe the panel if we're the inactive GPU.
> - */
> - if (vga_switcheroo_client_probe_defer(pdev))
> - return true;
> -
> - /* If the LCD panel has a privacy-screen, wait for it */
> - privacy_screen = drm_privacy_screen_get(>dev, NULL);
> - if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
> - return true;
> -
> - drm_privacy_screen_put(privacy_screen);
> -
> - return false;
> -}
> -
> bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
> {
> return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index e46732d26b7c..6ff8faa1b5ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -521,7 +521,6 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state
> *crtc_state);
> void intel_update_watermarks(struct drm_i915_private *i915);
>
> /* modesetting */
> -bool intel_modeset_probe_defer(struct pci_dev *pdev);
> void intel_modeset_init_hw(struct drm_i915_private *i915);
> int intel_modeset_init_noirq(struct drm_i915_private *i915);
> int intel_modeset_init_nogem(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index d4a1893e9218..1386f2001613 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -7,8 +7,10 @@
> * details here.
> */
>
> +#include
> #include
> #include
> +#include
> #include
>
> #include "i915_drv.h"
> @@ -19,6 +21,27 @@
> #include "intel_fbdev.h"
> #include "intel_opregion.h"
>
> +bool intel_modeset_probe_defer(struct pci_dev *pdev)
> +{
> + struct drm_privacy_screen *privacy_screen;
> +
> + /*
> + * apple-gmux is needed on dual GPU MacBook Pro
> + * to probe the panel if we're the inactive GPU.
> + */
> + if (vga_switcheroo_client_probe_defer(pdev))
> + return true;
> +
> + /* If the LCD panel has a privacy-screen, wait for it */
> + privacy_screen = drm_privacy_screen_get(>dev, NULL);
> + if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
> + return true;
> +
> + drm_privacy_screen_put(privacy_screen);
> +
> + return false;
> +}
> +
> void intel_display_driver_register(struct drm_i915_private *i915)
> {
> if (!HAS_DISPLAY(i915))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h
> b/drivers/gpu/drm/i915/display/intel_display_driver.h
> index 4f6deef5a23f..4c18792fcafd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
> @@ -6,8 +6,12 @@
> #ifndef __INTEL_DISPLAY_DRIVER_H__
> #define __INTEL_DISPLAY_DRIVER_H__
>
> +#include
> +
> struct drm_i915_private;
> +struct pci_dev;
>
> +bool intel_modeset_probe_defer(struct pci_dev *pdev);
> void intel_display_driver_register(struct drm_i915_private *i915);
> void intel_display_driver_unregister(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index cddb6e197972..bda5caa33f12 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -27,6 +27,7 @@
> #include
>
> #include "display/intel_display.h"
> +#include "display/intel_display_driver.h"
> #include "gt/intel_gt_regs.h"
> #include "gt/intel_sa_media.h"
>
> --
> 2.39.2
>
Re: [Intel-gfx] [PATCH 02/10] drm/i915/display: start high level display driver file
Quoting Jani Nikula (2023-04-13 06:47:28)
> The only way to truly clean up intel_display.[ch] is to move stuff out
> of them until there's absolutely nothing left.
>
> Start moving the high level display driver entry points, i.e. functions
> called from top level driver code only, to a new file, which we'll call
> intel_display_driver.c. The intention is that there's no low-level
> display code or details here. This is an in-between layer.
>
> Initially, move intel_display_driver_register() and
> intel_display_driver_unregister() there.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 53 --
> drivers/gpu/drm/i915/display/intel_display.h | 3 -
> .../drm/i915/display/intel_display_driver.c | 71 +++
> .../drm/i915/display/intel_display_driver.h | 15
> drivers/gpu/drm/i915/i915_driver.c| 1 +
> 6 files changed, 88 insertions(+), 56 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_driver.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_driver.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 97b0d4ae221a..91f0c214ef28 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -237,6 +237,7 @@ i915-y += \
> display/intel_crtc_state_dump.o \
> display/intel_cursor.o \
> display/intel_display.o \
> + display/intel_display_driver.o \
> display/intel_display_power.o \
> display/intel_display_power_map.o \
> display/intel_display_power_well.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1c0149adcf49..7c66b9ce0db5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -32,7 +32,6 @@
> #include
> #include
> #include
> -#include
>
> #include
> #include
> @@ -70,7 +69,6 @@
> #include "intel_crtc_state_dump.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> -#include "intel_display_debugfs.h"
> #include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> @@ -8833,57 +8831,6 @@ bool intel_modeset_probe_defer(struct pci_dev *pdev)
> return false;
> }
>
> -void intel_display_driver_register(struct drm_i915_private *i915)
> -{
> - if (!HAS_DISPLAY(i915))
> - return;
> -
> - /* Must be done after probing outputs */
> - intel_opregion_register(i915);
> - intel_acpi_video_register(i915);
> -
> - intel_audio_init(i915);
> -
> - intel_display_debugfs_register(i915);
> -
> - /*
> - * Some ports require correctly set-up hpd registers for
> - * detection to work properly (leading to ghost connected
> - * connector status), e.g. VGA on gm45. Hence we can only set
> - * up the initial fbdev config after hpd irqs are fully
> - * enabled. We do it last so that the async config cannot run
> - * before the connectors are registered.
> - */
> - intel_fbdev_initial_config_async(i915);
> -
> - /*
> - * We need to coordinate the hotplugs with the asynchronous
> - * fbdev configuration, for which we use the
> - * fbdev->async_cookie.
> - */
> - drm_kms_helper_poll_init(>drm);
> -}
> -
> -void intel_display_driver_unregister(struct drm_i915_private *i915)
> -{
> - if (!HAS_DISPLAY(i915))
> - return;
> -
> - intel_fbdev_unregister(i915);
> - intel_audio_deinit(i915);
> -
> - /*
> - * After flushing the fbdev (incl. a late async config which
> - * will have delayed queuing of a hotplug event), then flush
> - * the hotplug events.
> - */
> - drm_kms_helper_poll_fini(>drm);
> - drm_atomic_helper_shutdown(>drm);
> -
> - acpi_video_unregister();
> - intel_opregion_unregister(i915);
> -}
> -
> bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
> {
> return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 287159bdeb0d..e46732d26b7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -518,9 +518,6 @@ void intel_set_plane_visible(struct intel_crtc_state
> *crtc_state,
> bool visible);
> void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
>
> -void intel_display_driver_register(struct drm_i915_private *i915);
> -void intel_display_driver_unregister(struct drm_i915_private *i915);
> -
> void intel_update_watermarks(struct drm_i915_private *i915);
>
> /* modesetting */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> new file mode 100644
> index ..d4a1893e9218
> --- /dev/null
> +++
Re: [Intel-gfx] [PATCH 9/9] drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
On Wed, Apr 12, 2023 at 03:49:25PM -0700, Radhakrishna Sripada wrote:
> From: Ankit Nautiyal
>
> MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
> to be filled with 4 lanes for TMDS mode.
> This patch enables D2D link and fills PORT_WIDTH in appropriate
> registers.
>
> v2:
> - Added fixes from Clint's Add HDMI implementation changes.
> - Modified commit message.
> v3:
> - Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
> of TRANS_DDI_FUNC_CTL_*. (Gustavo)
>
> Cc: Taylor, Clinton A
> Signed-off-by: Ankit Nautiyal
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9df3da46fdca..c5d210a6fb94 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -541,6 +541,8 @@ intel_ddi_transcoder_func_reg_val_get(struct
> intel_encoder *encoder,
> temp |= TRANS_DDI_HDMI_SCRAMBLING;
> if (crtc_state->hdmi_high_tmds_clock_ratio)
> temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
> + if (DISPLAY_VER(dev_priv) >= 14)
> + temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
> } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
> temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> temp |= (crtc_state->fdi_lanes - 1) << 1;
> @@ -3158,6 +3160,10 @@ static void intel_enable_ddi_hdmi(struct
> intel_atomic_state *state,
> if (has_buf_trans_select(dev_priv))
> hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
>
> + /* e. Enable D2D Link for C10/C20 Phy */
> + if (DISPLAY_VER(dev_priv) >= 14)
> + mtl_ddi_enable_d2d(encoder);
> +
> encoder->set_signal_levels(encoder, crtc_state);
>
> /* Display WA #1143: skl,kbl,cfl */
> @@ -3203,12 +3209,30 @@ static void intel_enable_ddi_hdmi(struct
> intel_atomic_state *state,
>*
>* On ADL_P the PHY link rate and lane count must be programmed but
>* these are both 0 for HDMI.
> + *
> + * But MTL onwards HDMI2.1 is supported and in TMDS mode this
> + * is filled with lane count, already set in the crtc_state.
> + * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
>*/
> buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> - if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> + u32 port_buf = 0;
> +
> + port_buf |= XELPDP_PORT_WIDTH(lane_count);
> +
> + if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> + port_buf |= XELPDP_PORT_REVERSAL;
> +
> + intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> + XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
> port_buf);
> +
> + buf_ctl |= DDI_PORT_WIDTH(lane_count);
> + } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> drm_WARN_ON(_priv->drm,
> !intel_tc_port_in_legacy_mode(dig_port));
> buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> }
> +
> intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
>
> intel_wait_ddi_buf_active(dev_priv, port);
> @@ -3669,7 +3693,11 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> fallthrough;
> case TRANS_DDI_MODE_SELECT_DVI:
> pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
> - pipe_config->lane_count = 4;
> + if (DISPLAY_VER(dev_priv) >= 14)
> + pipe_config->lane_count =
> + ((temp & DDI_PORT_WIDTH_MASK) >>
> DDI_PORT_WIDTH_SHIFT) + 1;
> + else
> + pipe_config->lane_count = 4;
> break;
> case TRANS_DDI_MODE_SELECT_DP_SST:
> if (encoder->type == INTEL_OUTPUT_EDP)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d917353d4161..2f0371f8bcf0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5596,6 +5596,8 @@ enum skl_power_gate {
> #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> #define TRANS_DDI_BFI_ENABLE(1 << 4)
> #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> +#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define TRANS_DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
> #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> #define
Re: [Intel-gfx] [PATCH 3/9] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
On Wed, Apr 12, 2023 at 03:49:19PM -0700, Radhakrishna Sripada wrote:
> [...]
> @@ -980,21 +981,38 @@ static int hsw_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> int ret;
>
> ret = intel_mpllb_calc_state(crtc_state, encoder);
> if (ret)
> return ret;
>
> + /* TODO: Do the readback via intel_compute_shared_dplls() */
> + if (intel_is_c10phy(i915, phy))
> + crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder,
> _state->cx0pll_state.c10);
> +
Added to the wrong function.
> crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
The above is also missing for mtl.
>
> return 0;
> }
>
> +static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
> +
> + return intel_cx0pll_calc_state(crtc_state, encoder);
> +}
> +
>
> [...]
>
> +/**
> + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to put in the field
> + *
> + * Local copy of FIELD_PREP8() to generate an integer constant expression,
> force
Local copy of FIELD_PREP()
> + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and
> REG_GENMASK8().
> + *
> + * @return: @__val masked and shifted into the field defined by @__mask.
> + */
> +#define REG_FIELD_PREP8(__mask, __val)
>\
> + ((u8)typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +
> \
> +BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> +BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) +
> \
> +BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask + \
> +BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> (~((__mask) >> __bf_shf(__mask)) & (__val)), 0
> +
> /**
> * REG_FIELD_GET() - Extract a u32 bitfield value
> * @__mask: shifted mask defining the field's length and position
> @@ -155,6 +200,18 @@
> */
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
[Intel-gfx] [PATCH v2 7/7] drm/i915: Do state check for color management changes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.39.2
[Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up the necessary stuff to expose the WGC as the CTM
crtc property.
One additional crazy idea that came to mind would be to use
the WGC as an output CSC on CHV for YCbCr output. But it
would be incompatible with the legacy LUT usage. In fact
since the WGC lacks post-offsets we'd probably have to
use the legacy LUT to do that final part of the RGB->YCbCr
conversion. Sounds doable, but perhaps not worth the hassle.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c| 170 +-
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/i915_reg.h | 15 ++
5 files changed, 198 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 7a705e7d8776..e36d8c248b84 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits,
int frac_bits)
return c & (BIT(int_bits + frac_bits) - 1);
}
+/*
+ * VLV/CHV Wide Gamut Color Correction (WGC) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s2.10.
+ */
+static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
+ struct intel_csc_matrix *csc)
+{
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
+ int i;
+
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10);
+}
+
+static void vlv_load_wgc_csc(struct intel_crtc *crtc,
+const struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
+ csc->coeff[1] << 16 | csc->coeff[0]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
+ csc->coeff[2]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
+ csc->coeff[4] << 16 | csc->coeff[3]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
+ csc->coeff[5]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
+ csc->coeff[7] << 16 | csc->coeff[6]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
+ csc->coeff[8]);
+}
+
+static void vlv_read_wgc_csc(struct intel_crtc *crtc,
+struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
+ csc->coeff[0] = tmp & 0x;
+ csc->coeff[1] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
+ csc->coeff[2] = tmp & 0x;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
+ csc->coeff[3] = tmp & 0x;
+ csc->coeff[4] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
+ csc->coeff[5] = tmp & 0x;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
+ csc->coeff[6] = tmp & 0x;
+ csc->coeff[7] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
+ csc->coeff[8] = tmp & 0x;
+}
+
+static void vlv_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->wgc_enable)
+ vlv_read_wgc_csc(crtc, _state->csc);
+}
+
+static void vlv_assign_csc(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (crtc_state->hw.ctm) {
+ drm_WARN_ON(>drm, !crtc_state->wgc_enable);
+
+ vlv_wgc_csc_convert_ctm(crtc_state, _state->csc);
+ } else {
+ drm_WARN_ON(>drm, crtc_state->wgc_enable);
+
+ intel_csc_clear(_state->csc);
+ }
+}
+
/*
* CHV Color Gamut Mapping (CGM) CSC
* |r| | c0 c1 c2 | |r|
@@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ drm_WARN_ON(>drm, crtc_state->wgc_enable);
+
if (crtc_state->hw.ctm) {
drm_WARN_ON(>drm, (crtc_state->cgm_mode &
CGM_PIPE_MODE_CSC)
[Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 46 ++
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 4fc16cac052d..63141f4ed372 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
intel_crtc_state *crtc_state)
icl_update_output_csc(crtc, _state->output_csc);
}
+static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
+{
+ s64 c = CTM_COEFF_ABS(coeff);
+
+ /* leave an extra bit for rounding */
+ c >>= 32 - frac_bits - 1;
+
+ /* round and drop the extra bit */
+ c = (c + 1) >> 1;
+
+ if (CTM_COEFF_NEGATIVE(coeff))
+ c = -c;
+
+ c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
+ (s64)(BIT(int_bits + frac_bits - 1) - 1));
+
+ return c & (BIT(int_bits + frac_bits) - 1);
+}
+
+/*
+ * CHV Color Gamut Mapping (CGM) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s4.12.
+ */
static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
struct intel_csc_matrix *csc)
{
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
int i;
- for (i = 0; i < 9; i++) {
- u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
-
- /* Round coefficient. */
- abs_coeff += 1 << (32 - 13);
- /* Clamp to hardware limits. */
- abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
- csc->coeff[i] = 0;
-
- /* Write coefficients in S3.12 format. */
- if (ctm->matrix[i] & (1ULL << 63))
- csc->coeff[i] |= 1 << 15;
-
- csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
- csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
- }
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
--
2.39.2
[Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
From: Ville Syrjälä
On CHV toggling the CGM CSC on/off while the pipe is running leads
to underruns. Looks like we'd have to do the toggling strictly inside
the start_of_vblank-frame_start window to avoid this, but that window
is less than a scanline so there's no way we can guarantee hitting it.
As a workaround let's just leave the CGM CSC permanently enabled.
Fortunately the CGM gamma/degamma units don't seem to suffer from
this malady.
I also tried turning off CGM unit clock gating, but that did not
help.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 63141f4ed372..7a705e7d8776 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct
intel_crtc_state *crtc_state,
csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
+#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
+
+static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
+ .coeff = {
+ CHV_CGM_CSC_COEFF_1_0, 0, 0,
+ 0, CHV_CGM_CSC_COEFF_1_0, 0,
+ 0, 0, CHV_CGM_CSC_COEFF_1_0,
+ },
+};
+
static void chv_load_cgm_csc(struct intel_crtc *crtc,
const struct intel_csc_matrix *csc)
{
@@ -667,9 +677,9 @@ static void chv_assign_csc(struct intel_crtc_state
*crtc_state)
chv_cgm_csc_convert_ctm(crtc_state, _state->csc);
} else {
- drm_WARN_ON(>drm, (crtc_state->cgm_mode &
CGM_PIPE_MODE_CSC) != 0);
+ drm_WARN_ON(>drm, (crtc_state->cgm_mode &
CGM_PIPE_MODE_CSC) == 0);
- intel_csc_clear(_state->csc);
+ crtc_state->csc = chv_cgm_csc_matrix_identity;
}
}
@@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
*crtc_state)
!lut_is_legacy(crtc_state->hw.gamma_lut))
cgm_mode |= CGM_PIPE_MODE_GAMMA;
+ /*
+* Toggling the CGM CSC on/off outside of the tiny window
+* between start of vblank and frame start causes underruns.
+* Always enable the CGM CSC as a workaround.
+*/
+ cgm_mode |= CGM_PIPE_MODE_CSC;
+
return cgm_mode;
}
--
2.39.2
[Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but generally
the desktop PNV variant looks more like a mobile part so
this is not entirely surprising.
Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cddb6e197972..305c05c3f93b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
.dma_mask_size = 32, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
+ I845_COLORS,
.has_coherent_ggtt = false,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = {
static const struct intel_device_info i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = {
static const struct intel_device_info i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = {
static const struct intel_device_info i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
@@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = {
static const struct intel_device_info g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = {
static const struct intel_device_info pnv_g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = {
static const struct intel_device_info pnv_m_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.has_overlay = 1,
--
2.39.2
[Intel-gfx] [PATCH v2 1/7] drm/uapi: Document CTM matrix better
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -834,6 +834,11 @@ struct drm_color_ctm {
/*
* Conversion matrix in S31.32 sign-magnitude
* (not two's complement!) format.
+*
+* out matrixin
+* |R| |0 1 2| |R|
+* |G| = |3 4 5| x |G|
+* |B| |6 7 8| |B|
*/
__u64 matrix[9];
};
--
2.39.2
[Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
From: Ville Syrjälä The ilk/snb code is internally fully capable of handling the CTM property, so expose it. Note that we still choose not to expose DEGAMMA_LUT though. The hardware is capable if degamma or gamma, but not both similtanously due to lack of the split gamma mode. Exposing both LUTs might encourage userspace to try enabling both at the same time. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 07f1afe1d406..4fc16cac052d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc) gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; - has_ctm = degamma_lut_size != 0; + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915); /* * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the -- 2.39.2
[Intel-gfx] [PATCH v2 0/7] drm/i915: CTM stuff mostly
From: Ville Syrjälä Mostly some CTM stuff: - document the uapi better - fix CHV CSC negative coefficients - expose CTM on ilk/snb/vlv - a bonus gamma patch for gen3 - cure CGM CSC underruns on CHV (new in v2) Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com Ville Syrjälä (7): drm/uapi: Document CTM matrix better drm/i915: Expose crtc CTM property on ilk/snb drm/i915: Fix CHV CGM CSC coefficient sign handling drm/i915: Always enable CGM CSC on CHV drm/i915: Implement CTM property support for VLV drm/i915: No 10bit gamma on desktop gen3 parts drm/i915: Do state check for color management changes drivers/gpu/drm/i915/display/intel_color.c| 237 -- .../drm/i915/display/intel_crtc_state_dump.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 8 + .../drm/i915/display/intel_display_types.h| 3 + .../drm/i915/display/intel_modeset_verify.c | 2 + drivers/gpu/drm/i915/i915_pci.c | 8 +- drivers/gpu/drm/i915/i915_reg.h | 15 ++ include/uapi/drm/drm_mode.h | 5 + 8 files changed, 260 insertions(+), 24 deletions(-) -- 2.39.2
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On Thu, Apr 13, 2023 at 06:19:16PM +0200, Andi Shyti wrote:
> On Thu, Apr 13, 2023 at 09:03:29AM -0700, Ceraolo Spurio, Daniele wrote:
> >
> >
> > On 4/13/2023 8:52 AM, Matt Roper wrote:
> > > On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote:
> > > > Hi Tvrtko,
> > > >
> > > > (I forgot to CC Daniele)
> > > >
> > > > On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote:
> > > > > On 13/04/2023 10:20, Andi Shyti wrote:
> > > > > > From: Paulo Zanoni
> > > > > >
> > > > > > In multitile systems IRQ need to be reset and enabled per GT.
> > > > > >
> > > > > > Although in MTL the GUnit misc interrupts register set are
> > > > > > available only in GT-0, we need to loop through all the GT's
> > > > > > in order to initialize the media engine which lies on a different
> > > > > > GT.
> > > > > >
> > > > > > Signed-off-by: Paulo Zanoni
> > > > > > Cc: Tvrtko Ursulin
> > > > > > Signed-off-by: Andi Shyti
> > > > > > ---
> > > > > > Hi,
> > > > > >
> > > > > > proposing again this patch, apparently GuC needs this patch to
> > > > > > initialize the media GT.
> > > > > What is the resolution for Matt's concern that this is wrong for MTL?
> > > > There are two explanations, one easy and one less easy.
> > > >
> > > > The easy one: without this patch i915 doesn't boot on MTL!(*)
> > > >
> > > > The second explanation is that in MTL the media engine has it's
> > > > own set of misc irq's registers and those are on a different GT
> > > > (Daniele pointed this out).
> > > Assuming you're talking about MTL_GUC_MGUC_INTR_MASK, that's not true;
> > > it's just a single sgunit register (0x1900e8) that has different
> > > bitfields for the primary GuC and the media GuC. So I still think we
> > > should avoid looping over GTs; it's actually much simpler to handle
> > > things in a single pass since we can just determine the single register
> > > value once (all fields) and write it directly, instead of doing two
> > > separate RMW updates to the same register to try to avoid clobbering
> > > the other GuC's settings.
>
> if we handle exceptions in a single pass wouldn't we have many
> exceptions to handle in the long run?
I don't think so, it basically boils down to something along the lines
of
if (MEDIA_VER(i915) >= 13)
val = HIGH_BITS | LOW_BITS;
else
val = HIGH_BITS;
...
intel_uncore_write(val);
which isn't really any more complicated than today's logic:
called for each gt {
...
if (gt is MEDIA)
bits = LOW_BITS;
else
bits = HIGH_BITS;
...
intel_uncore_rmw(bits);
}
Matt
>
> > > For pre-MTL platforms, it's the same register, except that the bitfield
> > > now devoted to the media GuC was previously used for something else
> > > (scatter/gather).
> >
> > It's not just the GuC, the VCS/VECS engine programming is also tied to the
> > media GT (via the HAS_ENGINE checks). It looks like we unconditionally
> > program VCS 0 and 2, so it'll still work for MTL, but if we get a device
> > with more VCS engines it'll break. Maybe we can add a MTL version of the
> > function that just programs everything unconditionally? Going forward it
> > should be ok to program things for engines that don't exist, but I'm not
> > sure we can do that for older platforms that came before the extra engines
> > were ever defined in HW.
>
> This is more or less what Tvrtko has suggested, as well. Looks to
> me like replicating some code... anyway, I will try and see how
> it looks like.
>
> Andi
>
> PS Thanks Matt, Daniele and Tvrtko for the feedback.
>
> > Daniele
> >
> > >
> > >
> > > Matt
> > >
> > > > I sent this patch not to bypass any review, but to restart the
> > > > discussion as this patch was just dropped.
> > > >
> > > > Thanks,
> > > > Andi
> > > >
> > > >
> > > > (*)
> > > > [drm] *ERROR* GT1: GUC: CT: No response for request 0x550a (fence 7)
> > > > [drm] *ERROR* GT1: GUC: CT: Sending action 0x550a failed (-ETIMEDOUT)
> > > > status=0X0
> > > > [drm] *ERROR* GT1: GUC: Failed to enable usage stats: -ETIMEDOUT
> > > > [drm] *ERROR* GT1: GuC initialization failed -ETIMEDOUT
> > > > [drm] *ERROR* GT1: Enabling uc failed (-5)
> > > > [drm] *ERROR* GT1: Failed to initialize GPU, declaring it wedged!
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 8/9] drm/i915/mtl: Add C10 phy programming for HDMI
On Wed, Apr 12, 2023 at 03:49:24PM -0700, Radhakrishna Sripada wrote:
> [...]
> +/* Precomputed C10 HDMI PLL tables */
> +static const struct intel_c10pll_state mtl_c10_hdmi_25175 = {
> + .clock = 25175,
> + .tx = 0x10,
> + .cmn = 0x1,
> + .pll[0] = 0x34,
> + .pll[1] = 0x00,
> + .pll[2] = 0xB0,
> + .pll[3] = 0x00,
> + .pll[4] = 0x00,
> + .pll[5] = 0x00,
> + .pll[6] = 0x00,
> + .pll[7] = 0x00,
> + .pll[8] = 0x20,
> + .pll[9] = 0xFF,
> + .pll[10] = 0xFF,
> + .pll[11] = 0x55,
> + .pll[12] = 0xE5,
> + .pll[13] = 0x55,
> + .pll[14] = 0x55,
> + .pll[15] = 0x0D,
> + .pll[16] = 0x09,
> + .pll[17] = 0x8F,
> + .pll[18] = 0x84,
> + .pll[19] = 0x23,
> +};
Something off with the above table,
intel_c10pll_calc_port_clock() calculates 25200 clock rate for it. So
either .clock above needs to be the same rate, or the PLL params need to
be corrected for the 25175 rate.
> [...]
> @@ -690,9 +1315,20 @@ static void intel_c10pll_update_pll(struct
> intel_crtc_state *crtc_state,
> static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> const struct intel_c10pll_state * const *tables;
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> int i;
>
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + if (intel_c10_phy_check_hdmi_link_rate(crtc_state->port_clock)
> + != MODE_OK) {
> + drm_dbg_kms(>drm, "Can't support HDMI link rate
> %d on phy %c.\n",
> + crtc_state->port_clock, phy_name(phy));
> + return -EINVAL;
> + }
> + }
The above check is not needed, covered already by the loop later in
the function.
> +
> tables = intel_c10pll_tables_get(crtc_state, encoder);
> if (!tables)
> return -EINVAL;
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On Thu, Apr 13, 2023 at 09:03:29AM -0700, Ceraolo Spurio, Daniele wrote: > > > On 4/13/2023 8:52 AM, Matt Roper wrote: > > On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote: > > > Hi Tvrtko, > > > > > > (I forgot to CC Daniele) > > > > > > On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote: > > > > On 13/04/2023 10:20, Andi Shyti wrote: > > > > > From: Paulo Zanoni > > > > > > > > > > In multitile systems IRQ need to be reset and enabled per GT. > > > > > > > > > > Although in MTL the GUnit misc interrupts register set are > > > > > available only in GT-0, we need to loop through all the GT's > > > > > in order to initialize the media engine which lies on a different > > > > > GT. > > > > > > > > > > Signed-off-by: Paulo Zanoni > > > > > Cc: Tvrtko Ursulin > > > > > Signed-off-by: Andi Shyti > > > > > --- > > > > > Hi, > > > > > > > > > > proposing again this patch, apparently GuC needs this patch to > > > > > initialize the media GT. > > > > What is the resolution for Matt's concern that this is wrong for MTL? > > > There are two explanations, one easy and one less easy. > > > > > > The easy one: without this patch i915 doesn't boot on MTL!(*) > > > > > > The second explanation is that in MTL the media engine has it's > > > own set of misc irq's registers and those are on a different GT > > > (Daniele pointed this out). > > Assuming you're talking about MTL_GUC_MGUC_INTR_MASK, that's not true; > > it's just a single sgunit register (0x1900e8) that has different > > bitfields for the primary GuC and the media GuC. So I still think we > > should avoid looping over GTs; it's actually much simpler to handle > > things in a single pass since we can just determine the single register > > value once (all fields) and write it directly, instead of doing two > > separate RMW updates to the same register to try to avoid clobbering > > the other GuC's settings. > > > > For pre-MTL platforms, it's the same register, except that the bitfield > > now devoted to the media GuC was previously used for something else > > (scatter/gather). > > It's not just the GuC, the VCS/VECS engine programming is also tied to the > media GT (via the HAS_ENGINE checks). It looks like we unconditionally > program VCS 0 and 2, so it'll still work for MTL, but if we get a device > with more VCS engines it'll break. Maybe we can add a MTL version of the > function that just programs everything unconditionally? Going forward it > should be ok to program things for engines that don't exist, but I'm not > sure we can do that for older platforms that came before the extra engines > were ever defined in HW. Right, so I think the engine handling is already correct for MTL today; the main concern would be how it might need to change for other future platforms if more media engines show back up on a media GT. I think we can wait and cross that bridge if/when we get to it. With focus moving over to the Xe KMD, we might be on a completely different driver by the time the hardware adds back in more media engines that aren't already covered unconditionally. Matt > > Daniele > > > > > > > Matt > > > > > I sent this patch not to bypass any review, but to restart the > > > discussion as this patch was just dropped. > > > > > > Thanks, > > > Andi > > > > > > > > > (*) > > > [drm] *ERROR* GT1: GUC: CT: No response for request 0x550a (fence 7) > > > [drm] *ERROR* GT1: GUC: CT: Sending action 0x550a failed (-ETIMEDOUT) > > > status=0X0 > > > [drm] *ERROR* GT1: GUC: Failed to enable usage stats: -ETIMEDOUT > > > [drm] *ERROR* GT1: GuC initialization failed -ETIMEDOUT > > > [drm] *ERROR* GT1: Enabling uc failed (-5) > > > [drm] *ERROR* GT1: Failed to initialize GPU, declaring it wedged! > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
Hi Paulo, > https://en.wikipedia.org/wiki/Ship_of_Theseus > > My original patch was written in 2018. Since then, the implementation > has been rebased and changed multiple times, the commit message has > been changed, the subject line has been changed, yet none of that is > documented in the patch's revision history: it was all removed and it > now looks like I'm the author of the version that was submitted this > month. I never liked this "erase the internal patch's changelog before > submitting it upstream for the first time" process, I think it erases > crucial information and misleads people. > > I know I said something different earlier in private, but after further > reflection, I concluded I do not feel comfortable having my name as the > Author or as the Signed-off-by in this patch. Please remove it. You can > add a "Based-on-patch-by: Paulo Zanoni " if > you want, but that's not necessary. > > This should also help in case some bug is bisected to this patch, then > I won't need to spend time researching who I should forward the emails > to. Sure! When porting and back porting patches I try to preserve as much as possible the original authorship. But, if you feel more comfortable, I can take it on me. Andi > Thanks, > Paulo > > > > > In multitile systems IRQ need to be reset and enabled per GT. > > > > Although in MTL the GUnit misc interrupts register set are > > available only in GT-0, we need to loop through all the GT's > > in order to initialize the media engine which lies on a different > > GT. > > > > Signed-off-by: Paulo Zanoni > > Cc: Tvrtko Ursulin > > Signed-off-by: Andi Shyti
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On Thu, Apr 13, 2023 at 09:03:29AM -0700, Ceraolo Spurio, Daniele wrote: > > > On 4/13/2023 8:52 AM, Matt Roper wrote: > > On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote: > > > Hi Tvrtko, > > > > > > (I forgot to CC Daniele) > > > > > > On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote: > > > > On 13/04/2023 10:20, Andi Shyti wrote: > > > > > From: Paulo Zanoni > > > > > > > > > > In multitile systems IRQ need to be reset and enabled per GT. > > > > > > > > > > Although in MTL the GUnit misc interrupts register set are > > > > > available only in GT-0, we need to loop through all the GT's > > > > > in order to initialize the media engine which lies on a different > > > > > GT. > > > > > > > > > > Signed-off-by: Paulo Zanoni > > > > > Cc: Tvrtko Ursulin > > > > > Signed-off-by: Andi Shyti > > > > > --- > > > > > Hi, > > > > > > > > > > proposing again this patch, apparently GuC needs this patch to > > > > > initialize the media GT. > > > > What is the resolution for Matt's concern that this is wrong for MTL? > > > There are two explanations, one easy and one less easy. > > > > > > The easy one: without this patch i915 doesn't boot on MTL!(*) > > > > > > The second explanation is that in MTL the media engine has it's > > > own set of misc irq's registers and those are on a different GT > > > (Daniele pointed this out). > > Assuming you're talking about MTL_GUC_MGUC_INTR_MASK, that's not true; > > it's just a single sgunit register (0x1900e8) that has different > > bitfields for the primary GuC and the media GuC. So I still think we > > should avoid looping over GTs; it's actually much simpler to handle > > things in a single pass since we can just determine the single register > > value once (all fields) and write it directly, instead of doing two > > separate RMW updates to the same register to try to avoid clobbering > > the other GuC's settings. if we handle exceptions in a single pass wouldn't we have many exceptions to handle in the long run? > > For pre-MTL platforms, it's the same register, except that the bitfield > > now devoted to the media GuC was previously used for something else > > (scatter/gather). > > It's not just the GuC, the VCS/VECS engine programming is also tied to the > media GT (via the HAS_ENGINE checks). It looks like we unconditionally > program VCS 0 and 2, so it'll still work for MTL, but if we get a device > with more VCS engines it'll break. Maybe we can add a MTL version of the > function that just programs everything unconditionally? Going forward it > should be ok to program things for engines that don't exist, but I'm not > sure we can do that for older platforms that came before the extra engines > were ever defined in HW. This is more or less what Tvrtko has suggested, as well. Looks to me like replicating some code... anyway, I will try and see how it looks like. Andi PS Thanks Matt, Daniele and Tvrtko for the feedback. > Daniele > > > > > > > Matt > > > > > I sent this patch not to bypass any review, but to restart the > > > discussion as this patch was just dropped. > > > > > > Thanks, > > > Andi > > > > > > > > > (*) > > > [drm] *ERROR* GT1: GUC: CT: No response for request 0x550a (fence 7) > > > [drm] *ERROR* GT1: GUC: CT: Sending action 0x550a failed (-ETIMEDOUT) > > > status=0X0 > > > [drm] *ERROR* GT1: GUC: Failed to enable usage stats: -ETIMEDOUT > > > [drm] *ERROR* GT1: GuC initialization failed -ETIMEDOUT > > > [drm] *ERROR* GT1: Enabling uc failed (-5) > > > [drm] *ERROR* GT1: Failed to initialize GPU, declaring it wedged!
Re: [Intel-gfx] [PATCH 6/9] drm/i915/mtl/display: Implement DisplayPort sequences
On Wed, Apr 12, 2023 at 03:49:22PM -0700, Radhakrishna Sripada wrote:
> [...]
> +static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> + u32 val;
> +
> + /* 3.b Clear DDI_CTL_DE Enable to 0. */
> + val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
> + if (val & DDI_BUF_CTL_ENABLE) {
> + val &= ~DDI_BUF_CTL_ENABLE;
> + intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
> +
> + /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after
> 100us */
> + mtl_wait_ddi_buf_idle(dev_priv, port);
> + }
> +
> + /* 3.d Disable D2D Link */
> + mtl_ddi_disable_d2d_link(encoder);
> +
> + /* 3.e Disable DP_TP_CTL */
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder,
> crtc_state));
> + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
Only DP_TP_CTL_ENABLE should be cleared and could use intel_de_rmw().
> + intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
> val);
> + }
> +}
Re: [Intel-gfx] [PATCH 7/9] drm/i915/mtl: Initial DDI port setup
On Wed, Apr 12, 2023 at 03:49:23PM -0700, Radhakrishna Sripada wrote:
Could you move this to the end of the patchset?
> From: Clint Taylor
>
> Initialization sequences and C10 phy are in place to be able to enable
> the first 2 ports of MTL. The other ports use C20 phy that still need
> to be properly added. Enable the first ports for now, keeping a TODO
> comment about the others.
>
> Reviewed-by: Lucas De Marchi
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 27b47680573a..1fec49c5d23a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7791,7 +7791,11 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG2(dev_priv)) {
> + if (IS_METEORLAKE(dev_priv)) {
> + /* TODO: initialize TC ports as well */
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + } else if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
> --
> 2.34.1
>
Re: [Intel-gfx] [PATCH 01/10] drm/i915/display: remove intel_display_commit_duplicated_state()
Quoting Jani Nikula (2023-04-13 06:47:27)
> This seems like an unnecessary wrapper layer. Removing it will be
> helpful later.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++-
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 27b47680573a..1c0149adcf49 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -701,20 +701,6 @@ intel_plane_fence_y_offset(const struct
> intel_plane_state *plane_state)
> return y;
> }
>
> -static int
> -intel_display_commit_duplicated_state(struct intel_atomic_state *state,
> -struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> - int ret;
> -
> - ret = drm_atomic_helper_commit_duplicated_state(>base, ctx);
> -
> - drm_WARN_ON(>drm, ret == -EDEADLK);
> -
> - return ret;
> -}
> -
> static int
> __intel_display_resume(struct drm_i915_private *i915,
>struct drm_atomic_state *state,
> @@ -722,7 +708,7 @@ __intel_display_resume(struct drm_i915_private *i915,
> {
> struct drm_crtc_state *crtc_state;
> struct drm_crtc *crtc;
> - int i;
> + int ret, i;
>
> intel_modeset_setup_hw_state(i915, ctx);
> intel_vga_redisable(i915);
> @@ -748,7 +734,11 @@ __intel_display_resume(struct drm_i915_private *i915,
> if (!HAS_GMCH(i915))
> to_intel_atomic_state(state)->skip_intermediate_wm = true;
>
> - return intel_display_commit_duplicated_state(to_intel_atomic_state(state),
> ctx);
> + ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
> +
> + drm_WARN_ON(>drm, ret == -EDEADLK);
> +
> + return ret;
> }
>
> static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
> @@ -839,10 +829,12 @@ void intel_display_finish_reset(struct drm_i915_private
> *i915)
> /* reset doesn't touch the display */
> if (!gpu_reset_clobbers_display(i915)) {
> /* for testing only restore the display */
> - ret =
> intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
> - if (ret)
> + ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
> + if (ret) {
> + drm_WARN_ON(>drm, ret == -EDEADLK);
> drm_err(>drm,
> "Restoring old state failed with %i\n", ret);
> + }
> } else {
> /*
> * The display has been reset as well,
> --
> 2.39.2
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: split out high level display entry points
== Series Details ==
Series: drm/i915/display: split out high level display entry points
URL : https://patchwork.freedesktop.org/series/116431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13001_full -> Patchwork_116431v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_116431v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][1] ([i915#2846])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk2/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][2] -> [FAIL][3] ([i915#2842])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-glk3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk2/igt@gem_lmem_swapp...@verify-ccs.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][5] -> [ABORT][6] ([i915#5566]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-glk4/igt@gen9_exec_pa...@allowed-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk9/igt@gen9_exec_pa...@allowed-all.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3886]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#72])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#658])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk2/igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html
* igt@kms_vrr@negative-basic:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +67 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-glk2/igt@kms_...@negative-basic.html
Possible fixes
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][12] ([i915#2842]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][14] ([i915#2842]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-rkl-7/igt@gem_exec_fair@basic-n...@vcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-rkl-4/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- {shard-tglu}: [ABORT][16] ([i915#7975]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devi...@smem.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-tglu-5/igt@gem_exec_suspend@basic-s4-devi...@smem.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}:[SKIP][18] ([i915#1397]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-rkl-2/igt@i915_pm_...@modeset-lpsp.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-rkl-7/igt@i915_pm_...@modeset-lpsp.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- {shard-rkl}:[FAIL][20] ([i915#3743]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13001/shard-rkl-7/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116431v1/shard-rkl-4/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][22] ([i915#2346]) -> [PASS][23]
[22]:
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On 4/13/2023 8:52 AM, Matt Roper wrote: On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote: Hi Tvrtko, (I forgot to CC Daniele) On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote: On 13/04/2023 10:20, Andi Shyti wrote: From: Paulo Zanoni In multitile systems IRQ need to be reset and enabled per GT. Although in MTL the GUnit misc interrupts register set are available only in GT-0, we need to loop through all the GT's in order to initialize the media engine which lies on a different GT. Signed-off-by: Paulo Zanoni Cc: Tvrtko Ursulin Signed-off-by: Andi Shyti --- Hi, proposing again this patch, apparently GuC needs this patch to initialize the media GT. What is the resolution for Matt's concern that this is wrong for MTL? There are two explanations, one easy and one less easy. The easy one: without this patch i915 doesn't boot on MTL!(*) The second explanation is that in MTL the media engine has it's own set of misc irq's registers and those are on a different GT (Daniele pointed this out). Assuming you're talking about MTL_GUC_MGUC_INTR_MASK, that's not true; it's just a single sgunit register (0x1900e8) that has different bitfields for the primary GuC and the media GuC. So I still think we should avoid looping over GTs; it's actually much simpler to handle things in a single pass since we can just determine the single register value once (all fields) and write it directly, instead of doing two separate RMW updates to the same register to try to avoid clobbering the other GuC's settings. For pre-MTL platforms, it's the same register, except that the bitfield now devoted to the media GuC was previously used for something else (scatter/gather). It's not just the GuC, the VCS/VECS engine programming is also tied to the media GT (via the HAS_ENGINE checks). It looks like we unconditionally program VCS 0 and 2, so it'll still work for MTL, but if we get a device with more VCS engines it'll break. Maybe we can add a MTL version of the function that just programs everything unconditionally? Going forward it should be ok to program things for engines that don't exist, but I'm not sure we can do that for older platforms that came before the extra engines were ever defined in HW. Daniele Matt I sent this patch not to bypass any review, but to restart the discussion as this patch was just dropped. Thanks, Andi (*) [drm] *ERROR* GT1: GUC: CT: No response for request 0x550a (fence 7) [drm] *ERROR* GT1: GUC: CT: Sending action 0x550a failed (-ETIMEDOUT) status=0X0 [drm] *ERROR* GT1: GUC: Failed to enable usage stats: -ETIMEDOUT [drm] *ERROR* GT1: GuC initialization failed -ETIMEDOUT [drm] *ERROR* GT1: Enabling uc failed (-5) [drm] *ERROR* GT1: Failed to initialize GPU, declaring it wedged!
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On Thu, 2023-04-13 at 11:20 +0200, Andi Shyti wrote:
> From: Paulo Zanoni
Hi
https://en.wikipedia.org/wiki/Ship_of_Theseus
My original patch was written in 2018. Since then, the implementation
has been rebased and changed multiple times, the commit message has
been changed, the subject line has been changed, yet none of that is
documented in the patch's revision history: it was all removed and it
now looks like I'm the author of the version that was submitted this
month. I never liked this "erase the internal patch's changelog before
submitting it upstream for the first time" process, I think it erases
crucial information and misleads people.
I know I said something different earlier in private, but after further
reflection, I concluded I do not feel comfortable having my name as the
Author or as the Signed-off-by in this patch. Please remove it. You can
add a "Based-on-patch-by: Paulo Zanoni " if
you want, but that's not necessary.
This should also help in case some bug is bisected to this patch, then
I won't need to spend time researching who I should forward the emails
to.
Thanks,
Paulo
>
> In multitile systems IRQ need to be reset and enabled per GT.
>
> Although in MTL the GUnit misc interrupts register set are
> available only in GT-0, we need to loop through all the GT's
> in order to initialize the media engine which lies on a different
> GT.
>
> Signed-off-by: Paulo Zanoni
> Cc: Tvrtko Ursulin
> Signed-off-by: Andi Shyti
> ---
> Hi,
>
> proposing again this patch, apparently GuC needs this patch to
> initialize the media GT.
>
> Andi
>
> Changelog
> =
> v1 -> v2
> - improve description in the commit log.
>
> drivers/gpu/drm/i915/i915_irq.c | 28 ++--
> 1 file changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d24bdea65a3dc..524d64bf5d186 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2764,14 +2764,19 @@ static void dg1_irq_reset(struct drm_i915_private
> *dev_priv)
> {
> struct intel_gt *gt = to_gt(dev_priv);
> struct intel_uncore *uncore = gt->uncore;
> + unsigned int i;
>
>
>
>
> dg1_master_intr_disable(dev_priv->uncore.regs);
>
>
>
>
> - gen11_gt_irq_reset(gt);
> - gen11_display_irq_reset(dev_priv);
> + for_each_gt(gt, dev_priv, i) {
> + gen11_gt_irq_reset(gt);
>
>
>
>
> - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> - GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> + uncore = gt->uncore;
> + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> + GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> + }
> +
> + gen11_display_irq_reset(dev_priv);
> }
>
>
>
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3425,13 +3430,16 @@ static void gen11_irq_postinstall(struct
> drm_i915_private *dev_priv)
>
>
>
>
> static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - struct intel_gt *gt = to_gt(dev_priv);
> - struct intel_uncore *uncore = gt->uncore;
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> + struct intel_gt *gt;
> + unsigned int i;
>
>
>
>
> - gen11_gt_irq_postinstall(gt);
> + for_each_gt(gt, dev_priv, i) {
> + gen11_gt_irq_postinstall(gt);
>
>
>
>
> - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
> + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
> + gu_misc_masked);
> + }
>
>
>
>
> if (HAS_DISPLAY(dev_priv)) {
> icp_irq_postinstall(dev_priv);
> @@ -3440,8 +3448,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
> *dev_priv)
> GEN11_DISPLAY_IRQ_ENABLE);
> }
>
>
>
>
> - dg1_master_intr_enable(uncore->regs);
> - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
> + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
> }
>
>
>
>
> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
Re: [Intel-gfx] [PATCH 4/9] drm/i915/mtl: Add vswing programming for C10 phys
On Wed, Apr 12, 2023 at 03:49:20PM -0700, Radhakrishna Sripada wrote:
> From: Mika Kahola
>
> C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
> Program the levels directly to the fields in the VDR Registers.
>
> Bspec: 65449
>
> v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
> and preemphasis 1 instead of two times of level 1 preemphasis 0.
> Fix this in the driver code as well.
> v3: VSwing update (Clint)
> v4: Add vboost termination ctl programming(Imre)
> Fix tx llogic and other nits
> Restrict C10 vdr ctl register access for C10 phy(RK)
>
> Cc: Imre Deak
> Cc: Uma Shankar
> Signed-off-by: Clint Taylor
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> Reviewed-by: Imre Deak (v3)
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 102 +-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 14 ++-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> .../drm/i915/display/intel_ddi_buf_trans.c| 31 +-
> 5 files changed, 143 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9ab1e686a40b..ca7626eadd7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -6,6 +6,8 @@
> #include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> +#include "intel_ddi.h"
> +#include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> @@ -292,6 +294,97 @@ static void intel_cx0_rmw(struct drm_i915_private *i915,
> enum port port,
> __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
> }
>
> +static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state
> *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> + (crtc_state->port_clock == 54 ||
> + crtc_state->port_clock == 81))
> + return 5;
> + else
> + return 4;
> + } else {
> + return 5;
> + }
> +}
> +
> +static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state
> *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> + (crtc_state->port_clock == 54 ||
> + crtc_state->port_clock == 81))
> + return 5;
> + else
> + return 2;
> + } else {
> + return 6;
> + }
> +}
> +
> +void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + const struct intel_ddi_buf_trans *trans;
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + intel_wakeref_t wakeref;
> + int n_entries, ln;
> +
> + wakeref = intel_cx0_phy_transaction_begin(encoder);
> +
> + trans = encoder->get_buf_trans(encoder, crtc_state, _entries);
> + if (drm_WARN_ON_ONCE(>drm, !trans)) {
> + intel_cx0_phy_transaction_end(encoder, wakeref);
> + return;
> + }
> +
> + if (intel_is_c10phy(i915, phy)) {
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> + 0, C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C10_VDR_CMN(3),
> + C10_CMN3_TXVBOOST_MASK,
> +
> C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
> + MB_WRITE_UNCOMMITTED);
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C10_VDR_TX(1),
> + C10_TX1_TERMCTL_MASK,
> +
> C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
> + MB_WRITE_COMMITTED);
Both PHY lanes need to be programmed for all these vswing settings.
> + }
> +
> + for (ln = 0; ln < crtc_state->lane_count; ln++) {
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> + int lane, tx;
> +
> + lane = ln / 2;
> + tx = ln % 2;
> +
> + intel_cx0_rmw(i915, encoder->port, BIT(lane),
> PHY_CX0_VDROVRD_CTL(lane, tx, 0),
> + C10_PHY_OVRD_LEVEL_MASK,
> +
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
> + MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, BIT(lane),
>
Re: [Intel-gfx] [PATCH v2] drm/i915: Make IRQ reset and postinstall multi-gt aware
On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote: > Hi Tvrtko, > > (I forgot to CC Daniele) > > On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote: > > > > On 13/04/2023 10:20, Andi Shyti wrote: > > > From: Paulo Zanoni > > > > > > In multitile systems IRQ need to be reset and enabled per GT. > > > > > > Although in MTL the GUnit misc interrupts register set are > > > available only in GT-0, we need to loop through all the GT's > > > in order to initialize the media engine which lies on a different > > > GT. > > > > > > Signed-off-by: Paulo Zanoni > > > Cc: Tvrtko Ursulin > > > Signed-off-by: Andi Shyti > > > --- > > > Hi, > > > > > > proposing again this patch, apparently GuC needs this patch to > > > initialize the media GT. > > > > What is the resolution for Matt's concern that this is wrong for MTL? > > There are two explanations, one easy and one less easy. > > The easy one: without this patch i915 doesn't boot on MTL!(*) > > The second explanation is that in MTL the media engine has it's > own set of misc irq's registers and those are on a different GT > (Daniele pointed this out). Assuming you're talking about MTL_GUC_MGUC_INTR_MASK, that's not true; it's just a single sgunit register (0x1900e8) that has different bitfields for the primary GuC and the media GuC. So I still think we should avoid looping over GTs; it's actually much simpler to handle things in a single pass since we can just determine the single register value once (all fields) and write it directly, instead of doing two separate RMW updates to the same register to try to avoid clobbering the other GuC's settings. For pre-MTL platforms, it's the same register, except that the bitfield now devoted to the media GuC was previously used for something else (scatter/gather). Matt > > I sent this patch not to bypass any review, but to restart the > discussion as this patch was just dropped. > > Thanks, > Andi > > > (*) > [drm] *ERROR* GT1: GUC: CT: No response for request 0x550a (fence 7) > [drm] *ERROR* GT1: GUC: CT: Sending action 0x550a failed (-ETIMEDOUT) > status=0X0 > [drm] *ERROR* GT1: GUC: Failed to enable usage stats: -ETIMEDOUT > [drm] *ERROR* GT1: GuC initialization failed -ETIMEDOUT > [drm] *ERROR* GT1: Enabling uc failed (-5) > [drm] *ERROR* GT1: Failed to initialize GPU, declaring it wedged! -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH v4 4/6] drm/i915: Switch to fdinfo helper
On Thu, Apr 13, 2023 at 6:07 AM Tvrtko Ursulin
wrote:
>
>
> On 12/04/2023 23:42, Rob Clark wrote:
> > From: Rob Clark
>
> There is more do to here to remove my client->id fully (would now be
> dead code) so maybe easiest if you drop this patch and I do it after you
> land this and it propagates to our branches? I'd like to avoid pain with
> conflicts if possible..
That is fine by me
BR,
-R
> Regards,
>
> Tvrtko
>
> >
> > Signed-off-by: Rob Clark
> > ---
> > drivers/gpu/drm/i915/i915_driver.c | 3 ++-
> > drivers/gpu/drm/i915/i915_drm_client.c | 18 +-
> > drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> > 3 files changed, 8 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index db7a86def7e2..0d91f85f8b97 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1696,7 +1696,7 @@ static const struct file_operations i915_driver_fops
> > = {
> > .compat_ioctl = i915_ioc32_compat_ioctl,
> > .llseek = noop_llseek,
> > #ifdef CONFIG_PROC_FS
> > - .show_fdinfo = i915_drm_client_fdinfo,
> > + .show_fdinfo = drm_show_fdinfo,
> > #endif
> > };
> >
> > @@ -1796,6 +1796,7 @@ static const struct drm_driver i915_drm_driver = {
> > .open = i915_driver_open,
> > .lastclose = i915_driver_lastclose,
> > .postclose = i915_driver_postclose,
> > + .show_fdinfo = i915_drm_client_fdinfo,
> >
> > .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> > .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
> > b/drivers/gpu/drm/i915/i915_drm_client.c
> > index b09d1d386574..4a77e5e47f79 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.c
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> > @@ -101,7 +101,7 @@ static u64 busy_add(struct i915_gem_context *ctx,
> > unsigned int class)
> > }
> >
> > static void
> > -show_client_class(struct seq_file *m,
> > +show_client_class(struct drm_printer *p,
> > struct i915_drm_client *client,
> > unsigned int class)
> > {
> > @@ -117,22 +117,20 @@ show_client_class(struct seq_file *m,
> > rcu_read_unlock();
> >
> > if (capacity)
> > - seq_printf(m, "drm-engine-%s:\t%llu ns\n",
> > + drm_printf(p, "drm-engine-%s:\t%llu ns\n",
> > uabi_class_names[class], total);
> >
> > if (capacity > 1)
> > - seq_printf(m, "drm-engine-capacity-%s:\t%u\n",
> > + drm_printf(p, "drm-engine-capacity-%s:\t%u\n",
> > uabi_class_names[class],
> > capacity);
> > }
> >
> > -void i915_drm_client_fdinfo(struct seq_file *m, struct file *f)
> > +void i915_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file)
> > {
> > - struct drm_file *file = f->private_data;
> > struct drm_i915_file_private *file_priv = file->driver_priv;
> > struct drm_i915_private *i915 = file_priv->dev_priv;
> > struct i915_drm_client *client = file_priv->client;
> > - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > unsigned int i;
> >
> > /*
> > @@ -141,12 +139,6 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct
> > file *f)
> >* **
> >*/
> >
> > - seq_printf(m, "drm-driver:\t%s\n", i915->drm.driver->name);
> > - seq_printf(m, "drm-pdev:\t%04x:%02x:%02x.%d\n",
> > -pci_domain_nr(pdev->bus), pdev->bus->number,
> > -PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
> > - seq_printf(m, "drm-client-id:\t%u\n", client->id);
> > -
> > /*
> >* Temporarily skip showing client engine information with GuC
> > submission till
> >* fetching engine busyness is implemented in the GuC submission
> > backend
> > @@ -155,6 +147,6 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct
> > file *f)
> > return;
> >
> > for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)
> > - show_client_class(m, client, i);
> > + show_client_class(p, client, i);
> > }
> > #endif
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.h
> > b/drivers/gpu/drm/i915/i915_drm_client.h
> > index 69496af996d9..ef85fef45de5 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.h
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> > @@ -60,7 +60,7 @@ static inline void i915_drm_client_put(struct
> > i915_drm_client *client)
> > struct i915_drm_client *i915_drm_client_add(struct i915_drm_clients
> > *clients);
> >
> > #ifdef CONFIG_PROC_FS
> > -void i915_drm_client_fdinfo(struct seq_file *m, struct file *f);
> > +void i915_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file);
> > #endif
> >
> > void i915_drm_clients_fini(struct i915_drm_clients *clients);
Re: [Intel-gfx] [PATCH i-g-t] tests/gem_reset_stats: Don't allow request watchdog to interfere
On 13.04.2023 16:36, Janusz Krzysztofik wrote:
A user reported recently that some subtests are failing. The test was
blocklisted in 2018, so we've lost CI feedback on its results since then.
In 2021, request watchdog with 20 seconds timeout was introduced to i915.
Kernel logs from failed subtest runs indicate that the request watchdog
interfers with engine heartbeat and request preemption used by the test
for exercising reset statistics.
Disable request watchdog during the test execution.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8310
Signed-off-by: Janusz Krzysztofik
---
tests/i915/gem_reset_stats.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/i915/gem_reset_stats.c b/tests/i915/gem_reset_stats.c
index baa101517d..7b003d88b6 100644
--- a/tests/i915/gem_reset_stats.c
+++ b/tests/i915/gem_reset_stats.c
@@ -906,6 +906,7 @@ igt_main
igt_fixture {
bool has_reset_stats;
bool using_full_reset;
+ char *tmp;
device = drm_open_driver(DRIVER_INTEL);
devid = intel_get_drm_devid(device);
@@ -922,6 +923,12 @@ igt_main
"No reset stats ioctl support. Too old
kernel?\n");
igt_require_f(using_full_reset,
"Full GPU reset is not enabled. Is enable_hangcheck
set?\n");
+
+ /* Don't allow request watchdog to interfere */
+ tmp = __igt_params_get(device, "request_timeout_ms");
With presence of igt_params_scanf it would be simpler.
Reviewed-by: Andrzej Hajda
Regards
Andrzej
+ if (tmp && atoi(tmp))
+ igt_params_save_and_set(device, "request_timeout_ms",
"%u", 0);
+ free(tmp);
}
igt_subtest("params")
Re: [Intel-gfx] [PATCH] drm/i915/color: Fix typo for Plane CSC indexes
> -Original Message-
> From: Intel-gfx On Behalf Of
> Shankar, Uma
> Sent: Friday, March 31, 2023 1:52 AM
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org
> Cc: sta...@vger.kernel.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/color: Fix typo for Plane CSC
> indexes
>
>
>
> > -Original Message-
> > From: Borah, Chaitanya Kumar
> > Sent: Thursday, March 30, 2023 8:31 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Shankar, Uma ; Borah, Chaitanya Kumar
> > ; sta...@vger.kernel.org
> > Subject: [PATCH] drm/i915/color: Fix typo for Plane CSC indexes
> >
> > Replace _PLANE_INPUT_CSC_RY_GY_2_* with _PLANE_CSC_RY_GY_2_* for
> Plane
> > CSC
> >
> > Fixes: 6eba56f64d5d ("drm/i915/pxp: black pixels on pxp disabled")
>
> Looks Good, thanks for catching it.
> Reviewed-by: Uma Shankar
Pushed the changes to din. Thanks
Regards,
Animesh
>
> > Cc:
> >
> > Signed-off-by: Chaitanya Kumar Borah
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8e4aca888b7a..85885b01e6ac
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7496,8 +7496,8 @@ enum skl_power_gate {
> >
> > #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A,
> \
> > _PLANE_CSC_RY_GY_1_B)
> > -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe,
> > _PLANE_INPUT_CSC_RY_GY_2_A, \
> > - _PLANE_INPUT_CSC_RY_GY_2_B)
> > +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe,
> _PLANE_CSC_RY_GY_2_A, \
> > + _PLANE_CSC_RY_GY_2_B)
> > #define PLANE_CSC_COEFF(pipe, plane, index)
> _MMIO_PLANE(plane, \
> >
> > _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> >
> > _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> > --
> > 2.25.1
