Hi Ville, > -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Ville > Syrjala > Sent: 04 April 2023 23:25 > To: [email protected] > Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Evade transcoder's vblank when > doing seamless M/N changes > > From: Ville Syrjälä <[email protected]> > > The transcoder M/N values are double buffered on the transcoder's > undelayed vblank. So when doing seamless M/N fastsets we need to evade > also that. > > Not that currently the pipe's delayed vblank == transcoder's undelayed > vblank, so this is still a nop change. But in the future when we may have to > delay the pipe's vblank to create a register programming window > ("window2") for the DSB. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c > b/drivers/gpu/drm/i915/display/intel_crtc.c > index ed45a6934854..f3b836829296 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c > @@ -510,6 +510,13 @@ void intel_pipe_update_start(struct intel_crtc_state > *new_crtc_state) > > VBLANK_EVASION_TIME_US); > max = vblank_start - 1; > > + /* > + * M/N is double buffered on the transcoder's undelayed vblank, > + * so with seamless M/N we must evade both vblanks. > + */ > + if (new_crtc_state->seamless_m_n && > intel_crtc_needs_fastset(new_crtc_state)) > + min -= adjusted_mode->crtc_vblank_start - > +adjusted_mode->crtc_vdisplay; > +
changes LGTM. Thanks Reviewed-by: Mitul Golani <[email protected] >> if (min <= 0 || max <= 0) > goto irq_disable; > > -- > 2.39.2
