== Series Details ==
Series: Enable Wa_14019159160 and Wa_16019325821 for MTL
URL : https://patchwork.freedesktop.org/series/123813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_123813v1
Summary
---
== Series Details ==
Series: Enable Wa_14019159160 and Wa_16019325821 for MTL
URL : https://patchwork.freedesktop.org/series/123813/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable Wa_14019159160 and Wa_16019325821 for MTL
URL : https://patchwork.freedesktop.org/series/123813/
State : warning
== Summary ==
Error: dim checkpatch failed
41e13ed5cde2 drm/i915/guc: Update 'recommended' version to 70.11.0 for
DG2/ADL-P/MTL
c2d869434453
== Series Details ==
Series: drm/i915/pxp: Add drm_dbgs for critical PXP events.
URL : https://patchwork.freedesktop.org/series/123803/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_123803v1
Summary
== Series Details ==
Series: drm/i915/pxp: Add drm_dbgs for critical PXP events.
URL : https://patchwork.freedesktop.org/series/123803/
State : warning
== Summary ==
Error: dim checkpatch failed
2eab9e4e637a drm/i915/pxp: Add drm_dbgs for critical PXP events.
-:7:
== Series Details ==
Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw
spec
URL : https://patchwork.freedesktop.org/series/123795/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_123795v1
== Series Details ==
Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw
spec
URL : https://patchwork.freedesktop.org/series/123795/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Alan,
kernel test robot noticed the following build errors:
[auto build test ERROR on cf1e91e884bb1113c653e654e9de1754fc1d4488]
url:
https://github.com/intel-lab-lkp/linux/commits/Alan-Previn/drm-i915-pxp-mtl-Update-pxp-firmware-response-timeout/20230916-023150
base:
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_122799v5
Summary
---
**FAILURE**
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim checkpatch failed
0891930bfe21 drm/i915/xelpdp: Add XE_LPDP_FEATURES
d93689afdf8e drm/i915/lnl: Add display definitions
6d075298baed
== Series Details ==
Series: drm/i915/gt: Update RC6 mask for mtl_drpc
URL : https://patchwork.freedesktop.org/series/123775/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_123775v1
Summary
---
On 9/14/2023 6:28 PM, Umesh Nerlige Ramappa wrote:
Ideally the busyness worker should take a gt pm wakeref because the
worker only needs to be active while gt is awake. However, the gt_park
path cancels the worker synchronously and this complicates the flow if
the worker is also running at
On Fri, Sep 15, 2023 at 10:31:05PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 14, 2023 at 10:26:44PM +0300, Imre Deak wrote:
> > At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> > lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> > link bpp in this case,
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 3 +
From: John Harrison
Use the new w/a KLV support to enable a MTL w/a. Note, this w/a is a
super-set of Wa_16019325821, so requires turning that one as well as
setting the new flag for Wa_14019159160 itself.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +++
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 19 +++
From: John Harrison
The latest GuC has new features and new workarounds that we wish to
enable. So let the universe know that it is useful to update their
firmware.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 6 +++---
1 file changed, 3 insertions(+), 3
From: John Harrison
Enable Wa_14019159160 and Wa_16019325821 for MTL
RCS/CCS workarounds for MTL.
Signed-off-by: John Harrison
John Harrison (4):
drm/i915/guc: Update 'recommended' version to 70.11.0 for
DG2/ADL-P/MTL
drm/i915: Enable Wa_16019325821
drm/i915/guc: Add support for
On Fri, Sep 15, 2023 at 10:11:38PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 15, 2023 at 03:33:54AM +0300, Imre Deak wrote:
> > At the moment a modeset fails if the config computation of a pipe can't
> > fit its required BW to the available link BW even though the limitation
> > may be resolved by
On Fri, 2023-09-15 at 13:15 -0700, Teres Alexis, Alan Previn wrote:
> Debugging PXP issues can't even begin without understanding precedding
> sequence of important events. Add drm_dbg into the most important PXP events.
>
> v3 : - move gt_dbg to after mutex block in function
>
Debugging PXP issues can't even begin without understanding precedding
sequence of important events. Add drm_dbg into the most important PXP events.
v3 : - move gt_dbg to after mutex block in function
i915_gsc_proxy_component_bind. (Vivaik)
v2 : - remove __func__ since drm_dbg covers
On Fri, Sep 15, 2023 at 09:34:26PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 14, 2023 at 10:26:40PM +0300, Imre Deak wrote:
> > Add intel_modeset_pipes_in_mask_early() to modeset a provided set of
> > pipes, used in a follow-up patch.
> >
> > While at it add _late suffix to
On Fri, Sep 15, 2023 at 05:37:53AM +, Patchwork wrote:
Patch Details
Series: i915/guc: Get runtime pm in busyness worker only if already active
URL: [1]https://patchwork.freedesktop.org/series/123744/
State: failure
Details:
On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor
>
> We use multiple variables for HDMI and DisplayPort to store the value of
> DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> to just one in struct intel_digital_port. This is a
On Thu, Sep 14, 2023 at 10:26:44PM +0300, Imre Deak wrote:
> At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> link bpp in this case, until pipe B uses only up to 2 FDI lanes.
>
> For this instead of the
Thanks for catching all of this! for the whole series:
Reviewed-by: Lyude Paul
On Thu, 2023-09-14 at 01:32 +0300, Imre Deak wrote:
> Fix the NULL dereference leading to the following stack trace:
>
> [ 129.687181] i915 :00:02.0: [drm:drm_dp_add_payload_part1
> [drm_display_helper]] VCPI
On Fri, Sep 15, 2023 at 03:33:54AM +0300, Imre Deak wrote:
> At the moment a modeset fails if the config computation of a pipe can't
> fit its required BW to the available link BW even though the limitation
> may be resolved by reducing the BW requirement of other pipes.
>
> To improve the above
On Thu, Sep 14, 2023 at 10:26:40PM +0300, Imre Deak wrote:
> Add intel_modeset_pipes_in_mask_early() to modeset a provided set of
> pipes, used in a follow-up patch.
>
> While at it add _late suffix to intel_modeset_all_pipes() for clarity
> and add DocBook descriptions for the two exported
Update the GSC-fw input/output HECI packet size to match
updated internal fw specs.
Signed-off-by: Alan Previn
Reviewed-by: Vivaik Balasubrawmanian
---
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Update the max GSC-fw response time to match updated internal
fw specs. Because this response time is an SLA on the firmware,
not inclusive of i915->GuC->HW handoff latency, when submitting
requests to the GSC fw via intel_gsc_uc_heci_cmd_submit helpers,
start the count after the request hits the
On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.
Signed-off-by: Alan Previn
Reviewed-by: Vivaik Balasubrawmanian
---
For MTL, update the GSC-HECI packet size and the max firmware
response timeout to match internal fw specs. Enforce setting
run-alone bit in LRC for protected contexts.
Changes from prio revs:
v5: - PAGE_ALIGN typo fix (Alan).
- Use macro for runalone bit (Vivaik)
- Spec alignment
For MTL, update the GSC-HECI packet size and the max firmware
response timeout to match internal fw specs. Enforce setting
run-alone bit in LRC for protected contexts.
Changes from prio revs:
v5: - PAGE_ALIGN typo fix (Alan).
- Use macro for runalone bit (Vivaik)
- Spec alignment
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> On Meteorlake onwards, HW specs require that all user contexts that
> run on render or compute engines and require PXP must enforce
> run-alone bit in lrc. Add this enforcement for protected contexts.
alan:snip
>
>
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the GSC-fw input/output HECI packet size to match
> updated internal fw specs.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
> 1 file changed, 2 insertions(+), 2
On Fri, Sep 15, 2023 at 10:46:45AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
> so reuse the code. PGPICA1 contains type-C capable port slices
> which requires the well to power powered up, so add new power
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the max GSC-fw response time to match updated internal
> fw specs. Because this response time is an SLA on the firmware,
> not inclusive of i915->GuC->HW handoff latency, when submitting
> requests to the GSC fw via
On 9/14/2023 3:28 PM, Balasubrawmanian, Vivaik wrote:
On 9/6/2023 5:15 PM, Alan Previn wrote:
Update the GSC-fw input/output HECI packet size to match
updated internal fw specs.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
1 file changed, 2
From: Stanislav Lisovskiy
Add a new CDCLK table for Lunar Lake.
v2:
- Remove mdclk from the table as it's not needed (Matt Roper)
- Update waveform values to the latest from spec (Matt Roper)
- Rename functions and calculation to match by pixel rate (Lucas)
v3: Keep only the table: as far
From: Stanislav Lisovskiy
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa
Reviewed-by:
From: Ravi Kumar Vodapalli
Add programming sequence for changes on CDCLK for Lunar Lake
platforms. It's mostly the same as MTL, but with some
additional programming for the squash and crawling steps when
a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for
From: Stanislav Lisovskiy
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count()
XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer
using _PICK_EVEN_2RANGES() over PICK().
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 30 +++
1 file changed, 10 insertions(+), 20 deletions(-)
From: Juha-Pekka Heikkilä
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal
Signed-off-by: Juha-Pekka Heikkilä
Reviewed-by: Suraj Kandpal
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
1 file changed, 8 insertions(+)
From: Stanislav Lisovskiy
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do
From: Stanislav Lisovskiy
Introduce correspondent definitions for choosing between CD2X CDCLK
and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
defined with PLL CDCLK as source, so simply set it. Also
skl_cdclk_decimal() shouldn't be set in CDCLK_CTL anymore, so skip it
From: Gustavo Sousa
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
While at it, drop some trailing newlines.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
From: Gustavo Sousa
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge. The approach used by BXT/GLK can't be used here since
leaving it
Xe2_LPD also needs workaround 15010685871. While adding the new display
version, also re-order the condition to follow the convention of new
version first.
v2: Remove redundant HAS_CDCLK_SQUASH(). As the platform or IP version
needing the workaround are handpicked, there is no need to also
From: Clint Taylor
We use multiple variables for HDMI and DisplayPort to store the value of
DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
to just one in struct intel_digital_port. This is a preparation step for
future changes in D2D enable/disable sequence for xe2lpd
From: Clint Taylor
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
Reviewed-by: Vinod Govindapillai
Signed-off-by: Lucas De Marchi
---
From: Ravi Kumar Vodapalli
Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.
The DC_OFF fake power well will be added in a
Fix some whitespace issues for register definitions and keep the defines
for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with
the bit definition.
While at it add a TODO entry that those defines shouldn't be using an
implicit dev_priv.
Signed-off-by: Lucas De Marchi
From: Matt Roper
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha
From: Gustavo Sousa
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD:
now they are all in a single range, with CH_A and CH_B coming right after
the USBC instances. Like was done when moving registers to PICA, use
a helper macro to remap the ch passed to an index that can be used to
calculate
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
to work with multiple reg location and bitfield layout.
v2: Set/Clear
From: Matt Roper
FBC is no longer limited by pipe: add the defines for pipes B and C that
will be used by platforms supporting FBC on such pipes.
Bspec: 68881, 68904
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Vinod Govindapillai
---
From: Clint Taylor
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
From: Balasubramani Vivekanandan
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Xe2 display is derived from the Xe_LPD+ IP; additional feature
deltas will be introduced in subsequent patches, so
From: Matt Roper
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.
From: Stanislav Lisovskiy
We now start calculating relative plane data rate for cursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Bspec: 68907
Signed-off-by: Stanislav
Now that DDI doesn't use that field anymore and it's restricted to
display/g4x_dp.c, rename it to follow the correspondent output_reg
field. This should avoid misuses of the old DP field, which would not
end up having the desired effect, and also make it clear what is
stashed in this variable.
Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/soc/intel_pch.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
v2: Move everything from xe_lpdp_display to the new macro and remove
the version setting: it's not needed with GMD_ID.
Signed-off-by: Lucas De Marchi
Reviewed-by:
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register
Cross posting this to the i915 and xe mailing lists. The basic platform
enabling for Lunar Lake is already applied in the xe driver[1].
This patch series adds the display support in the i915 driver, that is
going to be shared with xe.
Like v3, this is based off drm-tip and the goal is to start
On 9/14/2023 3:03 PM, Balasubrawmanian, Vivaik wrote:
On 9/13/2023 3:57 PM, Alan Previn wrote:
Debugging PXP issues can't even begin without understanding precedding
sequence of events. Add drm_dbg into the most important PXP events.
v2 : - remove __func__ since drm_dbg covers that (Jani).
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the max GSC-fw response time to match updated internal
> fw specs. Because this response time is an SLA on the firmware,
> not inclusive of i915->GuC->HW handoff latency, when submitting
> requests to the GSC fw via
On 9/14/2023 3:28 PM, Balasubrawmanian, Vivaik wrote:
On 9/6/2023 5:15 PM, Alan Previn wrote:
Update the GSC-fw input/output HECI packet size to match
updated internal fw specs.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
1 file changed, 2
On 9/14/2023 3:51 PM, Balasubrawmanian, Vivaik wrote:
On 9/9/2023 3:38 PM, Alan Previn wrote:
On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the GSC-fw input/output HECI packet size to match
> updated internal fw specs.
>
> Signed-off-by: Alan Previn
>
alan:snip
> -/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
> -#define PXP43_MAX_HECI_INOUT_SIZE
On Fri, Sep 15, 2023 at 09:48:54AM -0700, Matt Roper wrote:
> On Thu, Sep 14, 2023 at 02:38:50PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The 16k max plane stride limit seems to be originally from
> > i965gm, and no limit explicit limit has been specified since (g4x+).
>
>
On Thu, Sep 14, 2023 at 02:38:50PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The 16k max plane stride limit seems to be originally from
> i965gm, and no limit explicit limit has been specified since (g4x+).
There are maximum limits specified on the PLANE_STRIDE register pages
(bspec
On Fri, Sep 15, 2023 at 09:02:05AM -0700, Umesh Nerlige Ramappa wrote:
On Thu, Sep 14, 2023 at 04:18:34AM +, Patchwork wrote:
Patch Details
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
(rev2)
URL:
On Wed, 13 Sep 2023, Jani Nikula wrote:
> On Tue, 12 Sep 2023, Matt Roper wrote:
>> On Tue, Sep 12, 2023 at 03:05:37PM +0300, Jani Nikula wrote:
>>> Don't hide display probe in device info code.
>>>
>>> Cc: Matt Roper
>>> Signed-off-by: Jani Nikula
>>> ---
>>>
On Fri, Sep 15, 2023 at 07:55:11AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add Wa_18022495364 (rev2)
> URL : https://patchwork.freedesktop.org/series/123721/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13633_full ->
Zeng, Oak wrote on pią [2023-wrz-15 17:56:56 +0200]:
>
>
> Thanks,
> Oak
>
> > -Original Message-
> > From: Das, Nirmoy
> > Sent: Friday, September 15, 2023 4:34 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> > Piorkowski,
> > Piotr ;
On Thu, Sep 14, 2023 at 04:18:34AM +, Patchwork wrote:
Patch Details
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
(rev2)
URL: [1]https://patchwork.freedesktop.org/series/123616/
State: failure
Details:
== Series Details ==
Series: drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
(rev4)
URL : https://patchwork.freedesktop.org/series/123637/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13635_full -> Patchwork_123637v4_full
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Friday, September 15, 2023 4:34 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ; Das, Nirmoy
>
Reviewed-by: Oak Zeng
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Friday, September 15, 2023 4:34 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ;
On Tue, 12 Sep 2023, Rodrigo Vivi wrote:
> On Tue, Sep 12, 2023 at 03:05:35PM +0300, Jani Nikula wrote:
>> Initializing i915->display.info.__device_info and DISPLAY_RUNTIME_INFO()
>> really belongs in display code. Move them there.
>>
>> Cc: Matt Roper
>> Signed-off-by: Jani Nikula
>
>
On Thu, 14 Sep 2023, Rodrigo Vivi wrote:
> On Thu, Sep 14, 2023 at 12:34:57PM +0300, Jani Nikula wrote:
>> Avoid using GEM_BUG_ON() in display code.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
Thanks, pushed the series.
BR,
Jani.
>
>> ---
>>
> -Original Message-
> From: Nilawar, Badal
> Sent: Friday, September 15, 2023 7:26 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Vivi, Rodrigo
>
> Subject: [PATCH] drm/i915/gt: Update RC6 mask for mtl_drpc
>
> It is seen that for RC6 status register is sometimes
On 9/15/2023 11:50 AM, Jani Nikula wrote:
On Fri, 15 Sep 2023, Nirmoy Das wrote:
Toggle binder context ready status when needed.
To issue gpu commands, the driver must be primed to receive
requests. Maintain binder-based GGTT update disablement until driver
probing completes. Moreover,
Hi Maíra,
Thanks for review.
On Friday, 15 September 2023 16:01:31 CEST Maira Canal wrote:
> Hi,
>
> On 9/11/23 10:03, Janusz Krzysztofik wrote:
> > While drm_mm test was converted form igt selftest to kunit, unexpected
> > value of "end" argument equal "start" was introduced to one of calls to
It is seen that for RC6 status register is sometimes setting unused bits
without affecting functionality. So updated the mask with used bits.
As mtl_drpc is debug fs function removing MISSING_CASE from default case.
Cc: Anshuman Gupta
Signed-off-by: Badal Nilawar
---
On Friday, 15 September 2023 15:09:58 CEST Janusz Krzysztofik wrote:
> Hi Mauro,
>
> On Friday, 15 September 2023 14:28:49 CEST Mauro Carvalho Chehab wrote:
> > On Fri, 8 Sep 2023 14:32:47 +0200
> > Janusz Krzysztofik wrote:
> >
> > Forgot to mention on my past review:
> >
> > > +
Hi Mauro,
On Friday, 15 September 2023 14:28:49 CEST Mauro Carvalho Chehab wrote:
> On Fri, 8 Sep 2023 14:32:47 +0200
> Janusz Krzysztofik wrote:
>
> Forgot to mention on my past review:
>
> > + , ) == 1 && len == strlen(buf))) {
> > + /*
> > +
On Friday, 15 September 2023 14:25:24 CEST Mauro Carvalho Chehab wrote:
> On Wed, 13 Sep 2023 16:04:10 +0200
> Janusz Krzysztofik wrote:
>
> > On Monday, 11 September 2023 11:01:42 CEST Mauro Carvalho Chehab wrote:
> > > On Fri, 8 Sep 2023 14:32:41 +0200
> > > Janusz Krzysztofik wrote:
> > >
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev5)
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13635_full -> Patchwork_122589v5_full
On Fri, 8 Sep 2023 14:32:47 +0200
Janusz Krzysztofik wrote:
Forgot to mention on my past review:
> +, ) == 1 && len == strlen(buf))) {
> + /*
> + * TODO: drop the following workaround as soon as
> + * kernel side issue
On Wed, 13 Sep 2023 16:04:10 +0200
Janusz Krzysztofik wrote:
> On Monday, 11 September 2023 11:01:42 CEST Mauro Carvalho Chehab wrote:
> > On Fri, 8 Sep 2023 14:32:41 +0200
> > Janusz Krzysztofik wrote:
> >
> > > While reading KTAP data from /dev/kmsg we now ignore interrupt signals
> > >
On Fri, 8 Sep 2023 14:32:48 +0200
Janusz Krzysztofik wrote:
> For igt_runner to be able to correlate a stream of IGT results from
> dynamic sub-subtests that correspond to individual kunit test cases, read
> by the igt_runner from stdout / stderr of the test process, with a stream
> of kernel
On Fri, 8 Sep 2023 14:32:47 +0200
Janusz Krzysztofik wrote:
> Current implementation of KTAP parser suffers from several issues:
> - in most cases, kernel messages that are not part of KTAP output but
> happen to appear in between break the parser,
> - results from parametrized test cases,
On Fri, 8 Sep 2023 14:32:50 +0200
Janusz Krzysztofik wrote:
> If a user (an IGT test) doesn't provide a subtest name when calling
> igt_kunit() then we now use the requested kernel module name as IGT
> subtest name. Since names of kunit test modules usually end with a
> "_test" or "_kunit"
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