On Tue, 2023-11-07 at 05:01 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Monday, November 6, 2023 1:33 PM
> > To: dri-de...@lists.freedesktop.org; Manna, Animesh
> > ; intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R ; Nikula, Jani
>
== Series Details ==
Series: DP DSC min/max src bpc fixes (rev2)
URL : https://patchwork.freedesktop.org/series/125571/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_125571v2
Summary
---
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, November 6, 2023 1:33 PM
> To: dri-de...@lists.freedesktop.org; Manna, Animesh
> ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Nikula, Jani
>
> Subject: Re: [PATCH v8 6/6] drm/i915/panelreplay: Debugfs support for
== Series Details ==
Series: DP DSC min/max src bpc fixes (rev2)
URL : https://patchwork.freedesktop.org/series/125571/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
At the moment, while choosing the input bpc for DSC, we take into
account the max_requested_bpc property. This creates a problem, if the
max_requested_bpc is lower than the minimum bpc required by source with
DSC.
So consider max_requested_bpc if its within the limits that we can
support with
Use helpers for source min/max input bpc with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ---
3 files changed, 6 insertions(+), 9
Use correct helper for getting max DSC bpc supported by the source.
Fixes: 1c56e9a39833 ("drm/i915/dp: Get optimal link config to have best
compressed bpp")
Cc: Ankit Nautiyal
Cc: Stanislav Lisovskiy
Cc: Jani Nikula
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
Return 0 if platform doesn't support DSC, and return 12 for Display ver
12+.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
Use helpers for source min/max src bpc appropriately for dp mst case and
to limit max_requested_bpc property min/max values.
Rev2: Dropped patch to limit max_requested_bpc based on src DSC bpc
limits. Instead added change to ignore max_requested_bpc if its
too low for DSC.
Ankit Nautiyal (4):
The reason to dump on GTs is to make consistent SSEU information in i915. It is
fine that the information was moved to i915/gt*.
-Original Message-
From: Tvrtko Ursulin
Sent: Monday, November 6, 2023 8:30 PM
To: Roper, Matthew D
Cc: Yu, Gareth ; intel-gfx@lists.freedesktop.org; Shyti,
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_125490v16
Summary
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Improve BW management on MST links (rev16)
URL : https://patchwork.freedesktop.org/series/125490/
State : warning
== Summary ==
Error: dim checkpatch failed
7c2ff14192aa drm/i915/dp_mst: Fix race between connector registration and setup
3ddb8fb6b152
== Series Details ==
Series: Selftest for FAST_REQUEST feature
URL : https://patchwork.freedesktop.org/series/126044/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_126044v1
Summary
---
**SUCCESS**
== Series Details ==
Series: Selftest for FAST_REQUEST feature
URL : https://patchwork.freedesktop.org/series/126044/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Enabling / disabling DSC decompression in the branch device downstream
of the source may reset the whole branch device. To avoid this while the
streams are still active, force a modeset on all CRTC/ports connected to
this branch device.
v2:
- Check the CRTC state for each connector in the
Enable DSC decompression for all streams. In particular atm if a sink is
connected to a last branch device that is downstream of the first branch
device connected to the source, decompression is not enabled for it.
Similarly it's not enabled if the sink supports this with the last
branch device
Factor out a helper to clear the pipe update flags, used by a follow-up
patch to modeset an MST topology.
v2:
- Move the intel_crtc_needs_modeset() check to the callers. (Ville)
v3 (Ville):
- Rename clear_pipe_update_flags_on_modeset_crtc() to
intel_crtc_flag_modeset().
- Also set
Enable/disable the DSC decompression in the sink/branch from the MST
encoder hooks. This prepares for an upcoming patch toggling DSC for each
stream as needed, but for now keeps the current behavior, as DSC is only
enabled for the first MST stream.
v2:
- Rebased on latest drm-tip.
Reviewed-by:
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
v2:
- Rebase on upstream include "intel_vdsc.h" change.
Reviewed-by: Stanislav Lisovskiy
The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK
period, presumedly to save BW, which the hub expands before forwarding
the stream to the sink. In particular a 4k mode with a standard CVT
HBLANK period is exposed with either a CVT reduced blank RBv1,v2 (80,
160 pixel) or a
Atm, the BW allocated for an MST stream doesn't take into account the
DSC control symbol (EOC) and data alignment overhead on the local (first
downstream) MST link (reflected by the data M/N/TU values) and - besides
the above overheads - the FEC symbol overhead on 8b/10b remote
(after a downstream
Add helpers drivers can use to calculate the BW allocation overhead -
due to SSC, FEC, DSC and data alignment on symbol cycles - and the
channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
128b/132b links the FEC overhead is part of the coding efficiency, so
not accounted for in
From: John Harrison
There is a mechanism for reporting errors from fire and forget H2G
messages. This is the only way to find out about almost any error in
the GuC backend submission path. So it would be useful to know that it
is working.
Signed-off-by: John Harrison
---
From: John Harrison
Noticed that the hangcheck selftest is submitting a non-preemptoble
spinner. That means that even if the GuC does not die, the heartbeat
will still kick in and trigger a reset. Which is rather defeating the
purpose of the test - to verify that the heartbeat will kick in if
From: John Harrison
Add a selftest to verify that the FAST_REQUEST mechanism (getting
errors back from fire-and-forget H2G commands) is functional.
Also fix up a potential false positive in the GuC hang selftest.
Signed-off-by: John Harrison
John Harrison (2):
drm/i915/guc: Fix for
== Series Details ==
Series: drm/i915: Audio fastset, and some fixes
URL : https://patchwork.freedesktop.org/series/126041/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_126041v1
Summary
---
== Series Details ==
Series: drm/i915: Audio fastset, and some fixes
URL : https://patchwork.freedesktop.org/series/126041/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/xelpmp: Add Wa_16021867713 (rev2)
URL : https://patchwork.freedesktop.org/series/126033/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_126033v2
Summary
---
On Mon, Nov 06, 2023 at 11:31:51PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> > Add helpers drivers can use to calculate the BW allocation overhead -
> > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > channel coding efficiency
== Series Details ==
Series: drm/i915: Fix potential spectre vulnerability (rev2)
URL : https://patchwork.freedesktop.org/series/125950/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_125950v2
Summary
== Series Details ==
Series: drm/i915: Fix potential spectre vulnerability (rev2)
URL : https://patchwork.freedesktop.org/series/125950/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
On Mon, Nov 06, 2023 at 10:49:13PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > Atm, the BW allocated for an MST stream doesn't take into account the
> > DSC control symbol (EOC) and data alignment overhead on the local (first
> > downstream) MST
On Mon, Oct 30, 2023 at 05:58:22PM +0200, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC
On Mon, Nov 06, 2023 at 11:15:54PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 06, 2023 at 11:02:32PM +0200, Imre Deak wrote:
> > On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> > > On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > > > Atm, the BW allocated for an MST
From: Ville Syrjälä
There's no real why we'd need a full modeset for audio changes.
So let's allow audio to be toggled during fastset. In case the
ELD changes while has_audio isn't changing state we force both
audio disable and enable so the new ELD gets propagated to the
audio driver.
From: Ville Syrjälä
Relocate the audio enable/disable from the full modeset hooks into
the common pre/post plane update stage of the commit. Audio fastset
is within easy reach now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 31 +++-
1 file
From: Ville Syrjälä
Push he encoder->audio_{enable,disable}() calls out from the
encoder->{enable,disable}() hooks. Moving towards audio fastset.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c| 2 -
drivers/gpu/drm/i915/display/g4x_hdmi.c | 10
From: Ville Syrjälä
Add encoder vfuncs for audio enable/disable. This will enable
audio to be enable/disabe during fastsets. An encoder hook
is necessary as on pre-hsw platforms different encoder types
implement audio in different ways.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Follow the hsw+ approach toggle the audio presence detect
when we set up the ELD, instead of doing it when turning the
port on/off.
This will facilitate audio enable/disable to happen during
fastsets instead of requiring a full modeset.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Follow the hsw+ approach toggle the audio presence detect
when we set up the ELD, instead of doing it when turning the
port on/off.
This will facilitate audio enable/disable to happen during
fastsets instead of requiring a full modeset.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Put a wrapper around the intel_audio_codec_{enable,disable}()
calls in the g4x+ DP/HDMI code. We shall move the presence
detect enable/disable into the wrappers later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 26 --
From: Ville Syrjälä
Push the audio enable/disable to be the last/first thing
respectively that is done in the encoder enable/disable hooks.
The goal is to move it further out of these encoder hooks entirely.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 8
From: Ville Syrjälä
Doing the if-else around RMWs is kinda silly. Just set/clear the
apporiate bits with a single RMW.
Also unify the coding style a bit icl_wa_cursorclkgating() while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 19
From: Ville Syrjälä
We used to call intel_pre_plane_updates() for any pipe going through
a modeset whether the pipe was previously enabled or not. This in
fact needed to apply all the necessary clock gating workarounds/etc.
Restore the correct behaviour.
Fixes: 39919997322f ("drm/i915: Disable
From: Ville Syrjälä
Implement audio fastset. Probably mosy useful in avoiding
some fastboot blinks, runtime audio fastset is less likely
to be a typical use case.
Also try to fix up a mess with pre_plane_update() vs.
already disabled pipe.
Ville Syrjälä (11):
drm/i915: Check pipe active
From: Ville Syrjälä
{planes,vrr}_{enabling,disabling}() are supposed to indicate
whether the specific hardware feature is supposed to be enabling
or disabling. That can only makes sense if the pipe is active
overall. So check for that before we go poking at the hardware.
I think we're semi-safe
On Mon, Nov 06, 2023 at 11:02:32PM +0200, Imre Deak wrote:
> On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > > Atm, the BW allocated for an MST stream doesn't take into account the
> > > DSC control symbol (EOC) and
On Mon, Nov 06, 2023 at 10:39:25PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> > Atm, the BW allocated for an MST stream doesn't take into account the
> > DSC control symbol (EOC) and data alignment overhead on the local (first
> > downstream) MST
== Series Details ==
Series: series starting with [CI,1/9] tests/i915/drm_fdinfo: Check engine info
is supported
URL : https://patchwork.freedesktop.org/series/126024/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/126024/revisions/1/mbox/ not
On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> Atm, the BW allocated for an MST stream doesn't take into account the
> DSC control symbol (EOC) and data alignment overhead on the local (first
> downstream) MST link (reflected by the data M/N/TU values) and - besides
> the above
On Mon, Oct 30, 2023 at 05:58:26PM +0200, Imre Deak wrote:
> Atm, the BW allocated for an MST stream doesn't take into account the
> DSC control symbol (EOC) and data alignment overhead on the local (first
> downstream) MST link (reflected by the data M/N/TU values) and - besides
> the above
Quoting Matt Roper (2023-11-06 17:07:21-03:00)
>On Mon, Nov 06, 2023 at 04:46:27PM -0300, Gustavo Sousa wrote:
>> This workaround applies to all steppings of Xe_LPM+. Implement the KMD
>> part.
>>
>> Signed-off-by: Gustavo Sousa
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
>>
== Series Details ==
Series: drm/i915/display: Support PSR entry VSC packet to be transmitted one
frame earlier (rev4)
URL : https://patchwork.freedesktop.org/series/125558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_125558v4
This workaround applies to all steppings of Xe_LPM+. Implement the KMD
part.
v2:
- Put the definition of VDBOX_CGCTL3F1C() in the correct sort order.
(Matt)
Reviewed-by: Matt Roper
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 2 ++
On Thu, Nov 02, 2023 at 11:55:18PM +0200, Vinod Govindapillai wrote:
> If both PSR2 + FBC is supported, in cases where the selective
> fetch area is greater than 25% of the screen area, FBC might
> be more efficient.
"might be more efficient" is a very weak justification.
This sort of stuff
== Series Details ==
Series: drm/i915/display: Support PSR entry VSC packet to be transmitted one
frame earlier (rev4)
URL : https://patchwork.freedesktop.org/series/125558/
State : warning
== Summary ==
Error: dim checkpatch failed
bf91ea0e1133 drm/i915/display: Support PSR entry VSC packet
On Mon, Nov 06, 2023 at 04:46:27PM -0300, Gustavo Sousa wrote:
> This workaround applies to all steppings of Xe_LPM+. Implement the KMD
> part.
>
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 14
On Tue, Oct 31, 2023 at 10:45:57AM +0200, Jouni Högander wrote:
> intel_atomic_commit_tail(state);
> }
>
> -static int
> -intel_atomic_commit_ready(struct i915_sw_fence *fence,
> - enum i915_sw_fence_notify notify)
> -{
> - struct intel_atomic_state *state =
> -
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Remove incomplete PVC plumbing
URL : https://patchwork.freedesktop.org/series/126013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_126013v1
This workaround applies to all steppings of Xe_LPM+. Implement the KMD
part.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++
2 files changed, 17 insertions(+)
diff --git
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Remove incomplete PVC plumbing
URL : https://patchwork.freedesktop.org/series/126013/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/vma: Fix potential UAF on multi-tile platforms
URL : https://patchwork.freedesktop.org/series/126012/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13844 -> Patchwork_126012v1
Summary
== Series Details ==
Series: drm/i915/mtl: C20 state verification (rev3)
URL : https://patchwork.freedesktop.org/series/125855/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13843 -> Patchwork_125855v3
Summary
---
Hi Jonathan,
On Thu, Nov 02, 2023 at 10:58:31AM -0700, Jonathan Cavitt wrote:
> FIXME: It is suspected that some Address Translation Service (ATS)
> issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> Applying a write barrier to the ppgtt set entry functions appeared
> to have
Dual-license drm_gpuvm to GPL-2.0 OR MIT.
diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c
index 02ce6baacdad..08c088319652 100644
--- a/drivers/gpu/drm/drm_gpuvm.c
Hi Tvrtko,
Thank you very much for your kind suggestion, I have modified it in
accordance with your suggestion.
On 2023/11/2 19:32, Tvrtko Ursulin wrote:
On 02/11/2023 10:16, chentao wrote:
Fix smatch warning:
drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu()
warn:
Fix smatch warning:
drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu()
warn: potential spectre issue 'pc->user_engines' [r] (local cap)
Signed-off-by: chentao
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Fix smatch warning:
drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu()
warn: potential spectre issue 'pc->user_engines' [r] (local cap)
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create
parameters (v5)")
Cc: # v5.15+
Signed-off-by: Kunwu Chan
On Mon, Nov 06, 2023 at 01:01:19PM +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Friday, November 3, 2023 2:55 PM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org; Maxime Ripard ; Thomas
> > Zimmermann ; Maarten Lankhorst
> >
> >
> -Original Message-
> From: Nikula, Jani
> Sent: Friday, November 3, 2023 2:55 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org; Maxime Ripard ; Thomas
> Zimmermann ; Maarten Lankhorst
>
> Cc: dri-de...@lists.freedesktop.org; Manna, Animesh
> ; Hogander, Jouni
> ; Murthy,
On 11/6/2023 1:45 PM, Jani Nikula wrote:
On Wed, 25 Oct 2023, Nirmoy Das wrote:
Handle platforms with multiple GTs by iterate over all GTs.
Add a Fixes commit so this gets propagated for MTL support.
Fixes: 213c43676beb ("drm/i915/mtl: Remove the 'force_probe' requirement for Meteor
Lake")
On Mon, 2023-11-06 at 13:42 +0200, Mika Kahola wrote:
> Display driver shall read DPCD 00071h[3:1] during configuration
> to get PSR setup time. This register provides the setup time
> requirement on the VSC SDP entry packet. If setup time cannot be
> met with the current timings
> (e.g., PSR
On Wed, 25 Oct 2023, Nirmoy Das wrote:
> Handle platforms with multiple GTs by iterate over all GTs.
> Add a Fixes commit so this gets propagated for MTL support.
>
> Fixes: 213c43676beb ("drm/i915/mtl: Remove the 'force_probe' requirement for
> Meteor Lake")
This came up in another patch. I
On Mon, 06 Nov 2023, Janusz Krzysztofik
wrote:
> Hi Jani,
>
> Thanks for looking at this.
>
> On Monday, 6 November 2023 10:53:11 CET Jani Nikula wrote:
>> On Mon, 06 Nov 2023, Janusz Krzysztofik
> wrote:
>> > Object debugging tools were sporadically reporting illegal attempts to
>> > free a
On 03/11/2023 18:32, Kamil Konieczny wrote:
Hi Tvrtko,
On 2023-10-12 at 09:15:40 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
A short smoke tests to exercise fdinfo reads in parallel to contexts
getting created and destroyed.
Signed-off-by: Tvrtko Ursulin
---
From: Tvrtko Ursulin
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
and accumulate object size into the respective drm_memory_stats
categories.
From: Tvrtko Ursulin
Account page table backing store against the owning client memory usage
stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Tvrtko Ursulin
Account ring buffers and logical context space against the owning client
memory usage stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_context.c | 14 ++
drivers/gpu/drm/i915/i915_drm_client.c | 10
From: Tvrtko Ursulin
At the moment memory region names are a bit too varied and too
inconsistent to be used for ABI purposes, like for upcoming fdinfo
memory stats.
System memory can be either system or system-ttm. Local memory has the
instance number appended, others do not. Not only
From: Tvrtko Ursulin
In order to show per client memory usage lets add some infrastructure
which enables tracking buffer objects owned by clients.
We add a per client list protected by a new per client lock and to support
delayed destruction (post client exit) we make tracked objects hold
From: Tvrtko Ursulin
To enable accounting of indirect client memory usage (such as page tables)
in the following patch, lets start recording the creator of each PPGTT.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11
From: Tvrtko Ursulin
Test-with: 20231106123518.588528-1-tvrtko.ursu...@linux.intel.com
Tvrtko Ursulin (6):
drm/i915: Add ability for tracking buffer objects per client
drm/i915: Record which client owns a VM
drm/i915: Track page table backing store usage
drm/i915: Account ring buffer
From: Tvrtko Ursulin
Similar as we can toggle between aggregated engines and clients, add the
capability to toggle between aggregated and per memory region stats.
It starts in aggregated mode by default and interactive command 'm' and
command line switch '-m' can be used to toggle that.
Both
From: Tvrtko Ursulin
JSON output has the full breakdown but for now the interactive mode only
shows total and resident aggregated for all memory regions.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
tools/intel_gpu_top.c | 114 +-
1
From: Tvrtko Ursulin
Wrap all operations on clients via the Intel specific wrappers in order to
simplify upcoming work.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
tools/intel_gpu_top.c | 42 ++
1 file changed, 22 insertions(+), 20
From: Tvrtko Ursulin
Same concept as with the engine map, allowing callers to pass in fixed
map of names to indices, simplifying their implementation and avoiding
auto-detection while parsing.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
lib/igt_drm_clients.c | 5 +++--
From: Tvrtko Ursulin
Igt_drm_fdinfo defines it as an unsigned long so it is best that it
matches here as well.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
lib/igt_drm_clients.c | 2 +-
lib/igt_drm_clients.h | 2 +-
tools/intel_gpu_top.c | 2 +-
3 files changed, 3
From: Tvrtko Ursulin
I will need some record of which regions were found for intel_gpu_top so
lets just copy over the region name from the map on the first match.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
lib/igt_drm_fdinfo.c | 4
1 file changed, 4 insertions(+)
From: Tvrtko Ursulin
A few basic smoke tests to check per client memory info looks legit.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
tests/intel/drm_fdinfo.c | 217 +++
1 file changed, 217 insertions(+)
diff --git
From: Tvrtko Ursulin
A short smoke tests to exercise fdinfo reads in parallel to contexts
getting created and destroyed.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
tests/intel/drm_fdinfo.c | 68
1 file changed, 68 insertions(+)
From: Tvrtko Ursulin
On top of checking that parsing works, check that there are some engines
present. This will be needed once the memory stats are added and so return
value from __igt_parse_drm_fdinfo() will then be possible to be greater
than zero even when engine stats are not supported.
On 03/11/2023 17:24, Matt Roper wrote:
On Fri, Nov 03, 2023 at 11:17:18AM +, Tvrtko Ursulin wrote:
On 03/11/2023 05:29, Gareth Yu wrote:
Print another SSEU information addition to the first one.
Cc : Tejas Upadhyay
Cc : Matt Roper
Cc : Ville Syrjälä
Signed-off-by: Gareth Yu
---
Display driver shall read DPCD 00071h[3:1] during configuration
to get PSR setup time. This register provides the setup time
requirement on the VSC SDP entry packet. If setup time cannot be
met with the current timings
(e.g., PSR setup time + other blanking requirements > blanking time),
driver
On Sat, Nov 04, 2023 at 01:50:20PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev3)
> URL : https://patchwork.freedesktop.org/series/125895/
> State : failure
Thanks for the review, pushed to -din with the commit log fixed.
The
On Mon, Nov 06, 2023 at 11:37:34AM +0100, Thomas Hellström wrote:
> On 11/6/23 11:20, Maxime Ripard wrote:
> > On Mon, Nov 06, 2023 at 11:01:51AM +0100, Thomas Hellström wrote:
> > > Hi, David.
> > >
> > > On 11/3/23 17:37, David Edelsohn wrote:
> > > > Dual-license drm_gpuvm to GPL-2.0 OR MIT.
>
On 11/6/23 11:37, Thomas Hellström wrote:
Hi,
On 11/6/23 11:20, Maxime Ripard wrote:
On Mon, Nov 06, 2023 at 11:01:51AM +0100, Thomas Hellström wrote:
Hi, David.
On 11/3/23 17:37, David Edelsohn wrote:
Dual-license drm_gpuvm to GPL-2.0 OR MIT.
diff --git a/drivers/gpu/drm/drm_gpuvm.c
On Wed, 27 Sep 2023 14:38:37 +0100, Tvrtko Ursulin wrote:
> It is better not to lose precision and not revert to 1 MiB size
> granularity for every size greater than 1 MiB.
>
> Sizes in KiB should not be so troublesome to read (and in fact machine
> parsing is I expect the norm here), they align
Hi,
On 11/6/23 11:20, Maxime Ripard wrote:
On Mon, Nov 06, 2023 at 11:01:51AM +0100, Thomas Hellström wrote:
Hi, David.
On 11/3/23 17:37, David Edelsohn wrote:
Dual-license drm_gpuvm to GPL-2.0 OR MIT.
diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c
index
On Thu, 2023-11-02 at 23:55 +0200, Vinod Govindapillai wrote:
> If both PSR2 + FBC is supported, in cases where the selective
> fetch area is greater than 25% of the screen area, FBC might
> be more efficient. So have a possibility to check this and add
> provision to enable FBC in such cases.
>
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