Hello, again.
On Mon, Dec 04, 2023 at 04:03:47PM +, Naohiro Aota wrote:
...
> In summary, we misuse max_active, considering it is a global limit. And,
> the recent commit introduced a huge performance drop in some cases. We
> need to review alloc_workqueue() usage to check if its max_active
On Tue, Dec 19, 2023 at 05:49:52PM -0800, Radhakrishna Sripada wrote:
> Discrete cards do not have ACPI opregion. The vbt is stored in a special
> flash accessible by the display controller. In order to access the vbt
> in such cases, re-use the vbt, vbt_size fields in the opregion structure.
Discrete cards do not have ACPI opregion. The vbt is stored in a special
flash accessible by the display controller. In order to access the vbt
in such cases, re-use the vbt, vbt_size fields in the opregion structure.
We should move away from storing the vbt in the opregion and store it,
if
We are relying on end-less if-else ladders for a type-c phy
capabilities check. Though it made sense when platforms supported
legacy type-c support, modern platforms rely on the information
passed by vbt. This cleanup restricts the if-else ladder to the
platforms supporting legacy type-c phys and
intel_bios_encoder_data_lookup takes enum port as an argument. A variant
based out of phy based lookup is required to be used out of vbt code which
will be introduced in a later patch. Hence indicate the current variant as
intel_bios_encoder_port_data_lookup.
Signed-off-by: Radhakrishna Sripada
Starting MTL and DG2 if a phy is not marked as USB-typeC or TBT capable
by vbt we should not consider it as a Legacy type-c phy.
The concept of Legacy-tc existed in platforms from Icelake to Alder lake
where an external FIA can be routed to one of the phy's thus making the phy
tc capable without
This patch introduces phy version of intel_encoder_port_data_lookup.
Port based variant is dependent on vbt child data extraction and
conversion to port data to be used further. Port data is not immediately
available and is difficult to be determined from phy info.
Signed-off-by: Radhakrishna
From: John Harrison
Avoid the following lockdep complaint:
<4> [298.856498] ==
<4> [298.856500] WARNING: possible circular locking dependency detected
<4> [298.856503] 6.7.0-rc5-CI_DRM_14017-g58ac4ffc75b6+ #1 Tainted: G
N
<4> [298.856505]
== Series Details ==
Series: drm/i915/mtl: Add fake PCH for Meteor Lake (rev2)
URL : https://patchwork.freedesktop.org/series/127963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14045 -> Patchwork_127963v2
Summary
== Series Details ==
Series: drm/i915/mtl: Add fake PCH for Meteor Lake (rev2)
URL : https://patchwork.freedesktop.org/series/127963/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, 13 Dec 2023, Khaled Almahallawy wrote:
> Starting from DP2.0 specs, DPCD 248h is renamed
> LINK_QUAL_PATTERN_SELECT and it has the same values of registers
> DPCD 10Bh-10Eh.
> Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add
> CP2520 Pattern 3 (TPS4) phy pattern
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
On 12/19/2023 10:39 PM, Matt Roper wrote:
On Tue, Dec 19, 2023 at 02:58:00PM +0530, Haridhar Kalvala wrote:
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC
On Mon, Dec 18, 2023 at 11:46:44AM +, Shuicheng Lin wrote:
> Some of the wa registers are MCR registers, which have different
> read/write process with normal MMIO registers.
> Add function intel_gt_is_mcr_reg to check whether it is mcr register
> or not.
>
> Signed-off-by: Shuicheng Lin
>
On Tue, Dec 19, 2023 at 02:58:00PM +0530, Haridhar Kalvala wrote:
> Correct the implementation trying to detect MTL PCH with
> the MTL fake PCH id.
>
> On MTL, both the North Display (NDE) and South Display (SDE) functionality
> reside on the same die (the SoC die in this case), unlike many past
In order to introduce a pwm api which can be used from atomic context,
we will need two functions for applying pwm changes:
int pwm_apply_might_sleep(struct pwm *, struct pwm_state *);
int pwm_apply_atomic(struct pwm *, struct pwm_state *);
This commit just deals with renaming
On Tue, 19 Dec 2023, Ville Syrjälä wrote:
> On Tue, Dec 19, 2023 at 12:47:46PM +0200, Jani Nikula wrote:
>> intel_hdcp_get_repeater_ctl() is supposed to return unsigned register
>> contents. Returning negative error values is unexpected, and none of the
>> callers check for that.
>>
>> Sort of
Hi Jonathan,
On Mon, Dec 18, 2023 at 06:33:44PM +, Cavitt, Jonathan wrote:
...
> > On Tue, Nov 28, 2023 at 08:25:05AM -0800, Jonathan Cavitt wrote:
> > > Never block for outstanding work on userptr object upon receipt of a
> > > mmu-notifier. The reason we originally did so was to immediately
On 13/12/2023 14:13, Christian König wrote:
Am 13.12.23 um 12:46 schrieb Tvrtko Ursulin:
Hi,
On 12/12/2023 14:10, Christian König wrote:
Hi Tvrtko,
Thanks for pointing this mail out once more, I've totally missed it.
That's okay, if it was really urgent I would have re-raised the thread
== Series Details ==
Series: drm/i915: Rework global state serialization
URL : https://patchwork.freedesktop.org/series/127968/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14042 -> Patchwork_127968v1
Summary
---
== Series Details ==
Series: drm/i915: Cursor vblank evasion
URL : https://patchwork.freedesktop.org/series/127744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14017_full -> Patchwork_127744v1_full
Summary
---
== Series Details ==
Series: drm/i915: Rework global state serialization
URL : https://patchwork.freedesktop.org/series/127968/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/display: Skip C10 state verification in case of fastset
URL : https://patchwork.freedesktop.org/series/127966/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14042 -> Patchwork_127966v1
From: Ville Syrjälä
Pull all the state swap stuff into its own function to declutter
intel_atomic_commit() a bit.
Note that currently the state swap is spread across both
sides of the unprepare branch in intel_atomic_commit(), but
we can pull all of it ahead a bit since we bail on the first
From: Ville Syrjälä
Instead of injecting extra crtc commits to serialize the global
state let's hand roll a but of commit machinery to take care of
the hardware synchronization.
Rather than basing everything on the crtc commits we track these
as their own thing. I think this makes more sense as
From: Ville Syrjälä
drm_atomic_check_only() gets upset if we try to add extra crtcs
to any commit that isn't flagged with DRM_MODE_ATOMIC_ALLOW_MODESET.
This conflicts with how SAGV watermarks work on pre-ADL as we
need to manually switch over the SAGV watermarks before we can
safely enable
From: Ville Syrjälä
Rework the way we do the hardware serialization with
global states. This avoids angering drm_atomic_check_only(),
and I suppose it's a bit more efficient as well.
Ville Syrjälä (3):
drm/i915: Compute use_sagv_wm differently
drm/i915: Rework global state serializaiton
On Tue, Dec 19, 2023 at 12:47:46PM +0200, Jani Nikula wrote:
> intel_hdcp_get_repeater_ctl() is supposed to return unsigned register
> contents. Returning negative error values is unexpected, and none of the
> callers check for that.
>
> Sort of fix the error cases by returning 0. I don't think
== Series Details ==
Series: drm/i915/display: Skip C10 state verification in case of fastset
URL : https://patchwork.freedesktop.org/series/127966/
State : warning
== Summary ==
Error: dim checkpatch failed
9b8ec3f52711 drm/i915/display: Skip C10 state verification in case of fastset
-:8:
== Series Details ==
Series: drm/i915/display: Skip C10 state verification in case of fastset
URL : https://patchwork.freedesktop.org/series/127966/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/127966/revisions/1/mbox/ not
found
On Tue, Dec 19, 2023 at 12:47:45PM +0200, Jani Nikula wrote:
> It's customary to debug log connectors using [CONNECTOR:%d:%s]
> format. Make the HDCP code follow suit.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 68
On Tue, Dec 19, 2023 at 11:55:01AM +0100, Andrzej Hajda wrote:
> On 15.12.2023 11:59, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Declutter initial_plane_vma() a bit by pulling the lmem and smem
> > readout paths into their own functions.
> >
> > TODO: the smem path should still be
PLL's are not programmed in case of fastset so the state
verfication compares bios programmed PLL values against
sw PLL values. To overcome this limitation, we can skip
the state verification for C10 in fastset case as the
driver is not writing PLL values.
Signed-off-by: Mika Kahola
---
> I created an immutable branch for this which the buildbots will
> hopefully check over night. I will reply with comments tomorrow when I
> got the buildbot results.
Applied to for-next, thanks!
signature.asc
Description: PGP signature
== Series Details ==
Series: series starting with [1/2] drm/i915/hdcp: unify connector logging format
URL : https://patchwork.freedesktop.org/series/127965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14042 -> Patchwork_127965v1
== Series Details ==
Series: drm/i915: Cursor vblank evasion
URL : https://patchwork.freedesktop.org/series/127744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14017 -> Patchwork_127744v1
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/mtl: Add fake PCH for Meteor Lake
URL : https://patchwork.freedesktop.org/series/127963/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14042 -> Patchwork_127963v1
Summary
---
== Series Details ==
Series: drm/i915/mtl: Add fake PCH for Meteor Lake
URL : https://patchwork.freedesktop.org/series/127963/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable Adaptive Sync SDP Support for DP (rev5)
URL : https://patchwork.freedesktop.org/series/126829/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14042 -> Patchwork_126829v5
Summary
---
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
There's no reason the caller of intel_initial_plane_config() should
have to loop over the CRTCs. Pull the loop into the function to
make life simpler for the caller.
Cc: Paz Zcharya
Signed-off-by: Ville Syrjälä
Reviewed-by:
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
MTL stolen memory looks more like local memory, so use the
(now fixed) lmem path when doing the initial plane readout.
Cc: Paz Zcharya
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_plane_initial.c| 25
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
The address we read from the PTE is a dma address, not a physical
address. Rename the variable to say so.
Cc: Paz Zcharya
Signed-off-by: Ville Syrjälä
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
On 15.12.2023 11:59, Ville Syrjala wrote:
From: Ville Syrjälä
Declutter initial_plane_vma() a bit by pulling the lmem and smem
readout paths into their own functions.
TODO: the smem path should still be fixed to get and validate
the dma address from the pte as well
Cc: Paz Zcharya
intel_hdcp_get_repeater_ctl() is supposed to return unsigned register
contents. Returning negative error values is unexpected, and none of the
callers check for that.
Sort of fix the error cases by returning 0. I don't think we should hit
these cases anyway, and using 0 for the registers is safer
== Series Details ==
Series: Enable Adaptive Sync SDP Support for DP (rev5)
URL : https://patchwork.freedesktop.org/series/126829/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
It's customary to debug log connectors using [CONNECTOR:%d:%s]
format. Make the HDCP code follow suit.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 68 +++
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
On 12/18/2023 9:24 PM, Matt Roper wrote:
Oh, and one more thing I forgot to mention before hitting send...the
title for this patch doesn't make sense. Xe_LPG is the graphics IP used
by MTL; that's completely unrelated to the display IP (which is
Xe_LPD+).
Since we're assigning the fake PCH
On Tue, 19 Dec 2023, Jouni Högander wrote:
Commit message goes here.
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 103 ++
> 1 file changed, 103 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used.
An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.
Computes AS SDP values based on the
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used.
An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.
Computes AS SDP values based on the
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used.
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.
Computes AS SDP values based on the
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