WA 14019877138 needed for Graphics 12.70/71 both
V2(Jani):
- Use drm/i915
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
From: John Harrison
A failure to load the HuC is occasionally observed where the cause is
believed to be a low GT frequency leading to very long load times.
So a) increase the timeout so that the user still gets a working
system even in the case of slow load. And b) report the frequency
during
On Tue, 02 Jan 2024, Juha-Pekka Heikkila wrote:
> Aux ccs framebuffers don't work on Xe driver hence disable them
> from plane capabilities until they are fixed. Flat ccs framebuffers
> work and they are left enabled. Here is separated plane capabilities
> check on i915 so it can behave
Aux ccs framebuffers don't work on Xe driver hence disable them
from plane capabilities until they are fixed. Flat ccs framebuffers
work and they are left enabled. Here is separated plane capabilities
check on i915 so it can behave differencly depending on the driver.
Closes:
On Tue, Jan 02, 2024 at 01:02:31AM +, Shuicheng Lin wrote:
> Some of the wa registers are MCR register, and EU_PERF_CNTL registers
> are MCR register.
> MCR register needs extra process for read/write.
> As normal MMIO register also could work with the MCR register process,
> change all wa
On Wed, 2023-12-27 at 20:55 -0800, Teres Alexis, Alan Previn wrote:
> This series is the result of debugging issues root caused to
> races between the GuC's destroyed_worker_func being triggered
> vs repeating suspend-resume cycles with concurrent delayed
> fence signals for engine-freeing.
>
LGTM
Reviewed-by: Swati Sharma
On 13-Dec-23 2:46 PM, Ankit Nautiyal wrote:
Use correct helper for getting max DSC bpc supported by the source.
Fixes: 1c56e9a39833 ("drm/i915/dp: Get optimal link config to have best compressed
bpp")
Cc: Ankit Nautiyal
Cc: Stanislav Lisovskiy
Cc: Jani
Hi Maxime
On Mon, 14 Nov 2022 at 13:00, Maxime Ripard wrote:
>
> The current construction of the named mode parsing doesn't allow to extend
> it easily. Let's move it to a separate function so we can add more
> parameters and modes.
>
> In order for the tests to still pass, some extra checks are
On Tue, 02 Jan 2024, Tejas Upadhyay wrote:
> WA 14019877138 needed for Graphics 12.70/71 both
You're changing i915. The subject prefix should be drm/i915.
BR,
Jani.
>
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 1 file changed, 3
WA 14019877138 needed for Graphics 12.70/71 both
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index
The function intel_c20_use_mplla() is not really
widely used and can be replaced with the more suitable
pll->tx[0] & C20_PHY_USE_MPLLB
expression. Let's remove the intel_c20_use_mplla()
alltogether and replace mplla/mpllb selection by
checking mpllb bit.
Signed-off-by: Mika Kahola
---
We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 97
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if
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