Re: [PATCH] drm/xe/display: check for error on drmm_mutex_init
On Thu, Mar 21, 2024 at 05:04:51AM +, Murthy, Arun R wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Wednesday, March 20, 2024 6:06 AM
To: Murthy, Arun R
Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Subject: Re: [PATCH] drm/xe/display: check for error on drmm_mutex_init
On Tue, Mar 19, 2024 at 08:33:41AM +0530, Arun R Murthy wrote:
>Check return value for drmm_mutex_init as it can fail and return on
>failure.
>
>Signed-off-by: Arun R Murthy
>---
> drivers/gpu/drm/xe/display/xe_display.c | 24 ++--
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_display.c
>b/drivers/gpu/drm/xe/display/xe_display.c
>index e4db069f0db3..c59fa832758d 100644
>--- a/drivers/gpu/drm/xe/display/xe_display.c
>+++ b/drivers/gpu/drm/xe/display/xe_display.c
>@@ -107,12 +107,24 @@ int xe_display_create(struct xe_device *xe)
>
>xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
>
>- drmm_mutex_init(>drm, >sb_lock);
>- drmm_mutex_init(>drm, >display.backlight.lock);
>- drmm_mutex_init(>drm, >display.audio.mutex);
>- drmm_mutex_init(>drm, >display.wm.wm_mutex);
>- drmm_mutex_init(>drm, >display.pps.mutex);
>- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
>+ err = drmm_mutex_init(>drm, >sb_lock);
>+ if (err)
>+ return err;
>+ err = drmm_mutex_init(>drm, >display.backlight.lock);
>+ if (err)
>+ return err;
>+ err = drmm_mutex_init(>drm, >display.audio.mutex);
>+ if (err)
>+ return err;
>+ err = drmm_mutex_init(>drm, >display.wm.wm_mutex);
>+ if (err)
>+ return err;
>+ err = drmm_mutex_init(>drm, >display.pps.mutex);
>+ if (err)
>+ return err;
>+ err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
>+ if (err)
>+ return err;
humn... but not very pretty. What about?
if ((err = drmm_mutex_init(>drm, >sb_lock)) ||
(err = drmm_mutex_init(>drm, >display.backlight.lock)) ||
(err = ...))
return err;
I think there are few places in life for assignment + check in single statement,
but IMO this is one of them where the alternative is uglier and more error
prone.
thoughts?
We should not proceed with the remaining mutex_init in case of failures. As an
alternative we can have
with the code above, we are not proceeding with the other drmm_mutex_init()
initializations.
foo() || bar() doesn't execute bar() if foo() returned != 0.
Lucas De Marchi
drmm_mutex_init(var1) ? (drmm_mutex_init(var2) ? drmm_mutex_init(var3) : return
ret) : return ret;
With the existing one traversing the code is more easier, these optimization
might make the code look complex.
Thanks and Regards,
Arun R Murthy
Lucas De Marchi
>xe->enabled_irq_mask = ~0;
>
>err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
>--
>2.25.1
>
✓ Fi.CI.BAT: success for drm/i915/display: Fixed a screen flickering when turning on display from off (rev6)
== Series Details == Series: drm/i915/display: Fixed a screen flickering when turning on display from off (rev6) URL : https://patchwork.freedesktop.org/series/130780/ State : success == Summary == CI Bug Log - changes from CI_DRM_14459 -> Patchwork_130780v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/index.html Participating hosts (36 -> 35) -- Additional (2): bat-dg1-7 bat-jsl-1 Missing(3): bat-kbl-2 fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_130780v6 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][7] ([i915#6621]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4212]) +7 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4215]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-1: NOTRUN -> [SKIP][11] ([i915#4103]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-jsl-1: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9886]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@kms_...@dsc-basic.html - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html - bat-jsl-1: NOTRUN -> [SKIP][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html - bat-dg1-7: NOTRUN -> [SKIP][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg1-7/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#5274]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#5354]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130780v6/bat-dg2-8/igt@kms_frontbuffer_track...@basic.html * igt@kms_hdmi_inject@inject-audio: -
RE: [PATCH] drm/xe/display: check for error on drmm_mutex_init
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, March 20, 2024 6:06 AM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/xe/display: check for error on drmm_mutex_init
>
> On Tue, Mar 19, 2024 at 08:33:41AM +0530, Arun R Murthy wrote:
> >Check return value for drmm_mutex_init as it can fail and return on
> >failure.
> >
> >Signed-off-by: Arun R Murthy
> >---
> > drivers/gpu/drm/xe/display/xe_display.c | 24 ++--
> > 1 file changed, 18 insertions(+), 6 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/xe/display/xe_display.c
> >b/drivers/gpu/drm/xe/display/xe_display.c
> >index e4db069f0db3..c59fa832758d 100644
> >--- a/drivers/gpu/drm/xe/display/xe_display.c
> >+++ b/drivers/gpu/drm/xe/display/xe_display.c
> >@@ -107,12 +107,24 @@ int xe_display_create(struct xe_device *xe)
> >
> > xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
> >
> >-drmm_mutex_init(>drm, >sb_lock);
> >-drmm_mutex_init(>drm, >display.backlight.lock);
> >-drmm_mutex_init(>drm, >display.audio.mutex);
> >-drmm_mutex_init(>drm, >display.wm.wm_mutex);
> >-drmm_mutex_init(>drm, >display.pps.mutex);
> >-drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
> >+err = drmm_mutex_init(>drm, >sb_lock);
> >+if (err)
> >+return err;
> >+err = drmm_mutex_init(>drm, >display.backlight.lock);
> >+if (err)
> >+return err;
> >+err = drmm_mutex_init(>drm, >display.audio.mutex);
> >+if (err)
> >+return err;
> >+err = drmm_mutex_init(>drm, >display.wm.wm_mutex);
> >+if (err)
> >+return err;
> >+err = drmm_mutex_init(>drm, >display.pps.mutex);
> >+if (err)
> >+return err;
> >+err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
> >+if (err)
> >+return err;
>
>
> humn... but not very pretty. What about?
>
> if ((err = drmm_mutex_init(>drm, >sb_lock)) ||
> (err = drmm_mutex_init(>drm, >display.backlight.lock)) ||
> (err = ...))
> return err;
>
> I think there are few places in life for assignment + check in single
> statement,
> but IMO this is one of them where the alternative is uglier and more error
> prone.
>
> thoughts?
>
We should not proceed with the remaining mutex_init in case of failures. As an
alternative we can have
drmm_mutex_init(var1) ? (drmm_mutex_init(var2) ? drmm_mutex_init(var3) : return
ret) : return ret;
With the existing one traversing the code is more easier, these optimization
might make the code look complex.
Thanks and Regards,
Arun R Murthy
> Lucas De Marchi
>
> > xe->enabled_irq_mask = ~0;
> >
> > err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
> >--
> >2.25.1
> >
[PATCH] drm/i915/display: Fixed a screen flickering when turning on display from off
From: Gareth Yu
Turn on the panel from zero brightness of the last state, the panel was
set a maximum PWM in the flow. Once the panel initialization is completed,
the backlight is restored to xero brightness. There is a flckering
generated. This flicker happens in "Screen dimming and power off" of
Google's design and resume from sleep. The sample of DMESG is below.
(suspend)
[53949.248875] i915 :00:02.0: [drm:intel_edp_backlight_off]
[53949.452046] i915 :00:02.0: [drm:intel_backlight_set_pwm_level] set
backlight PWM = 0
(wakeup)
[53986.067356] i915 :00:02.0: [drm:intel_edp_backlight_on]
[53986.067367] i915 :00:02.0: [drm:intel_backlight_enable] pipe A
[53986.067476] i915 :00:02.0: [drm:intel_backlight_set_pwm_level] set
backlight PWM = 96000
[53986.119766] backlight intel_backlight: PM: calling backlight_resume+0x0/0x7a
@ 4916, parent: card0-eDP-1
[53986.119781] backlight intel_backlight: PM: backlight_resume+0x0/0x7a
returned 0 after 0 usecs
[53986.220068] [drm:intel_backlight_device_update_status] updating
intel_backlight, brightness=26321/96000
[53986.220086] i915 :00:02.0: [drm:intel_panel_actually_set_backlight] set
backlight level = 27961
Set the brightness to the minimum value when the new brightness is less
or equal to the minimum value to mitigate this flickering.
Cc : Tejas Upadhyay
Cc : Matt Roper
Cc : Ville Syrjälä
Signed-off-by: Gareth Yu
---
drivers/gpu/drm/i915/display/intel_backlight.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 3f3cd944a1c5..23fd011b6bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -761,8 +761,8 @@ static void __intel_backlight_enable(const struct
intel_crtc_state *crtc_state,
WARN_ON(panel->backlight.max == 0);
- if (panel->backlight.level <= panel->backlight.min) {
- panel->backlight.level = panel->backlight.max;
+ if (panel->backlight.level < panel->backlight.min) {
+ panel->backlight.level = panel->backlight.min;
if (panel->backlight.device)
panel->backlight.device->props.brightness =
scale_hw_to_user(connector,
--
2.25.1
RE: [PATCH] drm/i915/gt: Report full vm address range
> If we provide the total GTT size we will have one page that will be contended > between kernel and userspace and, if userspace is unaware that the page > belongs to the > kernel, we might step on each other toe. That's fine, Compute needs to know total GTT size. Not available GTT size.
Re: [PATCH v20 8/9] drm/i915/display: Compute vrr_vsync params
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/20/2024 10:30 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)
--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.
--v4:
- Use VRR_SYNC_START/END macros correctly.
--v5:
- Send AS SDP only when VRR is enabled.
--v6:
- Add TRANS_VRR_VSYNC befor enabling VRR as per bspec. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 33 +--
drivers/gpu/drm/i915/i915_reg.h | 7
4 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index eb8f36b38c41..9e5924e21eee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5356,6 +5356,8 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_I(vrr.vsync_start);
+ PIPE_CONF_CHECK_I(vrr.vsync_end);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 36fcded7564a..95da3cf27188 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1431,6 +1431,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+ u32 vsync_end, vsync_start;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index eb5bd0743902..856378f8b90e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_vrr.h"
+#include "intel_dp.h"
bool intel_vrr_is_capable(struct intel_connector *connector)
{
@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
const struct drm_display_info *info = >base.display_info;
int vmin, vmax;
@@ -165,6 +167,14 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+
crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ crtc_state->hw.adjusted_mode.vsync_end);
+ }
}
}
@@ -240,6 +250,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
return;
intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+
+ if (HAS_AS_SDP(dev_priv))
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
+ VRR_VSYNC_START(crtc_state->vrr.vsync_start));
+
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
}
@@ -258,13 +274,16 @@ void intel_vrr_disable(const struct intel_crtc_state
*old_crtc_state)
intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
+
+ if (HAS_AS_SDP(dev_priv))
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0);
}
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
✓ Fi.CI.BAT: success for drm/i915: Do not print 'pxp init failed with 0' when it succeed
== Series Details == Series: drm/i915: Do not print 'pxp init failed with 0' when it succeed URL : https://patchwork.freedesktop.org/series/131389/ State : success == Summary == CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131389v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/index.html Participating hosts (36 -> 35) -- Additional (1): bat-jsl-1 Missing(2): fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_131389v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@i915_pm_rps@basic-api: - bat-dg2-8: NOTRUN -> [SKIP][4] ([i915#6621]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#4103]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9886]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html - bat-jsl-1: NOTRUN -> [SKIP][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#5274]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#5354]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@read-crc: - bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#9197]) +6 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#9673] / [i915#9732]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#3555]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@kms_setm...@basic-clone-single-crtc.html - bat-jsl-1: NOTRUN -> [SKIP][14] ([i915#3555]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-jsl-1/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#3708] / [i915#9197]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-write: - bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#3291] / [i915#3708]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/bat-dg2-8/igt@prime_v...@basic-write.html Possible fixes * igt@i915_module_load@reload: - fi-apl-guc: [DMESG-WARN][18] ([i915#180] / [i915#1982] / [i915#8585]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/fi-apl-guc/igt@i915_module_l...@reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131389v1/fi-apl-guc/igt@i915_module_l...@reload.html *
✓ Fi.CI.BAT: success for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
== Series Details == Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix URL : https://patchwork.freedesktop.org/series/131386/ State : success == Summary == CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131386v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/index.html Participating hosts (36 -> 36) -- Additional (3): bat-dg1-7 bat-jsl-1 bat-mtlp-8 Missing(3): bat-kbl-2 fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_131386v1 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: NOTRUN -> [FAIL][1] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-jsl-1/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@gem_m...@basic.html - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#6621]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@dmabuf: - bat-dg2-9: [PASS][13] -> [ABORT][14] ([i915#10366]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/bat-dg2-9/igt@i915_selftest@l...@dmabuf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg2-9/igt@i915_selftest@l...@dmabuf.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][15] ([i915#4212]) +7 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][18] ([i915#4215]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4213]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][20] ([i915#4103] / [i915#4213]) +1 other test skip [20]:
✗ Fi.CI.SPARSE: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
== Series Details == Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix URL : https://patchwork.freedesktop.org/series/131386/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
== Series Details ==
Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
URL : https://patchwork.freedesktop.org/series/131386/
State : warning
== Summary ==
Error: dim checkpatch failed
9183ac6af689 drm/i915/dp: Fix DSC line buffer depth programming
ca44bf249961 drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp
limit
fef91e101fcb drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp
f44ec86a39d8 drm/i915/dp_mst: Account for channel coding efficiency in the DSC
DPT bpp limit
cab48f1e5ee6 drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
56c30e6af3ff drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit
29ba369e9dd0 drm/dp: Add drm_dp_uhbr_channel_coding_supported()
a76031363d87 drm/dp_mst: Factor out drm_dp_mst_port_is_logical()
b3fcdcd1049b drm/dp_mst: Add drm_dp_mst_aux_for_parent()
601ece014625 drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports
f5895020cbbb drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates
-:35: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#35: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2284:
+ /* MediaTek panels (at least in U3224KBA) require DSC for modes with a
short HBLANK on UHBR links. */
-:36: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#36: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2285:
+ { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false,
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
total: 0 errors, 2 warnings, 0 checks, 55 lines checked
✓ Fi.CI.BAT: success for drm/i915: Allow the first async flip to change modifier
== Series Details == Series: drm/i915: Allow the first async flip to change modifier URL : https://patchwork.freedesktop.org/series/131379/ State : success == Summary == CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131379v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/index.html Participating hosts (36 -> 36) -- Additional (2): bat-dg1-7 bat-jsl-1 Missing(2): fi-glk-j4005 fi-snb-2520m Known issues Here are the changes found in Patchwork_131379v1 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: NOTRUN -> [FAIL][1] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-jsl-1/boot.html - fi-apl-guc: [PASS][2] -> [FAIL][3] ([i915#8293]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/fi-apl-guc/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/fi-apl-guc/boot.html - fi-cfl-8109u: [PASS][4] -> [FAIL][5] ([i915#8293]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/fi-cfl-8109u/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/fi-cfl-8109u/boot.html ### IGT changes ### Issues hit * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-14: [PASS][6] -> [FAIL][7] ([i915#10378]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hugepages: - bat-dg2-8: NOTRUN -> [ABORT][13] ([i915#10366]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-8/igt@i915_selftest@l...@hugepages.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#4212]) +7 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-7: NOTRUN -> [SKIP][15] ([i915#4215]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg1-7: NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-dg1-7: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#3840]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html - bat-dg1-7: NOTRUN -> [SKIP][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg1-7/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#5274]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-dg2-8: NOTRUN -> [SKIP][21] ([i915#5354]) +1 other test skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131379v1/bat-dg2-8/igt@kms_frontbuffer_track...@basic.html * igt@kms_hdmi_inject@inject-audio: - bat-dg1-7: NOTRUN ->
✗ Fi.CI.SPARSE: warning for drm/i915: Allow the first async flip to change modifier
== Series Details == Series: drm/i915: Allow the first async flip to change modifier URL : https://patchwork.freedesktop.org/series/131379/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/de: register wait function renames
== Series Details ==
Series: series starting with [1/2] drm/i915/de: register wait function renames
URL : https://patchwork.freedesktop.org/series/131378/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131378v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/index.html
Participating hosts (36 -> 37)
--
Additional (2): bat-jsl-1 bat-mtlp-8
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_131378v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@dmabuf@all-tests@dma_fence:
- {bat-arls-4}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/bat-arls-4/igt@dmabuf@all-tests@dma_fence.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-arls-4/igt@dmabuf@all-tests@dma_fence.html
* igt@dmabuf@all-tests@sanitycheck:
- {bat-arls-4}: [PASS][3] -> [ABORT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/bat-arls-4/igt@dmabuf@all-te...@sanitycheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-arls-4/igt@dmabuf@all-te...@sanitycheck.html
Known issues
Here are the changes found in Patchwork_131378v1 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-jsl-1: NOTRUN -> [FAIL][5] ([i915#8293])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-jsl-1/boot.html
- fi-kbl-8809g: [PASS][6] -> [FAIL][7] ([i915#8293])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/fi-kbl-8809g/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/fi-kbl-8809g/boot.html
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#9318])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4083])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@gem_m...@basic.html
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@gem_mmap_...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#6621])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#6621])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-dg2-8/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#5190])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4212]) +8 other tests skip
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4213]) +1 other test skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840] /
[i915#9159])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131378v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html
- bat-dg2-8: NOTRUN -> [SKIP][20]
[20]:
✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/de: register wait function renames
== Series Details == Series: series starting with [1/2] drm/i915/de: register wait function renames URL : https://patchwork.freedesktop.org/series/131378/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol
✓ Fi.CI.BAT: success for drm/i915: pass encoder around more for port/phy checks (rev2)
== Series Details == Series: drm/i915: pass encoder around more for port/phy checks (rev2) URL : https://patchwork.freedesktop.org/series/131031/ State : success == Summary == CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131031v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/index.html Participating hosts (36 -> 38) -- Additional (3): bat-dg1-7 bat-jsl-1 bat-mtlp-8 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_131031v2 that come from known issues: ### CI changes ### Issues hit * boot: - fi-cfl-8109u: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/fi-cfl-8109u/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/fi-cfl-8109u/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-14: [PASS][6] -> [FAIL][7] ([i915#10378]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14459/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html - bat-jsl-1: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg1-7/igt@gem_m...@basic.html - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#6621]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gem: - bat-dg2-8: NOTRUN -> [ABORT][19] ([i915#10366]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg2-8/igt@i915_selftest@l...@gem.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][20] ([i915#4212]) +7 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#5190]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v2/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html *
✗ Fi.CI.SPARSE: warning for drm/i915: pass encoder around more for port/phy checks (rev2)
== Series Details == Series: drm/i915: pass encoder around more for port/phy checks (rev2) URL : https://patchwork.freedesktop.org/series/131031/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
✗ Fi.CI.CHECKPATCH: warning for drm/i915: pass encoder around more for port/phy checks (rev2)
== Series Details == Series: drm/i915: pass encoder around more for port/phy checks (rev2) URL : https://patchwork.freedesktop.org/series/131031/ State : warning == Summary == Error: dim checkpatch failed f421cc680f3a drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin() 2eb685bfa6e8 drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active() 863e0275374c drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state() 463fce01dc0c drm/i915/display: add intel_encoder_is_*() and _to_*() functions 521c1af5ed6b drm/i915/display: use intel_encoder_is/to_* functions -:656: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #656: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1696: + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_encoder_is_c10phy(encoder))) total: 0 errors, 1 warnings, 0 checks, 964 lines checked df1a3802376e drm/i915/cx0: remove the unused intel_is_c10phy() c7e1159eb5dd drm/i915/cx0: pass encoder instead of i915 and port around -:209: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #209: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:295: + ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, ); -:453: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #453: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1923: + intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); -:454: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #454: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1924: + intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); -:474: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #474: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2168: + cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; -:539: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #539: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2358: + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); -:548: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #548: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2366: + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); -:551: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #551: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2368: + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); -:558: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #558: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2374: + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); -:561: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #561: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2376: + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); total: 0 errors, 9 warnings, 0 checks, 730 lines checked
Re: [PATCH 00/11] drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
Thank You for the fixes Tested-by: Khaled Almahallawy On Wed, 2024-03-20 at 22:11 +0200, Imre Deak wrote: > This patchset fixes a few MTL/DSC 1.2 related issues and adds a > workaround for the native 5k@60Hz uncompressed mode on a > MediaTek/Dell > UHBR monitor, force-enabling DSC on it as required, similarly to the > existing HBLANK expansion quirk for Synaptics hubs. > > Imre Deak (11): > drm/i915/dp: Fix DSC line buffer depth programming > drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp > limit > drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp > drm/i915/dp_mst: Account for channel coding efficiency in the DSC > DPT > bpp limit > drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL > drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit > drm/dp: Add drm_dp_uhbr_channel_coding_supported() > drm/dp_mst: Factor out drm_dp_mst_port_is_logical() > drm/dp_mst: Add drm_dp_mst_aux_for_parent() > drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports > drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates > > drivers/gpu/drm/display/drm_dp_helper.c | 2 + > drivers/gpu/drm/display/drm_dp_mst_topology.c | 22 - > drivers/gpu/drm/i915/display/intel_dp.c | 18 ++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 87 - > -- > include/drm/display/drm_dp_helper.h | 6 ++ > include/drm/display/drm_dp_mst_helper.h | 7 ++ > include/drm/display/drm_dsc.h | 3 - > 7 files changed, 98 insertions(+), 47 deletions(-) >
Re: [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation
Hi Stan
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> Problem is that on some platforms, we do get QGV point mask in wrong
> state on boot. However driver assumes it is set to 0
> (i.e all points allowed), however in reality we might get them all restricted,
> causing issues.
> Lets disable SAGV initially to force proper QGV point state.
> If more QGV points are available, driver will recalculate and update
> those then after next commit.
>
> v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
> disabled.
> v3: - Move force disable function to intel_bw_init in order to initialize
> bw state as well, so that hw/sw are immediately in sync after init.
> v4: - Don't try sending PCode request, seems like it is not possible at
> intel_bw_init, however assigning bw->state to be restricted as if
> SAGV is off, still forces driveer to send PCode request anyway on
> next modeset, so the solution still works.
> However we still need to address the case, when no display is connected,
> which anyway requires much more changes.
>
> v5: - Put PCode request back and apply temporary hack to make the
> request succeed(in case if there 2 PSF GV points with same BW, PCode
> accepts only if both points are restricted/unrestricted same time)
> - Fix argument sequence for adl_qgv_bw(Ville Syrjälä)
>
> v6: Fix wrong platform checks, not to break everything else.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 73 ++--
> drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> 3 files changed, 71 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 7baa1c13eccd..f9c301114f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -162,7 +162,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
> *dev_priv,
> 1);
>
> if (ret < 0) {
> - drm_err(_priv->drm, "Failed to disable qgv points (%d)
> points: 0x%x\n", ret,
> points_mask);
> + drm_err(_priv->drm, "Failed to disable qgv points (%x)
> points: 0x%x\n", ret,
> points_mask);
> return ret;
> }
>
> @@ -662,7 +662,7 @@ static unsigned int adl_psf_bw(struct drm_i915_private
> *i915,
> }
>
> static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
> - int qgv_point, int num_active_planes)
> + int num_active_planes, int qgv_point)
As mentioned in the previous patch, this change should be handled in the
previous patch.
> {
> unsigned int idx;
>
> @@ -833,7 +833,7 @@ static unsigned int icl_max_bw_qgv_point(struct
> drm_i915_private *i915,
> for (i = 0; i < num_qgv_points; i++) {
> unsigned int max_data_rate;
>
> - max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
> + max_data_rate = adl_qgv_bw(i915, num_active_planes, i);
>
> /*
> * We need to know which qgv point gives us
> @@ -852,6 +852,68 @@ static unsigned int icl_max_bw_qgv_point(struct
> drm_i915_private *i915,
> return max_bw_point;
> }
>
> +/*
> + * Due to some strange reason, we have to use a mask of PSF GV
> + * points, instead of finding the one which provides the highest bandwidth,
> + * this is because PCode rejects the request, if 2 PSF GV points, which have
> + * same bandwidth are not set/cleared same time.
> + */
> +static unsigned int icl_max_bw_psf_gv_point_mask(struct drm_i915_private
> *i915)
> +{
> + unsigned int num_psf_gv_points =
> i915->display.bw.max[0].num_psf_gv_points;
> + unsigned int max_bw = 0;
> + unsigned int max_bw_point_mask = 0;
> + int i;
> +
> + for (i = 0; i < num_psf_gv_points; i++) {
> + unsigned int max_data_rate = adl_psf_bw(i915, i);
> +
> + if (max_data_rate > max_bw) {
> + max_bw_point_mask = BIT(i);
> + max_bw = max_data_rate;
> + } else if (max_data_rate == max_bw)
> + max_bw_point_mask |= BIT(i);
> + }
> +
> + return max_bw_point_mask;
> +}
> +
> +static void icl_force_disable_sagv(struct drm_i915_private *i915, struct
> intel_bw_state
> *bw_state)
> +{
> + unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
There could be QGV points with similar values. Shouldn't we handle the QGV
point case also as mask..
. similar to psf_gv points?
> + unsigned int max_bw_psf_gv_point_mask =
> icl_max_bw_psf_gv_point_mask(i915);
> + unsigned int qgv_points;
> + unsigned int psf_points;
> + int ret;
> +
> + /*
> + * Just return if we can't control
Re: [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
Hi Stan.
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> We need that in order to force disable SAGV in next patch.
> Also it is beneficial to separate that code, as in majority cases,
> when SAGV is enabled, we don't even need those calculations.
> Also we probably need to determine max PSF GV point as well, however
> currently we don't do that when we disable SAGV, which might be
> actually causing some issues in that case.
>
> v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
> (Ville Syrjälä)
> - Don't restrict psf gv points for SAGV disable case
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 81 -
> 1 file changed, 53 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 77886cc21211..7baa1c13eccd 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> -static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
> +static unsigned int adl_psf_bw(struct drm_i915_private *i915,
> int psf_gv_point)
> {
> const struct intel_bw_info *bi =
> - _priv->display.bw.max[0];
> + >display.bw.max[0];
>
> return bi->psf_bw[psf_gv_point];
> }
This is probably not related to this patch..
>
> +static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
> + int qgv_point, int num_active_planes)
In the next patch you are chaging the order of these parameters and calling
with adl_qgv_bw(i915,
num_active_planes, i). As you are adding this functions in this patch, I think
you should fix the
position of parameters in this patch itself and next patch call this normally
Also about the naming of this function, should this be icl_* as this is called
from icl_* functions?
> +{
> + unsigned int idx;
> +
> + if (DISPLAY_VER(i915) > 11)
This is just fine.. but just for the sake of easy readability, wonder
DISPLAY_VER(i915) >= 12 is
better as TGL is display version 12.
BR
vinod
> + idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
> + else
> + idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
> +
> + if (idx >= ARRAY_SIZE(i915->display.bw.max))
> + return 0;
> +
> + return i915->display.bw.max[idx].deratedbw[qgv_point];
> +}
> +
> void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> {
> if (!HAS_DISPLAY(dev_priv))
> @@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state
> *state)
> return to_intel_bw_state(bw_state);
> }
>
> +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> + int num_active_planes)
> +{
> + unsigned int max_bw_point = 0;
> + unsigned int max_bw = 0;
> + unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> + int i;
> +
> + for (i = 0; i < num_qgv_points; i++) {
> + unsigned int max_data_rate;
> +
> + max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
> +
> + /*
> + * We need to know which qgv point gives us
> + * maximum bandwidth in order to disable SAGV
> + * if we find that we exceed SAGV block time
> + * with watermarks. By that moment we already
> + * have those, as it is calculated earlier in
> + * intel_atomic_check,
> + */
> + if (max_data_rate > max_bw) {
> + max_bw_point = i;
> + max_bw = max_data_rate;
> + }
> + }
> +
> + return max_bw_point;
> +}
> +
> static int mtl_find_qgv_points(struct drm_i915_private *i915,
> unsigned int data_rate,
> unsigned int num_active_planes,
> @@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private
> *i915,
> const struct intel_bw_state *old_bw_state,
> struct intel_bw_state *new_bw_state)
> {
> - unsigned int max_bw_point = 0;
> - unsigned int max_bw = 0;
> unsigned int num_psf_gv_points =
> i915->display.bw.max[0].num_psf_gv_points;
> unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> u16 psf_points = 0;
> @@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private
> *i915,
> return ret;
>
> for (i = 0; i < num_qgv_points; i++) {
> - unsigned int idx;
> unsigned int max_data_rate;
>
> -
✓ Fi.CI.BAT: success for Bigjoiner refactoring (rev14)
== Series Details == Series: Bigjoiner refactoring (rev14) URL : https://patchwork.freedesktop.org/series/128311/ State : success == Summary == CI Bug Log - changes from CI_DRM_14458 -> Patchwork_128311v14 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/index.html Participating hosts (36 -> 33) -- Missing(3): bat-mtlp-8 fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_128311v14 that come from known issues: ### CI changes ### Issues hit * boot: - fi-cfl-8109u: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14458/fi-cfl-8109u/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/fi-cfl-8109u/boot.html Possible fixes * boot: - bat-jsl-1: [FAIL][3] ([i915#8293]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14458/bat-jsl-1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gem: - bat-dg2-8: [PASS][8] -> [ABORT][9] ([i915#10366]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14458/bat-dg2-8/igt@i915_selftest@l...@gem.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-dg2-8/igt@i915_selftest@l...@gem.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-1: NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-jsl-1: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#9886]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-jsl-1: NOTRUN -> [SKIP][12] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_setmode@basic-clone-single-crtc: - bat-jsl-1: NOTRUN -> [SKIP][13] ([i915#3555]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-jsl-1/igt@kms_setm...@basic-clone-single-crtc.html Warnings * igt@i915_selftest@live@hangcheck: - bat-adls-6: [DMESG-WARN][14] ([i915#5591]) -> [ABORT][15] ([i915#5591]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14458/bat-adls-6/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128311v14/bat-adls-6/igt@i915_selftest@l...@hangcheck.html [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886 Build changes - * Linux: CI_DRM_14458 -> Patchwork_128311v14 CI-20190529: 20190529 CI_DRM_14458: 1cbe0387180a61b6abb4f5a6261763adaecbf51b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7771: 7771 Patchwork_128311v14: 1cbe0387180a61b6abb4f5a6261763adaecbf51b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits ed8081bde722 drm/i915: Allow bigjoiner for MST 99eb50944f95 drm/i915: Handle joined pipes inside hsw_crtc_enable() 5297eac655f9 drm/i915: Handle joined pipes inside hsw_crtc_disable() fcf2d66f09ec drm/i915: Utilize intel_crtc_joined_pipe_mask() more 7fb953e1fe42 drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst() 98516a8d2775 drm/i915: Add a small helper to compute the set of pipes for crtc == Logs == For more details see:
✗ Fi.CI.SPARSE: warning for Bigjoiner refactoring (rev14)
== Series Details == Series: Bigjoiner refactoring (rev14) URL : https://patchwork.freedesktop.org/series/128311/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
✗ Fi.CI.CHECKPATCH: warning for Bigjoiner refactoring (rev14)
== Series Details ==
Series: Bigjoiner refactoring (rev14)
URL : https://patchwork.freedesktop.org/series/128311/
State : warning
== Summary ==
Error: dim checkpatch failed
ab1e39980e9f drm/i915: Add a small helper to compute the set of pipes for crtc
921ae16a87ff drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()
-:77: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#77: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3136:
+{
+
total: 0 errors, 0 warnings, 1 checks, 57 lines checked
3516755b5a24 drm/i915: Utilize intel_crtc_joined_pipe_mask() more
9daccdcbc349 drm/i915: Handle joined pipes inside hsw_crtc_disable()
-:130: ERROR:CODE_INDENT: code indent should use tabs where possible
#130: FILE: drivers/gpu/drm/i915/display/intel_display.c:6819:
+if (intel_crtc_is_bigjoiner_slave(old_crtc_state))$
-:130: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#130: FILE: drivers/gpu/drm/i915/display/intel_display.c:6819:
+if (intel_crtc_is_bigjoiner_slave(old_crtc_state))$
-:131: ERROR:CODE_INDENT: code indent should use tabs where possible
#131: FILE: drivers/gpu/drm/i915/display/intel_display.c:6820:
+continue;$
-:131: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#131: FILE: drivers/gpu/drm/i915/display/intel_display.c:6820:
+continue;$
total: 2 errors, 2 warnings, 0 checks, 111 lines checked
ddc842056930 drm/i915: Handle joined pipes inside hsw_crtc_enable()
-:8: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible
unwrapped commit description?)
#8:
That way we can also remove a bunch of checks like
intel_crtc_is_bigjoiner_slave.
-:279: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#279: FILE: drivers/gpu/drm/i915/display/intel_display.c:1718:
+* to change the workaround. */
-:325: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#325: FILE: drivers/gpu/drm/i915/display/intel_display.c:6718:
+ if ((vrr_enabling(old_crtc_state, new_crtc_state) ||
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr) &&
-:367: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#367: FILE: drivers/gpu/drm/i915/display/intel_display.h:315:
+#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask)
\
+ list_for_each_entry_reverse(intel_crtc,
\
+ &(dev)->mode_config.crtc_list,
\
+ base.head)
\
+ for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
-:367: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_crtc' - possible
side-effects?
#367: FILE: drivers/gpu/drm/i915/display/intel_display.h:315:
+#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask)
\
+ list_for_each_entry_reverse(intel_crtc,
\
+ &(dev)->mode_config.crtc_list,
\
+ base.head)
\
+ for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
total: 1 errors, 2 warnings, 2 checks, 337 lines checked
cca39b46fd10 drm/i915: Allow bigjoiner for MST
[PATCH] drm/i915: Do not print 'pxp init failed with 0' when it succeed
It is misleading, if the intention was to also print something in case it succeed it should have a different string. Cc: Alan Previn Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 9ee902d5b72c4..4b9233c07a22c 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -800,7 +800,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto out_cleanup_modeset2; ret = intel_pxp_init(i915); - if (ret != -ENODEV) + if (ret && ret != -ENODEV) drm_dbg(>drm, "pxp init failed with %d\n", ret); ret = intel_display_driver_probe(i915); -- 2.44.0
[PATCH 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported()
Factor out a function to check for UHBR channel coding support used by a
follow-up patch in the patchset.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
include/drm/display/drm_dp_helper.h | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index dbe65651bf277..1d13a1ba2b97d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -217,7 +217,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
*intel_dp)
* Sink rates for 128b/132b. If set, sink should support all 8b/10b
* rates and 10 Gbps.
*/
- if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)
{
+ if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) {
u8 uhbr_rates = 0;
BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) <
ARRAY_SIZE(dp_rates) + 3);
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index a62fcd051d4d4..150c37a99a16f 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -221,6 +221,12 @@ drm_dp_channel_coding_supported(const u8
dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
}
+static inline bool
+drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
+}
+
static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
--
2.43.3
[PATCH 10/11] drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports
The DPCD OUI of the logical port on a Dell UHBR monitor - on which the
AUX device is used to enable DSC - is all 0. To detect if the HBLANK
expansion quirk is required for this monitor use the OUI of the port's
parent instead.
Since in the above case the DPCD of both the logical port and the parent
port reports being a sink device (vs. branch device) type, read the
proper sink/branch OUI based on the DPCD device type.
This is required by a follow-up patch enabling the quirk for the above
Dell monitor.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 516b00f791420..76a8fb21b8e52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1512,23 +1512,33 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct
intel_dp *intel_dp,
static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector
*connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;
struct drm_dp_desc desc;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
- if (!connector->dp.dsc_decompression_aux)
+ if (!aux)
return false;
- if (drm_dp_read_desc(connector->dp.dsc_decompression_aux,
-, true) < 0)
+ /*
+* A logical port's OUI (at least for affected sinks) is all 0, so
+* instead of that the parent port's OUI is used for identification.
+*/
+ if (drm_dp_mst_port_is_logical(connector->port)) {
+ aux = drm_dp_mst_aux_for_parent(connector->port);
+ if (!aux)
+ aux = >mst_port->aux;
+ }
+
+ if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)
+ return false;
+
+ if (drm_dp_read_desc(aux, , drm_dp_is_branch(dpcd)) < 0)
return false;
if (!drm_dp_has_quirk(,
DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
return false;
- if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) <
0)
- return false;
-
if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
return false;
--
2.43.3
[PATCH 08/11] drm/dp_mst: Factor out drm_dp_mst_port_is_logical()
Factor out a function to check if an MST port is logical, used by a
follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++---
include/drm/display/drm_dp_mst_helper.h | 7 +++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 03d5282094262..6bd471a2266ce 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2274,7 +2274,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch
*mstb,
if (port->pdt != DP_PEER_DEVICE_NONE &&
drm_dp_mst_is_end_device(port->pdt, port->mcs) &&
- port->port_num >= DP_MST_LOGICAL_PORT_0)
+ drm_dp_mst_port_is_logical(port))
port->cached_edid = drm_edid_read_ddc(port->connector,
>aux.ddc);
@@ -4213,7 +4213,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
case DP_PEER_DEVICE_SST_SINK:
ret = connector_status_connected;
/* for logical ports - cache the EDID */
- if (port->port_num >= DP_MST_LOGICAL_PORT_0 &&
!port->cached_edid)
+ if (drm_dp_mst_port_is_logical(port) && !port->cached_edid)
port->cached_edid = drm_edid_read_ddc(connector,
>aux.ddc);
break;
case DP_PEER_DEVICE_DP_LEGACY_CONV:
@@ -5977,7 +5977,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct
drm_dp_mst_port *port)
return false;
/* Virtual DP Sink (Internal Display Panel) */
- if (port->port_num >= 8)
+ if (drm_dp_mst_port_is_logical(port))
return true;
/* DP-to-HDMI Protocol Converter */
diff --git a/include/drm/display/drm_dp_mst_helper.h
b/include/drm/display/drm_dp_mst_helper.h
index 3ae88a383a41f..c12f18b744d01 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -927,6 +927,13 @@ int __must_check drm_dp_mst_root_conn_atomic_check(struct
drm_connector_state *n
void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);
void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port);
+static inline
+bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port)
+{
+ return port->port_num >= DP_MST_LOGICAL_PORT_0;
+}
+
+struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port);
struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port);
static inline struct drm_dp_mst_topology_state *
--
2.43.3
[PATCH 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates
Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
monitor results in a blank screen, at least on MTL platforms on UHBR
link rates with some (<30) uncompressed bpp values. Enabling compression
fixes the problem, so do that for now. Windows enables DSC always if the
sink supports it and forcing it to enable the mode without compression
leads to the same problem above (which suggests a panel issue with
uncompressed mode).
The same 5k mode on non-UHBR link rates is not affected and lower
resolution modes are not affected either. The problem is similar to the
one fixed by the HBLANK expansion quirk on Synaptics hubs, with the
difference that the problematic mode has a longer HBLANK duration. Also
the monitor doesn't report supporting HBLANK expansion; either its
internal MST hub does the expansion internally - similarly to the
Synaptics hub - or the issue has another root cause, but still related
to the mode's short HBLANK duration. Enable the quirk for the monitor
adjusting the detection for the above differences.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_helper.c | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index f5d4be8978660..3e8e1bb59dea3 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
/* Synaptics DP1.4 MST hubs require DSC for some modes on which it
applies HBLANK expansion. */
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
+ /* MediaTek panels (at least in U3224KBA) require DSC for modes with a
short HBLANK on UHBR links. */
+ { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false,
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low
DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false,
BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 76a8fb21b8e52..b5224fe6cc16b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -407,15 +407,22 @@ static int mode_hblank_period_ns(const struct
drm_display_mode *mode)
static bool
hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
-const struct intel_crtc_state *crtc_state)
+const struct intel_crtc_state *crtc_state,
+const struct link_config_limits *limits)
{
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
+ bool is_uhbr_sink = connector->mst_port &&
+
drm_dp_uhbr_channel_coding_supported(connector->mst_port->dpcd);
+ int hblank_limit = is_uhbr_sink ? 500 : 300;
if (!connector->dp.dsc_hblank_expansion_quirk)
return false;
- if (mode_hblank_period_ns(adjusted_mode) > 300)
+ if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
+ return false;
+
+ if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
return false;
return true;
@@ -431,7 +438,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct
intel_connector *conne
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
int min_bpp_x16 = limits->link.min_bpp_x16;
- if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
+ if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
return true;
if (!dsc) {
@@ -1539,7 +1546,14 @@ static bool detect_dsc_hblank_expansion_quirk(const
struct intel_connector *conn
DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
return false;
- if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
+ /*
+* UHBR (MST sink) devices requiring this quirk doesn't advertise the
+* HBLANK expansion support. Presuming that they perform HBLANK
+* expansion internally, or are affected by this issue on modes with a
+* short HBLANK for other reasons.
+*/
+ if (!drm_dp_uhbr_channel_coding_supported(dpcd) &&
+ !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
return false;
drm_dbg_kms(>drm,
--
2.43.3
[PATCH 09/11] drm/dp_mst: Add drm_dp_mst_aux_for_parent()
Add a function to get the AUX device of the parent of an MST port, used
by a follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 6bd471a2266ce..d70f7de644371 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -6004,6 +6004,22 @@ static bool drm_dp_mst_is_virtual_dpcd(struct
drm_dp_mst_port *port)
return false;
}
+/**
+ * drm_dp_mst_aux_for_parent() - Get the AUX device for an MST port's parent
+ * @port: MST port whose parent's AUX device is returned
+ *
+ * Return the AUX device for @port's parent or NULL if port's parent is the
+ * root port.
+ */
+struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port)
+{
+ if (!port->parent || !port->parent->port_parent)
+ return NULL;
+
+ return >parent->port_parent->aux;
+}
+EXPORT_SYMBOL(drm_dp_mst_aux_for_parent);
+
/**
* drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
* @port: The port to check. A leaf of the MST tree with an attached display.
--
2.43.3
[PATCH 06/11] drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit
Instead of checking each compressed bpp value against the maximum
DSC/DPT bpp, simplify things by calculating the maximum bpp upfront and
limiting the range of bpps looped over using this maximum.
While at it add a comment about the origin of the DSC/DPT bpp limit.
Bspec: 49259, 68912
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 45 +++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 40660dc5edb45..516b00f791420 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -51,27 +51,24 @@
#include "intel_vdsc.h"
#include "skl_scaler.h"
-static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
bpp,
- const struct drm_display_mode
*adjusted_mode,
- struct intel_crtc_state *crtc_state,
- bool dsc)
+static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
+ bool dsc)
{
- if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) {
- int output_bpp = bpp;
- int symbol_clock =
intel_dp_link_symbol_clock(crtc_state->port_clock);
- int available_bw = mul_u32_u32(symbol_clock * 72,
-
drm_dp_bw_channel_coding_efficiency(true)) /
- 100;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
- if (output_bpp * adjusted_mode->crtc_clock >
- available_bw) {
- drm_dbg_kms(>drm, "UHBR check failed(required bw
%d available %d)\n",
- output_bpp * adjusted_mode->crtc_clock,
available_bw);
- return -EINVAL;
- }
- }
+ if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc)
+ return INT_MAX;
- return 0;
+ /*
+* DSC->DPT interface width:
+* ICL-MTL: 72 bits (each branch has 72 bits, only left branch is
used)
+* LNL+:144 bits (not a bottleneck in any config)
+*/
+ return
div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
+drm_dp_bw_channel_coding_efficiency(true)),
+mul_u32_u32(adjusted_mode->crtc_clock, 100));
}
static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
@@ -160,6 +157,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
int bpp, slots = -EINVAL;
+ int max_dpt_bpp;
int ret = 0;
mst_state = drm_atomic_get_mst_topology_state(state,
_dp->mst_mgr);
@@ -180,6 +178,13 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
crtc_state->port_clock,
crtc_state->lane_count);
+ max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
+ if (max_bpp > max_dpt_bpp) {
+ drm_dbg_kms(>drm, "Limiting bpp to max DPT bpp (%d ->
%d)\n",
+ max_bpp, max_dpt_bpp);
+ max_bpp = max_dpt_bpp;
+ }
+
drm_dbg_kms(>drm, "Looking for slots in range min bpp %d max bpp
%d\n",
min_bpp, max_bpp);
@@ -191,10 +196,6 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
drm_dbg_kms(>drm, "Trying bpp %d\n", bpp);
- ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode,
crtc_state, dsc);
- if (ret)
- continue;
-
link_bpp_x16 = to_bpp_x16(dsc ? bpp :
intel_dp_output_bpp(crtc_state->output_format, bpp));
--
2.43.3
[PATCH 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 79f34be5c89da..40660dc5edb45 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct
drm_i915_private *i915, int bpp
struct intel_crtc_state *crtc_state,
bool dsc)
{
- if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
+ if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) {
int output_bpp = bpp;
int symbol_clock =
intel_dp_link_symbol_clock(crtc_state->port_clock);
int available_bw = mul_u32_u32(symbol_clock * 72,
--
2.43.3
[PATCH 04/11] drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit
The DSC DPT interface BW limit check should take into account the link
clock's (aka DDI clock in bspec) channel coding efficiency overhead.
Bspec doesn't mention this, however this matches how the link BW limit
is checked (that is the BW limit on wire as opposed to the above DPT
limit) for which Bspec doesn't mention the overhead either.
This fixes the DPT bpp limit for at least the 5k@60Hz/DSC mode on a Dell
UHBR monitor/link I tested.
Bspec: 49259
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c21fd7a2cd44f..79f34be5c89da 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -59,11 +59,14 @@ static int intel_dp_mst_check_constraints(struct
drm_i915_private *i915, int bpp
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
int output_bpp = bpp;
int symbol_clock =
intel_dp_link_symbol_clock(crtc_state->port_clock);
+ int available_bw = mul_u32_u32(symbol_clock * 72,
+
drm_dp_bw_channel_coding_efficiency(true)) /
+ 100;
if (output_bpp * adjusted_mode->crtc_clock >
- symbol_clock * 72) {
+ available_bw) {
drm_dbg_kms(>drm, "UHBR check failed(required bw
%d available %d)\n",
- output_bpp * adjusted_mode->crtc_clock,
symbol_clock * 72);
+ output_bpp * adjusted_mode->crtc_clock,
available_bw);
return -EINVAL;
}
}
--
2.43.3
[PATCH 02/11] drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit
The expected link symbol clock unit when calculating the DSC DPT bpp
limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit
based on the crtc clock. As opposed to this port_clock is used - which
has a 10 kbits/sec unit - with the resulting symbol clock in 10
kSymbols/sec units (disregarding the rounding error for the 13.5Gbps
rate). Fix the calculation using the expected 10x factor.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 53aec023ce92f..b2bcf66071b05 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct
drm_i915_private *i915, int bpp
{
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
int output_bpp = bpp;
- /* DisplayPort 2 128b/132b, bits per lane is always 32 */
- int symbol_clock = crtc_state->port_clock / 32;
+ int symbol_clock =
intel_dp_link_symbol_clock(crtc_state->port_clock);
if (output_bpp * adjusted_mode->crtc_clock >=
symbol_clock * 72) {
--
2.43.3
[PATCH 03/11] drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp
The DSC DPT bpp limit check should only fail if the available DPT BW is
less than the required BW, fix the check accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b2bcf66071b05..c21fd7a2cd44f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -60,7 +60,7 @@ static int intel_dp_mst_check_constraints(struct
drm_i915_private *i915, int bpp
int output_bpp = bpp;
int symbol_clock =
intel_dp_link_symbol_clock(crtc_state->port_clock);
- if (output_bpp * adjusted_mode->crtc_clock >=
+ if (output_bpp * adjusted_mode->crtc_clock >
symbol_clock * 72) {
drm_dbg_kms(>drm, "UHBR check failed(required bw
%d available %d)\n",
output_bpp * adjusted_mode->crtc_clock,
symbol_clock * 72);
--
2.43.3
[PATCH 01/11] drm/i915/dp: Fix DSC line buffer depth programming
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall limit is simply the minimum of the
source/sink's limit, regardless of the DSC version.
This leaves the DSI DSC line buffer depth calculation as-is, trusting
VBT.
On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16
the line buffer depth was incorrectly programmed as 0, leading to a
corruption in color gradients / lines on the decompressed screen image.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
include/drm/display/drm_dsc.h | 3 ---
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index af7ca00e9bc0a..dbe65651bf277 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -89,6 +89,9 @@
#define DP_DSC_MAX_ENC_THROUGHPUT_034
#define DP_DSC_MAX_ENC_THROUGHPUT_140
+/* Max DSC line buffer depth supported by HW. */
+#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH13
+
/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
@@ -1703,7 +1706,6 @@ static int intel_dp_dsc_compute_params(const struct
intel_connector *connector,
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
- u8 line_buf_depth;
int ret;
/*
@@ -1732,20 +1734,14 @@ static int intel_dp_dsc_compute_params(const struct
intel_connector *connector,
connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
DP_DSC_SUPPORT] &
DP_DSC_RGB;
- line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
- if (!line_buf_depth) {
+ vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
+
drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
+ if (!vdsc_cfg->line_buf_depth) {
drm_dbg_kms(>drm,
"DSC Sink Line Buffer Depth invalid\n");
return -EINVAL;
}
- if (vdsc_cfg->dsc_version_minor == 2)
- vdsc_cfg->line_buf_depth = (line_buf_depth ==
DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
- else
- vdsc_cfg->line_buf_depth = (line_buf_depth >
DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
-
vdsc_cfg->block_pred_enable =
connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT -
DP_DSC_SUPPORT] &
DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h
index bc90273d06a62..bbbe7438473d3 100644
--- a/include/drm/display/drm_dsc.h
+++ b/include/drm/display/drm_dsc.h
@@ -40,9 +40,6 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
-#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
-#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
-#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/**
* struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
--
2.43.3
[PATCH 00/11] drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
This patchset fixes a few MTL/DSC 1.2 related issues and adds a workaround for the native 5k@60Hz uncompressed mode on a MediaTek/Dell UHBR monitor, force-enabling DSC on it as required, similarly to the existing HBLANK expansion quirk for Synaptics hubs. Imre Deak (11): drm/i915/dp: Fix DSC line buffer depth programming drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit drm/dp: Add drm_dp_uhbr_channel_coding_supported() drm/dp_mst: Factor out drm_dp_mst_port_is_logical() drm/dp_mst: Add drm_dp_mst_aux_for_parent() drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates drivers/gpu/drm/display/drm_dp_helper.c | 2 + drivers/gpu/drm/display/drm_dp_mst_topology.c | 22 - drivers/gpu/drm/i915/display/intel_dp.c | 18 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 87 --- include/drm/display/drm_dp_helper.h | 6 ++ include/drm/display/drm_dp_mst_helper.h | 7 ++ include/drm/display/drm_dsc.h | 3 - 7 files changed, 98 insertions(+), 47 deletions(-) -- 2.43.3
Re: [PATCH] drm/i915/gt: Reset queue_priority_hint on parking
Hi Andi,
On Wednesday, 20 March 2024 15:29:58 CET Andi Shyti wrote:
> Hi Janusz,
>
> ...
>
> > Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Signed-off-by: Janusz Krzysztofik
> > Cc: Chris Wilson
> > Cc: # v5.4+
>
> this tag list is a bit confusing. Let's keep all Cc's together
> and, besides, Cc'eing the author looks a bit redundant.
You're right, please feel free to fix that while applying.
Thanks,
Janusz
>
> No need to resend also because I retriggered another round of
> test.
>
> Reviewed-by: Andi Shyti
>
> Thanks,
> Andi
>
Re: [PATCH] drm/i915/gt: Report full vm address range
Hi Michal, On Mon, Mar 18, 2024 at 05:21:54AM +, Mrozek, Michal wrote: > > > Lionel, Michal, thoughts? > Compute UMD needs to know exact GTT total size. the problem is that we cannot apply the workaround without reserving one page from the GTT total size and we need to apply the workaround. If we provide the total GTT size we will have one page that will be contended between kernel and userspace and, if userspace is unaware that the page belongs to the kernel, we might step on each other toe. The ask here from kernel side is to relax the check on the maxNBitValue() in userspace and take what the kernel provides. Thanks, Andi
Re: [PATCH v6 0/3] Disable automatic load CCS load balancing
Hi Tvrtko, On Wed, Mar 20, 2024 at 03:40:18PM +, Tvrtko Ursulin wrote: > On 20/03/2024 15:06, Andi Shyti wrote: > > Ping! Any thoughts here? > > I only casually observed the discussion after I saw Matt suggested further > simplifications. As I understood it, you will bring back the uabi engine > games when adding the dynamic behaviour and that is fine by me. yes, the refactoring suggested by you will come later. Thanks, Andi
Re: [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling
Hi Stan
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> For debug purposes we need those - error path won't flood the log,
> however there has been already numerous cases, when due to lack
> of debugs, we couldn't immediately tell what was the problem on
> customer machine, which slowed down the investigation, requiring
> to get access to target device and adding those traces manually.
>
> v2: - Make the debug more generic and move it to intel_dram_detect
> (Gustavo Sousa)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
> drivers/gpu/drm/i915/soc/intel_dram.c | 2 ++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 7f2a50b4f494..77886cc21211 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -290,8 +290,10 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> struct intel_qgv_point *sp = >points[i];
>
> ret = intel_read_qgv_point_info(dev_priv, sp, i);
> - if (ret)
> + if (ret) {
> + drm_dbg_kms(_priv->drm, "Could not read QGV %d
> info\n", i);
> return ret;
> + }
>
> drm_dbg_kms(_priv->drm,
> "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d
> tRC=%d\n",
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 15492b69f698..e957be5bfb35 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -681,6 +681,8 @@ void intel_dram_detect(struct drm_i915_private *i915)
> if (ret)
> return;
>
> + drm_dbg_kms(>drm, "Num qgv points %d\n",
> dram_info->num_qgv_points);
> +
There was a suggestion from Gustavo to use %u as num_qgv_points is u8.. in case
if you missed it!
Reviewed-by: Vinod Govindapillai
> drm_dbg_kms(>drm, "DRAM channels: %u\n",
> dram_info->num_channels);
>
> drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
Re: Weirdness in parsing cpp macros
On Wed, 20 Mar 2024, Jani Nikula wrote:
> On Wed, 20 Mar 2024, Julia Lawall wrote:
> > On Wed, 20 Mar 2024, Jani Nikula wrote:
> >> Okay, I have another one wrt macros. :)
> >>
> >> I'm trying to add a completely new variadic macro, but it fails at
> >> "...". I've tried all sorts of things, but can't seem to be able to add
> >> a literal "...".
> >>
> >> I've tested that my cocci patch works with x's:
> >>
> >> + #define fn(p, xxx) foo(__VA_ARGS__)
> >>
> >> but when I try to make it actually variadic like:
> >>
> >> + #define fn(p, ...) foo(__VA_ARGS__)
> >>
> >> it gives me error. Is there a way to escape? Even tried to use a fresh
> >> identifier vararg = "..."; but cocci made them unique with numbering
> >> "...0" and "...1" etc.
> >
> > Put 6 dots. It's silly, but ... is a Coccinelle thing, so we had to use
> > something else.
>
> I've tried, but it doesn't seem to work in the + side:
>
> plus: parse error:
> File "/tmp/tmp.clvvc812Qe", line 20, column 2, charpos = 254
> around = '#define fn(',
> whole content = + #define fn(p, ..) __fn(__to_intel_display(p),
> __VA_ARGS__)
OK, maybe it doesn't work for macros. I will take a look.
julia
[PATCH 6/6] drm/i915: Extract ilk_must_disable_lp_wm()
From: Ville Syrjälä
Pull the ilk/snb/ivb LP watermark disable checks into a separate
function similar to the gmch counterpart (i9xx_must_disable_cxsr()).
Reduces the clutter in intel_plane_atomic_calc_changes() significantly.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 95 +++
1 file changed, 57 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b083b985d170..19bcf5754ee2 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -482,6 +482,61 @@ static bool i9xx_must_disable_cxsr(const struct
intel_crtc_state *new_crtc_state
return old_ctl != new_ctl;
}
+static bool ilk_must_disable_lp_wm(const struct intel_crtc_state
*new_crtc_state,
+ const struct intel_plane_state
*old_plane_state,
+ const struct intel_plane_state
*new_plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+ bool old_visible = old_plane_state->uapi.visible;
+ bool new_visible = new_plane_state->uapi.visible;
+ bool modeset, turn_on;
+
+ if (plane->id == PLANE_CURSOR)
+ return false;
+
+ modeset = intel_crtc_needs_modeset(new_crtc_state);
+ turn_on = new_visible && (!old_visible || modeset);
+
+ /*
+* ILK/SNB DVSACNTR/Sprite Enable
+* IVB SPR_CTL/Sprite Enable
+* "When in Self Refresh Big FIFO mode, a write to enable the
+* plane will be internally buffered and delayed while Big FIFO
+* mode is exiting."
+*
+* Which means that enabling the sprite can take an extra frame
+* when we start in big FIFO mode (LP1+). Thus we need to drop
+* down to LP0 and wait for vblank in order to make sure the
+* sprite gets enabled on the next vblank after the register write.
+* Doing otherwise would risk enabling the sprite one frame after
+* we've already signalled flip completion. We can resume LP1+
+* once the sprite has been enabled.
+*
+* With experimental results seems this is needed also for primary
+* plane, not only sprite plane.
+*/
+ if (turn_on)
+ return true;
+
+ /*
+* WaCxSRDisabledForSpriteScaling:ivb
+* IVB SPR_SCALE/Scaling Enable
+* "Low Power watermarks must be disabled for at least one
+* frame before enabling sprite scaling, and kept disabled
+* until sprite scaling is disabled."
+*
+* ILK/SNB DVSASCALE/Scaling Enable
+* "When in Self Refresh Big FIFO mode, scaling enable will be
+* masked off while Big FIFO mode is exiting."
+*
+* Despite the w/a only being listed for IVB we assume that
+* the ILK/SNB note has similar ramifications, hence we apply
+* the w/a on all three platforms.
+*/
+ return !intel_plane_is_scaled(old_plane_state) &&
+ intel_plane_is_scaled(new_plane_state);
+}
+
static int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state
*new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -557,44 +612,8 @@ static int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_cr
i9xx_must_disable_cxsr(new_crtc_state, old_plane_state,
new_plane_state))
new_crtc_state->disable_cxsr = true;
- /*
-* ILK/SNB DVSACNTR/Sprite Enable
-* IVB SPR_CTL/Sprite Enable
-* "When in Self Refresh Big FIFO mode, a write to enable the
-* plane will be internally buffered and delayed while Big FIFO
-* mode is exiting."
-*
-* Which means that enabling the sprite can take an extra frame
-* when we start in big FIFO mode (LP1+). Thus we need to drop
-* down to LP0 and wait for vblank in order to make sure the
-* sprite gets enabled on the next vblank after the register write.
-* Doing otherwise would risk enabling the sprite one frame after
-* we've already signalled flip completion. We can resume LP1+
-* once the sprite has been enabled.
-*
-*
-* WaCxSRDisabledForSpriteScaling:ivb
-* IVB SPR_SCALE/Scaling Enable
-* "Low Power watermarks must be disabled for at least one
-* frame before enabling sprite scaling, and kept disabled
-* until sprite scaling is disabled."
-*
-* ILK/SNB DVSASCALE/Scaling Enable
-* "When in Self Refresh Big FIFO mode, scaling enable will be
-* masked off while Big FIFO mode is exiting."
-*
-* Despite the w/a only being
[PATCH 5/6] drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/
From: Ville Syrjälä
Rename need_async_flip_disable_wa to need_async_flip_toggle_wa to
better reflect the fact that we need to deal with the bad
PLANE_CTL_ASYNC_FLIP double buffering behaviour going both
ways.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 ++---
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 76fc7626051b..3442264443e5 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -456,7 +456,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
/* see intel_plane_atomic_calc_changes() */
- if (plane->need_async_flip_disable_wa &&
+ if (plane->need_async_flip_toggle_wa &&
crtc_state->async_flip_planes & BIT(plane->id))
dspcntr |= DISP_ASYNC_FLIP;
@@ -878,7 +878,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->enable_flip_done = vlv_primary_enable_flip_done;
plane->disable_flip_done = vlv_primary_disable_flip_done;
} else if (IS_BROADWELL(dev_priv)) {
- plane->need_async_flip_disable_wa = true;
+ plane->need_async_flip_toggle_wa = true;
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7098a34a17c8..b083b985d170 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -600,7 +600,7 @@ static int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_cr
if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
new_crtc_state->do_async_flip = true;
new_crtc_state->async_flip_planes |= BIT(plane->id);
- } else if (plane->need_async_flip_disable_wa &&
+ } else if (plane->need_async_flip_toggle_wa &&
new_crtc_state->uapi.async_flip) {
/*
* On platforms with double buffered async flip bit we
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index dbcda79cf53c..8a10130c6f37 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1109,7 +1109,7 @@ static void intel_crtc_async_flip_disable_wa(struct
intel_atomic_state *state,
int i;
for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
- if (plane->need_async_flip_disable_wa &&
+ if (plane->need_async_flip_toggle_wa &&
plane->pipe == crtc->pipe &&
disable_async_flip_planes & BIT(plane->id)) {
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8b9860cefaae..4cbb6be5ff48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1557,7 +1557,7 @@ struct intel_plane {
enum i9xx_plane_id i9xx_plane;
enum plane_id id;
enum pipe pipe;
- bool need_async_flip_disable_wa;
+ bool need_async_flip_toggle_wa;
u32 frontbuffer_bit;
struct {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ad4c90344f68..0a8e781a3648 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1175,7 +1175,7 @@ skl_plane_update_arm(struct intel_plane *plane,
skl_plane_ctl_crtc(crtc_state);
/* see intel_plane_atomic_calc_changes() */
- if (plane->need_async_flip_disable_wa &&
+ if (plane->need_async_flip_toggle_wa &&
crtc_state->async_flip_planes & BIT(plane->id))
plane_ctl |= PLANE_CTL_ASYNC_FLIP;
@@ -2371,8 +2371,7 @@ skl_universal_plane_create(struct drm_i915_private
*dev_priv,
plane->check_plane = skl_plane_check;
if (plane_id == PLANE_PRIMARY) {
- plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
- 9, 10);
+ plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9,
10);
[PATCH 4/6] drm/i915: Eliminate extra frame from skl-glk sync->async flip change
From: Ville Syrjälä
On bdw-glk the sync->async flip change takes an extra frame due to
the double buffering behaviour of the async flip plane control bit.
Since on skl+ we are now explicitly converting the first async flip
to a sync flip (in order to allow changing the modifier and/or
ddb/watermarks) we are now taking two extra frames until async flips
are actually active. We can drop that back down to one frame by
setting the async flip bit already during the sync flip.
Note that on bdw we don't currently do the extra sync flip (see
intel_plane_do_async_flip()) so technically we wouldn't have
to deal with this in i9xx_plane_update_arm(). But I added the
relevant snippet of code there as well, just in case we ever
decide to go for the extra sync flip on pre-skl platforms as
well (we might, for example, want to change the fb stride).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 15 +++
.../gpu/drm/i915/display/skl_universal_plane.c| 5 +
3 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0279c8aabdd1..76fc7626051b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -455,6 +455,11 @@ static void i9xx_plane_update_arm(struct intel_plane
*plane,
dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
+ /* see intel_plane_atomic_calc_changes() */
+ if (plane->need_async_flip_disable_wa &&
+ crtc_state->async_flip_planes & BIT(plane->id))
+ dspcntr |= DISP_ASYNC_FLIP;
+
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (DISPLAY_VER(dev_priv) >= 4)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 769010d0ebc4..7098a34a17c8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -437,10 +437,6 @@ static bool intel_plane_do_async_flip(struct intel_plane
*plane,
* only X-tile is supported with async flips, though we could
* extend this so other scanout parameters (stride/etc) could
* be changed as well...
-*
-* FIXME: Platforms with need_async_flip_disable_wa==true will
-* now end up doing two sync flips initially. Would be nice to
-* combine those into just the one sync flip...
*/
return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip;
}
@@ -604,6 +600,17 @@ static int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_cr
if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
new_crtc_state->do_async_flip = true;
new_crtc_state->async_flip_planes |= BIT(plane->id);
+ } else if (plane->need_async_flip_disable_wa &&
+ new_crtc_state->uapi.async_flip) {
+ /*
+* On platforms with double buffered async flip bit we
+* set the bit already one frame early during the sync
+* flip (see {i9xx,skl}_plane_update_arm()). The
+* hardware will therefore be ready to perform a real
+* async flip during the next commit, without having
+* to wait yet another frame for the bit to latch.
+*/
+ new_crtc_state->async_flip_planes |= BIT(plane->id);
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 860574d04f88..ad4c90344f68 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1174,6 +1174,11 @@ skl_plane_update_arm(struct intel_plane *plane,
plane_ctl = plane_state->ctl |
skl_plane_ctl_crtc(crtc_state);
+ /* see intel_plane_atomic_calc_changes() */
+ if (plane->need_async_flip_disable_wa &&
+ crtc_state->async_flip_planes & BIT(plane->id))
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
if (DISPLAY_VER(dev_priv) >= 10)
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
--
2.43.2
[PATCH 3/6] drm/i915: Allow the initial async flip to change modifier
From: Ville Syrjälä
With Xorg+modesetting on skl+ we see the following behaviour:
1. root pixmap is X-tiled
2. client submitted buffers can be Y-tiled (w/ 'Option "dmabuf_capable"')
3. we try to switch from the X-tiled buffer to the Y-tiled buffer
using an async flip (when vsync is disabled).
4. the async flip will be rejected by i915 due to the modifier change
Relax the rules a bit by turning the first async flip into a sync
flip so that we can change the modifier if necessary. Note that
we already convert the first async flip into a sync flip on adl+
in order to reprogram the watermarks.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16 +---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 76d77d5a0409..769010d0ebc4 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -429,10 +429,20 @@ static bool intel_plane_do_async_flip(struct intel_plane
*plane,
* In platforms after DISPLAY13, we might need to override
* first async flip in order to change watermark levels
* as part of optimization.
-* So for those, we are checking if this is a first async flip.
-* For platforms earlier than DISPLAY13 we always do async flip.
+*
+* And let's do this for all skl+ so that we can eg. change the
+* modifier as well.
+*
+* TODO: For older platforms there is less reason to do this as
+* only X-tile is supported with async flips, though we could
+* extend this so other scanout parameters (stride/etc) could
+* be changed as well...
+*
+* FIXME: Platforms with need_async_flip_disable_wa==true will
+* now end up doing two sync flips initially. Would be nice to
+* combine those into just the one sync flip...
*/
- return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
+ return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip;
}
static bool i9xx_must_disable_cxsr(const struct intel_crtc_state
*new_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d366a103a707..dbcda79cf53c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6061,6 +6061,13 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
return -EINVAL;
}
+ /*
+* We turn the first async flip request into a sync flip
+* so that we can reconfigure the plane (eg. change modifier).
+*/
+ if (!new_crtc_state->do_async_flip)
+ continue;
+
if (old_plane_state->view.color_plane[0].mapping_stride !=
new_plane_state->view.color_plane[0].mapping_stride) {
drm_dbg_kms(>drm,
--
2.43.2
[PATCH 2/6] drm/i915: Reject async flips if we need to change DDB/watermarks
From: Ville Syrjälä
DDB/watermarks are always double buffered on the vblank, so we
can't safely change them during async flips. Currently this never
happens, but we'll be making changing between sync and async
flips a bit more flexible, in which case we can actually end up
here.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index bc341abcab2f..1fa416a70d51 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2540,6 +2540,12 @@ skl_ddb_add_affected_planes(const struct
intel_crtc_state *old_crtc_state,
_crtc_state->wm.skl.plane_ddb_y[plane_id]))
continue;
+ if (new_crtc_state->do_async_flip) {
+ drm_dbg_kms(>drm, "[PLANE:%d:%s] Can't change DDB
during async flip\n",
+ plane->base.base.id, plane->base.name);
+ return -EINVAL;
+ }
+
plane_state = intel_atomic_get_plane_state(state, plane);
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
@@ -2906,6 +2912,12 @@ static int skl_wm_add_affected_planes(struct
intel_atomic_state *state,
_crtc_state->wm.skl.optimal))
continue;
+ if (new_crtc_state->do_async_flip) {
+ drm_dbg_kms(>drm, "[PLANE:%d:%s] Can't change
watermarks during async flip\n",
+ plane->base.base.id, plane->base.name);
+ return -EINVAL;
+ }
+
plane_state = intel_atomic_get_plane_state(state, plane);
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
--
2.43.2
[PATCH 1/6] drm/i915: Align PLANE_SURF to 16k on ADL for async flips
From: Ville Syrjälä
On ADL async flips apparently generate DMAR and GGTT faults
(with accompanying visual glitches) unless PLANE_SURF is
aligned to at least 16k. Bump up the alignment to 16k.
TODO: analyze things better to figure out what is really
going on here
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c| 7 ---
drivers/gpu/drm/i915/display/intel_dpt.h| 3 ++-
drivers/gpu/drm/i915/display/intel_fb.c | 17 -
drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +-
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index b29bceff73f2..786d3f2e94c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -121,7 +121,8 @@ static void dpt_cleanup(struct i915_address_space *vm)
i915_gem_object_put(dpt->obj);
}
-struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
+struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
+ unsigned int alignment)
{
struct drm_i915_private *i915 = vm->i915;
struct i915_dpt *dpt = i915_vm_to_dpt(vm);
@@ -143,8 +144,8 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space
*vm)
if (err)
continue;
- vma = i915_gem_object_ggtt_pin_ww(dpt->obj, , NULL, 0, 4096,
- pin_flags);
+ vma = i915_gem_object_ggtt_pin_ww(dpt->obj, , NULL, 0,
+ alignment, pin_flags);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
continue;
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h
b/drivers/gpu/drm/i915/display/intel_dpt.h
index e18a9f767b11..f467578a4950 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.h
+++ b/drivers/gpu/drm/i915/display/intel_dpt.h
@@ -13,7 +13,8 @@ struct i915_vma;
struct intel_framebuffer;
void intel_dpt_destroy(struct i915_address_space *vm);
-struct i915_vma *intel_dpt_pin(struct i915_address_space *vm);
+struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
+ unsigned int alignment);
void intel_dpt_unpin(struct i915_address_space *vm);
void intel_dpt_suspend(struct drm_i915_private *i915);
void intel_dpt_resume(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 3ea6470d6d92..58ead05fba6f 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -805,8 +805,23 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
- if (intel_fb_uses_dpt(fb))
+ if (intel_fb_uses_dpt(fb)) {
+ /* AUX_DIST needs only 4K alignment */
+ if (intel_fb_is_ccs_aux_plane(fb, color_plane))
+ return 512 * 4096;
+
+ /*
+* FIXME ADL sees GGTT/DMAR faults with async
+* flips unless we align to 16k at least.
+* Figure out what's going on here...
+*/
+ if (IS_ALDERLAKE_P(dev_priv) &&
+ !intel_fb_is_ccs_modifier(fb->modifier) &&
+ HAS_ASYNC_FLIPS(dev_priv))
+ return 512 * 16 * 1024;
+
return 512 * 4096;
+ }
/* AUX_DIST needs only 4K alignment */
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 7b42aef37d2f..c28ae99ebe6a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -19,6 +19,7 @@
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_gtt_view *view,
+unsigned int alignment,
bool uses_fence,
unsigned long *out_flags,
struct i915_address_space *vm)
@@ -28,7 +29,6 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
- u32 alignment;
int ret;
/*
@@ -41,8 +41,6 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
return ERR_PTR(-EINVAL);
- alignment = 4096 * 512;
-
atomic_inc(_priv->gpu_error.pending_fb_pin);
for_i915_gem_ww(, ret, true) {
@@ -257,14 +255,16 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
plane_state->ggtt_vma = vma;
} else {
struct intel_framebuffer *intel_fb =
[PATCH 0/6] drm/i915: Allow the first async flip to change modifier
From: Ville Syrjälä Xorg/modesetting expects to be able to change the modifier already when submitting the first async flip. Let's convert the first async flip to a sync flip so that we can accommodate it. For now I limit this behaviour to skl+ since earlier platforms don't support async flips with anything but X-tile anyway, but we could extend this if needed to allow eg. stride changes/etc. We already convert the first async flip to a sync flip on on ADL+ to reprogram the watermarks/DDB, and on BDW-GLK the hardware anyway converts the first async flip to a sync flip (due to the double buffering behaviour of the async flip bit). So actually this will only slow down the first async flip on ICL and TGL. I've also included a workaround for async flip GGTT/DMAR faults on ADL. Just bumping the alignment to 16k seems effective, and so that seems like a reasonable enough solution for the moment. But this probably needs further analysis later. Test-with: 20240319202443.27951-1-ville.syrj...@linux.intel.com Ville Syrjälä (6): drm/i915: Align PLANE_SURF to 16k on ADL for async flips drm/i915: Reject async flips if we need to change DDB/watermarks drm/i915: Allow the initial async flip to change modifier drm/i915: Eliminate extra frame from skl-glk sync->async flip change drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/ drm/i915: Extract ilk_must_disable_lp_wm() drivers/gpu/drm/i915/display/i9xx_plane.c | 7 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 118 -- drivers/gpu/drm/i915/display/intel_display.c | 9 +- .../drm/i915/display/intel_display_types.h| 2 +- drivers/gpu/drm/i915/display/intel_dpt.c | 7 +- drivers/gpu/drm/i915/display/intel_dpt.h | 3 +- drivers/gpu/drm/i915/display/intel_fb.c | 17 ++- drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +- .../drm/i915/display/skl_universal_plane.c| 8 +- drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++ 10 files changed, 137 insertions(+), 56 deletions(-) -- 2.43.2
[PATCH 2/2] drm/i915/display: prefer intel_de_wait*() functions over uncore ones
Prefer the intel_de_wait*() functions over the uncore interface. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 7 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 6 +++--- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 4ca910874a4f..2d7a71c8c69c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -399,11 +399,8 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, * The flag should get set in 100us according to the HW team, but * use 1ms due to occasional timeouts observed with that. */ - if (intel_wait_for_register_fw(_priv->uncore, - BXT_PORT_CL1CM_DW0(phy), - PHY_RESERVED | PHY_POWER_GOOD, - PHY_POWER_GOOD, - 1)) + if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy), +PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1)) drm_err(_priv->drm, "timeout during PHY%d power on\n", phy); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 9edac27bab26..d5ed4c7dfbc0 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -369,9 +369,9 @@ static int intel_hdcp_load_keys(struct drm_i915_private *i915) } /* Wait for the keys to load (500us) */ - ret = __intel_wait_for_register(>uncore, HDCP_KEY_STATUS, - HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, - 10, 1, ); + ret = intel_de_wait_custom(i915, HDCP_KEY_STATUS, + HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, + 10, 1, ); if (ret) return ret; else if (!(val & HDCP_KEY_LOAD_STATUS)) -- 2.39.2
[PATCH 1/2] drm/i915/de: register wait function renames
Do some renames on the register wait functions for clarity and brevity:
intel_de_wait_for_register -> intel_de_wait
intel_de_wait_for_register_fw -> intel_de_wait_fw
__intel_de_wait_for_register-> intel_de_wait_custom
In particular, it seemed odd to have a double-underscored function be
called in a number of places.
Signed-off-by: Jani Nikula
---
Use 'git show -w --color-words' for easy review.
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 +--
drivers/gpu/drm/i915/display/intel_de.h | 20 +++---
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
.../i915/display/intel_display_power_well.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 17 ++---
drivers/gpu/drm/i915/display/intel_gmbus.c| 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 3 +-
8 files changed, 58 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 64e0f820a789..eedd1b4de943 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -143,12 +143,12 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
*i915, enum port port,
{
enum phy phy = intel_port_to_phy(i915, port);
- if (__intel_de_wait_for_register(i915,
-XELPDP_PORT_P2M_MSGBUS_STATUS(i915,
port, lane),
-XELPDP_PORT_P2M_RESPONSE_READY,
-XELPDP_PORT_P2M_RESPONSE_READY,
-XELPDP_MSGBUS_TIMEOUT_FAST_US,
-XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+ if (intel_de_wait_custom(i915,
+XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port,
lane),
+XELPDP_PORT_P2M_RESPONSE_READY,
+XELPDP_PORT_P2M_RESPONSE_READY,
+XELPDP_MSGBUS_TIMEOUT_FAST_US,
+XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
drm_dbg_kms(>drm, "PHY %c Timeout waiting for message
ACK. Status: 0x%x\n",
phy_name(phy), *val);
@@ -2536,9 +2536,9 @@ static void intel_cx0_powerdown_change_sequence(struct
drm_i915_private *i915,
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
-
intel_cx0_get_powerdown_update(lane_mask), 0,
-
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
+ if (intel_de_wait_custom(i915, buf_ctl2_reg,
+intel_cx0_get_powerdown_update(lane_mask), 0,
+XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0,
NULL))
drm_warn(>drm, "PHY %c failed to bring out of Lane reset
after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
}
@@ -2593,19 +2593,19 @@ static void intel_cx0_phy_lane_reset(struct
drm_i915_private *i915,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),
-XELPDP_PORT_BUF_SOC_PHY_READY,
-XELPDP_PORT_BUF_SOC_PHY_READY,
-XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US,
0, NULL))
+ if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
+XELPDP_PORT_BUF_SOC_PHY_READY,
+XELPDP_PORT_BUF_SOC_PHY_READY,
+XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
drm_warn(>drm, "PHY %c failed to bring out of SOC reset
after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
lane_pipe_reset);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),
-lane_phy_current_status,
lane_phy_current_status,
-XELPDP_PORT_RESET_START_TIMEOUT_US, 0,
NULL))
+ if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+lane_phy_current_status,
lane_phy_current_status,
+XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
drm_warn(>drm, "PHY %c failed to bring out of Lane reset
after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
@@ -2613,10 +2613,10 @@ static void
Re: [PATCH v3 2/2] drm/i915: Add SIZE_HINTS property for cursors
look all ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 18.3.2024 22.44, Ville Syrjala wrote:
From: Ville Syrjälä
Advertize more suitable cursor sizes via the new SIZE_HINTS
plane property.
We can't really enumerate all supported cursor sizes on
the platforms where the cursor height can vary freely, so
for simplicity we'll just expose all square+POT sizes between
each platform's min and max cursor limits.
Depending on the platform this will give us one of three
results:
- 64x64,128x128,256x256,512x512
- 64x64,128x128,256x256
- 64x64
Cc: Simon Ser
Cc: Jonas Ådahl
Cc: Daniel Stone
Cc: Sameer Lattannavar
Cc: Sebastian Wick
Cc: Harry Wentland
Cc: Pekka Paalanen
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 24 +
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f8b33999d43f..49e9b9be2235 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -823,6 +823,28 @@ static const struct drm_plane_funcs
intel_cursor_plane_funcs = {
.format_mod_supported = intel_cursor_format_mod_supported,
};
+static void intel_cursor_add_size_hints_property(struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ const struct drm_mode_config *config = >drm.mode_config;
+ struct drm_plane_size_hint hints[4];
+ int size, max_size, num_hints = 0;
+
+ max_size = min(config->cursor_width, config->cursor_height);
+
+ /* for simplicity only enumerate the supported square+POT sizes */
+ for (size = 64; size <= max_size; size *= 2) {
+ if (drm_WARN_ON(>drm, num_hints >= ARRAY_SIZE(hints)))
+ break;
+
+ hints[num_hints].width = size;
+ hints[num_hints].height = size;
+ num_hints++;
+ }
+
+ drm_plane_add_size_hints_property(>base, hints, num_hints);
+}
+
struct intel_plane *
intel_cursor_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe)
@@ -881,6 +903,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180);
+ intel_cursor_add_size_hints_property(cursor);
+
zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
drm_plane_create_zpos_immutable_property(>base, zpos);
Re: Weirdness in parsing cpp macros
On Wed, 20 Mar 2024, Julia Lawall wrote:
> On Wed, 20 Mar 2024, Jani Nikula wrote:
>> Okay, I have another one wrt macros. :)
>>
>> I'm trying to add a completely new variadic macro, but it fails at
>> "...". I've tried all sorts of things, but can't seem to be able to add
>> a literal "...".
>>
>> I've tested that my cocci patch works with x's:
>>
>> + #define fn(p, xxx) foo(__VA_ARGS__)
>>
>> but when I try to make it actually variadic like:
>>
>> + #define fn(p, ...) foo(__VA_ARGS__)
>>
>> it gives me error. Is there a way to escape? Even tried to use a fresh
>> identifier vararg = "..."; but cocci made them unique with numbering
>> "...0" and "...1" etc.
>
> Put 6 dots. It's silly, but ... is a Coccinelle thing, so we had to use
> something else.
I've tried, but it doesn't seem to work in the + side:
plus: parse error:
File "/tmp/tmp.clvvc812Qe", line 20, column 2, charpos = 254
around = '#define fn(',
whole content = + #define fn(p, ..) __fn(__to_intel_display(p),
__VA_ARGS__)
BR,
Jani.
--
Jani Nikula, Intel
Re: [RFC 0/7] drm/i915: pass encoder around more for port/phy checks
On Wed, 20 Mar 2024, Ville Syrjälä wrote: > I have basically that same patch sitting in some branch. I would expect no less. ;D > With commit messages polished the series is > Reviewed-by: Ville Syrjälä Thanks, fixed up the commit messages and posted v1 for CI. BR, Jani. -- Jani Nikula, Intel
[CI 7/7] drm/i915/cx0: pass encoder instead of i915 and port around
The encoder is a much more useful thing to pass around than the i915 and
port combo. Also drive-by clean up some cases where both i915 and
encoder are passed; only the latter is needed.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 258 ++-
1 file changed, 136 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b88ffc75cf4a..d2e4439562e3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -49,8 +49,7 @@ static int lane_mask_to_lane(u8 lane_mask)
return ilog2(lane_mask);
}
-static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
- struct intel_encoder *encoder)
+static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -117,16 +116,20 @@ static void intel_cx0_phy_transaction_end(struct
intel_encoder *encoder, intel_w
intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
}
-static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
- enum port port, int lane)
+static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
+ int lane)
{
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port,
lane),
0, XELPDP_PORT_P2M_RESPONSE_READY |
XELPDP_PORT_P2M_ERROR_SET);
}
-static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port,
int lane)
+static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
{
- enum phy phy = intel_port_to_phy(i915, port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ enum phy phy = intel_encoder_to_phy(encoder);
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
@@ -138,13 +141,15 @@ static void intel_cx0_bus_reset(struct drm_i915_private
*i915, enum port port, i
return;
}
- intel_clear_response_ready_flag(i915, port, lane);
+ intel_clear_response_ready_flag(encoder, lane);
}
-static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port
port,
+static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
int command, int lane, u32 *val)
{
- enum phy phy = intel_port_to_phy(i915, port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ enum phy phy = intel_encoder_to_phy(encoder);
if (__intel_de_wait_for_register(i915,
XELPDP_PORT_P2M_MSGBUS_STATUS(i915,
port, lane),
@@ -161,31 +166,33 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
*i915, enum port port,
"PHY %c Hardware did not detect a
timeout\n",
phy_name(phy));
- intel_cx0_bus_reset(i915, port, lane);
+ intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
drm_dbg_kms(>drm, "PHY %c Error occurred during %s
command. Status: 0x%x\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ?
"read" : "write", *val);
- intel_cx0_bus_reset(i915, port, lane);
+ intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
drm_dbg_kms(>drm, "PHY %c Not a %s response. MSGBUS
Status: 0x%x.\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ?
"read" : "write", *val);
- intel_cx0_bus_reset(i915, port, lane);
+ intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
return 0;
}
-static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
+static int __intel_cx0_read_once(struct intel_encoder *encoder,
int lane, u16 addr)
{
- enum phy phy = intel_port_to_phy(i915, port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
@@ -194,7 +201,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
*i915, enum port port,
[CI 6/7] drm/i915/cx0: remove the unused intel_is_c10phy()
The intel_is_c10phy() is now unused. Remove.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 --
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 --
2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f893db353f91..b88ffc75cf4a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -29,21 +29,15 @@
#define INTEL_CX0_LANE1BIT(1)
#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
-/* Prefer intel_encoder_is_c10phy() */
-bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
-{
- if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
- return true;
-
- return false;
-}
-
bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
- return intel_is_c10phy(i915, phy);
+ if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
+ return true;
+
+ return false;
}
static int lane_mask_to_lane(u8 lane_mask)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 2be474877fdc..3e03af3e006c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -11,7 +11,6 @@
#include
enum icl_port_dpll_id;
-enum phy;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
@@ -22,7 +21,6 @@ struct intel_crtc_state;
struct intel_encoder;
struct intel_hdmi;
-bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.39.2
[CI 2/7] drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()
Pass encoder to intel_wait_ddi_buf_active(). The encoder will be more
helpful than just port in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a755b1f13d51..82132fa1bb2c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -200,9 +200,10 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv,
port_name(port));
}
-static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
- enum port port)
+static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
int timeout_us;
int ret;
@@ -3354,7 +3355,7 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
- intel_wait_ddi_buf_active(dev_priv, port);
+ intel_wait_ddi_buf_active(encoder);
}
static void intel_enable_ddi(struct intel_atomic_state *state,
@@ -3574,7 +3575,7 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
*intel_dp,
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
- intel_wait_ddi_buf_active(dev_priv, port);
+ intel_wait_ddi_buf_active(encoder);
}
static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -3624,7 +3625,7 @@ static void intel_ddi_prepare_link_retrain(struct
intel_dp *intel_dp,
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
- intel_wait_ddi_buf_active(dev_priv, port);
+ intel_wait_ddi_buf_active(encoder);
}
static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
--
2.39.2
[CI 1/7] drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
Pass encoder to the _port_to_ddc_pin() functions, and rename to
_encoder_to_ddc_pin(). The encoder will be more helpful than just port
in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 60 ++-
1 file changed, 37 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 90d2236fede3..f1fc9669238f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2664,8 +2664,9 @@ bool intel_hdmi_handle_sink_scrambling(struct
intel_encoder *encoder,
drm_scdc_set_scrambling(connector, scrambling);
}
-static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ enum port port = encoder->port;
u8 ddc_pin;
switch (port) {
@@ -2686,8 +2687,9 @@ static u8 chv_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
-static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ enum port port = encoder->port;
u8 ddc_pin;
switch (port) {
@@ -2705,9 +2707,9 @@ static u8 bxt_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
-static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
- enum port port)
+static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ enum port port = encoder->port;
u8 ddc_pin;
switch (port) {
@@ -2731,8 +2733,10 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv,
return ddc_pin;
}
-static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
if (intel_phy_is_combo(dev_priv, phy))
@@ -2744,8 +2748,10 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return GMBUS_PIN_2_BXT;
}
-static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
u8 ddc_pin;
@@ -2767,8 +2773,10 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
-static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
WARN_ON(port == PORT_C);
@@ -2785,8 +2793,10 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
-static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port
port)
+static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(i915, port);
drm_WARN_ON(>drm, port == PORT_A);
@@ -2803,13 +2813,18 @@ static u8 gen9bc_tgp_port_to_ddc_pin(struct
drm_i915_private *i915, enum port po
return GMBUS_PIN_1_BXT + phy;
}
-static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
return intel_port_to_phy(dev_priv, port) + 1;
}
-static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
WARN_ON(port == PORT_B || port == PORT_C);
@@ -2824,9 +2839,9 @@ static u8 adls_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port
return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
}
-static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
- enum port port)
+static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)
{
+ enum port port = encoder->port;
u8 ddc_pin;
switch
[CI 5/7] drm/i915/display: use intel_encoder_is/to_* functions
Wherever possible, replace the port/phy based functions with the encoder
based functions:
intel_is_c10phy() -> intel_encoder_is_c10phy()
intel_phy_is_combo()-> intel_encoder_is_combo()
intel_phy_is_tc() -> intel_encoder_is_tc()
intel_port_to_phy() -> intel_encoder_to_phy()
intel_port_to_tc() -> intel_encoder_to_tc()
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 36 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 116 +++---
.../drm/i915/display/intel_ddi_buf_trans.c| 14 +--
.../i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 15 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 38 +++---
drivers/gpu/drm/i915/display/intel_pmdemand.c | 14 +--
drivers/gpu/drm/i915/display/intel_snps_phy.c | 12 +-
drivers/gpu/drm/i915/display/intel_tc.c | 33 ++---
10 files changed, 110 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f0ae2fe70c41..f893db353f91 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -423,7 +423,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
- enum phy phy = intel_port_to_phy(i915, encoder->port);
u8 owned_lane_mask;
intel_wakeref_t wakeref;
int n_entries, ln;
@@ -442,7 +441,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
return;
}
- if (intel_is_c10phy(i915, phy)) {
+ if (intel_encoder_is_c10phy(encoder)) {
intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CMN(3),
@@ -483,7 +482,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
MB_WRITE_COMMITTED);
- if (intel_is_c10phy(i915, phy))
+ if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
@@ -2046,10 +2045,8 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
{
struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
- struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- if (intel_is_c10phy(i915, phy))
+ if (intel_encoder_is_c10phy(_port->base))
return intel_c10_phy_check_hdmi_link_rate(clock);
return intel_c20_phy_check_hdmi_link_rate(clock);
}
@@ -2097,10 +2094,7 @@ static int intel_c20pll_calc_state(struct
intel_crtc_state *crtc_state,
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
-
- if (intel_is_c10phy(i915, phy))
+ if (intel_encoder_is_c10phy(encoder))
return intel_c10pll_calc_state(crtc_state, encoder);
return intel_c20pll_calc_state(crtc_state, encoder);
}
@@ -2652,7 +2646,7 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
enum port port = encoder->port;
- if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+ if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_MSGBUS_ACCESS,
@@ -2681,7 +2675,7 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
MB_WRITE_COMMITTED);
}
- if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+ if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_UPDATE_CFG,
@@ -2744,7 +2738,7 @@ static void intel_cx0pll_enable(struct intel_encoder
*encoder,
*/
/* 5. Program PHY internal PLL internal registers. */
- if (intel_is_c10phy(i915, phy))
+ if (intel_encoder_is_c10phy(encoder))
intel_c10_pll_program(i915,
[CI 4/7] drm/i915/display: add intel_encoder_is_*() and _to_*() functions
Add a number of encoder based functions to check if the port/phy of the
encoder is of a certain type, or to convert to phy or tc_port. Initially
these are just wrappers around the existing functions, but they can be
improved to use VBT data or use some cached info in the future.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 40
drivers/gpu/drm/i915/display/intel_display.h | 7
4 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 64e0f820a789..f0ae2fe70c41 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -29,6 +29,7 @@
#define INTEL_CX0_LANE1BIT(1)
#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
+/* Prefer intel_encoder_is_c10phy() */
bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
{
if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
@@ -37,6 +38,14 @@ bool intel_is_c10phy(struct drm_i915_private *i915, enum phy
phy)
return false;
}
+bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_encoder_to_phy(encoder);
+
+ return intel_is_c10phy(i915, phy);
+}
+
static int lane_mask_to_lane(u8 lane_mask)
{
if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c6682677253a..2be474877fdc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -23,6 +23,7 @@ struct intel_encoder;
struct intel_hdmi;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d366a103a707..c35a6a68218d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1836,6 +1836,7 @@ static void i9xx_pfit_enable(const struct
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
}
+/* Prefer intel_encoder_is_combo() */
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
@@ -1857,6 +1858,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
return false;
}
+/* Prefer intel_encoder_is_tc() */
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
@@ -1877,6 +1879,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
return false;
}
+/* Prefer intel_encoder_is_snps() */
bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
@@ -1886,6 +1889,7 @@ bool intel_phy_is_snps(struct drm_i915_private *dev_priv,
enum phy phy)
return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
}
+/* Prefer intel_encoder_to_phy() */
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
@@ -1903,6 +1907,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915,
enum port port)
return PHY_A + port - PORT_A;
}
+/* Prefer intel_encoder_to_tc() */
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port
port)
{
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
@@ -1914,6 +1919,41 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
*dev_priv, enum port port)
return TC_PORT_1 + port - PORT_C;
}
+enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return intel_port_to_phy(i915, encoder->port);
+}
+
+bool intel_encoder_is_combo(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
+}
+
+bool intel_encoder_is_snps(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder));
+}
+
+bool intel_encoder_is_tc(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder));
+}
+
+enum tc_port
[CI 3/7] drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()
Pass encoder to intel_snps_phy_update_psr_power_state(). The encoder
will be more helpful than just port in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 ++-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 --
drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 ++--
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 747761efa4be..3f35572354ba 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1724,7 +1724,6 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
u32 val;
drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
@@ -1752,7 +1751,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
intel_dp->psr.psr2_enabled ? "2" : "1");
- intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
+ intel_snps_phy_update_psr_power_state(_port->base, true);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
intel_dp->psr.enabled = true;
@@ -1823,8 +1822,6 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- enum phy phy = intel_port_to_phy(dev_priv,
-dp_to_dig_port(intel_dp)->base.port);
lockdep_assert_held(_dp->psr.lock);
@@ -1859,7 +1856,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
}
- intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
+ intel_snps_phy_update_psr_power_state(_to_dig_port(intel_dp)->base,
false);
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index bc61e736f9b3..7fc002268482 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -44,9 +44,11 @@ void intel_snps_phy_wait_for_calibration(struct
drm_i915_private *i915)
}
}
-void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915,
- enum phy phy, bool enable)
+void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
+ bool enable)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
u32 val;
if (!intel_phy_is_snps(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h
b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 515abf7c5902..bc08b92a7cd9 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -17,8 +17,8 @@ struct intel_mpllb_state;
enum phy;
void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
-void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
- enum phy phy, bool enable);
+void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
+ bool enable);
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder);
--
2.39.2
[CI 0/7] drm/i915: pass encoder around more for port/phy checks
v1 after the reviewed RFC [1]. BR, Jani. [1] https://lore.kernel.org/r/cover.1710253533.git.jani.nik...@intel.com Jani Nikula (7): drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin() drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active() drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state() drm/i915/display: add intel_encoder_is_*() and _to_*() functions drm/i915/display: use intel_encoder_is/to_* functions drm/i915/cx0: remove the unused intel_is_c10phy() drm/i915/cx0: pass encoder instead of i915 and port around drivers/gpu/drm/i915/display/intel_cx0_phy.c | 299 +- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 +- drivers/gpu/drm/i915/display/intel_ddi.c | 127 .../drm/i915/display/intel_ddi_buf_trans.c| 14 +- drivers/gpu/drm/i915/display/intel_display.c | 40 +++ drivers/gpu/drm/i915/display/intel_display.h | 7 + .../i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 15 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 80 ++--- drivers/gpu/drm/i915/display/intel_pmdemand.c | 14 +- drivers/gpu/drm/i915/display/intel_psr.c | 7 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 16 +- drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 +- drivers/gpu/drm/i915/display/intel_tc.c | 33 +- 15 files changed, 339 insertions(+), 344 deletions(-) -- 2.39.2
✗ Fi.CI.SPARSE: warning for Disable automatic load CCS load balancing (rev11)
== Series Details == Series: Disable automatic load CCS load balancing (rev11) URL : https://patchwork.freedesktop.org/series/129951/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
✗ Fi.CI.CHECKPATCH: warning for Disable automatic load CCS load balancing (rev11)
== Series Details == Series: Disable automatic load CCS load balancing (rev11) URL : https://patchwork.freedesktop.org/series/129951/ State : warning == Summary == Error: dim checkpatch failed 5cc9ec8ba58f drm/i915/gt: Disable HW load balancing for CCS 4f9767936687 drm/i915/gt: Do not generate the command streamer for all the CCS 049d5c33fbef drm/i915/gt: Enable only one CCS for compute workload Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: new file mode 100644 -:109: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'cslice' may be better as '(cslice)' to avoid precedence issues #109: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1486: +#define XEHP_CCS_MODE_CSLICE(cslice, ccs)(ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) -:109: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ccs' may be better as '(ccs)' to avoid precedence issues #109: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1486: +#define XEHP_CCS_MODE_CSLICE(cslice, ccs)(ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) total: 0 errors, 1 warnings, 2 checks, 89 lines checked
✓ Fi.CI.BAT: success for Disable automatic load CCS load balancing (rev11)
== Series Details == Series: Disable automatic load CCS load balancing (rev11) URL : https://patchwork.freedesktop.org/series/129951/ State : success == Summary == CI Bug Log - changes from CI_DRM_14455 -> Patchwork_129951v11 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/index.html Participating hosts (39 -> 38) -- Additional (2): bat-mtlp-8 fi-kbl-8809g Missing(3): fi-blb-e6850 fi-snb-2520m bat-arls-3 Known issues Here are the changes found in Patchwork_129951v11 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#10462]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [PASS][6] -> [FAIL][7] ([i915#10378]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_mocs: - bat-dg2-8: [PASS][13] -> [ABORT][14] ([i915#10366]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/bat-dg2-8/igt@i915_selftest@live@gt_mocs.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-dg2-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@guc_multi_lrc: - bat-dg2-9: [PASS][15] -> [ABORT][16] ([i915#10366]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/bat-dg2-9/igt@i915_selftest@live@guc_multi_lrc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-dg2-9/igt@i915_selftest@live@guc_multi_lrc.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#5190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@bad-pitch-65536: - fi-kbl-8809g: NOTRUN -> [FAIL][18] ([i915#10457]) +1 other test fail [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@kms_addfb_ba...@bad-pitch-65536.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4212]) +8 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@too-high: - fi-kbl-8809g: NOTRUN -> [FAIL][20] ([i915#10455]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v11/fi-kbl-8809g/igt@kms_addfb_ba...@too-high.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN ->
Re: [PATCH v6 0/3] Disable automatic load CCS load balancing
On 20/03/2024 15:06, Andi Shyti wrote: Ping! Any thoughts here? I only casually observed the discussion after I saw Matt suggested further simplifications. As I understood it, you will bring back the uabi engine games when adding the dynamic behaviour and that is fine by me. Regards, Tvrtko On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote: Hi, this series does basically two things: 1. Disables automatic load balancing as adviced by the hardware workaround. 2. Assigns all the CCS slices to one single user engine. The user will then be able to query only one CCS engine >From v5 I have created a new file, gt/intel_gt_ccs_mode.c where I added the intel_gt_apply_ccs_mode(). In the upcoming patches, this file will contain the implementation for dynamic CCS mode setting. Thanks Tvrtko, Matt, John and Joonas for your reviews! Andi Changelog = v5 -> v6 (thanks Matt for the suggestions in v6) - Remove the refactoring and the for_each_available_engine() macro and instead do not create the intel_engine_cs structure at all. - In patch 1 just a trivial reordering of the bit definitions. v4 -> v5 - Use the workaround framework to do all the CCS balancing settings in order to always apply the modes also when the engine resets. Put everything in its own specific function to be executed for the first CCS engine encountered. (Thanks Matt) - Calculate the CCS ID for the CCS mode as the first available CCS among all the engines (Thanks Matt) - create the intel_gt_ccs_mode.c function to host the CCS configuration. We will have it ready for the next series. - Fix a selftest that was failing because could not set CCS2. - Add the for_each_available_engine() macro to exclude CCS1+ and start using it in the hangcheck selftest. v3 -> v4 - Reword correctly the comment in the workaround - Fix a buffer overflow (Thanks Joonas) - Handle properly the fused engines when setting the CCS mode. v2 -> v3 - Simplified the algorithm for creating the list of the exported uabi engines. (Patch 1) (Thanks, Tvrtko) - Consider the fused engines when creating the uabi engine list (Patch 2) (Thanks, Matt) - Patch 4 now uses a the refactoring from patch 1, in a cleaner outcome. v1 -> v2 - In Patch 1 use the correct workaround number (thanks Matt). - In Patch 2 do not add the extra CCS engines to the exposed UABI engine list and adapt the engine counting accordingly (thanks Tvrtko). - Reword the commit of Patch 2 (thanks John). Andi Shyti (3): drm/i915/gt: Disable HW load balancing for CCS drm/i915/gt: Do not generate the command streamer for all the CCS drm/i915/gt: Enable only one CCS for compute workload drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20 --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 39 + drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 13 +++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++-- 6 files changed, 103 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h -- 2.43.0
✓ Fi.CI.BAT: success for drm/i915/gt: Reset queue_priority_hint on parking (rev2)
== Series Details == Series: drm/i915/gt: Reset queue_priority_hint on parking (rev2) URL : https://patchwork.freedesktop.org/series/131268/ State : success == Summary == CI Bug Log - changes from CI_DRM_14455 -> Patchwork_131268v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/index.html Participating hosts (39 -> 37) -- Additional (1): bat-mtlp-8 Missing(3): fi-blb-e6850 fi-snb-2520m bat-arls-3 Known issues Here are the changes found in Patchwork_131268v2 that come from known issues: ### CI changes ### Issues hit * boot: - fi-apl-guc: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/fi-apl-guc/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/fi-apl-guc/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#5190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4212]) +8 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4213]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#3840] / [i915#9159]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-mtlp-8: NOTRUN -> [SKIP][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#5274]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_psr@psr-primary-mmap-gtt@edp-1: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4077] / [i915#9688]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_psr@psr-primary-mmap-...@edp-1.html * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#8809]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-mmap: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#3708]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131268v2/bat-mtlp-8/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-write: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#10216] / [i915#3708]) [19]:
Re: [RFC 0/7] drm/i915: pass encoder around more for port/phy checks
On Tue, Mar 12, 2024 at 04:28:55PM +0200, Jani Nikula wrote: > Based on my ideas at [1], pass the encoder around more instead of i915, > port pair. Look up phy and TC port based on encoder. > > This could be later extended to e.g. cache the info to encoder and/or > look up data from encoder->devdata. > > I know relying solely on encoder has its drawbacks, namely not being > able to do stuff unless you have that encoder for that specific > port/phy. And have a reference to it. > > Thoughts? Yes. > > BR, > Jani. > > > [1] https://lore.kernel.org/r/87y1dnswgo@intel.com > > Jani Nikula (7): > drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin() > drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active() > drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state() > drm/i915/display: add intel_encoder_is_*() and _to_*() functions > drm/i915/display: use intel_encoder_is/to_* functions > drm/i915/cx0: remove intel_is_c10phy() > drm/i915/cx0: pass encoder instead of i915 and port around I have basically that same patch sitting in some branch. With commit messages polished the series is Reviewed-by: Ville Syrjälä > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 299 +- > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 127 > .../drm/i915/display/intel_ddi_buf_trans.c| 14 +- > drivers/gpu/drm/i915/display/intel_display.c | 40 +++ > drivers/gpu/drm/i915/display/intel_display.h | 7 + > .../i915/display/intel_display_power_well.c | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 15 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 +- > drivers/gpu/drm/i915/display/intel_hdmi.c | 80 ++--- > drivers/gpu/drm/i915/display/intel_pmdemand.c | 14 +- > drivers/gpu/drm/i915/display/intel_psr.c | 7 +- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 16 +- > drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 +- > drivers/gpu/drm/i915/display/intel_tc.c | 33 +- > 15 files changed, 339 insertions(+), 344 deletions(-) > > -- > 2.39.2 -- Ville Syrjälä Intel
[PATCH 5/6] drm/i915: Handle joined pipes inside hsw_crtc_enable()
Handle only bigjoiner masters in skl_commit_modeset_enables/disables,
slave crtcs should be handled by master hooks. Same for encoders.
That way we can also remove a bunch of checks like
intel_crtc_is_bigjoiner_slave.
v2: - Moved skl_pfit_enable, intel_dsc_enable, intel_crtc_vblank_on to
intel_enable_ddi,
so that it is now finally symmetrical with the disable case, because
currently
for some weird reason we are calling those from
skl_commit_modeset_enables, while
for the disable case those are called from the ddi disable hooks.
v3: - Create intel_ddi_enable_hdmi_or_sst symmetrical to
intel_ddi_post_disable_hdmi_or_sst and move it also under non-mst check.
v4: - Fix intel_enable_ddi sequence
- Call intel_crtc_update_active_timings for slave pipes as well
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_ddi.c | 45 -
drivers/gpu/drm/i915/display/intel_display.c | 179 ++-
drivers/gpu/drm/i915/display/intel_display.h | 7 +
3 files changed, 137 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 290ccab7c9ee8..9128b82a49c31 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3366,15 +3366,28 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
intel_wait_ddi_buf_active(dev_priv, port);
}
-static void intel_enable_ddi(struct intel_atomic_state *state,
-struct intel_encoder *encoder,
-const struct intel_crtc_state *crtc_state,
-const struct drm_connector_state *conn_state)
+static void intel_ddi_enable_hdmi_or_sst(struct intel_atomic_state *state,
+struct intel_encoder *encoder,
+const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state)
{
- drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ u8 pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc_in_pipe_mask_reverse(>drm, crtc, pipe_mask) {
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ intel_dsc_enable(new_crtc_state);
+
+ if (DISPLAY_VER(i915) >= 9)
+ skl_pfit_enable(new_crtc_state);
+ else
+ ilk_pfit_enable(new_crtc_state);
+ }
- if (!intel_crtc_is_bigjoiner_slave(crtc_state))
- intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ intel_ddi_enable_transcoder_func(encoder, crtc_state);
/* Enable/Disable DP2.0 SDP split config before transcoder */
intel_audio_sdp_split_update(crtc_state);
@@ -3383,7 +3396,22 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
- intel_crtc_vblank_on(crtc_state);
+ for_each_intel_crtc_in_pipe_mask_reverse(>drm, crtc, pipe_mask) {
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ intel_crtc_vblank_on(new_crtc_state);
+ }
+}
+
+static void intel_enable_ddi(struct intel_atomic_state *state,
+struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state *conn_state)
+{
+ drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
+
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+ intel_ddi_enable_hdmi_or_sst(state, encoder, crtc_state,
conn_state);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
@@ -3391,7 +3419,6 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
intel_hdcp_enable(state, encoder, crtc_state, conn_state);
-
}
static void intel_disable_ddi_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a1eccefde9f09..af029577e58bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -794,7 +794,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state
*state,
return encoder;
}
-static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
+void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
Re: [PATCH v6 0/3] Disable automatic load CCS load balancing
Ping! Any thoughts here? Andi On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote: > Hi, > > this series does basically two things: > > 1. Disables automatic load balancing as adviced by the hardware >workaround. > > 2. Assigns all the CCS slices to one single user engine. The user >will then be able to query only one CCS engine > > >From v5 I have created a new file, gt/intel_gt_ccs_mode.c where > I added the intel_gt_apply_ccs_mode(). In the upcoming patches, > this file will contain the implementation for dynamic CCS mode > setting. > > Thanks Tvrtko, Matt, John and Joonas for your reviews! > > Andi > > Changelog > = > v5 -> v6 (thanks Matt for the suggestions in v6) > - Remove the refactoring and the for_each_available_engine() >macro and instead do not create the intel_engine_cs structure >at all. > - In patch 1 just a trivial reordering of the bit definitions. > > v4 -> v5 > - Use the workaround framework to do all the CCS balancing >settings in order to always apply the modes also when the >engine resets. Put everything in its own specific function to >be executed for the first CCS engine encountered. (Thanks >Matt) > - Calculate the CCS ID for the CCS mode as the first available >CCS among all the engines (Thanks Matt) > - create the intel_gt_ccs_mode.c function to host the CCS >configuration. We will have it ready for the next series. > - Fix a selftest that was failing because could not set CCS2. > - Add the for_each_available_engine() macro to exclude CCS1+ and >start using it in the hangcheck selftest. > > v3 -> v4 > - Reword correctly the comment in the workaround > - Fix a buffer overflow (Thanks Joonas) > - Handle properly the fused engines when setting the CCS mode. > > v2 -> v3 > - Simplified the algorithm for creating the list of the exported >uabi engines. (Patch 1) (Thanks, Tvrtko) > - Consider the fused engines when creating the uabi engine list >(Patch 2) (Thanks, Matt) > - Patch 4 now uses a the refactoring from patch 1, in a cleaner >outcome. > > v1 -> v2 > - In Patch 1 use the correct workaround number (thanks Matt). > - In Patch 2 do not add the extra CCS engines to the exposed >UABI engine list and adapt the engine counting accordingly >(thanks Tvrtko). > - Reword the commit of Patch 2 (thanks John). > > Andi Shyti (3): > drm/i915/gt: Disable HW load balancing for CCS > drm/i915/gt: Do not generate the command streamer for all the CCS > drm/i915/gt: Enable only one CCS for compute workload > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20 --- > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 39 + > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 13 +++ > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 > drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++-- > 6 files changed, 103 insertions(+), 6 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > > -- > 2.43.0
✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Reset queue_priority_hint on parking (rev2)
== Series Details == Series: drm/i915/gt: Reset queue_priority_hint on parking (rev2) URL : https://patchwork.freedesktop.org/series/131268/ State : warning == Summary == Error: dim checkpatch failed 8dae724cae08 drm/i915/gt: Reset queue_priority_hint on parking -:19: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #19: <3>[ 166.210729] __engine_park:283 GEM_BUG_ON(engine->sched_engine->queue_priority_hint != (-((int)(~0U >> 1)) - 1)) total: 0 errors, 1 warnings, 0 checks, 18 lines checked
Re: Weirdness in parsing cpp macros
On Wed, 20 Mar 2024, Jani Nikula wrote: > On Wed, 20 Mar 2024, Ville Syrjälä wrote: > > On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote: > >> > >> > >> On Wed, 20 Mar 2024, Ville Syrjälä wrote: > >> > >> > Hi Julia et al, > >> > > >> > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch]) > >> > we have a magic macro like this: > >> > > >> > #define with_intel_pps_lock(dp, wf) \ > >> > >> Did you try declaring: > >> > >> iterator name with_intel_pps_lock; > >> > >> up with the metavariables? > > > > Nope, didn't know about that one. > > > > Seems to work fine with that. Thanks. > > Okay, I have another one wrt macros. :) > > I'm trying to add a completely new variadic macro, but it fails at > "...". I've tried all sorts of things, but can't seem to be able to add > a literal "...". > > I've tested that my cocci patch works with x's: > > + #define fn(p, xxx) foo(__VA_ARGS__) > > but when I try to make it actually variadic like: > > + #define fn(p, ...) foo(__VA_ARGS__) > > it gives me error. Is there a way to escape? Even tried to use a fresh > identifier vararg = "..."; but cocci made them unique with numbering > "...0" and "...1" etc. Put 6 dots. It's silly, but ... is a Coccinelle thing, so we had to use something else. julia
Re: [PATCH] drm/i915/gt: Reset queue_priority_hint on parking
Hi Janusz,
...
> Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Janusz Krzysztofik
> Cc: Chris Wilson
> Cc: # v5.4+
this tag list is a bit confusing. Let's keep all Cc's together
and, besides, Cc'eing the author looks a bit redundant.
No need to resend also because I retriggered another round of
test.
Reviewed-by: Andi Shyti
Thanks,
Andi
✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/bios: Tolerate devdata==NULL in intel_bios_encoder_supports_dp_dual_mode() (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/bios: Tolerate devdata==NULL in intel_bios_encoder_supports_dp_dual_mode() (rev2) URL : https://patchwork.freedesktop.org/series/131316/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14455 -> Patchwork_131316v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_131316v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_131316v2, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/index.html Participating hosts (39 -> 40) -- Additional (3): bat-kbl-2 bat-mtlp-8 fi-kbl-8809g Missing(2): fi-blb-e6850 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_131316v2: ### IGT changes ### Possible regressions * igt@kms_force_connector_basic@force-connector-state: - fi-kbl-guc: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html Known issues Here are the changes found in Patchwork_131316v2 that come from known issues: ### CI changes ### Issues hit * boot: - bat-arls-3: [PASS][3] -> [FAIL][4] ([i915#10234]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/bat-arls-3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][5] ([i915#10462]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/fi-kbl-8809g/igt@core_hotunp...@unbind-rebind.html * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#1849]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/fi-kbl-8809g/igt@fb...@info.html - bat-kbl-2: NOTRUN -> [SKIP][8] ([i915#1849]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-kbl-2/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][9] ([i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-kbl-2: NOTRUN -> [SKIP][11] +39 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-adls-6: [PASS][17] -> [TIMEOUT][18] ([i915#10026]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14455/bat-adls-6/igt@i915_selftest@live@gt_engines.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131316v2/bat-adls-6/igt@i915_selftest@live@gt_engines.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8:
Re: Weirdness in parsing cpp macros
On Wed, 20 Mar 2024, Ville Syrjälä wrote: > On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote: >> >> >> On Wed, 20 Mar 2024, Ville Syrjälä wrote: >> >> > Hi Julia et al, >> > >> > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch]) >> > we have a magic macro like this: >> > >> > #define with_intel_pps_lock(dp, wf) \ >> >> Did you try declaring: >> >> iterator name with_intel_pps_lock; >> >> up with the metavariables? > > Nope, didn't know about that one. > > Seems to work fine with that. Thanks. Okay, I have another one wrt macros. :) I'm trying to add a completely new variadic macro, but it fails at "...". I've tried all sorts of things, but can't seem to be able to add a literal "...". I've tested that my cocci patch works with x's: + #define fn(p, xxx) foo(__VA_ARGS__) but when I try to make it actually variadic like: + #define fn(p, ...) foo(__VA_ARGS__) it gives me error. Is there a way to escape? Even tried to use a fresh identifier vararg = "..."; but cocci made them unique with numbering "...0" and "...1" etc. BR, Jani. -- Jani Nikula, Intel
Re: Weirdness in parsing cpp macros
On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote: > > > On Wed, 20 Mar 2024, Ville Syrjälä wrote: > > > Hi Julia et al, > > > > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch]) > > we have a magic macro like this: > > > > #define with_intel_pps_lock(dp, wf) \ > > Did you try declaring: > > iterator name with_intel_pps_lock; > > up with the metavariables? Nope, didn't know about that one. Seems to work fine with that. Thanks. > > julia > > > > for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), > > (wf))) > > > > > > which we can then use like so: > > ... > > with_intel_pps_lock(intel_dp, wakeref) > > wait_panel_power_cycle(intel_dp); > > ... > > > > > > If I try to modify this code with eg. > > > > @@ > > @@ > > - wait_panel_power_cycle > > + _wait_panel_power_cycle > > > > spatch fails to parse the macro and won't do the changes here. > > > > > > While experimenting with this I discovered that > > I can make it work by: > > - moving the macro definition into intel_pps.c file from intel_pps.h > > - renaming the macro to contain the substring "for" (doesn't matter > > where in the macro name the "for" appears) > > > > What on earth is going on here? > > > > -- > > Ville Syrjälä > > Intel > > -- Ville Syrjälä Intel
Re: Weirdness in parsing cpp macros
On Wed, 20 Mar 2024, Ville Syrjälä wrote: > Hi Julia et al, > > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch]) > we have a magic macro like this: > > #define with_intel_pps_lock(dp, wf) \ Did you try declaring: iterator name with_intel_pps_lock; up with the metavariables? julia > for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), > (wf))) > > > which we can then use like so: > ... > with_intel_pps_lock(intel_dp, wakeref) > wait_panel_power_cycle(intel_dp); > ... > > > If I try to modify this code with eg. > > @@ > @@ > - wait_panel_power_cycle > + _wait_panel_power_cycle > > spatch fails to parse the macro and won't do the changes here. > > > While experimenting with this I discovered that > I can make it work by: > - moving the macro definition into intel_pps.c file from intel_pps.h > - renaming the macro to contain the substring "for" (doesn't matter > where in the macro name the "for" appears) > > What on earth is going on here? > > -- > Ville Syrjälä > Intel >
Weirdness in parsing cpp macros
Hi Julia et al, In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch]) we have a magic macro like this: #define with_intel_pps_lock(dp, wf) \ for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf))) which we can then use like so: ... with_intel_pps_lock(intel_dp, wakeref) wait_panel_power_cycle(intel_dp); ... If I try to modify this code with eg. @@ @@ - wait_panel_power_cycle + _wait_panel_power_cycle spatch fails to parse the macro and won't do the changes here. While experimenting with this I discovered that I can make it work by: - moving the macro definition into intel_pps.c file from intel_pps.h - renaming the macro to contain the substring "for" (doesn't matter where in the macro name the "for" appears) What on earth is going on here? -- Ville Syrjälä Intel
Re: [PATCH] drm/xe/display: fix type of intel_uncore_read*() functions
On Tue, 19 Mar 2024, Luca Coelho wrote: > On Tue, 2024-03-19 at 17:06 +0200, Jani Nikula wrote: >> On Tue, 19 Mar 2024, Lucas De Marchi wrote: >> > On Thu, Mar 14, 2024 at 08:52:21AM +0200, Luca Coelho wrote: >> > > Some of the backported intel_uncore_read*() functions used the wrong >> > > types. Change the function declarations accordingly. >> > > >> > > Reviewed-by: Gustavo Sousa >> > > Signed-off-by: Luca Coelho >> > >> > if a patch affects xe, please always Cc the xe mailing list so it >> > triggers CI on those machines >> >> Indeed. I just bounced the patch to intel-xe to trigger CI. > > Thanks, guys! I'll do it always from now on. Thanks for the patch and review, pushed to drm-xe-next. BR, Jani. > > -- > Cheers, > Luca. -- Jani Nikula, Intel
✓ Fi.CI.BAT: success for Wa_16021440873 and early transport fixes (rev2)
== Series Details == Series: Wa_16021440873 and early transport fixes (rev2) URL : https://patchwork.freedesktop.org/series/131324/ State : success == Summary == CI Bug Log - changes from CI_DRM_14453 -> Patchwork_131324v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/index.html Participating hosts (37 -> 36) -- Additional (1): bat-dg1-7 Missing(2): bat-kbl-2 fi-snb-2520m Known issues Here are the changes found in Patchwork_131324v2 that come from known issues: ### CI changes ### Issues hit * boot: - fi-apl-guc: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/fi-apl-guc/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/fi-apl-guc/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][3] ([i915#10234]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-arls-3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-14: [PASS][6] -> [FAIL][7] ([i915#10378]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg2-14/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg1-7/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10197] / [i915#10211] / [i915#4079]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg1-7/igt@gem_tiled_pread_basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10209]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@i915_pm_...@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#6621]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10200]) +9 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][21] ([i915#4212]) +7 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131324v2/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-7: NOTRUN
✗ Fi.CI.SPARSE: warning for Wa_16021440873 and early transport fixes (rev2)
== Series Details == Series: Wa_16021440873 and early transport fixes (rev2) URL : https://patchwork.freedesktop.org/series/131324/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
✓ Fi.CI.BAT: success for drm/i915: cleanup dead code
== Series Details == Series: drm/i915: cleanup dead code URL : https://patchwork.freedesktop.org/series/131354/ State : success == Summary == CI Bug Log - changes from CI_DRM_14453 -> Patchwork_131354v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/index.html Participating hosts (37 -> 36) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_131354v1 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-jsl-1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-jsl-1/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][3] ([i915#10234]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14453/bat-arls-3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10197] / [i915#10211] / [i915#4079]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10196] / [i915#4077]) +2 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10206] / [i915#4079]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10209]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@i915_pm_...@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#6621]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10200]) +9 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10202]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#9886]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10207]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#5274] / [i915#9792]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4342] / [i915#5354] / [i915#9792]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@hang-read-crc: - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#9792]) +7 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131354v1/bat-mtlp-6/igt@kms_pipe_crc_ba...@hang-read-crc.html *
✗ Fi.CI.SPARSE: warning for drm/i915: cleanup dead code
== Series Details == Series: drm/i915: cleanup dead code URL : https://patchwork.freedesktop.org/series/131354/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915: cleanup dead code
== Series Details == Series: drm/i915: cleanup dead code URL : https://patchwork.freedesktop.org/series/131354/ State : warning == Summary == Error: dim checkpatch failed 8f73eff2311a drm/i915: Drop dead code for xehpsdv -:918: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #918: FILE: drivers/gpu/drm/i915/intel_uncore.c:1538: + 0x13400 - 0x147ff: reserved */ \ -:928: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #928: FILE: drivers/gpu/drm/i915/intel_uncore.c:1544: + GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* \ + 0x16e00 - 0x1: render \ -:929: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #929: FILE: drivers/gpu/drm/i915/intel_uncore.c:1545: + 0x2 - 0x21fff: reserved */ \ total: 0 errors, 3 warnings, 0 checks, 818 lines checked 7af567a833e9 drm/i915: Remove XEHP_FWRANGES() -:175: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #175: FILE: drivers/gpu/drm/i915/intel_uncore.c:1476: + GEN_FW_RANGE(0x0, 0x1fff, 0), /* + 0x0 - 0xaff: reserved -:176: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #176: FILE: drivers/gpu/drm/i915/intel_uncore.c:1477: + 0xb00 - 0x1fff: always on */ -:180: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #180: FILE: drivers/gpu/drm/i915/intel_uncore.c:1481: + GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* + 0x4b00 - 0x4fff: reserved -:181: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #181: FILE: drivers/gpu/drm/i915/intel_uncore.c:1482: + 0x5000 - 0x51ff: always on */ -:186: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #186: FILE: drivers/gpu/drm/i915/intel_uncore.c:1487: + GEN_FW_RANGE(0x8160, 0x81ff, 0), /* + 0x8160 - 0x817f: reserved -:187: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #187: FILE: drivers/gpu/drm/i915/intel_uncore.c:1488: + 0x8180 - 0x81ff: always on */ -:191: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #191: FILE: drivers/gpu/drm/i915/intel_uncore.c:1492: + GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* + 0x8500 - 0x87ff: gt -:193: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #193: FILE: drivers/gpu/drm/i915/intel_uncore.c:1494: + 0x8c80 - 0x8cff: gt (DG2 only) */ -:195: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #195: FILE: drivers/gpu/drm/i915/intel_uncore.c:1496: + GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* + 0x8d00 - 0x8dff: render (DG2 only) -:196: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #196: FILE: drivers/gpu/drm/i915/intel_uncore.c:1497: + 0x8e00 - 0x8fff: reserved */ -:198: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #198: FILE: drivers/gpu/drm/i915/intel_uncore.c:1499: + GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* + 0x9000 - 0x947f: gt -:199: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #199: FILE: drivers/gpu/drm/i915/intel_uncore.c:1500: + 0x9480 - 0x94cf: reserved */ -:202: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #202: FILE: drivers/gpu/drm/i915/intel_uncore.c:1503: + GEN_FW_RANGE(0x9560, 0x967f, 0), /* + 0x9560 - 0x95ff: always on -:203: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #203: FILE: drivers/gpu/drm/i915/intel_uncore.c:1504: + 0x9600 - 0x967f: reserved */ -:205: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #205: FILE: drivers/gpu/drm/i915/intel_uncore.c:1506: + GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* + 0x9680 - 0x96ff: render -:206: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #206: FILE: drivers/gpu/drm/i915/intel_uncore.c:1507: + 0x9700 - 0x97ff: reserved */ -:208: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #208: FILE: drivers/gpu/drm/i915/intel_uncore.c:1509: + GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* + 0x9800 - 0xb4ff: gt -:210: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #210: FILE: drivers/gpu/drm/i915/intel_uncore.c:1511: + 0xc000 - 0xcfff: gt */ -:216: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #216: FILE: drivers/gpu/drm/i915/intel_uncore.c:1517: + GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* + 0xdd00 - 0xddff: gt -:217:
Re: [PATCH] drm/i915/scaler: Update Pipe src size check in skl_update_scaler
On 3/15/2024 1:56 PM, Ville Syrjälä wrote:
On Wed, Mar 13, 2024 at 08:08:25PM +0530, Ankit Nautiyal wrote:
For Earlier platforms, the Pipe source size is 12-bits so
max pipe source width and height is 4096. For newer platforms it is
13-bits so theoretically max width/height is 8192. For few of the
earlier platforms the scaler did not use all bits of the PIPESRC,
so max scaler source size was used to make that the pipe source
size is programmed within limits, before using scaler.
This creates a problem, for MTL where scaler source size is 4096, but
max pipe source width can theroretically be 8192.
Switch the check to use the max scaler destination size, which closely
match the limits.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
Thanks for the review, pushed to drm-intel-next.
Regards,
Ankit
---
drivers/gpu/drm/i915/display/skl_scaler.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drivers/gpu/drm/i915/display/skl_scaler.c
index 8a934bada624..baa601d27815 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -213,10 +213,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
* The pipe scaler does not use all the bits of PIPESRC, at least
* on the earlier platforms. So even when we're scaling a plane
* the *pipe* source size must not be too large. For simplicity
-* we assume the limits match the scaler source size limits. Might
-* not be 100% accurate on all platforms, but good enough for now.
+* we assume the limits match the scaler destination size limits.
+* Might not be 100% accurate on all platforms, but good enough for
+* now.
*/
- if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
+ if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) {
drm_dbg_kms(_priv->drm,
"scaler_user index %u.%u: pipe src size %ux%u "
"is out of scaler range\n",
--
2.40.1
[CI 5/6] drm/i915: Drop dead code for pvc
PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.
The registers not used anymore are also removed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 30 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 82 +-
.../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 12 --
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_pci.c | 36 -
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 70 +
drivers/gpu/drm/i915/intel_uncore.c | 142 --
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 -
22 files changed, 27 insertions(+), 480 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0c5cdab278b69..1495b60744928 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
* and kernel mode driver for caching policy control after GEN12.
* In the meantime platform specific tables are created to translate
* i915_cache_level into pat index, for more details check the macros
-* defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
+* defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
* For backward compatibility, this field contains values exactly match
* the entries of enum i915_cache_level for pre-GEN12 platforms (See
* LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index f59914df6b5a7..e9f65f27b53fb 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs
*engine)
{
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
- if (IS_PONTEVECCHIO(engine->i915))
- return false;
-
/*
* So far platforms supported by i915 having flat ccs do not require
* AUX invalidation. Check also whether the engine requires it.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 75bde8c1aa5da..396f5fe993c3f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct
intel_gt *gt)
}
}
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
- struct drm_i915_private *i915 = gt->i915;
- struct intel_gt_info *info = >info;
- unsigned long meml3_mask;
- unsigned long quad;
-
- if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
- return;
-
- meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
- meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
- /*
-* Link Copy engines may be fused off according to meml3_mask. Each
-* bit is a quad that houses 2 Link Copy and two Sub Copy engines.
-*/
- for_each_clear_bit(quad, _mask, GEN12_MAX_MSLICES) {
- unsigned int instance = quad * 2 + 1;
- intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
- _BCS(instance));
-
- if (mask & info->engine_mask) {
- gt_dbg(gt, "bcs%u fused off\n", instance);
- gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
- info->engine_mask &= ~mask;
- }
- }
-}
-
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
engine_mask_apply_media_fuses(gt);
[CI 6/6] drm/i915: Remove special handling for !RCS_MASK()
With both XEHPSDV and PVC removed (as platforms, most of their code remain used by others), there's no need to handle !RCS_MASK() as other platforms don't ever have fused-off render. Remove those code paths and the special WA flag when initializing GuC. Reviewed-by: Matt Roper Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++--- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 396f5fe993c3f..476651bd0a210 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -497,9 +497,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, engine->logical_mask = BIT(logical_instance); __sprint_engine_name(engine); - if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) && -__ffs(CCS_MASK(engine->gt)) == engine->instance) || -engine->class == RENDER_CLASS) + if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) && + __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance) engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE; /* features common between engines sharing EUs */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 217277329546c..3dd7699f2ad3b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -320,10 +320,6 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (IS_DG2_G11(gt->i915)) flags |= GUC_WA_CONTEXT_ISOLATION; - /* Wa_18020744125 */ - if (!RCS_MASK(gt)) - flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; - /* * Wa_14018913170: Applicable to all platforms supported by i915 so * don't bother testing for all X/Y/Z platforms explicitly. -- 2.43.0
[CI 1/6] drm/i915: Drop dead code for xehpsdv
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 --
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 -
drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 31 --
drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_hwmon.c | 6 --
drivers/gpu/drm/i915/i915_pci.c | 17
drivers/gpu/drm/i915/i915_perf.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 10 --
drivers/gpu/drm/i915/intel_uncore.c | 23 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -
24 files changed, 55 insertions(+), 384 deletions(-)
diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac6..bc26dc1261041 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0ed..1bd0e041e15c2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res,
+ struct sgt_dma *iter,
+ unsigned int pat_index,
+ u32 flags)
{
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
- if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
- xehpsdv_ppgtt_insert_huge(vm, vma_res, ,
pat_index, flags);
+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+ xehp_ppgtt_insert_huge(vm, vma_res, , pat_index,
flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, , pat_index,
flags);
} else {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
-static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
-
[CI 4/6] drm/i915: Update IP_VER(12, 50)
With no platform using graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c| 4 ++--
.../gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 10 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c| 8
drivers/gpu/drm/i915/gt/intel_migrate.c| 4 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_getparam.c | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++---
drivers/gpu/drm/i915/i915_perf.c | 8
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c| 2 +-
23 files changed, 46 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3ff3d8889c6cc..edb54903be0a2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
{
struct drm_i915_private *i915 = arg;
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct i915_address_space *vm;
struct i915_gem_context *ctx;
unsigned long max_pages;
@@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg)
static int igt_ppgtt_64K(void *arg)
{
struct drm_i915_private *i915 = arg;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 10a7847f1b049..bac15196b4d24 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct
drm_i915_private *i915)
if (gen < 12)
return true;
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return false;
return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
src_pitch = t->width; /* in dwords */
if (src->tiling == CLIENT_TILING_Y) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 55))
src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
} else if (src->tiling == CLIENT_TILING_X) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
dst_pitch = t->width; /* in dwords */
if (dst->tiling == CLIENT_TILING_Y) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 55))
dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
} else if (dst->tiling == CLIENT_TILING_X) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
v += x;
swizzle =
[CI 3/6] drm/i915: Stop inheriting IP_VER(12, 50)
All the platforms that inherit the media/graphics version
from XE_HPM_FEATURES / XE_HP_FEATURES just override it to another
version. Just set the version directly in the respective struct
and remove the versions from the _FEATURES macros. Since that was the
only use for XE_HPM_FEATURES, remove it completely.
Reviewed-by: Gustavo Sousa
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b318b7c6bf737..8b673fdcf178f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .__runtime.graphics.ip.ver = 12, \
- .__runtime.graphics.ip.rel = 50, \
XE_HP_PAGE_SIZES, \
TGL_CACHELEVEL, \
.dma_mask_size = 46, \
@@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_size = 48, \
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
-#define XE_HPM_FEATURES \
- .__runtime.media.ip.ver = 12, \
- .__runtime.media.ip.rel = 50
-
#define DG2_FEATURES \
XE_HP_FEATURES, \
- XE_HPM_FEATURES, \
DGFX_FEATURES, \
+ .__runtime.graphics.ip.ver = 12, \
.__runtime.graphics.ip.rel = 55, \
+ .__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_64k_pages = 1, \
@@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
__maybe_unused
static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
- XE_HPM_FEATURES,
DGFX_FEATURES,
+ .__runtime.graphics.ip.ver = 12,
.__runtime.graphics.ip.rel = 60,
+ .__runtime.media.ip.ver = 12,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.has_flat_ccs = 0,
--
2.43.0
[CI 2/6] drm/i915: Remove XEHP_FWRANGES()
Now that DG2 is the only user of this forcewake table, remove the macro
and use FORCEWAKE_RENDER explicitly for range 0xd800 - 0xd87f.
Suggested-by: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 297 ++--
1 file changed, 145 insertions(+), 152 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 7695bb946fff4..b525318dbd53b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1471,159 +1471,152 @@ static const struct intel_forcewake_range
__gen12_fw_ranges[] = {
0x1d3f00 - 0x1d3fff: VD2 */
};
-/*
- * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
- * switching it from the GT domain to the render domain.
- */
-#define XEHP_FWRANGES(FW_RANGE_D800) \
- GEN_FW_RANGE(0x0, 0x1fff, 0), /*
\
- 0x0 - 0xaff: reserved
\
- 0xb00 - 0x1fff: always on */
\
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
\
- GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
\
- 0x4b00 - 0x4fff: reserved
\
- 0x5000 - 0x51ff: always on */
\
- GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
\
- GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
\
- 0x8160 - 0x817f: reserved
\
- 0x8180 - 0x81ff: always on */
\
- GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
\
- GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*
\
- 0x8500 - 0x87ff: gt
\
- 0x8800 - 0x8c7f: reserved
\
- 0x8c80 - 0x8cff: gt (DG2 only) */
\
- GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*
\
- 0x8d00 - 0x8dff: render (DG2 only)
\
- 0x8e00 - 0x8fff: reserved */
\
- GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*
\
- 0x9000 - 0x947f: gt
\
- 0x9480 - 0x94cf: reserved */
\
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x9560, 0x967f, 0), /*
\
- 0x9560 - 0x95ff: always on
\
- 0x9600 - 0x967f: reserved */
\
- GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
\
- 0x9680 - 0x96ff: render (DG2 only)
\
- 0x9700 - 0x97ff: reserved */
\
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
\
- 0x9800 - 0xb4ff: gt
\
- 0xb500 - 0xbfff: reserved
\
- 0xc000 - 0xcfff: gt */
\
- GEN_FW_RANGE(0xd000, 0xd7ff, 0),
\
- GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800),\
- GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),
\
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
\
- 0xdd00 - 0xddff: gt
\
- 0xde00 - 0xde7f: reserved */
\
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
\
- 0xde80 - 0xdfff: render
\
- 0xe000 - 0xe0ff: reserved
\
- 0xe100 - 0xe8ff: render */
\
- GEN_FW_RANGE(0xe900, 0x, FORCEWAKE_GT), /*
\
-
[CI 0/6] drm/i915: cleanup dead code
For CI coverage. No change from previous version except the rebase. See 20240312235145.2443975-1-lucas.demar...@intel.com and 20240312235145.2443975-1-lucas.demar...@intel.com for details. I will probably wait the drm-next backmerge anyway so drm-intel-next and drm-intel-gt-next are back in sync. Lucas De Marchi (6): drm/i915: Drop dead code for xehpsdv drm/i915: Remove XEHP_FWRANGES() drm/i915: Stop inheriting IP_VER(12, 50) drm/i915: Update IP_VER(12, 50) drm/i915: Drop dead code for pvc drm/i915: Remove special handling for !RCS_MASK() Documentation/gpu/rfc/i915_vm_bind.h | 11 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +- .../i915/gem/selftests/i915_gem_client_blt.c | 8 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 5 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +- .../drm/i915/gt/intel_execlists_submission.c | 10 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 - drivers/gpu/drm/i915/gt/intel_gt.c| 4 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 52 +-- drivers/gpu/drm/i915/gt/intel_gt_mcr.h| 2 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 59 --- drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +-- drivers/gpu/drm/i915/gt/intel_migrate.c | 22 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +-- drivers/gpu/drm/i915/gt/intel_rps.c | 6 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 13 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 181 + .../gpu/drm/i915/gt/intel_workarounds.c.rej | 18 + drivers/gpu/drm/i915/gt/uc/intel_guc.c| 6 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 - drivers/gpu/drm/i915/i915_debugfs.c | 12 - drivers/gpu/drm/i915/i915_drv.h | 13 - drivers/gpu/drm/i915/i915_getparam.c | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_hwmon.c | 6 - drivers/gpu/drm/i915/i915_pci.c | 61 +-- drivers/gpu/drm/i915/i915_perf.c | 19 +- drivers/gpu/drm/i915/i915_query.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/intel_clock_gating.c | 26 +- drivers/gpu/drm/i915/intel_device_info.c | 2 - drivers/gpu/drm/i915/intel_device_info.h | 2 - drivers/gpu/drm/i915/intel_step.c | 80 +--- drivers/gpu/drm/i915/intel_uncore.c | 380 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 3 - .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 6 - 43 files changed, 232 insertions(+), 1032 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds.c.rej -- 2.43.0
