✗ Fi.CI.IGT: failure for drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
== Series Details == Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4) URL : https://patchwork.freedesktop.org/series/132932/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14668_full -> Patchwork_132932v4_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_132932v4_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_132932v4_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_132932v4_full: ### IGT changes ### Possible regressions * igt@kms_flip@blocking-absolute-wf_vblank-interruptible@c-edp1: - shard-mtlp: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14668/shard-mtlp-5/igt@kms_flip@blocking-absolute-wf_vblank-interrupti...@c-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-mtlp-2/igt@kms_flip@blocking-absolute-wf_vblank-interrupti...@c-edp1.html Known issues Here are the changes found in Patchwork_132932v4_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-keep-cache: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-mtlp-4/igt@api_intel...@object-reloc-keep-cache.html * igt@device_reset@unbind-cold-reset-rebind: - shard-rkl: NOTRUN -> [SKIP][4] ([i915#7701]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-3/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@isolation@rcs0: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8414]) +5 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-mtlp-4/igt@drm_fdinfo@isolat...@rcs0.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][6] ([i915#7742]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-4/igt@drm_fdi...@virtual-idle.html * igt@gem_basic@multigpu-create-close: - shard-rkl: NOTRUN -> [SKIP][7] ([i915#7697]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-4/igt@gem_ba...@multigpu-create-close.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: NOTRUN -> [FAIL][8] ([i915#6268]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html - shard-tglu: [PASS][9] -> [FAIL][10] ([i915#6268]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14668/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_eio@reset-stress: - shard-dg1: [PASS][11] -> [FAIL][12] ([i915#5784]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14668/shard-dg1-18/igt@gem_...@reset-stress.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-dg1-15/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@bonded-true-hang: - shard-mtlp: NOTRUN -> [SKIP][13] ([i915#4812]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-mtlp-4/igt@gem_exec_balan...@bonded-true-hang.html * igt@gem_exec_balancer@parallel: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#4525]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-4/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-deadline: - shard-glk: NOTRUN -> [FAIL][15] ([i915#2846]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-glk6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-rkl: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-rkl-3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: NOTRUN -> [FAIL][17] ([i915#2842]) +1 other test fail [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/shard-glk3/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][18] -> [FAIL][19] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14668/shard-rkl-3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [19]:
✓ Fi.CI.BAT: success for drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
== Series Details == Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4) URL : https://patchwork.freedesktop.org/series/132932/ State : success == Summary == CI Bug Log - changes from CI_DRM_14668 -> Patchwork_132932v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/index.html Participating hosts (36 -> 40) -- Additional (6): fi-kbl-7567u fi-apl-guc fi-glk-j4005 fi-kbl-8809g bat-mtlp-8 bat-mtlp-6 Missing(2): bat-kbl-2 fi-snb-2520m Known issues Here are the changes found in Patchwork_132932v4 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#1849] / [i915#2582]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-kbl-7567u: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-glk-j4005: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-apl-guc/igt@gem_lmem_swapp...@basic.html - fi-glk-j4005: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html - fi-kbl-7567u: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html - fi-kbl-8809g: NOTRUN -> [SKIP][11] ([i915#4613]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4083]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@gem_m...@basic.html - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4083]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4079]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#4077]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#4079]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#6621]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v4/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#6621]) [21]:
✗ Fi.CI.SPARSE: warning for drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
== Series Details == Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4) URL : https://patchwork.freedesktop.org/series/132932/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2
✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
== Series Details == Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4) URL : https://patchwork.freedesktop.org/series/132932/ State : warning == Summary == Error: dim checkpatch failed 523d06a4a2c2 drm/i915/gt: Automate CCS Mode setting during engine resets -:20: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #20: Reported-by: Gnattu OC Signed-off-by: Andi Shyti total: 0 errors, 1 warnings, 0 checks, 45 lines checked
Re: [PATCH] drm/xe/display: Fix ADL-N detection
On Thu, Apr 25, 2024 at 11:22:30AM GMT, Matt Roper wrote: On Thu, Apr 25, 2024 at 11:16:09AM -0700, Lucas De Marchi wrote: Contrary to i915, in xe ADL-N is kept as a different platform, not a subplatform of ADL-P. Since the display side doesn't need to differentiate between P and N, i.e. IS_ALDERLAKE_P_N() is never called, just fixup the compat header to check for both P and N. Moving ADL-N to be a subplatform would be more complex as the firmware loading in xe only handles platforms, not subplatforms, as going forward the direction is to check on IP version rather than platforms/subplatforms. Fix warning when initializing display: xe :00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH [ cut here ] xe :00:02.0: drm_WARN_ON(!((dev_priv)->info.platform == XE_ALDERLAKE_S) && !((dev_priv)->info.platform == XE_ALDERLAKE_P)) And wrong paths being taken on the display side. Signed-off-by: Lucas De Marchi ADL-N uses exactly the same display IP as ADL-P (unlike on the GT side where they differ), so Reviewed-by: Matt Roper applied, thanks Lucas De Marchi
[linux-next:master] BUILD REGRESSION bb7a2467e6beef44a80a17d45ebf2931e7631083
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: bb7a2467e6beef44a80a17d45ebf2931e7631083 Add linux-next specific files for 20240426 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202404262217.dt4hoodh-...@intel.com Error/Warning: (recently discovered and may have been fixed) arch/riscv/mm/init.c:1495:25: error: 'MODULES_VADDR' undeclared (first use in this function) arch/riscv/mm/init.c:1496:23: error: 'MODULES_END' undeclared (first use in this function) drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c:181:58: error: arithmetic between enumeration type 'enum dentist_divider_range' and floating-point type 'double' [-Werror,-Wenum-float-conversion] drivers/gpu/drm/drm_mm.c:152:1: error: unused function 'drm_mm_interval_tree_insert' [-Werror,-Wunused-function] drivers/gpu/drm/drm_mm.c:152:1: error: unused function 'drm_mm_interval_tree_iter_next' [-Werror,-Wunused-function] Unverified Error/Warning (likely false positive, please contact us if interested): ERROR: modpost: "add_preferred_console_match" [drivers/tty/serial/serial_base.ko] undefined! ERROR: modpost: "pnp_bus_type" [drivers/tty/serial/serial_base.ko] undefined! drivers/usb/dwc3/core.c:679:15: warning: variable 'hw_mode' set but not used [-Wunused-but-set-variable] Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- arc-allmodconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- arc-allyesconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- arm-randconfig-r111-20240426 | `-- drivers-gpu-drm-panel-panel-lg-sw43408.c:sparse:sparse:symbol-sw43408_backlight_ops-was-not-declared.-Should-it-be-static |-- arm-randconfig-r132-20240426 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- csky-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- csky-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- i386-allyesconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- i386-randconfig-001-20240426 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- i386-randconfig-053-20240427 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- i386-randconfig-r121-20240426 | |-- drivers-gpu-drm-panel-panel-lg-sw43408.c:(.text):undefined-reference-to-drm_dsc_pps_payload_pack | |-- drivers-gpu-drm-panel-panel-lg-sw43408.c:sparse:sparse:symbol-sw43408_backlight_ops-was-not-declared.-Should-it-be-static | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- loongarch-randconfig-r064-20231215 | `-- ERROR:pnp_bus_type-drivers-tty-serial-serial_base.ko-undefined |-- mips-allyesconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- mips-randconfig-r064-20240427 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- nios2-allmodconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- nios2-allyesconfig | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- nios2-randconfig-001-20240426 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- powerpc-randconfig-r061-20240427 | `-- ERROR:drm_dsc_pps_payload_pack-drivers-gpu-drm-panel-panel-lg-sw43408.ko-undefined |-- powerpc64-randconfig-001-20240426 | `-- drivers-usb-dwc3-core.c:warning:variable-hw_mode-set-but-not-used |-- powerpc64-randconfig-002-20240426 | `-- drivers-usb-dwc3-core.c:warn
Re: [PATCH v3 4/6] drm/i915/alpm: Add compute config for lobf
Hi Animesh, kernel test robot noticed the following build errors: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm/drm-next drm-exynos/exynos-drm-next next-20240426] [cannot apply to drm-intel/for-linux-next-fixes linus/master v6.9-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-i915-alpm-Move-alpm-parameters-from-intel_psr/20240425-025652 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20240424183820.3591593-5-animesh.manna%40intel.com patch subject: [PATCH v3 4/6] drm/i915/alpm: Add compute config for lobf config: loongarch-allmodconfig (https://download.01.org/0day-ci/archive/20240427/202404270117.qrlkmdn7-...@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240427/202404270117.qrlkmdn7-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202404270117.qrlkmdn7-...@intel.com/ All errors (new ones prefixed by >>, old ones prefixed by <<): WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/mtd/maps/map_funcs.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/spmi/hisi-spmi-controller.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/spmi/spmi-pmic-arb.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_cif.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_aec.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_netx.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_pruss.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_mf624.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/pcmcia_rsrc.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/yenta_socket.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/i82092.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/hwmon/corsair-cpro.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/hwmon/mr75203.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/vhost/vringh.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/greybus/greybus.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/greybus/gb-es2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/rpmsg/rpmsg_char.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/adc/ingenic-adc.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/adc/xilinx-ams.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/buffer/kfifo_buf.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-core.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-hub.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-aspeed.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-gpio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-ast-cf.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-scom.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/siox/siox-bus-gpio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/counter/ftm-quaddec.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/core/snd-pcm-dmaengine.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/core/sound_kunit.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/drivers/snd-pcmtest.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/pci/hda/snd-hda-cirrus-scodec-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/soc-topology-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-ab8500-codec.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-sigmadsp.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-wm-adsp.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/fsl/imx-pcm-dma.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-da7219.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-dmic.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-i2s-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-max98927.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-max98357a.o WARNING: modp
Re: [PATCH] drm/i915/gt: Disarm breadcrumbs if engines are already idle
On 4/23/2024 6:23 PM, Janusz Krzysztofik wrote:
From: Chris Wilson
The breadcrumbs use a GT wakeref for guarding the interrupt, but are
disarmed during release of the engine wakeref. This leaves a hole where
we may attach a breadcrumb just as the engine is parking (after it has
parked its breadcrumbs), execute the irq worker with some signalers still
attached, but never be woken again.
That issue manifests itself in CI with IGT runner timeouts while tests
are waiting indefinitely for release of all GT wakerefs.
<6> [209.151778] i915: Running live_engine_pm_selftests/live_engine_busy_stats
<7> [209.231628] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_5
<7> [209.231816] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_4
<7> [209.231944] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_3
<7> [209.232056] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling PW_2
<7> [209.232166] i915 :00:02.0: [drm:intel_power_well_disable [i915]]
disabling DC_off
<7> [209.232270] i915 :00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [209.232368] i915 :00:02.0: [drm:gen9_set_dc_state.part.0 [i915]]
Setting DC state from 00 to 02
<4> [299.356116] [IGT] Inactivity timeout exceeded. Killing the current test
with SIGQUIT.
...
<6> [299.356526] sysrq: Show State
...
<6> [299.373964] task:i915_selftest state:D stack:11784 pid:5578 tgid:5578
ppid:873flags:0x4002
<6> [299.373967] Call Trace:
<6> [299.373968]
<6> [299.373970] __schedule+0x3bb/0xda0
<6> [299.373974] schedule+0x41/0x110
<6> [299.373976] intel_wakeref_wait_for_idle+0x82/0x100 [i915]
<6> [299.374083] ? __pfx_var_wake_function+0x10/0x10
<6> [299.374087] live_engine_busy_stats+0x9b/0x500 [i915]
<6> [299.374173] __i915_subtests+0xbe/0x240 [i915]
<6> [299.374277] ? __pfx___intel_gt_live_setup+0x10/0x10 [i915]
<6> [299.374369] ? __pfx___intel_gt_live_teardown+0x10/0x10 [i915]
<6> [299.374456] intel_engine_live_selftests+0x1c/0x30 [i915]
<6> [299.374547] __run_selftests+0xbb/0x190 [i915]
<6> [299.374635] i915_live_selftests+0x4b/0x90 [i915]
<6> [299.374717] i915_pci_probe+0x10d/0x210 [i915]
At the end of the interrupt worker, if there are no more engines awake,
disarm the breadcrumb and go to sleep.
Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to after
submission")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/10026
Signed-off-by: Chris Wilson
Cc: Andrzej Hajda
Cc: # v5.12+
Signed-off-by: Janusz Krzysztofik
Acked-by: Nirmoy Das
I will let others/Andrzej r-b this as I am not very familiar with the code.
Thanks,
Nirmoy
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index d650beb8ed22f..20b9b04ec1e0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -263,8 +263,13 @@ static void signal_irq_work(struct irq_work *work)
i915_request_put(rq);
}
+ /* Lazy irq enabling after HW submission */
if (!READ_ONCE(b->irq_armed) && !list_empty(>signalers))
intel_breadcrumbs_arm_irq(b);
+
+ /* And confirm that we still want irqs enabled before we yield */
+ if (READ_ONCE(b->irq_armed) && !atomic_read(>active))
+ intel_breadcrumbs_disarm_irq(b);
}
struct intel_breadcrumbs *
@@ -315,13 +320,7 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
return;
/* Kick the work once more to drain the signalers, and disarm the irq */
- irq_work_sync(>irq_work);
- while (READ_ONCE(b->irq_armed) && !atomic_read(>active)) {
- local_irq_disable();
- signal_irq_work(>irq_work);
- local_irq_enable();
- cond_resched();
- }
+ irq_work_queue(>irq_work);
}
void intel_breadcrumbs_free(struct kref *kref)
@@ -404,7 +403,7 @@ static void insert_breadcrumb(struct i915_request *rq)
* the request as it may have completed and raised the interrupt as
* we were attaching it into the lists.
*/
- if (!b->irq_armed || __i915_request_is_complete(rq))
+ if (!READ_ONCE(b->irq_armed) || __i915_request_is_complete(rq))
irq_work_queue(>irq_work);
}
Re: [PATCH] MAINTAINERS: Move the drm-intel repo location to fd.o GitLab
On 26/04/2024 16:47, Lucas De Marchi wrote: On Wed, Apr 24, 2024 at 01:41:59PM GMT, Ryszard Knop wrote: The drm-intel repo is moving from the classic fd.o git host to GitLab. Update its location with a URL matching other fd.o GitLab kernel trees. Signed-off-by: Ryszard Knop Acked-by: Lucas De Marchi Also Cc'ing maintainers Thanks, Acked-by: Tvrtko Ursulin Regards, Tvrtko --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index d6327dc12cb1..fbf7371a0bb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10854,7 +10854,7 @@ W: https://drm.pages.freedesktop.org/intel-docs/ Q: http://patchwork.freedesktop.org/project/intel-gfx/ B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html C: irc://irc.oftc.net/intel-gfx -T: git git://anongit.freedesktop.org/drm-intel +T: git https://gitlab.freedesktop.org/drm/i915/kernel.git F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon F: Documentation/gpu/i915.rst F: drivers/gpu/drm/ci/xfails/i915* -- 2.44.0
Re: [PATCH] MAINTAINERS: Move the drm-intel repo location to fd.o GitLab
On Wed, Apr 24, 2024 at 01:41:59PM GMT, Ryszard Knop wrote: The drm-intel repo is moving from the classic fd.o git host to GitLab. Update its location with a URL matching other fd.o GitLab kernel trees. Signed-off-by: Ryszard Knop Acked-by: Lucas De Marchi Also Cc'ing maintainers --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index d6327dc12cb1..fbf7371a0bb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10854,7 +10854,7 @@ W: https://drm.pages.freedesktop.org/intel-docs/ Q: http://patchwork.freedesktop.org/project/intel-gfx/ B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html C: irc://irc.oftc.net/intel-gfx -T: git git://anongit.freedesktop.org/drm-intel +T: git https://gitlab.freedesktop.org/drm/i915/kernel.git F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon F: Documentation/gpu/i915.rst F: drivers/gpu/drm/ci/xfails/i915* -- 2.44.0
Re: [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
On Fri, Apr 26, 2024 at 01:51:36PM +0300, Jani Nikula wrote: > Clean up i915_reg.h. > > v2: Drop chicken regs and comments (Ville) > > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 + > drivers/gpu/drm/i915/i915_reg.h | 123 -- > drivers/gpu/drm/i915/intel_clock_gating.c | 1 + > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + > 6 files changed, 125 insertions(+), 123 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index 7c4d2b2bf20b..151dcd0c45b6 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -54,6 +54,7 @@ > #include "intel_display_trace.h" > #include "intel_display_types.h" > #include "intel_fbc.h" > +#include "intel_fbc_regs.h" > #include "intel_frontbuffer.h" > > #define for_each_fbc_id(__dev_priv, __fbc_id) \ > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h > new file mode 100644 > index ..ae0699c3c2fe > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h > @@ -0,0 +1,120 @@ > +/* SPDX-License-Identifier: MIT */ > +/* Copyright © 2024 Intel Corporation */ > + > +#ifndef __INTEL_FBC_REGS__ > +#define __INTEL_FBC_REGS__ > + > +#include "intel_display_reg_defs.h" > + > +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ > +#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ > +#define FBC_CONTROL _MMIO(0x3208) > +#define FBC_CTL_EN REG_BIT(31) > +#define FBC_CTL_PERIODIC REG_BIT(30) > +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) > +#define FBC_CTL_INTERVAL(x) > REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) > +#define FBC_CTL_STOP_ON_MODREG_BIT(15) > +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ > +#define FBC_CTL_C3_IDLEREG_BIT(13) /* i945gm only */ > +#define FBC_CTL_STRIDE_MASKREG_GENMASK(12, 5) > +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) > +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) > +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, > (x)) > +#define FBC_COMMAND _MMIO(0x320c) > +#define FBC_CMD_COMPRESS REG_BIT(0) > +#define FBC_STATUS _MMIO(0x3210) > +#define FBC_STAT_COMPRESSING REG_BIT(31) > +#define FBC_STAT_COMPRESSEDREG_BIT(30) > +#define FBC_STAT_MODIFIED REG_BIT(29) > +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) > +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ > +#define FBC_CTL_FENCE_DBL REG_BIT(4) > +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) > +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) > +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) > +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) > +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) > +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1) > +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) > +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, > (i9xx_plane)) > +#define FBC_FENCE_OFF_MMIO(0x3218) /* i965gm only, BSpec > typo has 321Bh */ > +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ > +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) > +#define FBC_MOD_NUM_VALID REG_BIT(0) > +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ > +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags > per register */ > +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) > +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) > +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) > +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) > + > +#define FBC_LL_SIZE (1536) > + > +#define DPFC_CB_BASE _MMIO(0x3200) > +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) > +#define DPFC_CONTROL _MMIO(0x3208) > +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) > +#define DPFC_CTL_ENREG_BIT(31) > +#define DPFC_CTL_PLANE_MASK_G4XREG_BIT(30) /* g4x-snb */ > +#define DPFC_CTL_PLANE_G4X(i9xx_plane) > REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) > +#define DPFC_CTL_FENCE_EN_G4X
Re: [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
On Fri, 26 Apr 2024, Jani Nikula wrote: > Hey all, it's time to stop using the implicit dev_priv local variable in > register macros. Yes, this is huge. It's also (almost) completely > scripted. Okay, I was first going to send the entire series, but chickened out and hit ^C when git send-email was going though the patches. You get the idea with what's here. It's just more of the same. Plus I pushed the lot to [1]. I think we'll need to do this. The question is how to handle this churn. Do we want this many patches? If not, how much to squash? BR, Jani. [1] https://gitlab.freedesktop.org/jani/linux/-/commits/regs-mass-dev-priv-removal/?ref_type=heads -- Jani Nikula, Intel
[PATCH 017/123] drm/i915: pass dev_priv explicitly to TRANS_HSYNC
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HSYNC register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index af0d3159369e..f87a2170ac91 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -938,7 +938,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
+ intel_de_write(dev_priv,
+ TRANS_HSYNC(dev_priv, dsi_trans),
HSYNC_START(hsync_start - 1) |
HSYNC_END(hsync_end - 1));
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b9da3605b6aa..49c63b8855b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2711,7 +2711,7 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
@@ -2817,7 +2817,7 @@ static void intel_get_transcoder_timings(struct
intel_crtc *crtc,
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK,
tmp) + 1;
}
- tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp)
+ 1;
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
@@ -8167,7 +8167,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
HACTIVE(640 - 1) | HTOTAL(800 - 1));
intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
VACTIVE(480 - 1) | VTOTAL(525 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 625b1fedd54c..480c0e09434d 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -228,7 +228,7 @@ static void ilk_pch_transcoder_set_timings(const struct
intel_crtc_state *crtc_s
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
intel_de_read(dev_priv, TRANS_HBLANK(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HSYNC(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5ddcb6d9127..57a195c5b698 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1731,7 +1731,7 @@
#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HTOTAL_A)
#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HBLANK_A)
-#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
+#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans)_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
#define TRANS_VBLANK(trans)_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
diff --git
[PATCH 016/123] drm/i915: pass dev_priv explicitly to TRANS_HBLANK
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HBLANK register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d84c5541f3ee..b9da3605b6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2708,7 +2708,7 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
@@ -2811,7 +2811,8 @@ static void intel_get_transcoder_timings(struct
intel_crtc *crtc,
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_HBLANK(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hblank_start =
REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK,
tmp) + 1;
}
@@ -8164,7 +8165,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 2bf00d5336e3..625b1fedd54c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct
intel_crtc_state *crtc_s
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HBLANK(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ab39bbd1d2d..f5ddcb6d9127 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1730,7 +1730,7 @@
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HTOTAL_A)
-#define TRANS_HBLANK(trans)_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
+#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
_TRANS_HBLANK_A)
#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans)_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
#define TRANS_VBLANK(trans)_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 09db1d7a777d..7243b36b2a4e 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -227,7 +227,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HBLANK(TRANSCODER_A));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_HSYNC(TRANSCODER_A));
MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
MMIO_D(TRANS_VBLANK(TRANSCODER_A));
@@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
[PATCH 015/123] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HTOTAL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 79ecfc339430..af0d3159369e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -915,7 +915,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
/* program TRANS_HTOTAL register */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5b6025e2f621..d84c5541f3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2705,7 +2705,7 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
vsyncshift);
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
@@ -2806,7 +2806,7 @@ static void intel_get_transcoder_timings(struct
intel_crtc *crtc,
struct drm_display_mode *adjusted_mode = _config->hw.adjusted_mode;
u32 tmp;
- tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
@@ -8162,7 +8162,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 826e38a9e6a4..2bf00d5336e3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -224,7 +224,7 @@ static void ilk_pch_transcoder_set_timings(const struct
intel_crtc_state *crtc_s
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv,
cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index f85bf59cdeaf..63a8dfbe4cb3 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -672,7 +672,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu
*vgpu)
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
/* Get H/V total from transcoder timing */
- htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >>
TRANS_HTOTAL_SHIFT);
+ htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >>
TRANS_HTOTAL_SHIFT);
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >>
TRANS_VTOTAL_SHIFT);
if (dp_br && link_n && htotal && vtotal) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9bd827eba60..3ab39bbd1d2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1729,7 +1729,7 @@
#define _TRANS_VSYNC_DSI1 0x6b814
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
-#define TRANS_HTOTAL(trans)
[PATCH 014/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_RES2_G4X register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index b83e4f312f7e..04e867db0878 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -383,7 +383,8 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, res1 = 0; if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) - res2 = intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); + res2 = intel_uncore_read(_priv->uncore, +PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); else res2 = 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8c79bfc02714..c9bd827eba60 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1660,7 +1660,7 @@ #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A0x6 -- 2.39.2
[PATCH 013/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_RES1_I915 register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 5738e06a773c..b83e4f312f7e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -377,7 +377,8 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 res1, res2; if (DISPLAY_VER(dev_priv) >= 3) - res1 = intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); + res1 = intel_uncore_read(_priv->uncore, +PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); else res1 = 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b50115d1f1d4..8c79bfc02714 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1659,7 +1659,7 @@ #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) #define PIPE_CRC_RES_RES2_G4X(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) /* Pipe/transcoder A timing regs */ -- 2.39.2
[PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_BLUE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 77be9f2029ac..5738e06a773c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -389,7 +389,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, display_pipe_crc_irq_handler(dev_priv, pipe, intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), res1, res2); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 68a2dea9017b..b50115d1f1d4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1658,7 +1658,7 @@ #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) #define PIPE_CRC_RES_RES2_G4X(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) -- 2.39.2
[PATCH 011/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_GREEN register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 4593f5244706..77be9f2029ac 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -388,7 +388,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, display_pipe_crc_irq_handler(dev_priv, pipe, intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), res1, res2); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87c637039480..68a2dea9017b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1657,7 +1657,7 @@ #define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) #define PIPE_CRC_RES_BLUE(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) #define PIPE_CRC_RES_RES2_G4X(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) -- 2.39.2
[PATCH 010/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_RED register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 8bef21f74010..4593f5244706 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -387,7 +387,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, res2 = 0; display_pipe_crc_irq_handler(dev_priv, pipe, -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RED(pipe)), +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), res1, res2); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6f85d5b23c2c..87c637039480 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1656,7 +1656,7 @@ #define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) #define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) -#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) #define PIPE_CRC_RES_BLUE(pipe)_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -- 2.39.2
[PATCH 009/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_5_IVB register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 919ff34a7bb1..8bef21f74010 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -368,7 +368,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, intel_uncore_read(_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2544d2f0220c..6f85d5b23c2c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1654,7 +1654,7 @@ #define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) #define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) #define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -- 2.39.2
[PATCH 008/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_4_IVB
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_4_IVB register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index a17c258bb219..919ff34a7bb1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -367,7 +367,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, intel_uncore_read(_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 248312e6e06e..2544d2f0220c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1653,7 +1653,7 @@ #define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) #define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) #define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) +#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -- 2.39.2
[PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_3_IVB register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d810a0bab901..a17c258bb219 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -366,7 +366,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, display_pipe_crc_irq_handler(dev_priv, pipe, intel_uncore_read(_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), -intel_uncore_read(_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), +intel_uncore_read(_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), intel_uncore_read(_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7b7b9f73db02..248312e6e06e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1652,7 +1652,7 @@ #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) #define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) -- 2.39.2
[PATCH 006/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_2_IVB
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_2_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 45abbc169bf5..d810a0bab901 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -365,7 +365,7 @@ static void ivb_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
{
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
-intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_2_IVB(pipe)),
+intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_3_IVB(pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_4_IVB(pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_5_IVB(pipe)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cabc938843b3..7b7b9f73db02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1651,7 +1651,7 @@
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_1_A_IVB)
-#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_2_A_IVB)
+#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_5_A_IVB)
--
2.39.2
[PATCH 005/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_1_IVB
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_1_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c337e0597541..45abbc169bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -356,7 +356,7 @@ static void hsw_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
-intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_1_IVB(pipe)),
+intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
0, 0, 0, 0);
}
@@ -364,7 +364,7 @@ static void ivb_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
-intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_1_IVB(pipe)),
+intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_2_IVB(pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_3_IVB(pipe)),
intel_uncore_read(_priv->uncore,
PIPE_CRC_RES_4_IVB(pipe)),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c8a9c5ccd4f..cabc938843b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1650,7 +1650,7 @@
#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_CTL_A)
-#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_1_A_IVB)
+#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_4_A_IVB)
--
2.39.2
[PATCH 004/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_CTL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 5a468ed6e26c..35c3dd1130ce 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -608,8 +608,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const
char *source_name)
goto out;
pipe_crc->source = source;
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
if (!source) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -643,8 +643,8 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
/* Don't need pipe_crc->lock here, IRQs are not generated. */
pipe_crc->skipped = 0;
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
}
void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
@@ -658,7 +658,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
pipe_crc->skipped = INT_MIN;
spin_unlock_irq(_crc->lock);
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
intel_synchronize_irq(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c07b489073d..7c8a9c5ccd4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1649,7 +1649,7 @@
#define _PIPE_CRC_RES_4_B_IVB 0x61070
#define _PIPE_CRC_RES_5_B_IVB 0x61074
-#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_CTL_A)
+#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
_PIPE_CRC_RES_3_A_IVB)
--
2.39.2
[PATCH 003/123] drm/i915: pass dev_priv explicitly to PALETTE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PALETTE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 29 ++
drivers/gpu/drm/i915/i915_reg.h| 2 +-
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ca7112b32cb3..edb805fc9c97 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1227,7 +1227,7 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc,
lut = blob->data;
for (i = 0; i < 256; i++)
- intel_de_write_fw(dev_priv, PALETTE(pipe, i),
+ intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i),
i9xx_lut_8([i]));
}
@@ -1240,9 +1240,11 @@ static void i9xx_load_lut_10(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size - 1; i++) {
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0),
i9xx_lut_10_ldw([i]));
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1),
i9xx_lut_10_udw([i]));
}
}
@@ -1274,9 +1276,11 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size - 1; i++) {
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0),
i965_lut_10p6_ldw([i]));
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1),
i965_lut_10p6_udw([i]));
}
@@ -3150,7 +3154,8 @@ static struct drm_property_blob *i9xx_read_lut_8(struct
intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
- u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i));
+ u32 val = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, i));
i9xx_lut_8_pack([i], val);
}
@@ -3176,8 +3181,10 @@ static struct drm_property_blob *i9xx_read_lut_10(struct
intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
- udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
+ ldw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0));
+ udw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1));
i9xx_lut_10_pack([i], ldw, udw);
}
@@ -3224,8 +3231,10 @@ static struct drm_property_blob
*i965_read_lut_10p6(struct intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
- u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
+ u32 ldw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0));
+ u32 udw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1));
i965_lut_10p6_pack([i], ldw, udw);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 744698a9c107..5c07b489073d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1480,7 +1480,7 @@
#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
-#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
\
+#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
\
_PICK_EVEN_2RANGES(pipe, 2,
\
_PALETTE_A, _PALETTE_B,
\
_CHV_PALETTE_C,
_CHV_PALETTE_C) + \
--
2.39.2
[PATCH 001/123] drm/i915: pass dev_priv explicitly to DPLL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 21 -
.../drm/i915/display/intel_display_power.c| 2 +-
.../i915/display/intel_display_power_well.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 45 ++-
drivers/gpu/drm/i915/display/intel_dvo.c | 5 ++-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
7 files changed, 43 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f45e5f02096d..5b6025e2f621 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -376,11 +376,11 @@ void vlv_wait_port_ready(struct drm_i915_private
*dev_priv,
fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
break;
case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
expected_mask <<= 4;
break;
case PORT_D:
@@ -8185,11 +8185,12 @@ void i830_enable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+ dpll & ~DPLL_VGA_MODE_DIS);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -8197,12 +8198,12 @@ void i830_enable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* We do this three times for luck */
for (i = 0; i < 3 ; i++) {
- intel_de_write(dev_priv, DPLL(pipe), dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150); /* wait for warmup */
}
@@ -8235,8 +8236,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
intel_wait_for_pipe_scanline_stopped(crtc);
- intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
}
void intel_hpd_poll_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 03dc7edcc443..354083128efb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1768,7 +1768,7 @@ static void chv_phy_control_init(struct drm_i915_private
*dev_priv)
* current lane status.
*/
if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
- u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
+ u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
unsigned int mask;
mask = status & DPLL_PORTB_READY_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e8a6e53fd551..77b586f9e931 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1195,13 +1195,13 @@ static void vlv_display_power_well_init(struct
drm_i915_private *dev_priv)
* CHV DPLL B/C have some issues if VGA mode is enabled.
*/
for_each_pipe(dev_priv, pipe) {
- u32 val = intel_de_read(dev_priv, DPLL(pipe));
+ u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe));
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
- intel_de_write(dev_priv, DPLL(pipe), val);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
}
[PATCH 002/123] drm/i915: pass dev_priv explicitly to DPLL_MD
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL_MD register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index ccd299e31e95..3f29316da5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -397,7 +397,8 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
else
- tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+ tmp = intel_de_read(dev_priv,
+ DPLL_MD(dev_priv, crtc->pipe));
hw_state->dpll_md = tmp;
}
@@ -1849,7 +1850,8 @@ void i9xx_enable_pll(const struct intel_crtc_state
*crtc_state)
udelay(150);
if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+ hw_state->dpll_md);
} else {
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
@@ -2023,8 +2025,8 @@ void vlv_enable_pll(const struct intel_crtc_state
*crtc_state)
_vlv_enable_pll(crtc_state);
}
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
+ intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
}
static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -2183,7 +2185,8 @@ void chv_enable_pll(const struct intel_crtc_state
*crtc_state)
* the value from DPLLBMD to either pipe B or C.
*/
intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
- intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B),
+ hw_state->dpll_md);
intel_de_write(dev_priv, CBR4_VLV, 0);
dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
@@ -2195,8 +2198,9 @@ void chv_enable_pll(const struct intel_crtc_state
*crtc_state)
(intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
DPLL_VGA_MODE_DIS) == 0);
} else {
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+ hw_state->dpll_md);
+ intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f34069b05b0..744698a9c107 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1250,7 +1250,7 @@
#define _DPLL_A_MD 0x601c
#define _DPLL_B_MD 0x6020
#define _CHV_DPLL_C_MD 0x603c
-#define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+#define DPLL_MD(dev_priv, pipe)
_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
(pipe), _DPLL_A_MD,
_DPLL_B_MD, _CHV_DPLL_C_MD)
/*
--
2.39.2
[PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
Hey all, it's time to stop using the implicit dev_priv local variable in
register macros. Yes, this is huge. It's also (almost) completely
scripted.
Thoughts?
BR,
Jani.
Here's the script:
#!/bin/bash
set -e
# Find all the registers implicitly relying on dev_priv
REGS=$(git grep -h "#define.*dev_priv" --
drivers/gpu/drm/i915/i915_reg.h |\
grep -v '#define[ \t]\+[a-zA-Z0-9_]\+(dev_priv' |\
sed 's/#define[ \t]\+\([a-zA-Z0-9_]\+\).*/\1/')
for reg in $REGS; do
echo $reg
FILES=$(git grep -wl $reg -- drivers/gpu/drm/i915)
cocci=$(mktemp)
cat >$cocci <
EOF
# already function-like macros
sed -i "s/\(#define *${reg}(\)/\1dev_priv, /" $FILES
# new function-like macros
sed -i "s/\(#define *${reg}\)\([ \t]\)/\1(dev_priv)\2/" $FILES
spatch --sp-file $cocci --in-place --linux-spacing $FILES
>/dev/null
rm -f $cocci
git commit -as -F - <
Re: [PATCH] drm/i915/gt: Automate CCS Mode setting during engine resets
Hi,
On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote:
> We missed setting the CCS mode during resume and engine resets.
> Create a workaround to be added in the engine's workaround list.
> This workaround sets the XEHP_CCS_MODE value at every reset.
>
> The issue can be reproduced by running:
>
> $ clpeak --kernel-latency
>
> Without resetting the CCS mode, we encounter a fence timeout:
>
> Fence expiration time out i915-:03:00.0:clpeak[2387]:2!
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895
> Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload")
> Reported-by: Gnattu OC
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
based on the discussion on the issue and as agreed with Gnattu:
Tested-by: Gnattu OC
Thank you again, gnattu,
Andi
✓ Fi.CI.BAT: success for drm/i915: i915_reg.h cleanups (rev2)
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14663 -> Patchwork_132381v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/index.html
Participating hosts (40 -> 37)
--
Additional (1): bat-rpls-4
Missing(4): fi-kbl-8809g bat-jsl-1 fi-apl-guc fi-snb-2520m
Known issues
Here are the changes found in Patchwork_132381v2 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [CRASH][1] ([i915#10911]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@client:
- bat-arls-1: [ABORT][3] ([i915#9618]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/bat-arls-1/igt@i915_selftest@l...@client.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/bat-arls-1/igt@i915_selftest@l...@client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9618]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9618
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-
* Linux: CI_DRM_14663 -> Patchwork_132381v2
CI-20190529: 20190529
CI_DRM_14663: 47c509a8d4944e6276f7b956061c2020323f0a90 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7825: 28b2a1b0be86e33a2fc04a022e04f07bd25b66d9 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132381v2: 47c509a8d4944e6276f7b956061c2020323f0a90 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/index.html
✗ Fi.CI.SPARSE: warning for drm/i915: i915_reg.h cleanups (rev2)
== Series Details == Series: drm/i915: i915_reg.h cleanups (rev2) URL : https://patchwork.freedesktop.org/series/132381/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +drivers/gpu/drm/i915/display/intel_de.h:105:15: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9:
[PATCH v2 4/4] drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
Clean up i915_reg.h.
v2: Drop a redundant comment (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 348 ++
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c| 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 340 -
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
8 files changed, 357 insertions(+), 341 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index d7b440c8caef..36a253a19c74 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -47,6 +47,7 @@
#include "intel_fb.h"
#include "intel_frontbuffer.h"
#include "intel_sprite.h"
+#include "intel_sprite_regs.h"
static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int
sprite)
{
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
new file mode 100644
index ..bb67705652b2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __INTEL_SPRITE_REGS__
+#define __INTEL_SPRITE_REGS__
+
+#include "intel_display_reg_defs.h"
+
+#define _DVSACNTR 0x72180
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLEREG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010REG_FIELD_PREP(DVS_FORMAT_MASK,
1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616REG_FIELD_PREP(DVS_FORMAT_MASK,
3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILEDREG_BIT(10)
+#define DVS_DEST_KEY REG_BIT(2)
+#define _DVSALINOFF0x72184
+#define _DVSASTRIDE0x72188
+#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
+#define _DVSASIZE 0x72190
+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DVS_HEIGHT(h)REG_FIELD_PREP(DVS_HEIGHT_MASK,
(h))
+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
+#define _DVSAKEYVAL0x72194
+#define _DVSAKEYMSK0x72198
+#define _DVSASURF 0x7219c
+#define DVS_ADDR_MASKREG_GENMASK(31, 12)
+#define _DVSAKEYMAXVAL 0x721a0
+#define _DVSATILEOFF 0x721a4
+#define DVS_OFFSET_Y_MASKREG_GENMASK(31, 16)
+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+#define DVS_OFFSET_X_MASKREG_GENMASK(15, 0)
+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
+#define _DVSASURFLIVE 0x721ac
+#define _DVSAGAMC_G4X 0x721e0 /* g4x */
+#define _DVSASCALE 0x72204
+#define DVS_SCALE_ENABLE REG_BIT(31)
+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
+#define DVS_FILTER_MEDIUMREG_FIELD_PREP(DVS_FILTER_MASK, 0)
+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
[PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
Clean up i915_reg.h. v2: Drop chicken regs and comments (Ville) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 123 -- drivers/gpu/drm/i915/intel_clock_gating.c | 1 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 6 files changed, 125 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 7c4d2b2bf20b..151dcd0c45b6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -54,6 +54,7 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fbc.h" +#include "intel_fbc_regs.h" #include "intel_frontbuffer.h" #define for_each_fbc_id(__dev_priv, __fbc_id) \ diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h new file mode 100644 index ..ae0699c3c2fe --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2024 Intel Corporation */ + +#ifndef __INTEL_FBC_REGS__ +#define __INTEL_FBC_REGS__ + +#include "intel_display_reg_defs.h" + +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ +#define FBC_LL_BASE_MMIO(0x3204) /* 4k page aligned */ +#define FBC_CONTROL_MMIO(0x3208) +#define FBC_CTL_EN REG_BIT(31) +#define FBC_CTL_PERIODIC REG_BIT(30) +#define FBC_CTL_INTERVAL_MASKREG_GENMASK(29, 16) +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) +#define FBC_CTL_STRIDE(x)REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) +#define FBC_COMMAND_MMIO(0x320c) +#define FBC_CMD_COMPRESS REG_BIT(0) +#define FBC_STATUS _MMIO(0x3210) +#define FBC_STAT_COMPRESSING REG_BIT(31) +#define FBC_STAT_COMPRESSED REG_BIT(30) +#define FBC_STAT_MODIFIEDREG_BIT(29) +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ +#define FBC_CTL_FENCE_DBLREG_BIT(4) +#define FBC_CTL_IDLE_MASKREG_GENMASK(3, 2) +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) +#define FBC_CTL_IDLE_FULLREG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) +#define FBC_CTL_IDLE_LINEREG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1) +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) +#define FBC_CTL_PLANE(i9xx_plane)REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) +#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ +#define FBC_MOD_NUM_MMIO(0x3220) /* i965gm only */ +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) +#define FBC_MOD_NUM_VALIDREG_BIT(0) +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) + +#define FBC_LL_SIZE(1536) + +#define DPFC_CB_BASE _MMIO(0x3200) +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) +#define DPFC_CONTROL _MMIO(0x3208) +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) +#define DPFC_CTL_EN REG_BIT(31) +#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ +#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_G4XREG_BIT(29) /* g4x-snb */ +#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ +#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_IVBREG_BIT(28)
[PATCH v2 2/4] drm/i915/color: move palette registers to intel_color_regs.h
For some reason the paletter registers were missed when adding intel_color_regs.h. Finish the job. Adjust some comments while at it. v2: Fix comments (Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_color_regs.h | 30 ++- drivers/gpu/drm/i915/i915_reg.h | 30 --- 2 files changed, 29 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index ec8732401cd8..02033c882d7f 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -8,7 +8,35 @@ #include "intel_display_reg_defs.h" -/* legacy palette */ +/* GMCH palette */ +#define _PALETTE_A 0xa000 +#define _PALETTE_B 0xa800 +#define _CHV_PALETTE_C 0xc000 +/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ +#define PALETTE_RED_MASK REG_GENMASK(23, 16) +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) +#define PALETTE_BLUE_MASKREG_GENMASK(7, 0) +/* pre-i965 10bit interpolated mode ldw */ +#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) +#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) +#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) +/* pre-i965 10bit interpolated mode udw */ +#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) +#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) +#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) +#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) +#define PALETTE_10BIT_GREEN_MANT_MASKREG_GENMASK(13, 10) +#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) +#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) +#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) +#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ + _PICK_EVEN_2RANGES(pipe, 2, \ + _PALETTE_A, _PALETTE_B, \ + _CHV_PALETTE_C, _CHV_PALETTE_C) + \ + (i) * 4) + +/* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 /* see PALETTE_* for the bits */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4913b9a371c0..c5ea2ed653b9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1440,36 +1440,6 @@ #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) -/* - * Palette regs - */ -#define _PALETTE_A 0xa000 -#define _PALETTE_B 0xa800 -#define _CHV_PALETTE_C 0xc000 -/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ -#define PALETTE_RED_MASK REG_GENMASK(23, 16) -#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) -#define PALETTE_BLUE_MASKREG_GENMASK(7, 0) -/* pre-i965 10bit interpolated mode ldw */ -#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) -#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) -#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) -/* pre-i965 10bit interpolated mode udw */ -#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) -#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) -#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) -#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) -#define PALETTE_10BIT_GREEN_MANT_MASKREG_GENMASK(13, 10) -#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) -#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) -#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) -#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ - _PICK_EVEN_2RANGES(pipe, 2, \ - _PALETTE_A, _PALETTE_B, \ - _CHV_PALETTE_C, _CHV_PALETTE_C) + \ - (i) * 4) - #define PEG_BAND_GAP_DATA _MMIO(0x14d68) #define BXT_RP_STATE_CAP_MMIO(0x138170) -- 2.39.2
[PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h
There are too few registers to warrant a dedicated file for LPE audio regs, but the audio reg file is better than i915_reg.h. v2: Rebase Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_audio_regs.h | 16 drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 16 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h index 616e7b1275c4..88ea2740365d 100644 --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h @@ -148,4 +148,20 @@ #define HBLANK_START_COUNT_96 4 #define HBLANK_START_COUNT_128 5 +/* LPE Audio */ +#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) +#define I915_HDMI_LPE_AUDIO_SIZE 0x1000 + +#define VLV_AUD_CHICKEN_BIT_REG_MMIO(VLV_DISPLAY_BASE + 0x62F38) +#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) + +#define _VLV_AUD_PORT_EN_B_DBG 0x62F20 +#define _VLV_AUD_PORT_EN_C_DBG 0x62F30 +#define _VLV_AUD_PORT_EN_D_DBG 0x62F34 +#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \ + _VLV_AUD_PORT_EN_B_DBG, \ + _VLV_AUD_PORT_EN_C_DBG, \ +_VLV_AUD_PORT_EN_D_DBG) +#define VLV_AMP_MUTE (1 << 1) + #endif /* __INTEL_AUDIO_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 5863763de530..93e6cac9a4ed 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -72,7 +72,7 @@ #include "i915_drv.h" #include "i915_irq.h" -#include "i915_reg.h" +#include "intel_audio_regs.h" #include "intel_de.h" #include "intel_lpe_audio.h" #include "intel_pci_config.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4eb37f38d888..4913b9a371c0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -966,22 +966,6 @@ #define I915_ASLE_INTERRUPT(1 << 0) #define I915_BSD_USER_INTERRUPT(1 << 25) -#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) -#define I915_HDMI_LPE_AUDIO_SIZE 0x1000 - -/* DisplayPort Audio w/ LPE */ -#define VLV_AUD_CHICKEN_BIT_REG_MMIO(VLV_DISPLAY_BASE + 0x62F38) -#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) - -#define _VLV_AUD_PORT_EN_B_DBG 0x62F20 -#define _VLV_AUD_PORT_EN_C_DBG 0x62F30 -#define _VLV_AUD_PORT_EN_D_DBG 0x62F34 -#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \ - _VLV_AUD_PORT_EN_B_DBG, \ - _VLV_AUD_PORT_EN_C_DBG, \ -_VLV_AUD_PORT_EN_D_DBG) -#define VLV_AMP_MUTE (1 << 1) - #define GEN6_BSD_RNCID _MMIO(0x12198) #define GEN7_FF_THREAD_MODE_MMIO(0x20a0) -- 2.39.2
[PATCH v2 0/4] drm/i915: i915_reg.h cleanups
v2 of https://lore.kernel.org/r/cover.1712933479.git.jani.nik...@intel.com Jani Nikula (4): drm/i915/audio: move LPE audio regs to intel_audio_regs.h drm/i915/color: move palette registers to intel_color_regs.h drm/i915/display: split out intel_fbc_regs.h from i915_reg.h drm/i915/display: split out intel_sprite_regs.h from i915_reg.h .../gpu/drm/i915/display/intel_audio_regs.h | 16 + .../gpu/drm/i915/display/intel_color_regs.h | 30 +- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 + .../gpu/drm/i915/display/intel_lpe_audio.c| 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 1 + .../gpu/drm/i915/display/intel_sprite_regs.h | 348 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c| 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +- drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 509 -- drivers/gpu/drm/i915/intel_clock_gating.c | 1 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 + 15 files changed, 528 insertions(+), 512 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h -- 2.39.2
Re: ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV DPIO register cleanup
On Mon, 22 Apr 2024, Patchwork wrote: > == Series Details == > > Series: drm/i915: VLV/CHV DPIO register cleanup > URL : https://patchwork.freedesktop.org/series/132691/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1 > > > Summary > --- > > **SUCCESS** > > No regressions found. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html BAT passed, where are the shard results? BR, Jani. > > Participating hosts (31 -> 30) > -- > > Missing(1): fi-apl-guc > > Known issues > > > Here are the changes found in Patchwork_132691v1 that come from known > issues: > > ### IGT changes ### > > Warnings > > * igt@i915_module_load@reload: > - fi-kbl-7567u: [DMESG-WARN][1] ([i915#10636] / [i915#180] / > [i915#1982] / [i915#8585]) -> [DMESG-WARN][2] ([i915#10636] / [i915#180] / > [i915#8585]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/fi-kbl-7567u/igt@i915_module_l...@reload.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/fi-kbl-7567u/igt@i915_module_l...@reload.html > > > [i915#10636]: https://gitlab.freedesktop.org/drm/intel/issues/10636 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585 > > > Build changes > - > > * Linux: CI_DRM_14624 -> Patchwork_132691v1 > > CI-20190529: 20190529 > CI_DRM_14624: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_7814: 7814 > Patchwork_132691v1: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ > git://anongit.freedesktop.org/gfx-ci/linux > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html -- Jani Nikula, Intel
✓ Fi.CI.BAT: success for drm/i915/gt: Automate CCS Mode setting during engine resets (rev3)
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev3)
URL : https://patchwork.freedesktop.org/series/132932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14662 -> Patchwork_132932v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/index.html
Participating hosts (42 -> 35)
--
Additional (1): bat-dg2-11
Missing(8): fi-bsw-n3050 fi-apl-guc fi-snb-2520m fi-kbl-8809g
fi-cfl-8109u fi-elk-e7500 bat-arls-2 bat-mtlp-6
Known issues
Here are the changes found in Patchwork_132932v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#4083])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4077]) +2 other tests skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4079]) +1 other test skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#6621])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4212]) +7 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#5190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4215] / [i915#5190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4103] / [i915#4213]) +1
other test skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#5274])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5354])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#1072] / [i915#9732]) +3
other tests skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_...@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#3555])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#3708])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1
other test skip
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-read:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3291] / [i915#3708]) +2
other tests skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132932v3/bat-dg2-11/igt@prime_v...@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or
✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Automate CCS Mode setting during engine resets (rev3)
== Series Details == Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev3) URL : https://patchwork.freedesktop.org/series/132932/ State : warning == Summary == Error: dim checkpatch failed 42db64e85eff drm/i915/gt: Automate CCS Mode setting during engine resets -:20: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #20: Reported-by: Gnattu OC Signed-off-by: Andi Shyti total: 0 errors, 1 warnings, 0 checks, 45 lines checked
✗ Fi.CI.BAT: failure for drm/i915/mtl: Update workaround 14018778641 (rev4)
== Series Details == Series: drm/i915/mtl: Update workaround 14018778641 (rev4) URL : https://patchwork.freedesktop.org/series/119517/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14662 -> Patchwork_119517v4 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_119517v4 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_119517v4, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/index.html Participating hosts (42 -> 34) -- Additional (1): bat-dg2-11 Missing(9): fi-kbl-7567u bat-kbl-2 fi-snb-2520m fi-glk-j4005 fi-kbl-8809g fi-cfl-8109u fi-elk-e7500 bat-jsl-1 bat-mtlp-6 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_119517v4: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_timelines: - bat-arls-2: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14662/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-arls-2/igt@i915_selftest@live@gt_timelines.html Known issues Here are the changes found in Patchwork_119517v4 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4083]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][7] -> [ABORT][8] ([i915#10594]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14662/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4212]) +7 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#5190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][14] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5274]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#5354]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119517v4/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#1072] / [i915#9732]) +3 other tests skip [17]:
Re: ✗ Fi.CI.BAT: failure for drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev2)
Hi @I915-ci-infra, On Thursday, 25 April 2024 19:29:17 CEST Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev2) > URL : https://patchwork.freedesktop.org/series/132786/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14657 -> Patchwork_132786v2 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_132786v2 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_132786v2, please notify your bug team > (i915-ci-in...@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/index.html > > Participating hosts (41 -> 41) > -- > > Additional (1): fi-kbl-8809g > Missing(1): fi-snb-2520m > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_132786v2: > > ### IGT changes ### > > Possible regressions > > * igt@gem_flink_basic@bad-flink: > - bat-arls-2: NOTRUN -> [FAIL][1] +19 other tests fail >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@gem_flink_ba...@bad-flink.html > > * igt@kms_addfb_basic@addfb25-modifier-no-flag: > - bat-arls-2: NOTRUN -> [INCOMPLETE][2] +42 other tests incomplete >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html Plenty of fails and incompletes on a single bat-arls-2 machine. There must be something wrong with that piece of hardware. Please update filters and re-report. Thanks, Janusz > > > Known issues > > > Here are the changes found in Patchwork_132786v2 that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_huc_copy@huc-copy: > - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html > > * igt@gem_lmem_swapping@basic: > - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests > skip >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html > > * igt@gem_lmem_swapping@basic@lmem0: > - bat-dg2-9: [PASS][5] -> [FAIL][6] ([i915#10378]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14657/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html > - bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#10378]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14657/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html > > * igt@kms_force_connector_basic@force-load-detect: > - fi-kbl-8809g: NOTRUN -> [SKIP][9] +30 other tests skip >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html > > * igt@kms_pipe_crc_basic@read-crc: > - bat-arls-2: NOTRUN -> [INCOMPLETE][10] ([i915#10377]) +44 other > tests incomplete >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@kms_pipe_crc_ba...@read-crc.html > > * igt@kms_pm_rpm@basic-pci-d3-state: > - bat-arls-2: NOTRUN -> [INCOMPLETE][11] ([i915#10377] / > [i915#10553]) +1 other test incomplete >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@kms_pm_...@basic-pci-d3-state.html > > * igt@prime_vgem@basic-fence-mmap: > - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10196] / [i915#3708] / > [i915#4077]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@prime_v...@basic-fence-mmap.html > > > Possible fixes > > * igt@gem_exec_fence@basic-busy@ccs0: > - bat-arls-2: [ABORT][13] -> [PASS][14] >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14657/bat-arls-2/igt@gem_exec_fence@basic-b...@ccs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v2/bat-arls-2/igt@gem_exec_fence@basic-b...@ccs0.html > > * igt@gem_lmem_swapping@basic@lmem0: > - bat-dg2-11: [FAIL][15] ([i915#10378]) -> [PASS][16] >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14657/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html >[16]: >
Re: [PATCH v3 2/6] drm/i915/alpm: Move alpm related code to a new file
Hi Animesh, kernel test robot noticed the following build errors: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm/drm-next drm-exynos/exynos-drm-next next-20240424] [cannot apply to drm-intel/for-linux-next-fixes linus/master v6.9-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-i915-alpm-Move-alpm-parameters-from-intel_psr/20240425-025652 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20240424183820.3591593-3-animesh.manna%40intel.com patch subject: [PATCH v3 2/6] drm/i915/alpm: Move alpm related code to a new file config: loongarch-allmodconfig (https://download.01.org/0day-ci/archive/20240426/202404261542.p0fckhhm-...@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240426/202404261542.p0fckhhm-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202404261542.p0fckhhm-...@intel.com/ All errors (new ones prefixed by >>, old ones prefixed by <<): WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/mtd/maps/map_funcs.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/spmi/hisi-spmi-controller.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/spmi/spmi-pmic-arb.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_cif.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_aec.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_netx.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_pruss.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/uio/uio_mf624.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/pcmcia_rsrc.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/yenta_socket.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pcmcia/i82092.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/hwmon/corsair-cpro.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/hwmon/mr75203.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/vhost/vringh.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/greybus/greybus.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/greybus/gb-es2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/rpmsg/rpmsg_char.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/adc/ingenic-adc.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/adc/xilinx-ams.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/iio/buffer/kfifo_buf.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-core.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-hub.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-aspeed.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-gpio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-master-ast-cf.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/fsi/fsi-scom.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/siox/siox-bus-gpio.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/counter/ftm-quaddec.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/core/snd-pcm-dmaengine.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/core/sound_kunit.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/drivers/snd-pcmtest.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/pci/hda/snd-hda-cirrus-scodec-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/soc-topology-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-ab8500-codec.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-sigmadsp.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/codecs/snd-soc-wm-adsp.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/fsl/imx-pcm-dma.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-da7219.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-dmic.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-i2s-test.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-max98927.o WARNING: modpost: missing MODULE_DESCRIPTION() in sound/soc/intel/avs/boards/snd-soc-avs-max98357a.o WARNING: modp
RE: [PATCH] drm/i915/display: Fixed the main link lost in MST
Posted V5 that change the order of the existing flow.
Found Tejas' email address is incorrect. Will correct in V6.
Gareth
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, April 25, 2024 7:31 PM
> To: Yu, Gareth ; intel-gfx@lists.freedesktop.org
> Cc: Yu, Gareth
> Subject: Re: [PATCH] drm/i915/display: Fixed the main link lost in MST
>
> On Thu, 25 Apr 2024, gareth...@intel.com wrote:
> > From: Gareth Yu
> >
> > Re-train the main link when the sink asserts a HPD for the main lnk
> > lost.
>
> NAK.
>
> Please read the review comments.
>
> BR,
> Jani.
>
> >
> > v4: detect the main link state by intel_dp_needs_link_retrain
> > instead of intel_dp_mst_link_status because the main link
> > state can't detect correctly sometimes by
> > intel_dp_mst_link_status
> >
> > Cc : Tejas Upadhyay
> > Cc : Matt Roper Cc : Ville Syrjälä
> >
> > Signed-off-by: Gareth Yu
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e05e25cd4a94..e1b60303b256 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5849,8 +5849,14 @@ intel_dp_detect(struct drm_connector
> *connector,
> > /* Can't disconnect eDP */
> > if (intel_dp_is_edp(intel_dp))
> > status = edp_detect(intel_dp);
> > - else if (intel_digital_port_connected(encoder))
> > + else if (intel_digital_port_connected(encoder)) {
> > status = intel_dp_detect_dpcd(intel_dp);
> > + if (status == connector_status_connected && intel_dp->is_mst
> &&
> > + intel_dp_needs_link_retrain(intel_dp)) {
> > + if (intel_dp_retrain_link(encoder, ctx))
> > + status = connector_status_disconnected;
> > + }
> > + }
> > else
> > status = connector_status_disconnected;
>
> --
> Jani Nikula, Intel
[PATCH] drm/i915/mtl: Update workaround 14018778641
The WA should be extended to cover VDBOX engine. We found that 28-channels 1080p VP9 encoding may hit this issue. Signed-off-by: Chen, Angus --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d1ab560fcdfc..bf14749f5792 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1586,6 +1586,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); + /* Wa_22016670082 */ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); -- 2.34.1
[PULL] drm-intel-gt-next
Hi Dave & Sima, Here's the drm-intel-gt-next PR for v6.10 in one shot. We are adding a new uAPI for Mesa to request higher GT frequency for compute contexts on GuC platform. Then there is a W/A for DG2 to move to fixed CCS load balancing and make all DG2 SKUs appear with single CCS with all the EUs attached by default. Read more below under "UAPI Changes". There is one reported regression against it which we're working on resolving, so expect to see -next-fixes shortly once that happens. Beyond that we have a bunch of workaround updates/fixes, fix for UAF that has been hunted down for a while, GT reset fix for platforms that load GuC but don't submit via it, fix for execlists priority submission, proper capture of EIR register on hang. THe rest is usual code cleanups/refactoring and selftest fixes. Regards, Joonas *** drm-intel-gt-next-2024-04-26: UAPI Changes: - drm/i915/guc: Use context hints for GT frequency Allow user to provide a low latency context hint. When set, KMD sends a hint to GuC which results in special handling for this context. SLPC will ramp the GT frequency aggressively every time it switches to this context. The down freq threshold will also be lower so GuC will ramp down the GT freq for this context more slowly. We also disable waitboost for this context as that will interfere with the strategy. We need to enable the use of SLPC Compute strategy during init, but it will apply only to contexts that set this bit during context creation. Userland can check whether this feature is supported using a new param- I915_PARAM_HAS_CONTEXT_FREQ_HINT. This flag is true for all guc submission enabled platforms as they use SLPC for frequency management. The Mesa usage model for this flag is here - https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint - drm/i915/gt: Enable only one CCS for compute workload Enable only one CCS engine by default with all the compute sices allocated to it. While generating the list of UABI engines to be exposed to the user, exclude any additional CCS engines beyond the first instance *** NOTE: This W/A will make all DG2 SKUs appear like single CCS SKUs by default to mitigate a hardware bug. All the EUs will still remain usable, and all the userspace drivers have been confirmed to be able to dynamically detect the change in number of CCS engines and adjust. For the smaller percent of applications that get perf benefit from letting the userspace driver dispatch across all 4 CCS engines we will be introducing a sysfs control as a later patch to choose 4 CCS each with 25% EUs (or 50% if 2 CCS). NOTE: A regression has been reported at https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 However Andi has been triaging the issue and we're closing in a fix to the gap in the W/A implementation: https://lists.freedesktop.org/archives/intel-gfx/2024-April/348747.html Driver Changes: - Add new and fix to existing workarounds: Wa_14018575942 (MTL), Wa_16019325821 (Gen12.70), Wa_14019159160 (MTL), Wa_16015675438, Wa_14020495402 (Gen12.70) (Tejas, John, Lucas) - Fix UAF on destroy against retire race and remove two earlier partial fixes (Janusz) - Limit the reserved VM space to only the platforms that need it (Andi) - Reset queue_priority_hint on parking for execlist platforms (Chris) - Fix gt reset with GuC submission is disabled (Nirmoy) - Correct capture of EIR register on hang (John) - Remove usage of the deprecated ida_simple_xx() API - Refactor confusing __intel_gt_reset() (Nirmoy) - Fix the fix for GuC reset lock confusion (John) - Simplify/extend platform check for Wa_14018913170 (John) - Replace dev_priv with i915 (Andi) - Add and use gt_to_guc() wrapper (Andi) - Remove bogus null check (Rodrigo, Dan) . Selftest improvements (Janusz, Nirmoy, Daniele) The following changes since commit db7bbd13f08774cde0332c705f042e327fe21e73: drm/i915: Check before removing mm notifier (2024-02-28 13:11:32 +) are available in the Git repository at: https://anongit.freedesktop.org/git/drm/drm-intel tags/drm-intel-gt-next-2024-04-26 for you to fetch changes up to 4d3421e04c5dc38baf15224c051256204f223c15: drm/i915: Fix gt reset with GuC submission is disabled (2024-04-24 18:48:32 +0200) UAPI Changes: - drm/i915/guc: Use context hints for GT frequency Allow user to provide a low latency context hint. When set, KMD sends a hint to GuC which results in special handling for this context. SLPC will ramp the GT frequency aggressively every time it switches to this context. The down freq threshold will also be lower so GuC will ramp down the GT freq for this context more slowly. We also disable waitboost for this context as that will interfere with the strategy. We need to enable the use of SLPC
