for ICL.
Cc: martin.pe...@intel.com
Cc: daniel.vet...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index 9d6aff2
Enabled has_pc8 global for ICL and Gen9.
Added PC8+ residency test for display enabled case as well.
Signed-off-by: Anshuman Gupta
---
tests/pm_rpm.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index be296f5..c84f199 100644
Do not assert failure if PC8 state achieved with display enabled.
Signed-off-by: Anshuman Gupta
---
tests/pm_rpm.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index c84f199..878b63b 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
This patch series enable PC8+ residency test, earlier these tests
were only enabled for Haswell and Broadwell.
Anshuman Gupta (2):
tests/pm_rpm: Enable PC8+ residency test for ICL and GEN9.
tests/pm_rpm: Enable modeset-pc8-residency-stress for ICL and GEN9.
tests/pm_rpm.c | 21
silicons at local BA setup
are not entering to PC2 itself.
Planning a separate series for a subtest to validate pc8 with multiple pipes
and all planes enabled to create maximum memory bandwidth scenario.
Anshuman Gupta (2):
tests/i915/i915_pm_rpm: Enable PC8+ residency test for ICL
tests/i915
Enabled has_pc8 global for ICL and Gen9.
Added PC8+ residency test for display enabled case as well.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 75 +++-
1 file changed, 68 insertions(+), 7 deletions(-)
diff --git a/tests/i915
Introduced pc8_needs_screen_off flag in order to differentiate
between HASWELL/BROADWEEL and AT_LEAST_GEN9. GEN9 onwards
PC8+ residency does't require display to be turned on.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
to
other PM tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 6c1fa9c..02a59bf 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915
-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 865c1f6..56ceeea 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -248,6 +248,10 @@ int main(int argc, char *argv
to i915_pm_dc, aligning to
other PM tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 02a59bf..865c1f6 100644
pm_rpm changed to i915_pm_rpm.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
lib/igt_pm.c | 47 +++
lib/igt_pm.h | 2 ++
tests/i915/i915_pm_rpm.c | 17 +
3 files changed, 50 insertions(+), 16 deletions
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments and
other relevant changes.
1. Changing the name of test from pm_dc to
pport: yes".
v7: Rebased due to test name pm_dc changed to i915_pm_dc, aligning to
other PM tests, changed the DC5/6 counter check timeout to 3 second.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources | 3 +
tests/i91
to
other PM tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 3bb8083..cf79790 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915
pport: yes".
v7: Rebased due to test name pm_dc changed to i915_pm_dc, aligning to
other PM tests, changed the DC5/6 counter check timeout to 3 second.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources | 3 +
tests/i91
: Listing actual change in patch set changelog to make review easier.
v6: igt's lib added support for disabling runtime suspend, change in commit log.
rebased due to test name pm_rpm changed to i915_pm_rpm.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
lib/igt_pm.c | 47
to i915_pm_dc, aligning to
other PM tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index cf79790..813e38f 100644
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments and
other relevant changes.
1. Changing the name of test from pm_dc to
-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 813e38f..975e976 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -242,6 +242,10 @@ int main(int argc, char *argv
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments and
other relevant changes.
1. Changing the name of test from "pm_dc"
pport: yes".
v7: Rebased since test name changed from "pm_dc" to "i915_pm_dc",
this will align with other PM tests.
also changed the DC5/6 counter check timeout to 3 second.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources
pm_rpm changed to i915_pm_rpm.
v7: Addressed review comment by saving POWER_DIR values in
igt_disable_runtime_pm().
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
lib/igt_pm.c | 82
lib/igt_pm.h | 2 ++
tests
to disable i915 runtime PM for
the platform supports DC9.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 1b14262..8587f92 100644
--- a/tests
to i915_pm_dc, aligning to
other PM tests.
v8: Introduced setup_dc_dpms() in order to disable runtime pm, restoring
POWER_DIR values to its original and enabling runtime pm for other
followed sub-tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c
to
other PM tests.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_dc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 004a5c1..66e3e8f 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915
On Fri, Feb 08, 2019 at 04:53:18PM +0200, Imre Deak wrote:
> On Fri, Feb 01, 2019 at 09:43:02PM +0530, Anshuman Gupta wrote:
> > From: Jyoti Yadav
> >
> > Added new subtest for DC6 entry during DPMS on/off cycle.
> > During DPMS on/off cycle DC6 counter is increm
On Fri, Feb 08, 2019 at 04:49:31PM +0200, Imre Deak wrote:
> On Fri, Feb 01, 2019 at 09:42:59PM +0530, Anshuman Gupta wrote:
> > From: Jyoti Yadav
> >
> > Currently this test validates DC5 upon PSR entry for supported platforms.
> > Added new file for compilatio
From: Jyoti Yadav
This patch add subtest to check DC6 entry on PSR for the supported
platforms.
v2: Rename the subtest with more meaningful name.
v3: Rebased.
v4: Rebased and addressed review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 13
From: Jyoti Yadav
Added new subtest for DC5 entry during DPMS on/off cycle.
During DPMS on/off cycle DC5 counter is incremented.
v2: Rename the subtest with meaningful name.
v3: Rebased.
v4: Addressed review comments.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests
.
v3: one second timeout is introduced to read DC counters.
Skip the subtest if counters are not available for that platform.
v4: Rebased, addressed the review comment and spell correction.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources | 1 +
tests
From: Jyoti Yadav
Added new subtest for DC6 entry during DPMS on/off cycle.
During DPMS on/off cycle DC6 counter is incremented.
v2: Renamed the subtest name.
v3: Rebased.
v4: Rebased and address review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 9
-by: Anshuman Gupta
---
lib/igt_pm.c | 28
lib/igt_pm.h | 1 +
tests/pm_rpm.c | 17 +
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 4902723..8b87c58 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -38,6
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments.
Jyoti Yadav (5):
lib/igt_pm: Moves Dmc_loaded() function into
, only for ICL.
This hacky patch is only for ICL processor and for Core-for-CI branch.
v2: Fixed compilation errors raised by lkp.
commit message improvement.
Cc: martin.pe...@intel.com
Cc: daniel.vet...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 18
Enabling pm_lpsp igt tests for Gen11 as well as for all platforms
at least gen9, earlier these test were enabled only haswell and broadwell
platforms.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_lpsp.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index ee842a2f..9d6aff2 100644
--- a/drivers/acpi/processor_driver.c
+++ b/dr
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_params.c | 3 ++-
drivers/gpu
riate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
driv
, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b29761b4f55e
PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196
Anshuman Gupta (10):
drm/i915/tgl:Added DC3CO required register and bits.
i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
i915:Added DC3CO power well
This patch exposes DC3CO counter in i915_dmc_info debugfs.
Which will be useful for DC3CO validation.
DMC firmware is using DMC_DEBUG3 register as DC3CO counter.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
with already scheduled delayed work. [Imre]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c| 33 ++
drivers/gpu/drm/i915
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_psr.c | 55
drivers/gpu/drm/i915/intel_psr.h | 2 ++
2 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index
merged to drm-tip.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
d
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
DC3co must be disabled before PSR2 is disabled.
B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196
Anshuman Gupta (10):
drm/i915/tgl:Added DC3CO required register and bits.
i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
i915:Added DC3CO power well.
drm/i915/tgl:Added mutual
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
d
: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +
.../drm/i915/display/intel_display_power.c| 37 +++
.../drm/i915/display/intel_display_power.h| 4
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13
riate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 44
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915
DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
C
The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing
the IO/PHY functionality, which doesn't need the PG3
power power well. Accordingly fixing up the list of
PG3 power domains.
v2: Removed "DDI E/F IO"power domain as well [Imre]
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Ansh
The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing
the IO/PHY functionality, which doesn't need the PG3
power power well. Accordingly fixing up the list of
PG3 power domains.
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
support)
> return false;
>
> + if (!psr2_supported(dev_priv, crtc_state->cpu_transcoder)) {
> + DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
> + transcoder_name(crtc_state->cpu_transcoder
On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
> PSR registers are a mess, some have the full address while others just
> have the additional offset from psr_mmio_base.
>
> For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
> 0x800 and using it makes more difficult
On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> TGL PSR2 HW supports a bigger resolution, so lets add it
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
>
as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +
.../drm/i915
drigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 106 ++
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gp
eDP panel.
(when system boots with only eDP panel there will not be real
modeset). I observed sometimes hang while early bootup, which
seems side effect of forcing a modeset at bootup. I am working
to fix it.
Tagging this as RFC series, i need feedback, suggestion and ACK
to this new design.
Anshuma
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 43
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 45
dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915
() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 43
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 45
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 106 ++
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i9
dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
l.
Tested this series on real H/W, DC3CO counter is validated
without any other issue observed.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off" power
nstance of PSR.
Looks good to me.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
> 1 file changed, 5 insertion
cro and a new PSR irq handler with the
> transcoder parameter.
>
There are few minor comments below, apart from below comments
patch is looks ok to me.
Reviewed-by: Anshuman Gupta
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by
On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
Hi Imre ,
Thanks for review, could you please provide your response on below
comments.
> On Sat, Sep 07, 2019 at 10:44:42PM +0530, Anshuman Gupta wrote:
> > DC3CO is useful power state, when DMC detects PSR2 idle frame
> > while
On 2019-09-11 at 11:50:26 +0300, Imre Deak wrote:
> On Tue, Sep 10, 2019 at 03:26:20PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
> > Hi Imre ,
> > Thanks for review, could you please provide your response on below
> > comments.
On 2019-09-11 at 11:21:42 +0300, Imre Deak wrote:
> On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> > Hi Imre,
> > Than
On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
Hi Imre,
Thanks for reviewing the pacthes i will rework the patches.
There are few comments from my side which will help to rework.
> > Add max_dc_state and tgl_set_target
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 111 ++
.../drm/i915/display/intel_display_power.h| 3 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 95 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i9
pipe config state in encoder disable path.
v1: moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 51
as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
are most welcome for this new design
series.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off" power well
drm/i915/tgl: Do modeset to enable and confi
te instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gu
. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 97 +++
.../drm/i915/display/intel_display_power.h| 4 +
.../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
drivers/gpu/drm/i915
pipe config state in encoder disable path.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 51
v8 revision is a rework of series, which has fixed the review comments
provided by Imre and Animesh.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off&q
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915
: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b
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