intel_dgfx_alloc_opregion(), and added necessary
credit to Manasi.
PCI Firmware Spec: ID:12886
https://pcisig.com/specifications
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Badal Nilawar
Signed-off-by: Manasi Navare
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 339
2:
- Add kzalloc NULL check for opreg_rvda pointer.
v3:
- Added kmemdup() insead of kzalloc() + memcpy() in
intel_dgfx_alloc_rvda(), and added necessary
credit to Manasi.
Cc: Jani Nikula
Cc: Uma Shankar
Cc: Rodrigo Vivi
Cc: Badal Nilawar
Signed-off-by: Manasi Navare
Signed-off-by: Anshum
This series setup DGFX OpRegion.
Anshuman Gupta (4):
drm/i915/opregion: Abstract opregion function
drm/i915/opregion: Register opreg func only for disp parts
drm/i915/dgfx: OPROM OpRegion Setup
drm/i915/dgfx: Get VBT from rvda
drivers/gpu/drm/i915/display/intel_opregion.c | 533
: Rodrigo Vivi
Cc: Badal Nilawar
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 215 ++
drivers/gpu/drm/i915/display/intel_opregion.h | 8 +-
drivers/gpu/drm/i915/i915_driver.c| 2 +-
3 files changed, 172 insertions
It need to register opregion_func only for graphics sku
which has display. Use HAS_DISPLAY() to register
opregion_func.
Cc: Badal Nilawar
Cc: Jani Nikula
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 7 +--
1 file changed, 5 insertions
Signature.
After successful sanity check, driver will consume the OPROM
config data to get opreg and vbt accordingly.
PCI Firmware Spec: ID:12886
https://pcisig.com/specifications
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Badal Nilawar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm
Cc: Jani Nikula
Cc: Uma Shankar
Cc: Rodrigo Vivi
Cc: Badal Nilawar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/
i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (1):
drm/i915/dgfx: Release mmap on rpm suspend
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 48 ---
drivers/gpu/drm/i915/gt/intel_gt.c| 2
mem. [Matt Auld]
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 48 ---
drivers/gpu/drm/i915
Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
ject destruction patch. [Matt Auld]
- Use intel_wakeref_auto to delay runtime PM. [Matt Auld]
PCIe Specs 5.3.1.4.1
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem
Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem
ixed kernel test robot generated warning.
PCIe Specs 5.3.1.4.1
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 21 +
drivers/gpu/drm/i915/gem/i915_gem_
and DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..28f38f1cc5cc 100644
--- a/drivers/gpu/drm/i915
Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu
-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 21 +++
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
.../
:
With respect to i915_gem_object_pin_map(), every caller
has to grab a wakeref if gem object lies in lmem.
Till we fix all issues related to runtime PM, we need
to keep runtime PM disable on both DG1 and DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm
:
- Keep a smaller FIXME code comment for both DG1/DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gp
Checking DC3CO state against allowed DC mask, using WARN_ON()
in tgl_set_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 110 --
.../drm/i915/display/intel_display_power
Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..3ee9720af207
: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
, checking DC3CO state against
allowed DC mask, using WARN_ON() in
tgl_set_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 110 --
.../drm/i915/display/intel_display_p
the patches where they are getting used and used dc3co_exitline
check instead of TGL check. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files
AMES macro. [Imre]
v6: Inited the busy_frontbuffer_bits, used dc3co_exitline check instead
of TGL and dc3co allowed_dc_mask checks, used delayed_work_pending
with the psr lock and removed the psr2_deep_slp_disabled flag. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
_mask
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off" power well
drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
drm/i915/tgl: DC
coder pre_enable and post_disable hooks. [Imre]
Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++
drivers/gpu/drm/i915/display/intel_disp
On 2019-09-27 at 19:38:49 +0300, Imre Deak wrote:
> On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> > Adding DC3CO counter in i915_dmc_info debugfs will be
> > useful for DC3CO validation.
> > DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> &
This v10 revision has most of the chages related to dc3co series
code refactoring and fixes for few review comment provided by imre.
Anshuman Gupta (6):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable
Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..3ee9720af207
er_bits on psr.pipe check instead of
busy_frontbuffer_bits. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 45
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i9
, checking DC3CO state against
allowed DC mask, using WARN_ON() in
tgl_set_target_dc_state(). [Imre]
v10: Code refactoring and using sanitize_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display
te if crtc is not active
or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
Using IS_TGL check and dc3co exitline get_config
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c
: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
of IS_TIGERLAKE()
to print DMC_DEBUG3 counter value.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i
Resending this version v10 after adding Imre's RB and after fixing
few code refactoring related comments provided by Imre.
Anshuman Gupta (6):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO
: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a
er_bits on psr.pipe check instead of
busy_frontbuffer_bits. [Imre]
Calculating dc3co_exit_delay in intel_psr_enable_locked. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.
of IS_TIGERLAKE()
to print DMC_DEBUG3 counter value.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 9 insertions(+)
diff --gi
Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
te if crtc is not active
or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
Using GEN >= 12 check in dc3co exitline get_config. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
, checking DC3CO state against
allowed DC mask, using WARN_ON() in
tgl_set_target_dc_state(). [Imre]
v10: Code refactoring and using sanitize_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915
el-gfx-ci.01.org/tree/drm-tip/CI_DRM_6985/shard-iclb1/igt@gem_ctx_isolat...@rcs0-s3.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14612/shard-iclb2/igt@gem_ctx_isolat...@rcs0-s3.html
Hi Imre ,
FYI, above failure is a exisitng known issue
https://bugs.freedesktop.org/
-a-planes.html
It is also existing known issue as observed on earlier run
(https://bugs.freedesktop.org/show_bug.cgi?id=111764)
CI.IGT results are still RED even after updating the filter.
Thanks,
Anshuman Gupta.
>
>
> Known issues
>
>
> Here are the change
On 2019-10-02 at 23:11:36 +0530, Anshuman Gupta wrote:
> On 2019-10-02 at 16:21:59 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: DC3CO Support for TGL (rev15)
> > URL : https://patchwork.freedesktop.org/series/64923/
> > State : failure
>
Resending this series to test with DC3CO IGT series.
https://patchwork.freedesktop.org/series/66648/
Test-with: <1570088709-3605-2-git-send-email-jeeva...@intel.com>
Anshuman Gupta (6):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_ma
Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a
er_bits on psr.pipe check instead of
busy_frontbuffer_bits. [Imre]
Calculating dc3co_exit_delay in intel_psr_enable_locked. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.
of IS_TIGERLAKE()
to print DMC_DEBUG3 counter value.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 9 insertions(+)
diff --gi
te if crtc is not active
or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
Using GEN >= 12 check in dc3co exitline get_config. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
, checking DC3CO state against
allowed DC mask, using WARN_ON() in
tgl_set_target_dc_state(). [Imre]
v10: Code refactoring and using sanitize_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915
On 2019-10-04 at 18:48:08 +0300, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote:
> > Adding following definition to i915_reg.h
> > 1. DC_STATE_EN register DC3CO bit fields and masks.
> >DC3CO enable bit will be used by driver to ma
: Grouping EXITLINE reg bits with EXITLINE(trans) define,
no functional change. [Ville]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions
> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3538/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
Could you please create a bug for this CI failur
power cycle delay
in order to check for various DC state counters.
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
Test-with: <20200103081107.28144-1-ramalinga...@intel.com>
Anshuman Gupta (1):
drm/i915/hdcp: restore hdcp state same as previous
drivers/gpu/drm/i915/display/intel_ddi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
--
When port is disabled due to modeset or DPMS off actually
it disables the HDCP encryption keeping its state to
CP_ENABLED this doesn't enable HDCP again while port
gets enable again. HDCP state should set accordingly
when port is disabled.
CC: Ramalingam C
Signed-off-by: Anshuman
sure
when user explicitly set HDCP to UNDESRIED it should
make HDCP to desired while disabling DDI. (Ram)
CC: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++-
2
false. (Ram)
- Rephrasing commit log and small comment for is_hdcp_desired
flag. (Ram)
CC: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 13 -
2 files changed, 18
On 2020-01-13 at 23:11:28 -0500, Matt Atwood wrote:
> The bspec tells us we need to set this bit to avoid potential underruns.
>
> v2: use new register write convention (Anshuman) add bspec 7386 ref.
>
> Bspec: 7386
> Bspec: 33450
> Bspec: 33451
>
> Cc: Anshuman Gu
On 2020-01-16 at 10:54:20 -0800, José Roberto de Souza wrote:
> DC3C0 could have already exit so no need to always sleep, so lets
> read the register with the state.
>
> Cc: Imre Deak
> Cc: Anshuman Gupta
> Signed-off-by: José Roberto de Souza
> ---
> driv
Looks good to me.
On 2020-01-16 at 10:54:19 -0800, José Roberto de Souza wrote:
> This will calculaet the DC3CO exit delay only once per full modeset.
>
> Cc: Imre Deak
> Cc: Anshuman Gupta
> Signed-off-by: José Roberto de Souza
Reviewed-by: Anshuman Gupta
> ---
>
erated, so we switch to PSR1, so
> the previous code would compute dc3co_exitline=0 causing a full
> modeset that would shutdown pipe, enable and train link.
>
> BSpec: 49196
> Cc: Imre Deak
> Cc: Anshuman Gupta
> Signed-off-by: José Roberto de Souza
>
t the is_hdcp_undesired flag to false. (Ram)
- Rephrasing commit log and small comment for is_hdcp_desired
flag. (Ram)
CC: Ramalingam C
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_h
t the is_hdcp_undesired flag to false. (Ram)
- Rephrasing commit log and small comment for is_hdcp_desired
flag. (Ram)
CC: Ramalingam C
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_h
Test-with: <20200120085158.9151-2-anshuman.gu...@intel.com>
Anshuman Gupta (1):
drm/i915/hdcp: Update CP as per the kernel internal state
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 13 -
2 files chang
This is a proposed RFC solution for 3 display pipes combination
system support.
Anshuman Gupta (6):
drm/i915: Iterate over pipe and skip the disabled one
drm/i915: Remove (pipe == crtc->index) asummption
drm/i915: Fix wrongly populated plane possible_crtcs bit mask
drm/i915: Get right
Allow 3-display pipes SKU system with any combination
in INTEL_INFO pipe mask.
B.Spec:50075
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_device_info.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
As a disabled pipe in pipe_mask is not having a valid intel crtc,
driver wrongly populates the possible_crtcs mask while initializing
the plane for a CRTC. Fixing up the plane possible_crtc mask.
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c
accordingly due to
change in for_each_pipe() macro.
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.h | 5 +++--
drivers/gpu/drm/i915/i915_irq.c | 6 --
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
intel_plane_fb_max_stride should return the max stride of
primary plane for first available pipe in intel device info
pipe_mask.
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
we can't have (pipe == crtc->index) assumption in
driver in order to support 3 non-contiguous
display pipe system.
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff
Add a WARN_ON for a disabled pipe in pipe_mask at
intel_get_crtc_for_pipe() function.
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
On 2020-01-22 at 16:56:06 +0200, Jani Nikula wrote:
> On Wed, 22 Jan 2020, Ramalingam C wrote:
> > On 2020-01-21 at 14:15:57 +0200, Jani Nikula wrote:
> >> On Tue, 21 Jan 2020, Ramalingam C wrote:
> >> > On 2020-01-20 at 11:19:54 +0530, Anshuman Gupta wrote:
>
On 2020-01-23 at 15:48:05 +0200, Jani Nikula wrote:
> On Thu, 23 Jan 2020, Anshuman Gupta wrote:
> > It should not be assumed that a disabled display pipe will be
> > always last the pipe.
> > for_each_pipe() should iterate over I915_MAX_PIPES and check
> > for the
On 2020-01-24 at 14:15:30 +0200, Jani Nikula wrote:
> On Fri, 24 Jan 2020, Anshuman Gupta wrote:
> > On 2020-01-23 at 15:48:05 +0200, Jani Nikula wrote:
> >> On Thu, 23 Jan 2020, Anshuman Gupta wrote:
> >> > It should not be assumed that a disabled display pipe
fusing check. [Lucas]
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915
[PASS][1] -> [DMESG-WARN][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8113/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16920/fi-apl-guc/igt@i915_selftest@l...@hangchec
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 65
This series adds i915_lpsp_info connector debugfs.
Test-with: 20200312135642.13845-2-anshuman.gu...@intel.com
Anshuman Gupta (2):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
.../drm/i915/display/intel_display_debugfs.c | 65 +++
.../drm/i915
On 2020-03-04 at 20:45:20 +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2020 at 03:33:03PM +0200, Jani Nikula wrote:
> > On Wed, 04 Mar 2020, Anshuman Gupta wrote:
> > > Few edp panels like Sharp is triggering short and long
> > > hpd pulse after panel is getting p
immediately
after writing PP_OFF to PP_CTRL register.
v2:
- checking vdd along with panel power to ignore the hpd. [Jani,Ville]
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 27 +++--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a
side check to ignore the long hpd when eDP have power,
adding type of hpd to debug log. [Jani]
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
check integrity of
pipe_mask. [Ville]
v2:
- simplify condition in intel_pipe_mask_is_valid(). [Ville]
v3:
- removed non-contiguous pipe fusing check. [Lucas]
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Reviewed-by: Lucas De Marchi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_device_info.c
ged = true;
I would prefer to compute crtc_state->has_audio in compute_config at boot up
and then force a full modeset in intel_pipe_config_compare(), this way
atomically we can force the
full modeset on boot up.
Thanks,
Anshuman Gupta.
> }
>
> ret = drm_atomic_he
On 2020-03-18 at 18:48:27 +0200, Ville Syrjälä wrote:
> On Fri, Mar 13, 2020 at 12:39:17AM -0700, Lucas De Marchi wrote:
> > On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
> > >Allow 3-display pipes SKU system with any combination
> > >in INTEL_INFO p
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_connector.c | 3
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
v2:
- CI fixup.
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 102
This series adds i915_lpsp_info connector debugfs.
Test-with: 20200323063248.5261-2-anshuman.gu...@intel.com
Anshuman Gupta (3):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
drm/i915: Add connector dbgfs for all connectors
.../gpu/drm/i915/display
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_connector.c | 3
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
This series adds i915_lpsp_info connector debugfs.
Resend to test with below msgid of igt.
Test-with: 20200324130630.9388-2-anshuman.gu...@intel.com
Anshuman Gupta (3):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
drm/i915: Add connector dbgfs for all
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
v2:
- CI fixup.
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 104
On 2020-03-24 at 17:53:08 +0200, Jani Nikula wrote:
> On Tue, 24 Mar 2020, Anshuman Gupta wrote:
> > New i915_pm_lpsp igt solution approach relies on connector specific
> > debugfs attribute i915_lpsp_info, it exposes whether an output is
> > capable of driving lpsp and ex
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