Re: [Intel-gfx] [PATCH 10/14] drm/i915: Track which port is using which pipe's power sequencer

Reviewed-by: Antti Koskipaa antti.koski...@linux.intel.com -- - Antti On 08/18/2014 10:16 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com VLV/CHV have a per-pipe panel power sequencer which locks onto the port once used. We need to keep track wich

Re: [Intel-gfx] [PATCH v2] drm/i915: Always apply cursor width changes

On 06/02/2014 11:49 AM, Daniel Vetter wrote: On Fri, May 30, 2014 at 04:35:26PM +0300, Chris Wilson wrote: It is possible for userspace to create a big object large enough for a 256x256, and then switch over to using it as a 64x64 cursor. This requires the cursor update routines to check for a

Re: [Intel-gfx] [PATCH] drm/i915: Clean up display pipe register accesses

On 01/22/14 08:50, Barbalho, Rafael wrote: BCLRPAT is in the transcoder, not the pipe. PIPERSRC is in the transcoder not in the pipe. PIPECONF is in the pipe not the transcoder. Missing from that patch is also all the DSP* registers (DSPCNTR,DSPADDR, etc...) those should use the new

Re: [Intel-gfx] [PATCH v2] drm/i915: Clean up display pipe register accesses

On 01/24/14 14:52, Ville Syrjälä wrote: On Fri, Jan 24, 2014 at 02:13:14PM +0200, Antti Koskipaa wrote: +#define PIPE_A_OFFSET 0x7 +#define PIPE_B_OFFSET 0x71000 +#define PIPE_C_OFFSET 0x72000 I'd like a comment here to explain what PIPE_EDP_OFFSET actually means.

Re: [Intel-gfx] [PATCH] drm/i915: Clean up display pipe register accesses

Sorry, sent the wrong file. Ignore this one. -- - Antti ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Clean up display pipe register accesses

On 01/27/14 13:21, Chris Wilson wrote: On Mon, Jan 27, 2014 at 01:17:25PM +0200, Antti Koskipaa wrote: RFCv2: Reorganize array indexing so that full offsets can be used as is. It makes grepping for registers in i915_reg.h much easier. Also move offset arrays to intel_device_info. PATCHv1:

Re: [Intel-gfx] [PATCH v4] drm/i915: Reorganize display pipe register accesses

On 01/27/14 15:31, Ville Syrjälä wrote: On Mon, Jan 27, 2014 at 03:09:34PM +0200, Antti Koskipaa wrote: +.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ +.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ +.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }, \

Re: [Intel-gfx] [PATCH v2 0/4] drm/i915: dp: fix order of dp aux i2c device cleanup

, 110 insertions(+), 12 deletions(-) Signed-off-by: Imre Deak imre.d...@intel.com Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com -- - Antti ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman

Re: [Intel-gfx] [PATCH 0/2] drm/i915: vlv: preparation for enabling RPM

5 files changed, 30 insertions(+), 12 deletions(-) For the whole series, Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com -- - Antti ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo

Re: [Intel-gfx] [PATCH i-g-t 5/7] kms_cursor_crc: Add reference software rendering

On 04/02/2014 02:21 PM, Ville Syrjälä wrote: On Wed, Apr 02, 2014 at 02:06:28PM +0300, Antti Koskipaa wrote: snip @@ -184,9 +192,6 @@ static void test_crc_offscreen(test_data_t *test_data) do_test(test_data, left - (cursor_w+512), right + (cursor_w+512), top , bottom

Re: [Intel-gfx] [PATCH 58/71] drm/i915/chv: Register port D encoders and connectors

For 50-58, with Jani's coding style fix: Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com -- - Antti On 04/09/2014 01:28 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com

Re: [Intel-gfx] [RFC] drm/i915: Clean up display pipe register accesses

On 10/31/13 09:32, Jani Nikula wrote: On Wed, 30 Oct 2013, Antti Koskipaa antti.koski...@linux.intel.com wrote: Upcoming hardware will not have the various display pipe register ranges evenly spaced in memory. Change register address calculations into array lookups. Tested on SandyBridge.

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state

Both patches look ok. Reviewed-by: Antti Koskipaa antti.koski...@linux.intel.com On 08/21/12 02:15, Ben Widawsky wrote: ERR_INT can generate interrupts. However since most of the conditions seem quite fatal the patch opts to simply report it in error state instead of adding more complexity to

Re: [Intel-gfx] [PATCH v2] drm/i915: fix color order for BGR formats on IVB

Hi, On 08/22/12 12:17, Vijay Purushothaman wrote: This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 Author: Jesse Barnes jbar...@virtuousgeek.org Date: Mon Feb 27 12:40:10 2012 -0800 drm/i915: fix

Re: [Intel-gfx] [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV

On 11/01/12 16:50, Jesse Barnes wrote: No, it's in the gunit spec. I'm still working on getting that one opened up. In that case, for the whole lot: Reviewed-by: Antti Koskipää antti.koski...@intel.com -- - Antti ___ Intel-gfx mailing list

Re: [Intel-gfx] how to disable dpst on linux?

On 11/20/12 20:24, Роман Мельник wrote: Good day! I've sent already mail, but got no response, so trying again. Please advise how to disable dpst on linux? The module is i915. As I see, windows driver has such checkbox for this. Can I do the same on linux? The linux driver does not support

Re: [Intel-gfx] how to disable dpst on linux?

On 11/22/12 16:36, РоманМельник wrote: Antti Koskipää antti.koskipaa at linux.intel.com writes: On 11/20/12 20:24, Роман Мельник wrote: Good day! I've sent already mail, but got no response, so trying again. Please advise how to disable dpst on linux? The module is i915. As I see

[Intel-gfx] Bug team status

Another bug team week gone... Antti: Went through bugzilla, checking that work is still being done, general stuff. Mika: Fixed https://bugs.freedesktop.org/show_bug.cgi?id=58230 Tried to verify a fix (drm/i915: disable shrinker lock stealing for create_mmap_offset) for a problem i reported

Re: [Intel-gfx] [PATCH v2] drm/i915/bxt: map GTT as uncached

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/27/2015 01:07 PM, Imre Deak wrote: On Broxton per specification the GTT has to be mapped as uncached. This was caught by the PTE write readback warning, which showed a corrupted PTE value with using the current write-combine

Re: [Intel-gfx] [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Daisy Sun daisy@intel.com Enable FBC feature on Broxton Issue: VIZ-3784 Signed-off-by: Daisy Sun daisy@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com

Re: [Intel-gfx] [PATCH 02.1/49] drm/i915: use proper FBC base register on all new platforms

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/26/2015 05:35 PM, Imre Deak wrote: Starting from GEN5 the FBC base register is the same on all platforms. GEN=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make things work on BXT as well. Motivated by Rodrigo's

Re: [Intel-gfx] [PATCH 02/49] drm/i915/bxt: BXT FBC enablement

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Daisy Sun daisy@intel.com Enable FBC feature on Broxton Issue: VIZ-3784 Signed-off-by: Daisy Sun daisy@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com

Re: [Intel-gfx] [PATCH 09/49] drm/i915/bxt: Broxton raises the maximum number of planes to 4

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com Pipe A and b have 4 planes. Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file

Re: [Intel-gfx] [PATCH 06/49] drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Signed-off-by: Damien Lespiau damien.lesp...@intel.com

Re: [Intel-gfx] [PATCH 04/49] drm/i915/bxt: Broxton uses the same GMS values as Skylake

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com v2: Rebase on top of the early-quirks rework from Ville. Signed-off-by: Damien Lespiau damien.lesp...@intel.com (v1) Signed-off-by: Daniel

Re: [Intel-gfx] [PATCH 08/49] drm/i915/bxt: Broxton DDB is 512 blocks

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 +- 1 file changed, 5 insertions(+), 1

Re: [Intel-gfx] [PATCH 05/49] drm/i915/bxt: Enable PTE encoding

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Sumit Singh sumit.k.si...@intel.com The caching options for page table entries have remained the same as Cherryview. This patch fixes it so the right code path is taken on BXT. v2

Re: [Intel-gfx] [PATCH 07/49] drm/i915/bxt: Add the plane4 related interrupt definitions

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff

Re: [Intel-gfx] [PATCH 01/49] drm/i915/bxt: Add BXT PCI ids

Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 03/17/2015 11:39 AM, Imre Deak wrote: From: Damien Lespiau damien.lesp...@intel.com v2: Switch to info-ring_mask and add VEBOX support. v3: Fold in update from Damien. v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS v5

Re: [Intel-gfx] [PATCH] drm/i915: Per-DDI I_boost override

Just FYI, this patch depends on David Weinehall's Buffer translation improvements patch from earlier today. -- - Antti ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t] tests/pm_backlight: Add backlight test

On 05/26/2015 02:37 PM, Jani Nikula wrote: On Sat, 23 May 2015, Antti Koskipaa antti.koski...@linux.intel.com wrote: This is a basic sanity test of the backlight sysfs interface. Issue: VIZ-3377 Signed-off-by: Antti Koskipaa antti.koski...@linux.intel.com --- tests/.gitignore | 1 +

Re: [Intel-gfx] [PATCH v2] drm/i915: Per-DDI I_boost override

On 07/03/2015 06:09 PM, Paulo Zanoni wrote: 2015-07-03 8:28 GMT-03:00 Antti Koskipaa antti.koski...@linux.intel.com: An OEM may request increased I_boost beyond the recommended values by specifying an I_boost value to be applied to all swing entries for a port. These override values are

Re: [Intel-gfx] [PATCH v2] drm/i915/skl: Buffer translation improvements

Looks fine to me. Reviewed-by: Antti Koskipää antti.koski...@linux.intel.com On 06/25/2015 11:11 AM, David Weinehall wrote: This patch adds support for 0.85V VccIO on Skylake Y, separate buffer translation tables for Skylake U, and support for I_boost for the entries that needs