] On Behalf Of
jeff.mc...@intel.com
Sent: Thursday, July 31, 2014 3:00 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Slice/Subslice/EU info via GETPARAM
From: Jeff McGee jeff.mc...@intel.com
Define a struct to capture information on the device's Slice
:00 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/chv: Implement SSEU info for CHV
From: Jeff McGee jeff.mc...@intel.com
Cherryview can have different SSEU configurations within a given PCI ID, so
we collect the info from the fuse register.
I don't
On Mon, Aug 04, 2014 at 10:22:55AM +0200, Daniel Vetter wrote:
On Wed, Jul 30, 2014 at 08:59:47PM -0500, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Cherryview can have different SSEU configurations within a given PCI
ID, so we collect the info from the fuse
On Mon, Aug 04, 2014 at 10:20:37AM +0200, Daniel Vetter wrote:
On Wed, Jul 30, 2014 at 08:59:46PM -0500, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Define a struct to capture information on the device's Slice/Subslice/EU
(SSEU) configuration. Add this struct
On Tue, Aug 05, 2014 at 02:41:54PM +0100, Damien Lespiau wrote:
On Tue, Aug 05, 2014 at 08:47:54AM -0500, Jeff McGee wrote:
+
+ /* Copy SSEU info to the const device info with pointer magic */
+ *(struct intel_sseu_info *)dev_priv-info.sseu = sseu_info;
I've thought
On Tue, Aug 05, 2014 at 04:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 5, 2014 at 4:03 PM, Jeff McGee jeff.mc...@intel.com wrote:
Also, usual broken record request: I need open-source userspace using
this (mesa, ddx, libva).
-Daniel
This is kind of chicken-and-egg problem that I
-by: Tom O'Rourke Tom.O'rou...@intel.com
Reviewed-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
From: Jeff McGee jeff.mc...@intel.com
Use unbuffered file I/O to simplify and ensure proper sysfs access.
Bionic C library may not re-read a read-only file unless unbuffered,
which results in failure to monitor changes in gt_cur_freq_mhz.
Adapt do_writeval to assert that no write error occurs
On Fri, Jan 10, 2014 at 06:38:59PM +0100, Daniel Vetter wrote:
On Fri, Jan 10, 2014 at 11:20:42AM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Use unbuffered file I/O to simplify and ensure proper sysfs access.
Bionic C library may not re-read a read-only file
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 42 +++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index c968ecb..7c739b6 100644
--- a/tests
From: Jeff McGee jeff.mc...@intel.com
Jeff McGee (4):
pm_rps: Use unbuffered I/O on sysfs files
pm_rps: Assert that valid sysfs writes return success
pm_rps: Fix test to target original min and max
pm_rps: Use igt exit handler for restore
tests/pm_rps.c | 85
From: Jeff McGee jeff.mc...@intel.com
Bionic C library may not re-read a buffered, read-only file which
results in failure to monitor changes in gt_cur_freq_mhz.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff
From: Jeff McGee jeff.mc...@intel.com
do_writeval now always checks the return value, whether we expect
success or a specific error. Also add new macro writeval_inval to
simplify repeated use of do_writeval to test for EINVAL return code.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests
From: Jeff McGee jeff.mc...@intel.com
The goal of the test is to confirm that gt_cur_freq_mhz can be forced
to the boundaries of the frequency range by collapsing gt_min_freq_mhz
and gt_max_freq_mhz to the target value. But we miss testing the upper
end of the range by targetting the current
On Thu, Jan 16, 2014 at 10:27:03AM +0100, Daniel Vetter wrote:
On Thu, Jan 16, 2014 at 12:55 AM, Daniel Vetter dan...@ffwll.ch wrote:
Anything you put out to stderr will be tracked as a warn in piglit. Atm
we don't have any such use-case though I think, mostly since keeping
unbuffer stderr
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 7c739b6..ec07dd2 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -68,15
From: Jeff McGee jeff.mc...@intel.com
Jeff McGee (3):
pm_rps: Add read back checking on sysfs writes
pm_rps: Convert to subtest structure
pm_rps: Fix verbose option and streamline its use
tests/pm_rps.c | 142 +
1 file changed, 92
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 52 ++--
1 file changed, 42 insertions(+), 10 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 4d64f0a..192dca7 100644
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 119 ++---
1 file changed, 62 insertions(+), 57 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index ec07dd2..4d64f0a 100644
On Sun, Jan 19, 2014 at 02:49:19PM +0100, Daniel Vetter wrote:
If it's not in the multi-test target group testrunners won't pick up
on the fact that they need to enumerate subtests first.
OK. I haven't yet tried piglit, so missed this detail. Thanks
Jeff
On Mon, Jan 20, 2014 at 05:14:23PM +0100, Daniel Vetter wrote:
On Mon, Jan 20, 2014 at 09:06:40AM -0600, Jeff McGee wrote:
On Sun, Jan 19, 2014 at 02:49:19PM +0100, Daniel Vetter wrote:
If it's not in the multi-test target group testrunners won't pick up
on the fact that they need
From: Jeff McGee jeff.mc...@intel.com
Storing values avoids some unnecessary overhead but more importantly
allows all of our processing to be atomic.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 98 ++
1 file changed
From: Jeff McGee jeff.mc...@intel.com
Fill out the subtest with more min/max combinations and check that
current frequency tracks with minimum after each perturbation.
Jeff McGee (4):
pm_rps: Expand on min and max config testing
pm_rps: Remove repeat sysfs reads
pm_rps: Make frequency
From: Jeff McGee jeff.mc...@intel.com
The current frequency should reach the minimum frequency within a
reasonable time during idle. We hold forcewake to prevent interference
from sleep states.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 34
From: Jeff McGee jeff.mc...@intel.com
Add a function that methodically varies min and max to exercise
several valid and invalid combinations. Allow the caller to
define what is to be checked between each step.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 106
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 37f7020..7ae0438 100644
--- a/tests/pm_rps.c
There doesn't seem to be anything like the exit handlers for running when
a subtest exits. I need a failed subtest to be able to cleanup after
itself to avoid contaminating subsequent subtests. Have I missed something?
Perhaps this is not a problem when running subtests individually through
On Thu, Jan 23, 2014 at 11:40:18AM +0100, Daniel Vetter wrote:
On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
The current frequency should reach the minimum frequency within a
reasonable time during idle. We hold forcewake
On Thu, Jan 23, 2014 at 07:49:20PM +0100, Daniel Vetter wrote:
On Thu, Jan 23, 2014 at 11:15:42AM -0600, Jeff McGee wrote:
On Thu, Jan 23, 2014 at 11:40:18AM +0100, Daniel Vetter wrote:
On Tue, Jan 21, 2014 at 05:14:34PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc
From: Jeff McGee jeff.mc...@intel.com
The current frequency should reach the minimum frequency within a
reasonable time during idle.
v2: Not using forcewake for this particular subtest per Daniel's
suggestion.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 22
On Sat, Jan 25, 2014 at 08:46:45PM +0100, Daniel Vetter wrote:
On Thu, Jan 23, 2014 at 03:54:50PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
The current frequency should reach the minimum frequency within a
reasonable time during idle.
v2: Not using
On Mon, Jan 27, 2014 at 05:50:04PM +0100, Daniel Vetter wrote:
On Mon, Jan 27, 2014 at 10:24:53AM -0600, Jeff McGee wrote:
On Sat, Jan 25, 2014 at 08:46:45PM +0100, Daniel Vetter wrote:
On Thu, Jan 23, 2014 at 03:54:50PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc
From: Jeff McGee jeff.mc...@intel.com
Jeff McGee (4):
pm_rps: New subtest min-max-config-idle
lib/drmtest: Add igt_wait_helper
pm_rps: Add load helper for loading gpu
pm_rps: New subtest min-max-config-loaded
lib/drmtest.c | 17 +
lib/drmtest.h | 1 +
tests/pm_rps.c | 200
From: Jeff McGee jeff.mc...@intel.com
The load helper submits repeated dword store commands to keep the
gpu loaded while subtests running in the parent process check for
expected rps response.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 140
From: Jeff McGee jeff.mc...@intel.com
igt_wait_helper compliments igt_stop_helper and is used when helper
processes are expected to exit naturally.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
lib/drmtest.c | 17 +
lib/drmtest.h | 1 +
2 files changed, 18 insertions
From: Jeff McGee jeff.mc...@intel.com
Like subtest basic-api, but additionally requires that current
frequency is increasing to the configured maximum within reasonable
time since we are loaded.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 29
From: Jeff McGee jeff.mc...@intel.com
The load helper can be set to HIGH or LOW. HIGH is the original mode
of sending continuous dword store commands. LOW adds a pause between
each command to reduce throughput.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 35
From: Jeff McGee jeff.mc...@intel.com
Test that RPS functions as expected after a gpu reset.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/tests/pm_rps.c b/tests
From: Jeff McGee jeff.mc...@intel.com
This patch set is dependent on set Add two new subtests to pm_rps.
Jeff McGee (4):
pm_rps: Add stop rings injection utility
pm_rps: Load helper should stall for last write
pm_rps: Add variable load support to load helper
pm_rps: New subtest for gpu
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
tests/pm_rps.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 709e341..a6807d2 100644
--- a/tests/pm_rps.c
+++ b/tests
From: Jeff McGee jeff.mc...@intel.com
RPS manual mode disables/ignores load-based inputs and allows render
performance state to be controlled externally. The enabling of manual
mode and setting of desired frequency is done through debugfs.
i915_rps_manual:
'0' - RPS controlled normally using
From: Jeff McGee jeff.mc...@intel.com
i915_sr_disable:
'0' - CxSR enabled normally per device and settings.
'1' - CxSR explicitly disabled.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 43 +
drivers/gpu/drm/i915
From: Jeff McGee jeff.mc...@intel.com
i915_fbc_disable:
'0' - FBC enabled normally per device and settings.
'1' - FBC explicitly disabled.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 50 +
drivers/gpu/drm/i915
From: Jeff McGee jeff.mc...@intel.com
i915_ips_disable:
'0' - IPS enabled normally per device and settings.
'1' - IPS explicitly disabled.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 47
drivers/gpu/drm/i915
From: Jeff McGee jeff.mc...@intel.com
This series has recently been accepted into the Haswell Android kernel and
helps with debugging and profiling these power features. I would like it
to be considered for upstream incorporation. The patches here have been
rebased (minimal changes required
From: Jeff McGee jeff.mc...@intel.com
i915_rc6_disable:
'0' - RC6 states used normally per device and settings.
'1' - RC6 states explicitly disabled.
Supports Gen6+ except Valleyview and Broadwell.
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 49
On Tue, Feb 04, 2014 at 11:40:20AM +, Chris Wilson wrote:
On Tue, Feb 04, 2014 at 12:31:37PM +0100, Daniel Vetter wrote:
On Fri, Jan 31, 2014 at 03:42:48PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
RPS manual mode disables/ignores load-based inputs
From: Jeff McGee jeff.mc...@intel.com
A check of rps/rc6 state after i915_reset determined that the ring
MAX_IDLE registers were returned to their hardware defaults and that
the GEN6_PMIMR register was set to mask all interrupts. This change
restores those values to their pre-reset states by re
From: Jeff McGee jeff.mc...@intel.com
sysfs changes to rps min and max delay were only triggering an update
of the rps interrupt limits if the active delay required an update.
This change ensures that interrupt limits are always updated.
v2: correct compile issue missed on rebase
v3: add igt
Gentle ping on this patch set for igt.
Thanks,
Jeff
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Gentle ping on this patch set for igt.
Thanks,
Jeff
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On Thu, Feb 06, 2014 at 07:48:18AM +0100, Daniel Vetter wrote:
On Wed, Feb 05, 2014 at 01:21:34PM -0600, Jeff McGee wrote:
Gentle ping on this patch set for igt.
Both series pulled in, sorry for slacking off a bit.
-Daniel
Thanks, Daniel. The two driver patches to fix the failing subtests
On Tue, Feb 04, 2014 at 12:30:00PM +0100, Daniel Vetter wrote:
On Fri, Jan 31, 2014 at 03:42:47PM -0600, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
This series has recently been accepted into the Haswell Android kernel and
helps with debugging and profiling
On Thu, Feb 06, 2014 at 05:37:29PM +0100, Daniel Vetter wrote:
On Thu, Feb 6, 2014 at 4:44 PM, Jeff McGee jeff.mc...@intel.com wrote:
Our Android system validation tests are expecting these interfaces. That's
not igt, I know, but is supporting downstream test suites a priority? I can
get
on my machine here with 650-1300MHz range, where the
midpoint is 975.
Cc: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/pm_rps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 467038104ec6
On Fri, Mar 14, 2014 at 10:27:46AM +0100, Daniel Vetter wrote:
We don't call cleanup handlers when exiting a subtest currently, only
when exiting the entire binary. Which means pm_rps falls over when it
fails more than one subtest.
Cc: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Daniel
On Fri, Mar 14, 2014 at 10:27:47AM +0100, Daniel Vetter wrote:
There's no need to be fancy here.
Cc: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/pm_rps.c | 33 +++--
1 file changed, 7 insertions(+), 26 deletions
On Fri, Mar 14, 2014 at 10:27:48AM +0100, Daniel Vetter wrote:
Big core platforms need some seriuos omph to break a sweat.
This fixes min-max-config-loaded here on my ivb.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75146
Cc: Jeff McGee jeff.mc...@intel.com
Signed-off
On Thu, Mar 27, 2014 at 05:59:48PM +, oscar.ma...@intel.com wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
For the most part, logical rinf context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to
On Tue, Apr 15, 2014 at 11:00:33AM -0500, Jeff McGee wrote:
On Thu, Mar 27, 2014 at 05:59:48PM +, oscar.ma...@intel.com wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
For the most part, logical rinf context objects are similar to hardware
contexts in that the backing object
On Tue, Apr 15, 2014 at 11:10:34AM -0500, Jeff McGee wrote:
On Tue, Apr 15, 2014 at 11:00:33AM -0500, Jeff McGee wrote:
On Thu, Mar 27, 2014 at 05:59:48PM +, oscar.ma...@intel.com wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
For the most part, logical rinf context objects
On Tue, Apr 15, 2014 at 11:08:02PM +0200, Daniel Vetter wrote:
On Tue, Apr 15, 2014 at 03:43:23PM -0500, Jeff McGee wrote:
On Tue, Apr 15, 2014 at 11:10:34AM -0500, Jeff McGee wrote:
On Tue, Apr 15, 2014 at 11:00:33AM -0500, Jeff McGee wrote:
On Thu, Mar 27, 2014 at 05:59:48PM +
From: Jeff McGee jeff.mc...@intel.com
A check of rps/rc6 state after i915_reset determined that the ring
MAX_IDLE registers were returned to their hardware defaults and that
the GEN6_PMIMR register was set to mask all interrupts. This change
restores those values to their pre-reset states by re
From: Jeff McGee jeff.mc...@intel.com
Hello all,
Posting my first patch to the list. I have tested this fix on Android
kernel 3.9.1 and only compile-checked on drm-intel-nightly. I have
reviewed the changes to reset and rps/rc6 stuff and believe there
should be no hidden gotchas.
As I hope
From: Jeff McGee jeff.mc...@intel.com
This bug was found on OTC Haswell Android product which makes use of
sysfs to set rps min and max range at boot.
This patch follows the original patch in implementing the fix with
a minimum of code change, which was desirable for late
stage product
From: Jeff McGee jeff.mc...@intel.com
sysfs changes to rps min and max delay were only triggering an update
of the rps interrupt limits if the active delay required an update.
This change ensures that interrupt limits are always updated.
OTC-Tracker: VIZ-3144
Change-Id
From: Jeff McGee jeff.mc...@intel.com
sysfs changes to rps min and max delay were only triggering an update
of the rps interrupt limits if the active delay required an update.
This change ensures that interrupt limits are always updated.
v2: correct compile issue missed on rebase
OTC-Tracker
From: Jeff McGee jeff.mc...@intel.com
Setup new I915_GETPARAM ioctl entries for slice total, subslice
total, EU total, and threads per EU, so that userspace can query
the kernel for the values of these attributes instead of maintaining
individual lookup tables which must be indexed by PCI ID
From: Jeff McGee jeff.mc...@intel.com
Broadwell values could be tabulated by device ID, but we go ahead
and detect from fuses because it is easier and more flexible.
For: VIZ-4636
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 20
From: Jeff McGee jeff.mc...@intel.com
Cherryview fusing allows for different EU totals within a single
device ID, so fused-based detection is a must. Go ahead and determine
subslice total from fuse as well just in case. Slice total and
threads per EU are fixed for all CHV.
For: VIZ-4636
Signed
From: Jeff McGee jeff.mc...@intel.com
The motivation for this change is that fusing can be used to create
multiple slice, subslice, and EU configuration within the same PCI
ID. CHV is the first such device to do this and thus make an ID-based
lookup table approach unreliable. The best solution
From: Jeff McGee jeff.mc...@intel.com
New test core_getparams consists of 4 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: slice total, subslice total, EU total, and threads per
EU. drm/i915 implementation of these queries is required
On Fri, Jan 30, 2015 at 09:30:07AM +0200, Jani Nikula wrote:
On Thu, 29 Jan 2015, Jeff McGee jeff.mc...@intel.com wrote:
On Thu, Jan 29, 2015 at 02:13:38PM +, Damien Lespiau wrote:
We need to have a separate GT3 struct intel_device_info to declare they
have a second VCS. Let's start
this patch to help get total eu enabled and
read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store eu_total and
avoid sending info to userspace
v2: Format register definitions (Jani)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Jeff McGee
On Thu, Jan 29, 2015 at 02:13:38PM +, Damien Lespiau wrote:
We need to have a separate GT3 struct intel_device_info to declare they
have a second VCS. Let's start by splitting the PCI ids per-GT.
Would it be a good idea to do more programmatic population of
these fields, rather than
On Fri, Jan 09, 2015 at 10:56:16AM +0800, Zhenyu Wang wrote:
On 2014.12.18 12:12:33 -0600, jeff.mc...@intel.com wrote:
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 15dd01d..be38adf 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -340,6 +340,10
From: Jeff McGee jeff.mc...@intel.com
On Gen9 the render power gating can leave slice/subslice/EU in
a partially enabled state. We must make an explicit request for
full SSEU enablement through the Render Power Clock State
register when resuming render work. This register is save/
restored
From: Jeff McGee jeff.mc...@intel.com
Add a new section to the 'i915_sseu_status' debugfs entry to
report the currently enabled counts of slice, subslice, and
execution units on the device. The count of enabled subslice
per slice represents the most enabled subslice on any one
slice for devices
From: Jeff McGee jeff.mc...@intel.com
Read fuse registers to determine the available slice total,
subslice total, subslice per slice, EU total, and EU per subslice
counts of the SKL device. The EU per subslice attribute is more
precisely defined as the maximum EU available on any one subslice
From: Jeff McGee jeff.mc...@intel.com
The exit from SKL render power gating may not fully restore
slice and EU components. We have to explicitly restore them to
full enablement through the Render Power Clock State register.
Jeff McGee (3):
drm/i915/skl: Determine SKL slice/subslice/EU info
Link to the libdrm and igt patches corresponding to this change:
http://lists.freedesktop.org/archives/dri-devel/2014-December/074296.html
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057821.html
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On Thu, Mar 12, 2015 at 12:09:50PM +, Thomas Wood wrote:
On 10 March 2015 at 21:17, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full
On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
These two patches add detection of available and enabled
slice/subslice/EU on CHV following the implementation recently
merged for SKL. They have been requested to help CHV users
On Mon, Mar 09, 2015 at 09:40:50AM +0100, Daniel Vetter wrote:
On Fri, Mar 06, 2015 at 05:38:33PM -0800, Jeff McGee wrote:
On Fri, Feb 27, 2015 at 10:22:30AM -0800, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
These two patches add detection of available
From: Jeff McGee jeff.mc...@intel.com
Setup new I915_GETPARAM ioctl entries for subslice total and
EU total. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based tables that userspace drivers currently maintain
From: Jeff McGee jeff.mc...@intel.com
tests/core_getparams needs the new libdrm interfaces for
querying subslice and EU counts.
For: VIZ-4636
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b
From: Jeff McGee jeff.mc...@intel.com
Update kernel interface with new I915_GETPARAM ioctl entries for
subslice total and EU total. Add a wrapping function for each
parameter. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
From: Jeff McGee jeff.mc...@intel.com
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 8afee83..278f29b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ
From: Jeff McGee jeff.mc...@intel.com
tests/core_getparams needs the new libdrm interfaces for
querying subslice and EU counts.
For: VIZ-4636
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b
From: Jeff McGee jeff.mc...@intel.com
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices
From: Jeff McGee jeff.mc...@intel.com
Values of device max compute units and max subslice obtained
directly from the driver should be more accurate than our own
ID-based lookup values. This is particularly important when a
single device ID may encompass more than one configuration. If
the driver
From: Jeff McGee jeff.mc...@intel.com
tests/core_getparams needs the new libdrm interfaces for
querying subslice and EU counts.
For: VIZ-4636
Signed-off-by: Jeff McGee jeff.mc...@intel.com
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full enablement when the render engine is active. Starting with
Gen9
From: Jeff McGee jeff.mc...@intel.com
The media spin utility is derived from media fill. The purpose
is to create a simple means to keep the render engine (media
pipeline) busy for a controlled amount of time. It does so by
emitting a batch with a single execution thread that spins in
a tight
On Tue, Mar 10, 2015 at 01:58:52PM -0400, Rob Clark wrote:
On Tue, Mar 10, 2015 at 12:59 PM, Jeff McGee jeff.mc...@intel.com wrote:
On Tue, Mar 10, 2015 at 08:37:30AM +0100, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 04:41:02PM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc
patches for KMD/libdrm/Intel gpu tools and Beignet,
all look good to me.
And I just tested it on BDW and SKL platforms, it works fine.
Thanks,
Zhigang Gong.
On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Setup new
:37:32PM -0800, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Setup new I915_GETPARAM ioctl entries for subslice total and
EU total. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based
On Tue, Mar 10, 2015 at 08:37:30AM +0100, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 04:41:02PM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
tests/core_getparams needs the new libdrm interfaces for
querying subslice and EU counts.
For: VIZ-4636
Signed
From: Jeff McGee jeff.mc...@intel.com
New IGT testing to cover the RC6/SSEU issue recently resolved on SKL.
http://lists.freedesktop.org/archives/intel-gfx/2015-February/060058.html
Jeff McGee (2):
lib: Add media spin
tests/pm_sseu: Create new test pm_sseu
lib/Makefile.sources| 2
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full enablement when the render engine is active. Starting with
Gen9
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