Quoting Huang, Sean Z (2020-11-15 23:08:08)
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for
Quoting Huang, Sean Z (2020-11-15 23:07:58)
> With this ioctl action, ring3 driver can reserve a specific
> session slot/id assigned by ring0 PXP, as the first step of PXP
> session establishment flow. Ring3 PXP stores the session info in
> the session list structure.
The whole suggested userspace
Quoting Winkler, Tomas (2020-11-16 12:49:54)
>
>
> > -Original Message-
> > From: Joonas Lahtinen
> > Sent: Monday, November 16, 2020 11:47
> > To: Huang, Sean Z ; Intel-
> > g...@lists.freedesktop.org
> > Cc: Winkler, Tomas
> > Subject
+ Umesh, Lionel
Do we have a link to the userspace changes and IGT tests? Those are
absolutely needed before we can do a final review and merge.
We should really test and review the kernel and userspace changes
together to make sure that we're coming up with a solid uAPI.
Regards, Joonas
Quotin
Quoting Zhenyu Wang (2020-11-23 11:05:17)
>
> Hi,
>
> Here's gvt next pull for v5.11. Mostly it's for host suspend/resume
> fix with vGPU active and with some other enhancement as details below.
> Note that this includes some minor i915 driver change to add gvt hook
> in suspend/resume function w
+ intel-gfx mailing list
Quoting ira.we...@intel.com (2020-11-24 08:07:41)
> From: Ira Weiny
>
> The pattern of kmap/mem*/kunmap is repeated. Use the new mem*_page()
> calls instead.
>
> Cc: Patrik Jakobsson
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo
Quoting Thomas Zimmermann (2020-11-24 13:38:16)
> Using struct drm_device.pdev is deprecated. Convert i915 to struct
> drm_device.dev. No functional changes.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
Any chance of
Quoting Zhenyu Wang (2020-11-24 05:13:59)
> On 2020.11.23 11:32:38 +0200, Joonas Lahtinen wrote:
> > Quoting Zhenyu Wang (2020-11-23 11:05:17)
> > >
> > > Hi,
> > >
> > > Here's gvt next pull for v5.11. Mostly it's for host suspen
Quoting Huang, Sean Z (2020-12-07 02:21:19)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps user space to establish the hardware protected session
> and manage the status of each alive software session, as well as
> the life cycle of each session.
>
> By design P
Quoting Huang, Sean Z (2020-12-07 02:21:20)
> Create the irq worker that serves as callback handler, those
> callback stubs should be called while the hardware key teardown
> occurs.
>
> Signed-off-by: Huang, Sean Z
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include
Quoting Huang, Sean Z (2020-12-07 02:21:21)
> Add PXP context which represents combined view
> of driver and logical HW states.
>
> Signed-off-by: Huang, Sean Z
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "intel_pxp.h"
> +#include "in
Quoting Huang, Sean Z (2020-12-07 02:21:22)
> Set the KCR init during the boot time, which is required by
> hardware, to allow us doing further protection operation such
> as sending commands to GPU or TEE
>
> Signed-off-by: Huang, Sean Z
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6
Quoting Huang, Sean Z (2020-12-07 02:21:23)
> Implement the functions to check the hardware protected session
> state via reading the hardware register session in play.
>
> Signed-off-by: Huang, Sean Z
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -12,6 +12,9 @@
> #define PXP_IRQ_VECTOR_D
Quoting Huang, Sean Z (2020-12-07 02:21:24)
> Implement the functions to get/set the PXP tag, which is 32-bit
> bitwise value containing the hardware session info, such as its
> session id, protection mode or whether it's enabled.
>
> Signed-off-by: Huang, Sean Z
By my understanding, this patch
Quoting Huang, Sean Z (2020-12-07 02:21:25)
> Currently ring3 driver sends the TEE commands directly to TEE, but
> later, as our design, we would like to make ring3 sending the TEE
> commands via the ring0 PXP ioctl action instead of TEE ioctl, so
> we can centralize those protection operations at
Quoting Huang, Sean Z (2020-12-07 02:21:26)
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for
Quoting Huang, Sean Z (2020-12-07 02:21:27)
> Implement the functions to allow PXP to send a GPU command, in
> order to terminate the hardware session, so hardware can recycle
> this session slot for the next usage.
>
> Signed-off-by: Huang, Sean Z
As we only have a singleton session support in
Quoting Tvrtko Ursulin (2021-03-11 12:45:54)
>
> On 05/03/2021 12:58, Cooper Chiou wrote:
> > WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
> > resolve VP8 hardware encoding system hang up on GT1 sku for
> > ChromiumOS projects
> >
> > Slice specific MMIO read inaccurate so MG
E index of tgl_mocs_table
> with desired value.
>
> Cc: Chris Wilson
> Cc: Lucas De Marchi
> Cc: Tomasz Lis
> Cc: Matt Roper
> Cc: Joonas Lahtinen
> Cc: Francisco Jerez
> Cc: Mathew Alwin
> Cc: Mcguire Russell W
> Cc: Spruit Neil R
> Cc: Zhou Cheng
>
+ Lionel
Can you please take a look at best resolving the below problem.
Maybe we should eliminate the duplicate declarations? Updating such
a list manually seems error prone to me.
Regards, Joonas
Quoting Mauro Carvalho Chehab (2020-10-13 14:53:59)
> As reported by Sphinx:
>
> ./Docum
+ Zhenyu & Zhi,
Should not we instead fix the reason why the errors happen instead of
rate-limiting them?
Regards, Joonas
Quoting Stefan Fritsch (2020-10-16 18:23:40)
> If linux is running as a guest and the host is doing igd pass-through
> with VT-d enabled, this message is logged dozens of tim
Quoting Tvrtko Ursulin (2020-10-22 18:22:10)
>
> + Joonas for maintainer class question.
>
> On 15/10/2020 19:28, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > Update to the latest GuC firmware
> >
> > v2: Rebase to newer tree, updated a commit message (review feedback
> > f
Quoting john.c.harri...@intel.com (2020-10-28 16:58:23)
> From: John Harrison
>
> Update to the latest GuC firmware
>
> v2: Rebase to newer tree, updated a commit message (review feedback
> from Daniele) and dropped the patch to enable GuC/HuC loading by
> default as apparently this is not allow
+ intel-gfx mailing list
Quoting Joonas Lahtinen (2020-10-30 12:15:44)
> Quoting Jonny Grant (2020-10-27 22:42:19)
> > Hello Jani, Joonas
> >
> > https://gitlab.gnome.org/GNOME/eog/-/issues/146
> >
> > Is this issue something you could debug?
>
&
Quoting Tvrtko Ursulin (2020-11-03 11:14:32)
>
>
> On 03/11/2020 02:53, Lu Baolu wrote:
> > On 11/2/20 7:52 PM, Tvrtko Ursulin wrote:
> >>
> >> On 02/11/2020 02:00, Lu Baolu wrote:
> >>> Hi Tvrtko,
> >>> On 10/12/20 4:44 PM, Tvrtko Ursulin wrote:
>
> On 29/09/2020 01:11, Lu Baolu wrote:
Quoting Lucas De Marchi (2020-10-27 06:46:18)
> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
> Bridge"). Other than printing their values in debugfs we don't do
> anything with them. There's not much us
Quoting Chris Wilson (2019-12-22 16:40:46)
> From: Andi Shyti
>
> The GT system is becoming more and more a stand-alone system in
> i915 and it's fair to assign it its own debugfs directory.
>
> rc6, rps and llc debugfs files are gt related, move them into the
> gt debugfs directory.
>
> Signed
+ Rodrigo,
Quoting Aditya Swarup (2020-10-21 16:32:08)
> From: Anusha Srivatsa
>
> - Inherit the gen12 workarounds.
> - Add placeholders to setup GT WA.
> - Extend permanent driver WA Wa_1409767108 to adl-s and
> Wa_14010685332 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s
>
Quoting Lucas De Marchi (2020-11-05 03:04:22)
> On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
> >Quoting Lucas De Marchi (2020-10-27 06:46:18)
> >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> >> commit 3b8d8d91d51c ("
Quoting Dave Airlie (2020-05-07 21:27:27)
> On Fri, 8 May 2020 at 01:44, Chris Wilson wrote:
> >
> > Quoting Jason Ekstrand (2020-05-07 16:36:00)
> > > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > > it's running on a version of i915 that supports at least softpin whic
Ping for merging this? If there are no issues, I'd prefer to pull in
next gvt-next and tag the final pull sooner than later.
Regards, Joonas
Quoting Joonas Lahtinen (2020-04-30 15:49:04)
> Hi Dave & Daniel,
>
> Fix for performance regression GitLab #1698: Iris Plus 655 and
&g
Quoting Dave Airlie (2020-05-14 04:28:17)
> On Thu, 14 May 2020 at 03:10, Joonas Lahtinen
> wrote:
> >
> > Ping for merging this? If there are no issues, I'd prefer to pull in
> > next gvt-next and tag the final pull sooner than later.
>
> Can you check
Quoting Zhenyu Wang (2020-05-12 12:40:17)
>
> Hi,
>
> This includes support for ppgtt update by LRI command which gvt
> replaces by shadow ppgtt, another small optimization for shadow
> ctx and one workload destroy cleanup.
This is now pulled. Thanks for the PR.
Regards, Joonas
>
> Thanks
> -
Pushed using the note:: block. Thanks for the review and ack.
Regards, Joonas
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drm/i915: Stop sending DP SDPs on ddi disable
drm/i915/dp: Add compute routine for DP PSR VSC SDP
drm/i915/psr: Use new DP VSC SDP compute routine on PSR
Imre Deak (1):
drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
Joonas Lahtinen (3):
Merge tag 'gvt-
t; Fixes: 2e46a2a0b014 ("drm/i915: Use explicit flag to mark unreachable
> intel_context")
> Fixes: 2b703bbda271 ("Merge drm/drm-next into drm-intel-next-queued")
> Signed-off-by: Chris Wilson
> Cc: Rodrigo Vivi
> Cc: Joonas Lahtinen
Reviewed-by: Joon
ompute routine on PSR
Imre Deak (2):
drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
drm/i915: Fix AUX power domain toggling across TypeC mode resets
Joonas Lahtinen (3):
Merge tag 'gvt-next-2020-05-12' of https://github.com/intel/gvt-linux
into drm-intel
Hi Dave & Daniel,
Two bigger fixes to corner case kernel access faults
and three workload scheduling fixups this week.
CI_DINF_191 at:
https://intel-gfx-ci.01.org/tree/drm-intel-next-fixes/combined-alt.html?
I got gvt-next-fixes pull today, I'll pull it next week so it
has time to run through CI
Quoting Zhenyu Wang (2020-05-28 06:35:59)
>
> Hi,
>
> Here's two queued warning fixes for gvt-next. One is for clang warning
> on debug only function and another one from coccicheck to use ARRAY_SIZE.
Pulled now, thanks for the PR.
Regards, Joonas
>
> Thanks
> --
> The following changes since
drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions
Joonas Lahtinen (1):
Merge tag 'gvt-next-fixes-2020-05-28' of
https://github.com/intel/gvt-linux into drm-intel-next-fixes
Nathan Chancellor (1):
drm/i915: Mark check_shadow_context_ppgtt as maybe
lication.
Now we have the worst coherency by default if an application is using
reserved entry, making it more likely to be noticed at develop time. And
even if it would not be noticed, modifying the entry for better
coherency should not functionally break the application.
Regards, Joonas
> >
Hi Dave & Daniel,
Sending this one early for it to hopefully make it in before -rc1.
Two important fixes: OOPS fix that was missing "Fixes:" tag and
not picked up earlier. Also fix for a use-after-free in cmdparser.
Additional fixup to module param types.
Regards, Joonas
***
drm-intel-next-fi
Quoting Joonas Lahtinen (2020-06-10 12:37:00)
> Hi Dave & Daniel,
>
> Sending this one early for it to hopefully make it in before -rc1.
>
> Two important fixes: OOPS fix that was missing "Fixes:" tag and
> not picked up earlier. Also fix for a use-after-free in
Quoting Stephen Rothwell (2020-06-16 02:39:12)
> Hi all,
>
> After merging the drm-intel-fixes tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5972:
> drivers/gpu/drm/i915/gt/selftest_lrc.c: In function
> 'liv
Hi Dave & Daniel,
-rc1 required the usual juggling to get baseline from CI.
Needed to temporarily apply this fixup to drm-intel-fixes:
"ext4: mballoc: Use this_cpu_read instead of this_cpu_ptr"
For display side, fix for TypeC interrupt storm detection. Fixes to
TypeC, DDI and MST hardware registe
Quoting Zhenyu Wang (2020-06-17 07:34:18)
>
> Hi,
>
> This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL,
> one mask register bit checking fix exposed in suspend/resume path and
> one lockdep error fix for debugfs entry access.
Could not pull this one due to the extra hassle wit
Hi,
Based on there being no replies, I'll assume the below mentioned
patches can be skipped.
There is one new commit, which I'll skip considering we're at -rc7
already:
b588e7015c92 ("drm/i915: Provide the perf pmu.module")
Regards, Joonas
Quoting Jani Nikula (2020-07-15 16:16:19)
>
> Hi all
Quoting Zhenyu Wang (2020-07-20 11:05:41)
>
> Hi,
>
> Sorry that this might be a bit late as last week our QA people were
> busy on something else..So this is gvt changes queued for 5.9 which is
> to improve guest suspend/resume with proper PCI PM state tracking for
> resource handling, e.g ppgtt
Hi Dave & Daniel,
(Covering for Jani here for drm-intel-next-fixes)
5 new commits over drm-intel-next here.
Fix for KASAN detected race condition and linux-next scheduler
WARNs. Patch to avoid IRQ spinlock and Cc: stable PMU refcount
update.
CI machinery needed some kicking, so results didn't a
Quoting Dave Airlie (2020-07-20 00:52:19)
> On Thu, 16 Jul 2020 at 20:11, Matthew Auld wrote:
> >
> > On 16/07/2020 01:43, Dave Airlie wrote:
> > > On Wed, 15 Jul 2020 at 00:35, Matthew Auld wrote:
> > >>
> > >> On 13/07/2020 06:09, Dave Airlie wrote:
> > >>> On Fri, 10 Jul 2020 at 22:00, Matthew
Quoting Dave Airlie (2020-07-14 22:26:16)
> On Wed, 15 Jul 2020 at 02:57, Tang, CQ wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Auld, Matthew
> > > Sent: Tuesday, July 14, 2020 8:02 AM
> > > To: Dave Airlie
>
Quoting Dave Airlie (2020-07-13 08:09:30)
> On Fri, 10 Jul 2020 at 22:00, Matthew Auld wrote:
> >
> > We need to add support for pwrite'ing an LMEM object.
>
> why? DG1 is a discrete GPU, these interfaces we already gross and
> overly hacky for integrated, I'd prefer not to drag them across into
Hi Dave & Daniel,
Here goes the GT pull request for v5.10. It's the same patches as
previously at "topic/drm-intel-gem-next", one dropped and a few
re-ordered while creating the "drm-intel-gt-next" branch. So the
patches have been part of drm-tip already for weeks.
More about the PR itself at the
Hi Dave & Daniel,
Exactly same content as previous PR:
https://lists.freedesktop.org/archives/intel-gfx/2020-September/247626.html
Just rebased adding the missing S-o-b:s and updated "Fixes:" tags accordingly
as requested.
Regards, Joonas
***
drm-intel-gt-next-2020-09-07:
(Same content as dr
+ Jani and Ville
Quoting Matthew Auld (2020-09-11 11:56:56)
> On 11/09/2020 06:42, Dave Airlie wrote:
> > I've just been looking at the current DG1 uapi, and I can't see any
> > flag to allow userspace to upfront say it was a contiguous vram BO.
> >
> > I think you'd really want this for scanout,
check for hung contexts -- but we did not prevent those
> contexts from being resubmitted if they survived the final hangcheck.
>
> Fixes: 9a40bddd47ca ("drm/i915/gt: Expose heartbeat interval via sysfs")
> Testcase: igt/gem_ctx_persistence/heartbeat-stop
> Signed-
e kernel patches, the right thing to do.
Acked-by: Joonas Lahtinen
Regards, Joonas
> ---
> tests/i915/gem_ctx_persistence.c | 92
> 1 file changed, 92 insertions(+)
>
> diff --git a/tests/i915/gem_ctx_persistence.c
> b/tests/i915/gem_ctx_pers
+ Dave and Daniel
+ Stephen
Quoting Christoph Hellwig (2020-09-26 09:29:59)
> On Fri, Sep 25, 2020 at 07:43:49PM -0700, Andrew Morton wrote:
> > On Thu, 24 Sep 2020 15:58:42 +0200 Christoph Hellwig wrote:
> >
> > > this series removes alloc_vm_area, which was left over from the big
> > > vmalloc
Reviewed-by: Joonas Lahtinen
Regards, Joonas
> ---
> tests/i915/gem_exec_parallel.c | 31 +--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
> index bf94b93d4..96feb
(+ intel-gfx for being i915 related)
(+ Chris who has looked into the issue)
Hi,
Thanks for reporting!
Could you open a bug report according to following instructions:
https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
A full dmesg of a bad boot and git bisect logs will be
Quoting Christoph Hellwig (2020-09-28 15:37:41)
> On Mon, Sep 28, 2020 at 01:13:38PM +0300, Joonas Lahtinen wrote:
> > I think we have a gap that after splitting the drm-intel-next pull requests
> > into
> > two the drm-intel/for-linux-next branch is now missing material f
Quoting paul...@kernel.org (2020-09-29 02:30:58)
> From: Thomas Gleixner
>
> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be
> removed. Cleanup the leftovers before doing so.
Change looks fine:
Reviewed-by: Joonas Lahtinen
Are you looking for us to merge or m
Quoting Daniel Vetter (2020-10-01 18:13:26)
> On Thu, Oct 1, 2020 at 5:08 PM Jani Nikula
> wrote:
> >
> > On Thu, 01 Oct 2020, Daniel Vetter wrote:
> > > On Thu, Oct 1, 2020 at 3:53 PM Christoph Hellwig wrote:
> > >>
> > >> On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote:
> > >
> > --+--
> > HuC state | option B
> > --+--
> > no HuC hardware | -ENODEV
> > GuC fw disabled | -EOPNOTSUPP -> user decision, why error?
> > HuC fw disabled | -EOPNOTSUPP -> user decision, why error?
> > HuC
Rebase
>
> v8: Change to NEEDS_GUC_FW (Chris)
> Applying review comments (Michal)
> Clarifying commit message (Joonas)
>
> v9: Applying review comments (Michal)
>
> v10: Introducing enable_guc modparam
>Applying review comments (Michal)
>
> Signed-off-by:
t; drivers/gpu/drm/i915/gvt/scheduler.c | 33 +++---
> drivers/gpu/drm/i915/gvt/scheduler.h | 3 +++
> 6 files changed, 44 insertions(+), 51 deletions(-)
>
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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On Wed, 2017-11-29 at 11:47 +0530, Sagar Arun Kamble wrote:
> With new GuC firmwares (SKL v9.33, BXT v9.29, KBL v9.39) available now
> at 01.org downloads, let us update the default firmware versions.
I thought the agreement was for them to be at linux-firmware repo?
Regards, Joonas
--
On Mon, 2017-11-27 at 13:36 +, Rantala, Valtteri wrote:
> > -Original Message-
> > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> > Sent: Monday, November 27, 2017 11:13 AM
> > To: Intel graphics driver community testing & development
(Chris Wilson)
> v4: Move flag setting to intel_engines_reset_default_submission.
> (Chris Wilson)
> v5: Move flag setting to logical_ring_setup.
>
> Signed-off-by: Tvrtko Ursulin
> Suggested-by: Sagar Arun Kamble
> Cc: Sagar Arun Kamble
> Reviewed-by: Chris Wilson
sync fbdev config
Joonas Lahtinen (2):
Merge tag 'gvt-fixes-2017-11-28' of https://github.com/intel/gvt-linux
into drm-intel-fixes
drm/i915: Disable THP until we have a GPU read BW W/A
Ville Syrjälä (2):
drm/i915: Don't try indexed reads to alternate slave addresses
gister set name to nonpriv, as this is what bspec calls the
> registers that are writable by userspace.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> +static uint32_t read_regs(int fd,
> + uint32_t ctx,
> +
dered? Like:
#define FALLTHROUGH __attribute__((fallthrough));
With the appropriate version checks, of course.
Regards, Joonas
--
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Open Source Technology Center
Intel Corporation
___
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Intel-gfx@lists.freedeskto
: Chris Wilson
>
> Reviewed-by: Chris Wilson
> -Chris
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Joonas Lahtinen
Open Source Techn
From: Sinan Kaya
pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
where a PCI device is present. This restricts the device drivers to be
reused for other domain numbers.
Getting ready to remove pci_get_bus_and_slot() function in favor of
pci_get_domain_bus_and_slot().
Extr
t; Fixes: c5ad54cf7dd8 ("drm/i915: Use partial view in mmap fault handler")
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: sta...@vger.kernel.org
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporat
_ctx)
> +static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
> {
> if (!wa_ctx->indirect_ctx.obj)
> return;
--
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Open Source Technology Center
Intel Corporation
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s is important for igt, where if the
> + * GPU/driver fails we want to reboot and restart testing
> + * rather than continue on into oblivion.
> + */
As Marta mentioned too, How igt works on a given day is bit volatile to
document in the kernel comments.
eviewed-by: Joonas Lahtien
Regards, Joonas
--
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> Signed-off-by: Daniel Vetter
<foo> looks trippy.
As we're not trying to document HTML stuff, maybe simly ->
${foo}. I'm pretty sure everyone will be comfortable with that
notation.
Regards, Joonas
--
Joonas Lahtinen
Op
Wilson
Even the variable names were good.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
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e effectiveness of selftesting to GEM for the
> time being. To exercise KMS from selftests we would essentially have to
> always mock the displays.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=103718
> Signed-off-by: Chris Wilson
I think it's fair thing to do
> v2: {foo} instead of of tripy <foo> (Joonas)
>
> Cc: Joonas Lahtinen
> Signed-off-by: Daniel Vetter
> +++ b/lib/igt_core.c
> @@ -167,10 +167,10 @@
> * test logic.
> *
> * - When adding a new feature test function which uses igt_skip()
> in
pu/drm/i915/intel_dsi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > > @@ -1670,7 +1670,7 @@ static int intel_dsi_get_panel_orientation(struct
> > > > intel_connector *connector)
> > > > {
> > > > struct drm_i915_p
ing to give you atomicity.
> -Chris
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__
st remember to refresh the -fixup.patch).
Regards, Joonas
>
> > u32 val;
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > --
> > 2.13.6
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
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Open Source Technology Center
Intel Corporation
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Dropping GVT folks that are not affected.
Keeping Zhenyu and Zhi as a heads-up, there's no need for GVT pull for this rc?
On Tue, 2017-11-28 at 10:54 +0200, Joonas Lahtinen wrote:
> Hello,
>
> TL;DR Reply with backported patches for v4.15-rc1 latest TODAY
>
> Dear pat
: Export intel_gvt_render_mmio_to_ring_id()
>
> drivers/gpu/drm/i915/gvt/cfg_space.c | 21
> drivers/gpu/drm/i915/gvt/handlers.c | 47
>
> drivers/gpu/drm/i915/gvt/mmio.h | 2 ++
> drivers/gpu/drm/i915/gvt/scheduler.c |
end when wedged
drm/i915: Call i915_gem_init_userptr() before taking struct_mutex
James Ausmus (1):
drm/i915/cnl: Mask previous DDI - PLL mapping
Joonas Lahtinen (1):
Merge tag 'gvt-fixes-2017-12-06' of https://github.com/intel/gvt-linux
into drm-intel-fixes
Radhakri
->mode_config.max_width = 8192;
> - dev->mode_config.max_height = 8192;
> + dev->mode_config.max_width = 16384;
> + dev->mode_config.max_height = 16384;
> }
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_p
taining state (e.g. ensuring that all vma are flushed or rebound).
> As such maintenance needs to go on beyond the user's awareness of the
> vma, defer removal of the vma from the obj->vma_list from i915_vma_close()
> to i915_vma_destroy()
>
> Signed-off-by: Chris Wilson
&g
RCS may have
> been freed, or never existed!)
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=104002
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
One comment below, not strictly related to this patch.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
d by another upstream
patch, so while this revert removed the variable, the newly added non-
conflicting code still depended on it.
More specific variable names like "dpfc" and allowing compiler to
decide when to optimize and recycle variables woul
On Sat, 2017-12-09 at 10:44 +, Chris Wilson wrote:
> The per-engine seqno info is now available from
> debugfs/i915_engine_info obsoleting debugfs/i915_seqno_info, so remove it.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
On Sat, 2017-12-09 at 10:44 +, Chris Wilson wrote:
> Since the seqno information shown from i915_interrupt_info is just a
> small subset of i915_engine_info, remove it.
>
> Signed-off-by: Chris Wilson
One comment below.
Reviewed-by: Joonas Lahtinen
> +++ b/drive
On Fri, 2017-12-08 at 22:50 +, Chris Wilson wrote:
> Keep reloading the module with the next load failure until we run out of
> injection sites and the module loads successfully. Or it goes boom.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joona
ore
generic.
If this is all GuC related and only ever needs to be programmed for GuC
as the current naming suggest, then it's a great question why we are
not programming the register according to some firmware reported size
instead of replicating here.
Regards, Joo
uot;drm/i915: Add support for drm syncobjs")
There's been request to reduce the amount of Fixes: tags that are not
actually fixing bugs. This seems more like an optimization.
References: has been suggested for these cases instead.
Regards, Joonas
--
Joonas Lahtinen
Open Source
s a bit more debugging for when it fails.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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dition, this should have following
tags (adding them to this mail);
Fixes: b056f8f3d6b9 ("drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.")
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: David Airlie
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.fre
+ GVT folks.
On Fri, 2017-12-08 at 09:15 +1100, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> 365ad5df9caa ("drm/i915/gvt: Export
> intel_gvt_render_mmio_to_ring_id()")
>
> is missing a Signed-off-by from its committer.
>
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Joonas Lahtine
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