[Intel-gfx] [PATCH] drm/i915/icl: Disable pipe CSC and gamma in cursor plane

intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c9ec88acad9c..9

[Intel-gfx] [PATCH v3 7/7] drm/i915/psr: Avoid PSR exit max time timeout

nel will interrupt and assert one of the PSR errors handled in: 'drm/i915/psr: Handle PSR RFB storage error' and 'drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink' Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by:

[Intel-gfx] [PATCH v3 2/7] drm/i915/dp: Use intel_dp_aux_wait_done() to wait for previous aux xfer

This reduces the spaghetti that intel_dp_aux_xfer() and reuses code. The only difference is that now it will wait up to 10ms instead of 3ms. Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.

[Intel-gfx] [PATCH v3 1/7] drm/i915/psr: Nuke PSR support for VLV and CHV

From: Dhinakaran Pandiyan PSR hardware and hence the driver code for VLV and CHV deviates a lot from their DDI counterparts. While the feature has been disabled for a long time now, retaining support for these platforms is a maintenance burden. There have been

[Intel-gfx] [PATCH v3 5/7] drm/i915/psr: Handle PSR RFB storage error

Sink will interrupt source when it have any problem saving or reading the remote frame buffer. v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de So

[Intel-gfx] [PATCH v3 3/7] drm/i915/psr: Remove intel_crtc_state parameter from disable()

It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --

[Intel-gfx] [PATCH v3 6/7] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

as a trigger to exit PSR when CRC check is enabled to improve power savings. Spec: 7723 v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.

[Intel-gfx] [PATCH v3 4/7] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

), to avoid multiple rendering issues due to bad pannels. v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/d

[Intel-gfx] [PATCH v4 1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable()

It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/intel_psr.c | 5

[Intel-gfx] [PATCH v4 2/5] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

), to avoid multiple rendering issues due to bad pannels. v4: Using CAN_PSR instead of HAS_PSR in intel_psr_short_pulse v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 2

[Intel-gfx] [PATCH v4 3/5] drm/i915/psr: Handle PSR RFB storage error

Sink will interrupt source when it have any problem saving or reading the remote frame buffer. v3: disabling PSR instead of exiting on error Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 14 ++ 1 file

[Intel-gfx] [PATCH v4 4/5] drm/i915/psr: Avoid PSR exit max time timeout

side' to avoid touch in 2 patches EDP_PSR_DEBUG. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 5/5] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

/i915/psr: Avoid PSR exit max time timeout' to avoid touch in 2 patches EDP_PSR_DEBUG. v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 16

[Intel-gfx] [PATCH 2/2] drm/i915/aml: Introducing Amber Lake platform

but it will be handled as a KBL. Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 1 + include/drm/i915_pciids.h | 9 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 2/2] drm/i915/aml: Introducing Amber Lake platform

but it will be handled as a KBL. Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 1 + include/drm/i915_pciids.h | 9 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 1/2] drm/i915/whl: Introducing Whiskey Lake platform

review but it will be handled as a CFL. v2: Fixing GT level of some ids Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 4 +++- include/drm/i915_pciids.h | 28 ++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff

[Intel-gfx] [PATCH 1/2] drm/i915/whl: Introducing Whiskey Lake platform

review but it will be handled as a CFL. Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 4 +++- include/drm/i915_pciids.h | 28 ++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v5 3/5] drm/i915/psr: Handle PSR errors

changed v3: disabling PSR instead of exiting on error Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm

[Intel-gfx] [PATCH v5 5/5] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

/i915/psr: Avoid PSR exit max time timeout' to avoid touch in 2 patches EDP_PSR_DEBUG. v3: disabling PSR instead of exiting on error Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 7

[Intel-gfx] [PATCH v5 4/5] drm/i915/psr: Avoid PSR exit max time timeout

patches EDP_PSR_DEBUG. Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index

[Intel-gfx] [PATCH v5 1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable()

It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/intel_psr.c | 5

[Intel-gfx] [PATCH v5 2/5] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 62 ++-- 3 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH v7 2/5] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 62 ++-- 3 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v7 5/5] drm/i915/psr: Enable CRC check in the static frame on the sink side

DP_PSR_LINK_CRC_ERROR here and remove "bdw+" from commit message v4: patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout' to avoid touch in 2 patches EDP_PSR_DEBUG. v3: disabling PSR instead of exiting on error Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Robert

[Intel-gfx] [PATCH v7 3/5] drm/i915/psr: Handle PSR errors

all PSR errors here, so the commit message and comment have changed v3: disabling PSR instead of exiting on error Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 22 +- 1 file changed, 21

[Intel-gfx] [PATCH v7 4/5] drm/i915/psr: Avoid PSR exit max time timeout

patches EDP_PSR_DEBUG. Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index

[Intel-gfx] [PATCH v7 1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable_source()

It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. v7: Rebased Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 5 ++--- 1 file changed, 2

[Intel-gfx] [PATCH] drm/i915: Fix CHICKEN_TRANS register offset

. Spec: 7524 Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c30cfcd90754..098a4cb71310 100644

[Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths

to allocate the required CFB in the schedule activation work, it will happen after one vblank so is guarantee that FBC was completed disabled and is not using CFB. Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105683 --- drivers/gpu/drm

[Intel-gfx] [PATCH 1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_fbc.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index b431b6733cc1..eb0f95390968 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c

[Intel-gfx] [PATCH 3/5] drm/i915: Share PSR and PSR2 VSC setup

Just share the common code in PSR and PSR2. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c

[Intel-gfx] [PATCH 1/5] drm/i915: add and enable DP AUX CH mutex

be sent." BSpec: 7530 Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 9 drivers/gpu/drm/i915/intel_dp.c | 48 drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 4/5] drm/i915: Replace magic number with macro defined by drm

Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 60ca39d3b226..c24afc73e30b 100644 --- a/drivers/g

[Intel-gfx] [PATCH 2/5] drm/i915: keep AUX powered while PSR is enabled

tions. If PSR is enabled on a port, then the associated Aux IO must be kept powered up." BSpec: 4230 BSpec: 17722 Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 5/5] drm/i915: Make use of unused variable in hsw_write_infoframe()

data_reg was not being used but it can be used to reduce the number of calls to hsw_dip_data_reg() and just increment the reg by the size of uint32. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_hdmi.c | 12 1 file changed, 4 inse

[Intel-gfx] [PATCH 1/3] drm/i915: Share PSR and PSR2 VSC setup

Just share the common code in PSR and PSR2. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c

[Intel-gfx] [PATCH 2/3] drm/i915: Replace magic number with macro defined by drm

Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 71801a25a2b3..3fc1bdd65b14 100644 --- a/drivers/g

[Intel-gfx] [PATCH 3/3] drm/i915: Remove unused variable in hsw_write_infoframe()

Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_hdmi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index f5d7bfb43006..fe4bef081dae 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

- AUX programming sequence Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 9 drivers/gpu/drm/i91

[Intel-gfx] [PATCH v2 0/1] drm/i915: Add and enable DP AUX CH mutex

- moved register bits right after the DP_AUX_CH_MUTEX() - removed 'drm/i915: keep AUX powered while PSR is enabled' Dhinakaran Pandiyan will sent a better and final version José Roberto de Souza (1): drm/i915: Add and enable DP AUX CH mutex drivers/gpu/drm/i915/i915_reg.h | 9 drivers/gpu

[Intel-gfx] [PATCH 1/1] drm/i915/skl+: Add and enable DP AUX CH mutex

-prm-osrc-skl-vol12-display.pdf Page 198 - AUX programming sequence Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-b

[Intel-gfx] [PATCH v3 0/1] drm/i915: Add and enable DP AUX CH mutex

- rebased on top of Ville's AUX series - moved port registers to above DP_AUX_CH_MUTEX() - using intel_wait_for_register() instead of the internal version José Roberto de Souza (1): drm/i915/skl+: Add and enable DP AUX CH mutex drivers/gpu/drm/i915/i915_reg.h | 9 ++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH 5/6] drm/i915/psr: Handle PSR RFB storage error

Sink will interrupt source when it have any problem saving or reading the remote frame buffer. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_p

[Intel-gfx] [PATCH 2/6] drm/i915/psr: Share the common code between PSR exit and disable

Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 199 +++ 2 files changed, 96 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drive

[Intel-gfx] [PATCH 6/6] drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side

Sink can be configured to calculate the CRC over the static frame and compare with the CRC calculated and transmited in the VSC SDP by source, if there is a mismatch sink will do a short pulse in HPD and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS. Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH 4/6] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

Sink device will do a short pulse in HPD line when there is some PSR/PSR2 error that needs to be handled by source, this is handling the first and most simples error: DP_PSR_SINK_INTERNAL_ERROR. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 3/6] drm/i915: Exit PSR before do a aux transaction in gen < 9

As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR and wait until it is back to inactive state before do any aux ch transaction. Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 8 +++- drivers/gpu/drm/i915/intel_d

[Intel-gfx] [PATCH 1/6] drm/i915/skl+: Add and enable DP AUX CH mutex

programming sequence Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 9 ++ drivers/gpu/drm/i915/intel_dp.c | 67 drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 77 insertions(+) diff

[Intel-gfx] [PATCH v4 0/1] drm/i915: Add and enable DP AUX CH mutex

to the timeout debug message José Roberto de Souza (1): drm/i915/skl+: Add and enable DP AUX CH mutex drivers/gpu/drm/i915/i915_reg.h | 9 drivers/gpu/drm/i915/intel_dp.c | 47 + 2 files changed, 56 insertions(+) -- 2.16.2

[Intel-gfx] [PATCH v4 1/1] drm/i915/skl+: Add and enable DP AUX CH mutex

-prm-osrc-skl-vol12-display.pdf Page 198 - AUX programming sequence Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-b

[Intel-gfx] [PATCH v6 1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable()

It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/intel_psr.c | 5

[Intel-gfx] [PATCH v6 5/5] drm/i915/psr: Enable CRC check in the static frame on the sink side

DP_PSR_LINK_CRC_ERROR here and remove "bdw+" from commit message v4: patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout' to avoid touch in 2 patches EDP_PSR_DEBUG. v3: disabling PSR instead of exiting on error Reviewed-by: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Robert

[Intel-gfx] [PATCH v6 2/5] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 62 ++-- 3 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v6 4/5] drm/i915/psr: Avoid PSR exit max time timeout

patches EDP_PSR_DEBUG. Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index

[Intel-gfx] [PATCH v6 3/5] drm/i915/psr: Handle PSR errors

all PSR errors here, so the commit message and comment have changed v3: disabling PSR instead of exiting on error Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 22 +- 1 file changed, 21

[Intel-gfx] [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions

It is not used anymore after 'drm/i915/cnl+: Reload CSR firmware when coming back from low power state'. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/intel_drv.h| 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 19

[Intel-gfx] [PATCH 3/3] drm/i915: Keep overlay functions naming consistent

All other overlay functions(almost all other functions in i915) follow intel_overlay_verb, so renaming the ones that do not match that. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states

When returning from low power states the CSR firmware was not being loaded again in CNL and ICL. Also taking the opportunity to share the load call for gen >= 9, instead of calling it from each display_core_init() function. Cc: Paulo Zanoni Cc: Anusha Srivatsa Signed-off-by: José Roberto

[Intel-gfx] [PATCH 09/10] drm/i915: Do not call modeset related functions when display is disabled

, this is a initial work. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 146 +++- drivers/gpu/drm/i915/i915_suspend.c | 24 ++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +- 3 files changed, 107 insertions(+), 66 deletions(-) diff

[Intel-gfx] [PATCH 01/10] drm: Let userspace check if driver supports modeset

to detect if display is enabled but it is a hackish way it can fail for other reasons too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/drm_ioctl.c | 3 +++ include/uapi/drm/drm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 08/10] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()

IPC(Isochronous Priority Control not Inter-process communication btw) is a display feature, so i915_load_modeset_init() is the right place to initialize it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[Intel-gfx] [PATCH 06/10] drm/i915: Move FBC init and cleanup calls to modeset functions

in driver. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 1 - drivers/gpu/drm/i915/intel_display.c | 4 drivers/gpu/drm/i915/intel_pm.c | 2 -- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 04/10] drm/i915: Move out non-display related calls from display/modeset init/cleanup

, including gem/GT. Spec: 14370 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 86 ++-- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 28 ++--- drivers/gpu/drm/i915/intel_pm.c | 10 4 files

[Intel-gfx] [PATCH 02/10] drm/i915: Set PCH as NOP when display is disabled

() ... ... i915_driver_init_hw() intel_device_info_runtime_init() Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 07/10] drm/i915: Do not modifiy reserved bit in gens that do not have IPC

IPC was only added in SKL+(actually we don't even enable for SKL due WA) so without this change, driver was writing to a reserved bit. Also check for the WA in intel_init_ipc() to avoid further writes to ipc_enabled. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pm.c | 8

[Intel-gfx] [PATCH 10/10] drm/i915: Remove redundant checks for num_pipes == 0

This 'if's will always be false because of previous changes so let's drop then. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 12 +++- drivers/gpu/drm/i915/intel_audio.c | 3 --- drivers/gpu/drm/i915/intel_display.c | 3 --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 05/10] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()

i915_load_modeset_init() is a more suitable place than i915_driver_load() as vblank is part of modeset. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 03/10] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

Instead of have the same code spread into 4 platforms lets share it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++--- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b

[Intel-gfx] [PATCH 16/20] drm/i915: Do not initialize display clocks when display is disabled

cdclk and rawclk are the 2 display clocks that can now be completed not initialized when display is disabled. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 9 ++--- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++ 2 files changed, 9 insertions(+), 3

[Intel-gfx] [PATCH 07/20] drm/i915: Move FBC init and cleanup calls to modeset functions

in driver. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 1 - drivers/gpu/drm/i915/intel_display.c | 4 drivers/gpu/drm/i915/intel_pm.c | 2 -- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 15/20] drm/i915: Do not reset display when display is disabled

Display is disabled in the beginning of the reset and re-enabled afterreset each engine needed but if the display is disabled we should not do it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 17/20] drm/i915: Remove duplicated definition of intel_update_rawclk

A few line above we have another definition of intel_update_rawclk() keeping that one as the function is implemented in intel_cdclk.c. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_drv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b

[Intel-gfx] [PATCH 05/20] drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled

oad(). Also calling intel_display_set_init_power(false) in __intel_display_resume() as it would be executed by calling intel_modeset_setup_hw_state(). Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 drivers/gpu/drm/i915/intel_display.c | 8 +--- 2 fi

[Intel-gfx] [PATCH 20/20] drm/i915: Do not enable all power wells when display is disabled

is POWER_DOMAIN_GT_IRQ that is used by gem to inhibits DC power savings while using GT. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 8 +++- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++ 2 files changed, 17 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 10/20] drm/i915: Do not call modeset related functions when display is disabled

, this is a initial work. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 157 +++- drivers/gpu/drm/i915/i915_suspend.c | 24 ++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +- 3 files changed, 114 insertions(+), 70 deletions(-) diff

[Intel-gfx] [PATCH 12/20] drm/i915: Unset reset pch handshake when PCH is not present in one place

a different register and bits but with the same objective so moving it too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_gem.c | 12 drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git

[Intel-gfx] [PATCH 18/20] drm/i195: Do not initialize display core when display is disabled

enable. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 32 + 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 01e0c8e82fcf..8a84c77a1a88

[Intel-gfx] [PATCH 08/20] drm/i915: Do not modifiy reserved bit in gens that do not have IPC

IPC was only added in SKL+(actually we don't even enable for SKL due WA) so without this change, driver was writing to a reserved bit. Also check for the WA in intel_init_ipc() to avoid further writes to ipc_enabled. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pm.c | 8

[Intel-gfx] [PATCH 06/20] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()

i915_load_modeset_init() is a more suitable place than i915_driver_load() as vblank is part of modeset. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 11/20] drm/i915: Grab a runtime pm reference before run live selftests

device+0x2f5/0x470 So now grabbing and releasing a runtime pm reference around i915_live_selftests() call. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 04/20] drm/i915: Move out non-display related calls from display/modeset init/cleanup

, including gem/GT. Spec: 14370 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 86 ++-- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 28 ++--- drivers/gpu/drm/i915/intel_pm.c | 10 4 files

[Intel-gfx] [PATCH 19/20] drm/i915: Warn when display irq functions is executed when display is disabled

With previous patches any of this warnings shows up but lets add then so any other patch that breaks that can be caught by CI tests. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 14 ++ drivers/gpu/drm/i915/intel_hotplug.c | 2 ++ 2 files changed

[Intel-gfx] [PATCH 03/20] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

Instead of have the same code spread into 4 platforms lets share it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b

[Intel-gfx] [PATCH 01/20] drm: Let userspace check if driver supports modeset

to detect if display is enabled but it is a hackish way as it can fail for other reasons too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/drm_ioctl.c | 3 +++ include/uapi/drm/drm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled

() ... ... i915_driver_init_hw() intel_device_info_runtime_init() So now setting num_pipes = 0 earlier to avoid this problem. Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 5 + drivers/gpu/drm/i915/intel_device_info.c | 8

[Intel-gfx] [PATCH 14/20] drm/i915: Keep overlay functions naming consistent

All other overlay functions(almost all other functions in i915) follow intel_overlay_verb, so renaming the ones that do not match that. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 09/20] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()

IPC(Isochronous Priority Control not Inter-process communication btw) is a display feature, so i915_load_modeset_init() is the right place to initialize it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[Intel-gfx] [PATCH 13/20] drm/i915: Remove redundant checks for num_pipes == 0

This 'if's will always be false because of previous changes so let's drop then. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 12 +++- drivers/gpu/drm/i915/intel_audio.c | 3 --- drivers/gpu/drm/i915/intel_display.c | 3 --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 6/6] drm/i915: Remove redundante checks for num_pipes == 0

This 'if's will always be false because of previous changes. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 12 +++- drivers/gpu/drm/i915/intel_audio.c | 3 --- drivers/gpu/drm/i915/intel_display.c | 3 --- drivers/gpu/drm/i915/intel_i2c.c | 3

[Intel-gfx] [PATCH 5/6] drm/i915: Do not call modeset related functions when display is disabled

, this is a initial work. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 69 - 1 file changed, 41 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index aacb467fe3ea..e109815cfa51

[Intel-gfx] [PATCH 3/6] drm/i915: Move out non-modeset calls from modeset init and cleanup

i915_load_modeset_init() and intel_modeset_cleanup() was initializing and cleaning up things that is not modeset only. This will make easy initialize drive without display part. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 56

[Intel-gfx] [PATCH 1/6] drm: Let userspace check if driver supports modeset

GPU accelerators usually don't have display block or the display driver part can be disable when building driver(for servers it save some resources) so it is important let userspace check this capability too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/drm_ioctl.c | 3 +++ include

[Intel-gfx] [PATCH 2/6] drm/i915: Set PCH as NOP if display is disabled

() ... ... i915_driver_init_hw() intel_device_info_runtime_init() Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 4/6] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()

i915_load_modeset_init() is a more suitable place than i915_driver_load() as vblank is part of modeset API. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 19 +++ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS

Without this gem will not be able to turn off DC states to redunce interruption latency when no sink is being driven by driver. Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v6] drm/i915/skl+: Add and enable DP AUX CH mutex

-prm-osrc-skl-vol12-display.pdf Page 198 - AUX programming sequence Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-b

[Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- Changelog: v2 - removed the PSR dependency, now getting lock all the times when available - renamed functions to avoid nested calls - moved register bits right after the DP_AUX_CH_MUTEX() - removed 'drm/i915: keep AU

[Intel-gfx] [PATCH 2/6] drm/i915/psr: Tie PSR2 support to Y coordinate requirement in intel_psr_init_dpcd()

of VSC setup code that was handling a scenario that would never happen(PSR2 without Y coordinate). Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 6/6] drm/i915/psr: Enable aux frame sync in source

to avoid. Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 15 ++- 2 files cha

[Intel-gfx] [PATCH 4/6] drm/i915/psr: Do not override PSR2 sink support

. Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: José Roberto de Souza <jose.so...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i

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