[Intel-gfx] [PATCH v2 11/13] drm/i915/tgl: Add dkl phy pll calculations

Extending ICL mg calculations to also support dkl calculations. BSpec: 49204 Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 148 +++--- 2 files

[Intel-gfx] [PATCH v2 09/13] drm/i915/icl: Unify disable and enable phy clock gating functions

Adding a enable parameters allow us to share most of the code between enable and disable functions. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 71 1 file changed, 22 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 13/13] drm/i915/tgl: initialize TC and TBT ports

From: Lucas De Marchi Now that TC support was added, initialize DDIs. Signed-off-by: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2 06/13] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the bspec all the registers are read modify write. Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65

[Intel-gfx] [PATCH v2 05/13] drm/i915/tgl: Add initial dkl pll support

From: Lucas De Marchi The disable function can be the same as for MG phy since the same registers are used. The others are different as registers changed, also adding a empty dkl_pll_write() to be implemented later. v2: Setting the right HIP_INDEX_REG bits (José) Signed-off-by: José Roberto de

[Intel-gfx] [PATCH v2 04/13] drm/i915/tgl: Add dkl phy registers

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 162 1 file changed, 162 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ee5626579263..32f98d0e0e9c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH CI 6/6] drm/i915/tgl: Check the UC health of tc controllers after power on

New step added for TGL, required for us to check the TC microcontroller health after power on TC aux. BSpec: 49294 Reviewed-by: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display_power.c | 13 + 1 file changed, 13 insertions(+) diff

[Intel-gfx] [PATCH CI 2/6] drm/i915/tgl: Finish modular FIA support on registers

José Roberto de Souza --- .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_tc.c | 72 ++- drivers/gpu/drm/i915/i915_reg.h | 28 3 files changed, 53 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/di

[Intel-gfx] [PATCH CI 1/6] drm/i915/tgl: Add missing ddi clock select during DP init sequence

From: Clinton A Taylor Step 4.b was complete missed because it is only required to TC and TBT. Bspec: 49190 Reviewed-by: Imre Deak Reviewed-by: Lucas De Marchi Signed-off-by: Clinton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 - 1

[Intel-gfx] [PATCH CI 0/6] TGL TC enabling v2-CI

Patches from https://patchwork.freedesktop.org/series/66695/#rev2 that got rv-b and don't have dependencies over other patches, for CI testing. Clinton A Taylor (2): drm/i915/tgl: Add missing ddi clock select during DP init sequence drm/i915/tgl/pll: Set update_active_dpll José Rober

[Intel-gfx] [PATCH CI 5/6] drm/i915/icl: Unify disable and enable phy clock gating functions

Adding a enable parameters allow us to share most of the code between enable and disable functions. v3: Renamed icl_phy_clock_gating() to icl_phy_set_clock_gating() Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 73

[Intel-gfx] [PATCH CI 3/6] drm/i915/tgl/pll: Set update_active_dpll

ll modeset. Cc: Lucas De Marchi Cc: Imre Deak Reviewed-by: Lucas De Marchi Signed-off-by: Clinton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c

[Intel-gfx] [PATCH CI 4/6] drm/i915/tgl: Add dkl phy registers

: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 162 1 file changed, 162 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a6acda945e56..b82cf4725c05 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b

[Intel-gfx] [PATCH v3 7/9] drm/i915/tgl: Fix dkl link training

5 based on div2 value, that matches with dkl hardcoded table. So implementing this way as it proved to work in HW and leaving a comment so we know why it do not match BSpec. Issue reported on BSpec 49204. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c

[Intel-gfx] [PATCH v3 0/9] TGL TC enabling v3

, all noted in each patch. Clinton A Taylor (2): drm/i915/tgl: TC helper function to return pin mapping drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza (3): drm/i915/tgl: Add dkl phy pll calculations drm/i915/tgl: Fix dkl link training drm/i915/tgl: Return the mg/dkl

[Intel-gfx] [PATCH v3 5/9] drm/i915/tgl: re-indent code to prepare for DKL changes

From: Lucas De Marchi The final save operation into pll_state of the calculations done will be different for DKL PHY. Prepare for that by reindenting code so it's easier to check for correctness. This one has no change in behavior. Signed-off-by: Lucas De Marchi Signed-off-by: José Rober

[Intel-gfx] [PATCH v3 4/9] drm/i915/tgl: Add dkl phy programming sequences

if BSpec: 49292 BSpec: 49190 Signed-off-by: José Roberto de Souza Signed-off-by: Clinton A Taylor --- drivers/gpu/drm/i915/display/intel_ddi.c | 249 ++- 1 file changed, 240 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/

[Intel-gfx] [PATCH v3 9/9] drm/i915/tgl: initialize TC and TBT ports

From: Lucas De Marchi Now that TC support was added, initialize DDIs. Signed-off-by: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v3 2/9] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the bspec all the registers are read modify write. Reviewed-by: Lucas De Marchi Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 1/9] drm/i915/tgl: Add initial dkl pll support

Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 115 +- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v3 6/9] drm/i915/tgl: Add dkl phy pll calculations

Extending ICL mg calculations to also support dkl calculations. v3: Fixing iref_trim calculation for 38400 refclock BSpec: 49204 Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +--- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 3/9] drm/i915/tgl: TC helper function to return pin mapping

ton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 15 +++ drivers/gpu/drm/i915/display/intel_tc.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 5 + 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc

[Intel-gfx] [PATCH v3 8/9] drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports

TGL added 2 more TC ports that currently are not being handled by icl_pll_to_ddi_clk_sel(), so adding those. Cc: Lucas De Marchi Cc: Imre Deak Reported-by: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions

[Intel-gfx] [PATCH CI 3/6] drm/i915/tgl: TC helper function to return pin mapping

ton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 15 +++ drivers/gpu/drm/i915/display/intel_tc.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 5 + 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc

[Intel-gfx] [PATCH CI 5/6] drm/i915/tgl: Add dkl phy pll calculations

Extending ICL mg calculations to also support dkl calculations. v3: Fixing iref_trim calculation for 38400 refclock BSpec: 49204 Reviewed-by: Lucas De Marchi Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 29

[Intel-gfx] [PATCH CI 4/6] drm/i915/tgl: re-indent code to prepare for DKL changes

igned-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 119 ++ 1 file changed, 66 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 114116cdbf49..ce2dee3

[Intel-gfx] [PATCH CI 1/6] drm/i915/tgl: Add initial dkl pll support

registers of mg_pll_tdc_coldst_bias when getting hardware state Sharing mg_pll_enable() with TGL Reviewed-by: Imre Deak Acked-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 96 ++- 1 file

[Intel-gfx] [PATCH CI 2/6] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the bspec all the registers are read modify write. Reviewed-by: Lucas De Marchi Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH CI 6/6] drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports

TGL added 2 more TC ports that currently are not being handled by icl_pll_to_ddi_clk_sel(), so adding those. Reviewed-by: Lucas De Marchi Cc: Lucas De Marchi Cc: Imre Deak Reported-by: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file

[Intel-gfx] [PATCH 2/2] drm/i915: Add new ICL PCI ID

A new PCI ID for ICL was added to BSpec, lets keep it in tight sync as ICL is not protected by the alpha support flag anymore. BSepc: 21141 Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- include/drm/i915_pciids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm

[Intel-gfx] [PATCH 1/2] drm/i915: Sort ICL PCI IDs

Lets keep it sorted to make easy to spot missing PCI IDs. Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- include/drm/i915_pciids.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index

[Intel-gfx] [PATCH v6 2/9] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset

expected behavior or not but in the mean time this fix the issue. Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [PATCH v6 3/9] drm/i915: Compute and commit color features in fastsets

. Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v6 6/9] drm/i915: Disable PSR2 while getting pipe CRC

c_prepare() and crc_enabled, only setting mode_changed if it can do PSR. v2: Changed commit description to describe that PSR2 inhibit CRC calculations. Cc: Ville Syrjälä Reviewed-by: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH v6 9/9] drm/i915: Enable PSR2 by default

Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 053dbba6abde..7bab6a009e0d 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v6 7/9] drm/i915: Drop redundant checks to update PSR state

All of this checks are redudant and can be removed as the if bellow already takes care when there is no changes in the state. Reviewed-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 12 1 file changed

[Intel-gfx] [PATCH v6 5/9] drm/i915/crc: Make IPS workaround generic

changes to the functions that prepares the commit (Ville) Cc: Ville Syrjälä Reviewed-by: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 10 -- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v6 1/9] drm/i915/psr: Remove PSR2 FIXME

Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v6 8/9] drm/i915: Force PSR1 exit when getting pipe CRC

IL +17 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-kbl: PASS -> DMESG-FAIL +12 * igt@kms_pipe_crc_basic@read-crc-pipe-c: - shard-kbl: PASS -> FAIL +7 v6: s/PSR/PSR1 (Dhinakaran) Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: Jos

[Intel-gfx] [PATCH v6 4/9] drm/i915/psr: Drop test for EDP in CRTC when forcing commit

If has_psr is set it means that CRTC has a EDP panel attached so the EDP check is redundant and can be dropped. Cc: Ville Syrjälä Reviewed-by: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 4 +--- 1 file changed, 1

[Intel-gfx] [PATCH v2] drm/i915: Add new ICL PCI ID

A new PCI ID for ICL was added to BSpec, lets keep it in tight sync as ICL is not protected by the alpha support flag anymore. v2: Keeping BSpec order(Rodrigo) BSepc: 21141 Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- include/drm/i915_pciids.h | 3 ++- 1 file changed, 2

[Intel-gfx] [PATCH v4 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1

n Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87123861e41e..9b69cec21

[Intel-gfx] [PATCH v4 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 25 + drivers/gpu/drm/i915/intel_psr.c | 8 drivers/gpu/drm/i915/intel_vbt_defs.h | 3 +++ 4 files changed, 33

[Intel-gfx] [PATCH v4 2/3] drm/i915/psr: Move logic to get TPS registers values to another function

: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 57 ++-- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index f534d2aa6406..813be3b81bdc 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

previous mode that is not compatible with PSR2. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 2/2] drm/i915: Enable hotplug retry

would sink signal a long pulse if there is no change? Also the drawback of running the hotplug handler again is really low and that could fix another cases that we are not aware. Cc: Ville Syrjälä Cc: Imre Deak Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915: Add support for retrying hotplug

From: Imre Deak There is some scenarios that we are aware that sink probe can fail, so lets add the infrastructure to let hotplug() hook to request another probe after some time. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Imre Deak

[Intel-gfx] [PATCH v2] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

and comment to state that it may be a DMC firmware issue (Rodrigo) - No need to RMW, let's write 0 to PSR_CTL(Dhinakaran) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 8 1 file changed, 8 insertions(+) diff --

[Intel-gfx] [PATCH] drm/i915: Drop platform_mask

We don't have any platform that is composed by 2 or more platforms so we don't need a mask, lets drop it and remove the actual limit of 32 platforms. Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 2 -- drivers/gpu/drm/i915/

[Intel-gfx] [PATCH v2 1/2] drm/i915: Add support for retrying hotplug

From: Imre Deak There is some scenarios that we are aware that sink probe can fail, so lets add the infrastructure to let hotplug() hook to request another probe after some time. v2: Handle shared HPD pins (Imre) Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Jani

[Intel-gfx] [PATCH v2 2/2] drm/i915: Enable hotplug retry

to chamelium boards that will be used to simulate the issues reported in here. v2: Also retrying for old DP ports(non-DDI)(Imre) Cc: Ville Syrjälä Cc: Imre Deak Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 21 + drivers/gpu

[Intel-gfx] [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct

Lets keep all PSR variables packed in this struct. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/i915_reg.h | 12 ++-- drivers/gpu/drm/i915/intel_psr.c | 2 +- 3 files changed, 8

[Intel-gfx] [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders

PSR is only support in eDP transcoder and there is only one instance of it, so lets drop all of this code. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147

[Intel-gfx] [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs

This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers

PSR support for VLV and CHV was dropped in commit ce3508fd2a77 ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep this registers around. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines into several lines. No behavior changes intended here. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 63 +++-- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a

[Intel-gfx] [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset

register added is this one(PSR_CTL). Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 23 +++ drivers

[Intel-gfx] [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reload and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base

Right now it have a mix of PSR registers that are relative to PSR mmio base and other register with a hardcoded address, lets keep it consistented and have it all relative to mmio base. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Add not fenceable reason to not enable FBC

?id=108040 Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_fbc.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 656e684e7c9a..2980a3b579e0 100644 --- a/

[Intel-gfx] [PATCH] drm/i915/icl: Fix VEBOX mismatch BUG_ON()

5! BSpec: 20680 Fixes: 9511cb6481af ("drm/i915: Adding missing '; ' to ENGINE_INSTANCES") Fixes: 26376a7e74d2 ("drm/i915/icl: Check for fused-off VDBOX and VEBOX instances") Cc: Chris Wilson Cc: Tvrtko Ursulin Cc: Oscar Mateo Signed-off-by: José Roberto de Sou

[Intel-gfx] [PATCH] drm/i915/ehl: Add missing VECS engine

EHL can have up to one VECS(video enhancement) engine, so add it to the device_info. BSpec: 29152 Cc: Rodrigo Vivi Cc: Bob Paauwe Cc: Matt Roper Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[Intel-gfx] [PATCH] drm/i915/psr: Force manual PSR exit in older gens

Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 36 +--- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1

From: Vandita Kulkarni EHL has 2 additional steps in the DSI sequence, this is one of then the lane latency optimization for DW1. BSpec: 20597 Cc: Uma Shankar Cc: Rodrigo Vivi Cc: Jani Nikula Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++ driver

[Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap

The other additional step in the DSI sequqence for EHL. BSpec: 20597 Cc: Uma Shankar Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/icl_dsi.c | 8 drivers/gpu/drm/i915/i915_reg.h| 4 2 files changed, 12 insertions(+) diff --git a

[Intel-gfx] [PATCH 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 1/3] drm/i915/icl: Add new supported CD clocks

not reading it. BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 29 +++--- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu

[Intel-gfx] [PATCH 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 -- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH v6 3/4] drm/i915/psr: Make PSR registers relative to transcoders

Nikula Cc: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 89 +--- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_debugfs.c | 18 +++-- drivers/gpu/drm/i915/i915_drv.h | 3 +

[Intel-gfx] [PATCH v6 4/4] drm/i915: Add transcoder restriction to PSR2

Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ed422b788d88..da56b8b1b9b9 100644 --- a/drivers

[Intel-gfx] [PATCH v6 2/4] drm/i915: Add _TRANS2()

: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d98142940c38..4fc8dc083766

[Intel-gfx] [PATCH v6 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 45 ++--- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b2e27b5b0df9..14b0933809d8 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1

From: Vandita Kulkarni EHL has 2 additional steps in the DSI sequence, this is one of then the lane latency optimization for DW1. BSpec: 20597 Cc: Uma Shankar Cc: Rodrigo Vivi Cc: Jani Nikula Reviewed-by: Matt Roper Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c

[Intel-gfx] [PATCH v2 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap

The other additional step in the DSI sequence for EHL. v2: - Using REG_BIT()(Matt) - Fixed commit message typo(Vandita) BSpec: 20597 Cc: Uma Shankar Cc: Jani Nikula Reviewed-by: Vandita Kulkarni Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. v2: - Limiting maximum CD clock by max_cdclk_freq instead of remove it from icl_calc_cdclk()(Ville and Jani) BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++ 1 file changed, 23 insertions(+), 12 deletions

[Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks

not reading it. BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v3 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. v2: - Limiting maximum CD clock by max_cdclk_freq instead of remove it from icl_calc_cdclk()(Ville and Jani) BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Cc: Jani Nikula Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v3 1/3] drm/i915/icl: Add new supported CD clocks

not reading it. v3: - making icl clock arrays static (Ville) BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Cc: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--- 1 file changed, 21 insertions

[Intel-gfx] [PATCH v3 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++ 1 file changed, 23

[Intel-gfx] [PATCH v3 1/2] drm/i915: Add support for retrying hotplug

From: Imre Deak There is some scenarios that we are aware that sink probe can fail, so lets add the infrastructure to let hotplug() hook to request another probe after some time. v2: Handle shared HPD pins (Imre) v3: Rebased Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off

[Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry

to chamelium boards that will be used to simulate the issues reported in here. v2: Also retrying for old DP ports(non-DDI)(Imre) Cc: Ville Syrjälä Cc: Imre Deak Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 + drivers

[Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug

it consistent(Rodrigo) Cc: Ville Syrjälä Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++-- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 2/2] drm/i915: Enable hotplug retry

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++ drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++- 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a

[Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off

calling i915_gem_suspend() and by consequence i915_gem_drain_freed_objects() only after display is down making sure all buffers are freed. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH] drm: i915: fix a possible refcount leak in intel_dp_add_mst_connector()

ned-off-by: Hangyu Hua Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 061b277e5ce78..14d2a64193b2d 100644 --- a/drive

[Intel-gfx] [PATCH] drm/i915: Drain freed object after suspend display

issues. So here draining all freed objects released by display fixing suspend issues. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_driver.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index

[Intel-gfx] [PATCH] drm/i915/display/ehl: Update voltage swing table

EHL table was recently updated with some minor fixes. BSpec: 21257 Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH] drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence

TC voltage swing programming sequence was updated with a new step. BSpec: 54956 Cc: sta...@vger.kernel.org Cc: Jani Nikula Cc: Clint Taylor Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 22 ++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915/display: Fix HPD short pulse handling for eDP

fixed and fixing the check for what it is intended. Fixes: 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel powered off") Cc: Anshuman Gupta Cc: Jani Nikula Cc: Uma Shankar Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp.c

[Intel-gfx] [PATCH 2/2] drm/i915/display: Do not re-enable PSR after it was marked as not reliable

the next modeset where has_psr will be set false. v2: - release psr lock before continue Fixes: 9ce5884e5139 ("drm/i915/display: Only keep PSR enabled if there is active planes") Reported-by: Khaled Almahallawy Reported-by: Charlton Lin Cc: Jouni Högander Signed-off-by: José Robert

[Intel-gfx] [PATCH v2 1/2] drm/i915/display: Fix HPD short pulse handling for eDP

ed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_pps.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pps.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/d

[Intel-gfx] [PATCH v2 2/2] drm/i915/display: Do not re-enable PSR after it was marked as not reliable

the next modeset where has_psr will be set false. v2: - release psr lock before continue Fixes: 9ce5884e5139 ("drm/i915/display: Only keep PSR enabled if there is active planes") Reported-by: Khaled Almahallawy Reported-by: Charlton Lin Cc: Jouni Högander Signed-off-by: José Robert

[Intel-gfx] [PATCH] drm/i915/display/adlp: Update eDP voltage swing table

Up to now alderlake-p was using the same eDP voltage swing table for frequencies up to HBR2 as icelake but now it has its own table. BSpec: 49291 Cc: Clinton A Taylor Signed-off-by: José Roberto de Souza --- .../gpu/drm/i915/display/intel_ddi_buf_trans.c | 18 -- 1 file changed

[Intel-gfx] [PATCH] drm/i915/display/adlp: More voltage swing table updates

A few more updates in the alderlake-P voltage swing tables. eDP HBR3 table was the same as icelake one but now it has changes for voltage 0 and pre-emphasis 2 line. And DP tables also had one line change in each. Bspec: 49291 Signed-off-by: José Roberto de Souza --- .../drm/i915/display

[Intel-gfx] [PATCH 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

43 Cc: Matt Roper Cc: Stanislav Lisovskiy Signed-off-by: Caz Yokoyama Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gp

[Intel-gfx] [PATCH 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

uired by specification. BSpec: 49213 BSpec: 50343 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 36 + drivers/gpu/drm/i915/intel_pm.c | 55 +++- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 2/3] drm/i915/display: Add HAS_MBUS_JOINING

This will make easy to extend MBUS joining support to future platforms that also supports this feature. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a

[Intel-gfx] [PATCH v2 1/4] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Cc: Jani Nikula Signed-off-by: Caz Yokoyama Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/di

[Intel-gfx] [PATCH v2 3/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

modeset - remove the checks to wait a vblank BSpec: 49213 BSpec: 50343 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 37 +-- drivers/gpu/drm/i915/intel_pm.c | 47 drivers

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