From BDW+ most of the PSR registers is relative to eDP transcoder offset just PSR_IMR/IIR that have a fixed address, so lets set mmio_base with the transcoder offset and adjust all the others macros to the registers.
Also removing BDW_EDP_PSR_BASE from GVT because it is not used as the only PSR register added is this one(PSR_CTL). Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Zhi Wang <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++------------ drivers/gpu/drm/i915/intel_psr.c | 9 ++++++--- 4 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index b596cb42e24e..8163fef720bb 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2739,7 +2739,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); MMIO_D(WM_MISC, D_BDW); - MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5f60ad4d4296..4fc5ef568ef0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -511,6 +511,7 @@ struct i915_psr { bool enabled; struct intel_dp *dp; enum pipe pipe; + enum transcoder transcoder; bool active; struct work_struct work; unsigned busy_frontbuffer_bits; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e1ed2ba1c315..3c382aee2fec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4246,9 +4246,8 @@ enum { #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) /* HSW+ eDP PSR registers */ -#define HSW_EDP_PSR_BASE 0x64800 -#define BDW_EDP_PSR_BASE 0x6f800 -#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0) +#define HSW_EDP_PSR_BASE 0x64000 +#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0x800) #define EDP_PSR_ENABLE (1 << 31) #define BDW_PSR_SINGLE_FRAME (1 << 30) #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ @@ -4281,16 +4280,16 @@ enum { #define EDP_PSR_POST_EXIT (1 << 1) #define EDP_PSR_PRE_ENTRY (1 << 0) -#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr.mmio_base + 0x10) +#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr.mmio_base + 0x810) #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */ +#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x814 + (i) * 4) /* 5 registers */ -#define EDP_PSR_STATUS _MMIO(dev_priv->psr.mmio_base + 0x40) +#define EDP_PSR_STATUS _MMIO(dev_priv->psr.mmio_base + 0x840) #define EDP_PSR_STATUS_STATE_MASK (7 << 29) #define EDP_PSR_STATUS_STATE_SHIFT 29 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) @@ -4315,10 +4314,10 @@ enum { #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) #define EDP_PSR_STATUS_IDLE_MASK 0xf -#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr.mmio_base + 0x44) +#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr.mmio_base + 0x844) #define EDP_PSR_PERF_CNT_MASK 0xffffff -#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */ +#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x860) /* PSR_MASK on SKL+ */ #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) @@ -4326,7 +4325,7 @@ enum { #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ -#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x100) +#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x900) #define EDP_PSR2_ENABLE (1 << 31) #define EDP_SU_TRACK_ENABLE (1 << 30) #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ @@ -4344,7 +4343,7 @@ enum { #define EDP_PSR2_IDLE_FRAME_MASK 0xf #define EDP_PSR2_IDLE_FRAME_SHIFT 0 -#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x48) +#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x848) #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) #define PSR_EVENT_PSR2_DISABLED (1 << 16) #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) @@ -4362,11 +4361,11 @@ enum { #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) #define PSR_EVENT_PSR_DISABLE (1 << 0) -#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x140) +#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x940) #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) #define EDP_PSR2_STATUS_STATE_SHIFT 28 -#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x114 + (index) * 4) +#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x914 + (index) * 4) #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3)) #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 3bf887ef8573..5fee494cd9e9 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -671,6 +671,12 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; + dev_priv->psr.transcoder = crtc_state->cpu_transcoder; + + if (IS_HASWELL(dev_priv)) + dev_priv->psr.mmio_base = HSW_EDP_PSR_BASE; + else + dev_priv->psr.mmio_base = INTEL_INFO(dev_priv)->trans_offsets[dev_priv->psr.transcoder]; DRM_DEBUG_KMS("Enabling PSR%s\n", dev_priv->psr.psr2_enabled ? "2" : "1"); @@ -1135,9 +1141,6 @@ void intel_psr_init(struct drm_i915_private *dev_priv) if (!HAS_PSR(dev_priv)) return; - dev_priv->psr.mmio_base = IS_HASWELL(dev_priv) ? - HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; - if (!dev_priv->psr.sink_support) return; -- 2.21.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
