[Intel-gfx] [PATCH 1/2] drm/i915/hotplug: Move iteration over connectors to other function

The next patch will need to a second iteration over connectors so moving it to a function, no behavior changes intended here. While at it moving intel_connector and intel_encoder to inside of the block that actually uses it. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Probe again type-c connectors that failed

every type-c connector that failed in the initial probe. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_hotplug.c | 39 +++- 3 files changed, 37

[Intel-gfx] [PATCH v3] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

: Handling missing case: disabled to PSR1 v3: Not duplicating the whole atomic state(Maarten) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_ddi.c| 2

[Intel-gfx] [PATCH v2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

: Handling missing case: disabled to PSR1 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- Should I add IGT tests to test every state switch combination? drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/4] drm/i915/psr: Remove PSR2 FIXME

Now we are only checking sink capabilities when probing PSR DPCD register and then dynamically checking in intel_psr2_config_valid() to make sure the current modeset and features enables are compatible with PSR2. So this FIXME can be dropped. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto

[Intel-gfx] [PATCH 2/4] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reload and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 1

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Print why PSR or PSR2 was not enabled in debugfs

PSR2 reason even if PSR1 is enabled as PSR2 have some additional requirements. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c| 13

[Intel-gfx] [PATCH 3/4] drm/psr: Do not enable PSR when a interlaced mode set for all gens

This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH v3 4/5] drm/i915: Make PSR registers relative to transcoders

: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 +-- drivers/gpu/drm/i915/i915_reg.h | 52 - drivers/gpu/drm/i915/intel_psr.c| 11

[Intel-gfx] [PATCH v3 2/5] drm/i915/psr: Remove partial PSR support on multiple transcoders

Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147 --- 2 files changed, 42 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu

[Intel-gfx] [PATCH v3 5/5] drm/i915: Add transcoder parameter to PSR registers macros

Lets make PSR register macros explicit about what transcoder is used to calculate the register offset. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ drivers/gpu/drm/i915/i915_reg.h | 26

[Intel-gfx] [PATCH v3 1/5] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v3 3/5] drm/i915: Add _TRANS2()

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2803b120b6d..36420af2cd6f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu

[Intel-gfx] [PATCH v4 3/4] drm/i915: Make PSR registers relative to transcoders

: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 +-- drivers/gpu/drm/i915/i915_reg.h | 48 - drivers/gpu/drm/i915/intel_psr.c| 11 +-- 4 files changed, 45

[Intel-gfx] [PATCH v4 4/4] drm/i915: Add transcoder parameter to PSR registers macros

Lets make PSR register macros explicit about what transcoder is used to calculate the register offset. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ drivers/gpu/drm/i915/i915_reg.h | 24

[Intel-gfx] [PATCH v4 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v4 2/4] drm/i915: Add _TRANS2()

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b74824f0b5b1..9ef306b79e0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu

[Intel-gfx] [PATCH v2 2/3] drm/i915/psr: Remove partial PSR support on multiple transcoders

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147 --- 2 files changed, 42 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH v2 1/3] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 3/3] drm/i915: Make PSR registers relative to transcoders

: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_reg.h | 59 - drivers/gpu/drm/i915/intel_psr.c| 11

[Intel-gfx] [PATCH] drm/i915/ehl: Add missing VECS engine

EHL can have up to one VECS(video enhancement) engine, so add it to the device_info. BSpec: 29152 Cc: Rodrigo Vivi Cc: Bob Paauwe Cc: Matt Roper Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[Intel-gfx] [PATCH] drm/i915/psr: Force manual PSR exit in older gens

Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 36 +--- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap

The other additional step in the DSI sequqence for EHL. BSpec: 20597 Cc: Uma Shankar Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/icl_dsi.c | 8 drivers/gpu/drm/i915/i915_reg.h| 4 2 files changed, 12 insertions(+) diff --git

[Intel-gfx] [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1

From: Vandita Kulkarni EHL has 2 additional steps in the DSI sequence, this is one of then the lane latency optimization for DW1. BSpec: 20597 Cc: Uma Shankar Cc: Rodrigo Vivi Cc: Jani Nikula Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++

[Intel-gfx] [PATCH 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 -- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 1/3] drm/i915/icl: Add new supported CD clocks

are not reading it. BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 29 +++--- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu

[Intel-gfx] [PATCH v6 3/4] drm/i915/psr: Make PSR registers relative to transcoders

lle Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 89 +--- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_debugfs.c | 18 +++-- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/

[Intel-gfx] [PATCH v6 4/4] drm/i915: Add transcoder restriction to PSR2

Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ed422b788d88..da56b8b1b9b9 100644 --- a/drivers

[Intel-gfx] [PATCH v6 2/4] drm/i915: Add _TRANS2()

: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d98142940c38..4fc8dc083766

[Intel-gfx] [PATCH v6 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 45 ++--- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b2e27b5b0df9..14b0933809d8 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap

The other additional step in the DSI sequence for EHL. v2: - Using REG_BIT()(Matt) - Fixed commit message typo(Vandita) BSpec: 20597 Cc: Uma Shankar Cc: Jani Nikula Reviewed-by: Vandita Kulkarni Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1

From: Vandita Kulkarni EHL has 2 additional steps in the DSI sequence, this is one of then the lane latency optimization for DW1. BSpec: 20597 Cc: Uma Shankar Cc: Rodrigo Vivi Cc: Jani Nikula Reviewed-by: Matt Roper Signed-off-by: Vandita Kulkarni ---

[Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++ 1 file changed, 23 insertions(+), 12 deletions

[Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks

are not reading it. BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. v2: - Limiting maximum CD clock by max_cdclk_freq instead of remove it from icl_calc_cdclk()(Ville and Jani) BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v5 3/3] drm/i915: Make PSR registers relative to transcoders

hed with the patch that added the tran parameter to the macros (Dhinakaran) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_debugfs.c |

[Intel-gfx] [PATCH v5 1/3] drm/i915/bdw+: Move misc display IRQ handling to it own function

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 45 ++--- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b92cfd69134b..a1299f10ed49 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH v5 2/3] drm/i915: Add _TRANS2()

: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b74824f0b5b1..31163415479d

[Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug

it consistent(Rodrigo) Cc: Ville Syrjälä Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++-- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 2/2] drm/i915: Enable hotplug retry

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++ drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++- 3 files changed, 55 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH v5 2/2] drm/i915: Enable hotplug retry

Reviewed-by: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++ drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++- 3 files changed, 55 insertions(+), 1

[Intel-gfx] [PATCH v5 1/2] drm/i915: Add support for retrying hotplug

it consistent(Rodrigo) v5: Making the working queue used explicit through all the callers to hotplug_work (Ville) Tested-by: Timo Aaltonen Cc: Ville Syrjälä Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm

[Intel-gfx] [PATCH v3 2/3] drm/i915/ehl: Remove unsupported cd clocks

EHL do not support 648 and 652.8 MHz. v2: - Limiting maximum CD clock by max_cdclk_freq instead of remove it from icl_calc_cdclk()(Ville and Jani) BSpec: 20598 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Cc: Jani Nikula Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v3 1/3] drm/i915/icl: Add new supported CD clocks

are not reading it. v3: - making icl clock arrays static (Ville) BSpec: 20598 BSpec: 15729 Cc: Clint Taylor Cc: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++--- 1 file changed, 21 insertions

[Intel-gfx] [PATCH v3 3/3] drm/i915/ehl: Add voltage level requirement table

EHL has it own voltage level requirement depending on cd clock. BSpec: 21809 Cc: Clint Taylor Cc: Matt Roper Cc: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++ 1 file changed, 23

[Intel-gfx] [PATCH v3 1/2] drm/i915: Add support for retrying hotplug

From: Imre Deak There is some scenarios that we are aware that sink probe can fail, so lets add the infrastructure to let hotplug() hook to request another probe after some time. v2: Handle shared HPD pins (Imre) v3: Rebased Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off

[Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry

to chamelium boards that will be used to simulate the issues reported in here. v2: Also retrying for old DP ports(non-DDI)(Imre) Cc: Ville Syrjälä Cc: Imre Deak Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 + drivers

[Intel-gfx] [PATCH] drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT

In this case we want to apply the mask and then shift so the parentheses is needed. SPANK! SPANK! SPANK! Naughty programmer! Fixes: 9749a5b6c09f ("drm/i915/tgl: Fix the read of the DDI that transcoder is attached to") Cc: Lucas De Marchi Cc: Chris Wilson Signed-off-by: José Robert

[Intel-gfx] [PATCH v3 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 3 +-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c

[Intel-gfx] [PATCH v2 1/2] drm/i915: Get transcoder power domain before reading its register

is kept off and reading other transcoders registers would cause a unclaimed read warning. So here getting the power domain of the transcoder only if it is enabled, otherwise it is not connected to the DDI. Reviewed-by: Lucas De Marchi Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to

On TGL this register do not map directly to port, it was already handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when reading it. v2: Adding TGL_PORT_TRANS_DDI_SELECT() so all future users can reuse it (Lucas) Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers

[Intel-gfx] [PATCH] drm/connector: Allow max possible encoders to attach to a connector

...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: nouv...@lists.freedesktop.org Cc: amd-...@lists.freedesktop.org Signed-off-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +- drivers/gpu/drm/amd/amdgpu/dce_virtual.c

[Intel-gfx] [PATCH v8 1/3] drm/i915/psr: Make PSR registers relative to transcoders

v7: - Removing IS_HASWELL() from registers macros(Jani) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Zhi Wang Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c |

[Intel-gfx] [PATCH v8 2/3] drm/i915: Add transcoder restriction to PSR2

v8: Renamed _psr2_supported_in_trans() to psr2_supported() (Lucas) BSpec: 7713 BSpec: 20584 Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++

[Intel-gfx] [PATCH v8 3/3] drm/i915: Do not unmask PSR interruption in IRQ postinstall

No need to unmask PSR interrutpion if PSR is not enabled, better move the call to intel_psr_enable_source(). v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi

[Intel-gfx] [PATCH v2] drm/i915/tgl: Implement TGL DisplayPort training sequence

: Maarten Lankhorst Cc: Manasi Navare Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_ddi.c | 138 ++- drivers/gpu/drm/i915/display/intel_dp.c | 8 +- 2 files changed, 138 insertions(+), 8

[Intel-gfx] [PATCH 2/4] drm/i915: unify icp, tgp and mcc irq handling

From: Lucas De Marchi The differences are only on the pins, trigger and long_detect function. The MCC handling is already partially merged, so merge TGP as well. Remove the pins argument from icp_irq_handler() so we have all the differences between the 3 set in a common if ladder.

[Intel-gfx] [PATCH 1/4] drm/i915: parameterize south hpd macros

From: Lucas De Marchi South, follow the north. Instead of defining separate macros for each port, make them take port as parameter as done for TC ports and for north engine. This will allow us to easily extend this as needed. tgp_ddi_port_hotplug_long_detect() is also removed as after the EHL

[Intel-gfx] [PATCH 3/4] drm/i915: parameterize SDE hotplug registers

From: Lucas De Marchi Ice Lake, Tiger Lake and Elkhart Lake all have different port configurations and all of them can be parameterized the same way to form the SDE hotplug bitmask. Avoid making them a special case an just use the parameterized macros. Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH 4/4] drm/i915: unify icp, tgp and mcc irq setup

From: Lucas De Marchi Use a single function to setup the SDE irq and make MCC, ICP and TGP use it, just like was done for the irq handler. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_irq.c | 50 ++--- 1 file changed, 21 insertions(+), 29

[Intel-gfx] [PATCH v2.1] drm/connector: Allow max possible encoders to attach to a connector

: Ville Syrjälä Cc: Alex Deucher Cc: dri-de...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: nouv...@lists.freedesktop.org Cc: amd-...@lists.freedesktop.org Signed-off-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c

[Intel-gfx] [PATCH v2] drm/connector: Allow max possible encoders to attach to a connector

: Ville Syrjälä Cc: Alex Deucher Cc: dri-de...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: nouv...@lists.freedesktop.org Cc: amd-...@lists.freedesktop.org Signed-off-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c

[Intel-gfx] [PATCH 1/2] drm/i915: Apply FBC WA for TGL too

WA 1409120013 is also valid for TGL, so lets check for ">= 11". BSpec: 52890 Cc: Matt Roper Cc: Clinton Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH 2/2] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect

inging this patch back for now. Cc: Lucas De Marchi Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp

[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Finish modular FIA support on registers

but testing in real hardware have proven that it had moved for all other registers too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 2 + drivers/gpu/drm/i915/display/intel_tc.c | 52 drivers/gpu/drm/i915/display/intel_tc.h

[Intel-gfx] [PATCH 4/4] drm/i915/tgl: Fix driver crash when update_active_dpll is called

From: "Taylor, Clinton A" TGL PLL function table doesn't include and update_active_pll function. The driver attempts to make a call to this function and crashes during PLL changes. Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 1 file changed, 1

[Intel-gfx] [PATCH 2/4] drm/i915/tgl: TC helper function to return pin mapping

From: "Taylor, Clinton A" Add a helper function to return pin map for use during dkl phy DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it. The user of this function will come in future TC patches. Signed-off-by: Taylor, Clinton A ---

[Intel-gfx] [PATCH 1/4] drm/i915/tgl: Add missing ddi clock select during DP init sequence

From: "Taylor, Clinton A" Step 4.b was complete missed because it is only required to TC and TBT. Bspec: 49190 Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 2/2] drm/connector: Allow max possible encoders to attach to a connector

Pandiyan Signed-off-by: José Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++- drivers/gpu/drm/drm_client_modeset.c | 3 +- drivers/gpu/drm

[Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

() that was renamed in commit 297e30b5d9b6 ("drm/atomic-helper: Unexport drm_atomic_helper_best_encoder"). Suggested-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Daniel Vetter Cc: Laurent Pinchart Cc: dri-de...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Signed-off-by: José

[Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

Cc: dri-de...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/ast/ast_mode.c | 12 drivers/gpu/drm/drm_atomic_helper.c| 15 ++- drivers/gpu/drm/drm_crtc_helper.c | 17 - drive

[Intel-gfx] [PATCH 2/2] drm/connector: Allow max possible encoders to attach to a connector

Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 - drivers/gpu/drm/drm_client_modeset.c | 3 +- drivers/gpu/drm/drm_connector.c

[Intel-gfx] [PATCH 5/6] drm/i915/tgl: disable SAGV temporarily

From: Lucas De Marchi SAGV is not currently working for Tiger Lake. We better disable it until the implementation is stabilized and we can enable it. HSDES: 1409542895 2208191909 Signed-off-by: Lucas De Marchi Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pm.c | 4

[Intel-gfx] [PATCH 6/6] drm/i915/tgl: add gen12 to stolen initialization

From: Lucas De Marchi Add case for gen == 12 and add MISSING_CASE() for future gens. We were already handling gen12 as the default, so this doesn't change the current behavior. BSpec: 19481 and 44980 Cc: CQ Tang Signed-off-by: Lucas De Marchi Reviewed-by: José Roberto de Souza Reviewed

[Intel-gfx] [PATCH 2/6] drm/i915/tgl: Access the right register when handling PSR interruptions

g the bits offsets: it will be 0 for gen12+ and psr.transcoder otherwise. v2 (Lucas): change the implementation to use trans_shift instead of getting each bit value with a different macro Cc: Imre Deak Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza Signed-off-by

[Intel-gfx] [PATCH 4/6] drm/i915/tgl: move DP_TP_* to transcoder

toring the register directly made it cleaner. Cc: Matt Roper Cc: Ville Syrjälä Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 --- .../drm/i915/display/intel_display_types.h

[Intel-gfx] [PATCH 1/6] drm/i915/psr: Only handle interruptions of the transcoder in use

: Imre Deak Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_psr.c | 142 +-- drivers/gpu/drm/i915/i915_reg.h | 13 +-- 2 files changed, 60 insertions(+), 95

[Intel-gfx] [PATCH 0/6] Tiger Lake batch 3.5 v2

6 of 7 patches from https://patchwork.freedesktop.org/series/65982/ with Reviewed-by added and comments addressed. Just missing a Reviewed-by on "drm/i915: protect access to DP_TP_* on non-dp". José Roberto de Souza (2): drm/i915/psr: Only handle interruptions of the transcoder in

[Intel-gfx] [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp

From: Lucas De Marchi DP_TP_{CTL,STATUS} should only be programmed when the encoder is intel_dp. Checking its current usages intel_disable_ddi_buf() is the only offender, with other places being protected by checks like pipe_config->fec_enable that is only set by intel_dp. v3 (José): - Using

[Intel-gfx] [PATCH v2 00/13] TGL TC enabling v2

/i915/tgl: Add dkl phy programming sequences José Roberto de Souza (5): drm/i915/tgl: Finish modular FIA support on registers drm/i915/icl: Unify disable and enable phy clock gating functions drm/i915/tgl: Check the UC health of tc controllers after power on drm/i915/tgl: Add dkl phy pll

[Intel-gfx] [PATCH v2 01/13] drm/i915/tgl: Add missing ddi clock select during DP init sequence

From: Clinton A Taylor Step 4.b was complete missed because it is only required to TC and TBT. Bspec: 49190 Signed-off-by: Clinton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH v2 02/13] drm/i915/tgl: Finish modular FIA support on registers

but testing in real hardware have proven that it had moved for all other registers too. v2: - Caching index in tc_phy_fia_idx, instead of calculate it each time Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 03/13] drm/i915/tgl/pll: Set update_active_dpll

ll modeset. Cc: Lucas De Marchi Cc: Imre Deak Signed-off-by: Clinton A Taylor Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH v2 12/13] drm/i915/tgl: Fix dkl link training

or 5 based on div2 value, that matches with dkl hardcoded table. So implementing this way as it proved to work in HW and leaving a comment so we know why it do not match BSpec. Issue reported on BSpec 49204. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c

[Intel-gfx] [PATCH v2 07/13] drm/i915/tgl: TC helper function to return pin mapping

From: Clinton A Taylor Add a helper function to return pin map for use during dkl phy DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it. The user of this function will come in future TC patches. Signed-off-by: Clinton A Taylor Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v2 10/13] drm/i915/tgl: Check the UC health of tc controllers after power on

New step added for TGL, required for us to check the TC microcontroller health after power on TC aux. BSpec: 49294 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display_power.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 08/13] drm/i915/tgl: Add dkl phy programming sequences

causes all the following trainings to fail so not enabling it for. v2: Setting the right HIP_INDEX_REG bits (José) BSpec: 49292 BSpec: 49190 Signed-off-by: José Roberto de Souza Signed-off-by: Clinton A Taylor --- drivers/gpu/drm/i915/display/intel_ddi.c | 246 +-- 1 file ch

[Intel-gfx] [PATCH v2 11/13] drm/i915/tgl: Add dkl phy pll calculations

Extending ICL mg calculations to also support dkl calculations. BSpec: 49204 Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 148 +++--- 2 files

[Intel-gfx] [PATCH v2 09/13] drm/i915/icl: Unify disable and enable phy clock gating functions

Adding a enable parameters allow us to share most of the code between enable and disable functions. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 71 1 file changed, 22 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 13/13] drm/i915/tgl: initialize TC and TBT ports

From: Lucas De Marchi Now that TC support was added, initialize DDIs. Signed-off-by: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2 06/13] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the bspec all the registers are read modify write. Signed-off-by: Vandita Kulkarni Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65

[Intel-gfx] [PATCH v2 05/13] drm/i915/tgl: Add initial dkl pll support

From: Lucas De Marchi The disable function can be the same as for MG phy since the same registers are used. The others are different as registers changed, also adding a empty dkl_pll_write() to be implemented later. v2: Setting the right HIP_INDEX_REG bits (José) Signed-off-by: José Roberto de

[Intel-gfx] [PATCH v2 04/13] drm/i915/tgl: Add dkl phy registers

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 162 1 file changed, 162 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ee5626579263..32f98d0e0e9c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH CI 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

Cc: Daniel Vetter Cc: Laurent Pinchart Cc: dri-de...@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/ast/ast_mode.c | 12 drivers/gpu/drm/drm_atomic_helper.c| 15 ++- drive

[Intel-gfx] [PATCH CI 2/2] drm/connector: Allow max possible encoders to attach to a connector

Roberto de Souza --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 - drivers/gpu/drm/drm_client_modeset.c | 3 +- drivers/gpu/drm/drm_connector.c

[Intel-gfx] [PATCH 02/14] drm/i915/tgl: TC helper function to return pin mapping

From: "Taylor, Clinton A" Add a helper function to return pin map for use during dkl phy DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it. The user of this function will come in future TC patches. Signed-off-by: Taylor, Clinton A ---

[Intel-gfx] [PATCH 10/14] drm/i915/tgl: Fix dkl phy register space addressing

It was always modifing register space of the first phy in the HIP_INDEX_REG for all ports while it should shift 8 bits for each port inside of HIP_INDEX_REG. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH 04/14] drm/i915/tgl: Fix driver crash when update_active_dpll is called

From: "Taylor, Clinton A" TGL PLL function table doesn't include and update_active_pll function. The driver attempts to make a call to this function and crashes during PLL changes. Signed-off-by: Taylor, Clinton A --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + 1 file changed, 1

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