Re: [Intel-gfx] [PATCH] drm/i915: DP link training optimization

-Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, February 26, 2015 12:51 PM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: DP link training optimization On Thu, Feb 26, 2015 at 11:26:10AM +0200

Re: [Intel-gfx] [PATCH v6 2/8] drm/i915: Use cached cdclk value

-Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Monday, June 15, 2015 2:55 PM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v6 2/8] drm/i915: Use cached cdclk value On Wed, Jun 03, 2015

Re: [Intel-gfx] [PATCH v4 10/12] drm/i915: HSW cdclk support

-Original Message- From: Lespiau, Damien Sent: Friday, May 29, 2015 2:31 PM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v4 10/12] drm/i915: HSW cdclk support On Fri, May 22, 2015 at 11:22:40AM +0300, Mika Kahola wrote: From: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Disable FLT if DP config changes

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Friday, November 27, 2015 2:13 PM > To: Ander Conselvan De Oliveira > Cc: Kahola, Mika; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Disable FLT if

Re: [Intel-gfx] [PATCH] drm/i915: Make DP fast link training a module parameter

> -Original Message- > From: Jani Nikula [mailto:jani.nik...@linux.intel.com] > Sent: Friday, November 20, 2015 3:47 PM > To: Kahola, Mika; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Make DP fast link training a > module parameter >

Re: [Intel-gfx] [PATCH v4 09/11] drm/i915: Check pixel rate for DP to VGA dongle

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Thursday, June 9, 2016 11:14 AM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; > jim.br...@linux.intel.com

Re: [Intel-gfx] [PATCH 08/12] drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/

I'll second this idea. With small typo fixed on commit message this is Reviewed-by: Mika Kahola > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of ville.syrj...@linux.intel.com > Sent: Wednesday, June 8, 2016

Re: [Intel-gfx] [PATCH v4 0/6] Check pixel clock when setting mode

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Thursday, February 11, 2016 11:21 AM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATC

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915: Read DP branch device SW revision

> -Original Message- > From: Jim Bride [mailto:jim.br...@linux.intel.com] > Sent: Thursday, September 8, 2016 12:20 AM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; > ville.syrj...@lin

Re: [Intel-gfx] [PATCH v8 10/12] drm/i915: Update bits per component for display info

Thanks for the review. I'll fix those indentations. > -Original Message- > From: Jim Bride [mailto:jim.br...@linux.intel.com] > Sent: Thursday, September 8, 2016 12:27 AM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; dri-de...@

Re: [Intel-gfx] [PATCH v8 03/12] drm: Helper to read max clock rate

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Thursday, September 8, 2016 4:02 PM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; > jim.br...@lin

Re: [Intel-gfx] [PATCH i-g-t v7] tests/kms_plane_multiple: CRC based atomic correctness test

Thanks for the review! Cheers, Mika > -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Wednesday, November 16, 2016 11:48 AM > To: Kahola, Mika <mika.kah...@intel.com>; intel-gfx@lists.freedesktop.org > Cc: Latva

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_lowres: Plane visibility after atomic modesets

> -Original Message- > From: Daniel Stone [mailto:dan...@fooishbar.org] > Sent: Tuesday, November 15, 2016 3:20 PM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx <intel-gfx@lists.freedesktop.org> > Subject: Re: [Intel-gfx] [PATCH i-g-t]

Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_plane_lowres: Plane visibility after atomic modesets

Hi, Thanks for review comments! > -Original Message- > From: Daniel Stone [mailto:dan...@fooishbar.org] > Sent: Wednesday, December 7, 2016 5:02 PM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx <intel-gfx@lists.freedesktop.org> > Subje

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: Change number of iterations

> -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Thursday, January 12, 2017 2:00 PM > To: Maarten Lankhorst <maarten.lankho...@linux.intel.com> > Cc: Kahola, Mika <mika.kah...@intel.com>; intel-gfx@lists.freedesktop.org > Sub

Re: [Intel-gfx] [PATCH i-g-t v3] tests/kms_plane_lowres: Plane visibility after atomic modesets

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Thursday, December 29, 2016 1:57 PM > To: Kahola, Mika <mika.kah...@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH i-g-t v3] tests/km

Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_concurrent: Concurrent and interruptible subtests for atomic

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, April 10, 2017 3:39 PM > To: Kahola, Mika <mika.kah...@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH i-g-t v2] tests/kms_c

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: Fix reference CRC

> -Original Message- > From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of > Daniel Vetter > Sent: Monday, July 31, 2017 11:13 AM > To: Kahola, Mika <mika.kah...@intel.com> > Cc: intel-gfx <intel-gfx@lists.freedesktop.org> > Subj

Re: [Intel-gfx] [PATCH 2/5] drm/i915: always return something

Patch look ok to me. On Thu, 2019-01-17 at 12:21 -0800, Lucas De Marchi wrote: > Even if we don't have the correct clock and get a warning, we should > not > skip the return. > > Fixes: 1fa11ee2d9d0 ("drm/i915/icl: start adding the TBT pll") > Cc: Paulo Zanoni > Cc: # v4.19+ Reviewed-by: Mika

Re: [Intel-gfx] [PATCH] drm/i915: Avoid divide by zero

On Tue, 2019-01-22 at 15:07 +0200, Jani Nikula wrote: > On Tue, 22 Jan 2019, Mika Kahola wrote: > > Avoid divide by zero warning on static analysis. > > > > Signed-off-by: Mika Kahola > > --- > > drivers/gpu/drm/i915/intel_pm.c | 6 -- > > 1 file changed, 4 insertions(+), 2 deletions(-) >

Re: [Intel-gfx] [PATCH] drm/i915: Avoid divide by zero

On Tue, 2019-01-22 at 21:09 +0200, Ville Syrjälä wrote: > On Tue, Jan 22, 2019 at 08:09:40PM +0200, Jani Nikula wrote: > > On Tue, 22 Jan 2019, Ville Syrjälä > > wrote: > > > On Tue, Jan 22, 2019 at 02:58:24PM +0200, Mika Kahola wrote: > > > > Avoid divide by zero warning on static analysis. > >

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/icl: Add fallback detection method for TypeC legacy ports

The v2 looks ok to me. On Fri, 2018-12-14 at 20:27 +0200, Imre Deak wrote: > Add a fallback detection method for TypeC legacy ports in case the > VBT port information used to detect normally such ports is > incorrect. > > For the fallback method we use the TypeC legacy mode specific HPD >

Re: [Intel-gfx] [PATCH] drm/i915: Wait one vblank before sending hotplug event to userspace

On Tue, 2018-12-04 at 21:43 +0200, Ville Syrjälä wrote: > On Tue, Dec 04, 2018 at 11:46:39AM +0200, Mika Kahola wrote: > > Occasionally, we get the following error in our CI runs > > > > [853.132830] Workqueue: events i915_hotplug_work_func [i915] > > [853.132844] RIP:

Re: [Intel-gfx] [PATCH] drm/i915: Wait one vblank before sending hotplug event to userspace

On Tue, 2018-12-04 at 11:41 +, Chris Wilson wrote: > Quoting Mika Kahola (2018-12-04 09:46:39) > > Occasionally, we get the following error in our CI runs > > > > [853.132830] Workqueue: events i915_hotplug_work_func [i915] > > [853.132844] RIP: 0010:drm_wait_one_vblank+0x19b/0x1b0 > >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: allow platforms without eDP transcoder

On Fri, 2019-03-01 at 15:56 -0800, Lucas De Marchi wrote: > On Mon, Feb 25, 2019 at 06:17:13AM -0800, Mika Kahola wrote: > > Looks allright. > > > > On Fri, 2019-02-22 at 15:02 -0800, Lucas De Marchi wrote: > > > Define a HAS_TRANSCODER_EDP() macro that checks if we have > > > defined an > > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: refactor transcoders reporting on error state

Looks ok. On Fri, 2019-02-22 at 15:02 -0800, Lucas De Marchi wrote: > Instead of keeping track of the number of transcoders, loop through > all > the interesting ones and check if there is a correspondent offset. > > Cc: Rodrigo Vivi Reviewed-by: Mika Kahola > Signed-off-by: Lucas De Marchi

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance

This is also needed to fix failing IGT test case kms_cursor_crc on ICL. On Tue, 2019-03-05 at 17:26 -0800, Aditya Swarup wrote: > Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows > to passthrough FB pixels unmodified across pipe. This fixes the > failures > for DP link layer

Re: [Intel-gfx] [PATCH 2/2] drm/i915: allow platforms without eDP transcoder

Looks allright. On Fri, 2019-02-22 at 15:02 -0800, Lucas De Marchi wrote: > Define a HAS_TRANSCODER_EDP() macro that checks if we have defined an > offset for this transcoder. This allows platforms to be defined > without > eDP transcoder. > > Cc: Mika Kahola > Cc: Imre Deak > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance

The patch looks ok to me. On Wed, 2019-03-06 at 18:14 -0800, Aditya Swarup wrote: > Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows > to passthrough FB pixels unmodified across pipe. This fixes the > failures > for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3. >

Re: [Intel-gfx] [PATCH v2] drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen

The patch look ok to me. On Fri, 2019-01-11 at 19:49 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Certain SNB machines (eg. ASUS K53SV) seem to have a broken BIOS > which misprograms the hardware badly when encountering a suitably > high resolution display. The programmed pipe timings

Re: [Intel-gfx] [RFT i-g-t] tests/prime_vgem/basic-fence-flip: Probe display resolution

On Wed, 2019-04-10 at 13:11 +0100, Tvrtko Ursulin wrote: > On 10/04/2019 12:48, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-04-10 12:43:22) > > > @@ -754,8 +768,8 @@ static void test_flip(int i915, int vgem, > > > unsigned hang) > > > uint32_t offsets[4] = {}; > > >

Re: [Intel-gfx] [PATCH] drm/i915/icl: More workaround for port F detection due to broken VBTs

This fixes the issue on my ICL-Y. On Fri, 2019-05-10 at 17:02 +0300, Imre Deak wrote: > Add another ICL-Y PCIID that proved to have only 5 ports to the > corresponding PCIID list. > > Meanwhile I'm trying to get a complete list of all PCIIDs with less > than > 6 ports and/or get a VBT fix to

Re: [Intel-gfx] [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote: > From: José Roberto de Souza > > On Tiger Lake there is one more pipe - check if it's fused. > > Signed-off-by: José Roberto de Souza > Signed-off-by: Lucas De Marchi Reviewed-by: Mika Kahola > --- >

Re: [Intel-gfx] [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote: > Current list of PCI IDs for Tiger Lake. > > Cc: Rodrigo Vivi > Signed-off-by: Lucas De Marchi As per BSPec #44455 the IDs seems correct. Reviewed-by: Mika Kahola > --- > drivers/gpu/drm/i915/i915_pci.c | 1 + >

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions

On Tue, 2019-08-20 at 19:05 +0530, Shankar, Uma wrote: > > -Original Message- > > From: Kahola, Mika > > Sent: Tuesday, August 20, 2019 4:37 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Shankar, Uma ; Kahola, Mika > > > > Subject: [P

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions

On Tue, 2019-08-20 at 16:03 +0300, Ville Syrjälä wrote: > On Tue, Aug 20, 2019 at 02:06:31PM +0300, Mika Kahola wrote: > > In order to achieve improved power savings we can tune down CD > > clock frequency > > for sub 4k resolutions. The maximum CD clock frequency for sub 4k > > resolutions is set

Re: [Intel-gfx] [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()

On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote: > From: José Roberto de Souza > > Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse > order. > > v2: Fix additional blank line > > Cc: Rodrigo Vivi > Cc: Ville Syrjälä > Signed-off-by: José Roberto de Souza >

Re: [Intel-gfx] [PATCH v2 18/40] drm/i915: Disable pipes in reverse order

On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote: > From: José Roberto de Souza > > Disable CRTC/pipes in reverse order because some features (MST in > TGL+) requires master and slave relationship between pipes, so it > should always pick the lowest pipe as master as it will be enabled >

Re: [Intel-gfx] [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()

On Wed, 2019-08-21 at 11:22 +, Kahola, Mika wrote: > On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote: > > From: José Roberto de Souza > > > > Same as for_each_oldnew_intel_crtc_in_state() but iterates in > > reverse > > order. > > > &

Re: [Intel-gfx] [PATCH v2 16/40] drm/i915: Add for_each_new_intel_connector_in_state()

On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote: > From: José Roberto de Souza > > The same macro as for_each_new_connector_in_state() but it uses > intel/i915 types instead of the drm ones. > > Signed-off-by: José Roberto de Souza Reviewed-by: Mika Kahola > --- >

Re: [Intel-gfx] [PATCH 1/2] [v8] drm/i915/color: Extract icl_read_luts()

On Wed, 2019-11-27 at 19:45 +0530, Swati Sharma wrote: > For icl+, have hw read out to create hw blob of gamma > lut values. icl+ platforms supports multi segmented gamma > mode by default, add hw lut creation for this mode. > > This will be used to validate gamma programming using dsb > (display

Re: [Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > The CCS plane stride must be fixed on TGL, as it's not configurable > for > the display. Instead the HW has a hardwired logic to determine it > from > the main plane stride. Make sure userspace passes in the correct > stride. > > Cc:

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Make sure CCS YUV semiplanar format checks work

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > For CCS formats, the current DRM core check for YUV semiplanar > formats > doesn't work; use an i915 specific function for that. > > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjälä > Signed-off-by: Imre Deak There is still one call for

Re: [Intel-gfx] [PATCH 09/15] drm/i915: Make sure Y slave planes get all the required state

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > Y planes program the offset and stride of the AUX plane, so make sure > we > copy the required info for this into their plane state. > > Cc: Maarten Lankhorst > Cc: Ville Syrjälä > Cc: Dhinakaran Pandiyan > Signed-off-by: Imre Deak

Re: [Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Radhakrishna Sripada > > Gen12 display can decompress surfaces compressed by render engine > with > Clear Color, add a new modifier as the driver needs to know the > surface > was compressed by render engine. > > V2: Description

Re: [Intel-gfx] [PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Gen-12 display can decompress surfaces compressed by the media > engine, add > a new modifier as the driver needs to know the surface was compressed > by > the media or render engine. > > v2: Update code comment

Re: [Intel-gfx] [PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > addfb() uAPI has supported four planes for a while now, make > format_info > compatible with that. > > Cc: Ville Syrjälä > Cc: Matt Roper > Signed-off-by: Dhinakaran Pandiyan > Signed-off-by: Imre Deak

Re: [Intel-gfx] [PATCH v2 08/15] drm/i915: Skip rotated offset adjustment for unsupported modifiers

On Thu, 2019-12-19 at 01:34 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > During framebuffer creation, we pre-compute offsets for 90/270 plane > rotation. However, only Y and Yf modifiers support 90/270 rotation. > So, > skip the calculations for other modifiers. > > To keep the gem

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Use intel_tile_height() instead of re-implementing

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > intel_tile_dims() computes tile height using size and width, when > there > is already a function to do just that - intel_tile_height() > > Cc: Ville Syrjälä > Cc: Matt Roper > Signed-off-by: Dhinakaran

Re: [Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Gen-12 has a new compression format, add a new modifier to indicate > that. > > Cc: Ville Syrjälä > Cc: Matt Roper > Cc: Nanley G Chery > Cc: Jason Ekstrand > Signed-off-by: Dhinakaran Pandiyan >

Re: [Intel-gfx] [PATCH 03/15] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Easier to read if all the alignment changes are in one place and > contained > within a function. > > Cc: Ville Syrjälä > Cc: Matt Roper > Signed-off-by: Dhinakaran Pandiyan > Signed-off-by: Imre Deak

Re: [Intel-gfx] [PATCH 04/15] drm/i915: Extract framebufer CCS offset checks into a function

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > intel_fill_fb_info() has grown quite large and wrapping the offset > checks > into a separate function makes the loop a bit easier to follow. > > Cc: Ville Syrjälä > Cc: Matt Roper > Signed-off-by: Dhinakaran

Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > Using helpers instead of open coding this to select a CCS plane for a > main plane makes the code cleaner and less error-prone when the > location > of CCS plane can be different based on the format (packed vs. YUV > semiplanar). The same

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Pass intel_connector to intel_attached_*()

On Wed, 2019-12-04 at 20:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Life is usually easier when we pass around intel_ types instead > of drm_ types. In this case it might not be, but I think being > consistent is a good thing anyway. Also some of this might get > cleaned up a bit

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Relocate intel_attached_dp()

On Wed, 2019-12-04 at 20:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > We have uses for intel_attached_dp() outside of intel_dp.c. Move > it to a header. > > Signed-off-by: Ville Syrjälä Reviewed-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 5

Re: [Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote: > Currently the GGTT offset of a UV plane in a semiplanar YUV FB is > tile > size (4kB) aligned. I noticed, that enforcing only this alignment > leads > oddly to random memory corruptions on TGL while scanning out Y-tiled > FBs. This issue can be

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes

On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote: > As intel_fb_plane_get_subsampling() returns the subsampling factor > wrt. > its main plane, for a CCS plane we need to apply both the main and > the > CCS plane's subsampling factor on the FB's dimensions to get the CCS > plane's dimensions. >

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error

On Wed, 2020-01-01 at 01:37 +0200, Imre Deak wrote: > Print a debug message if the FB plane[0] offset is not 0 as expected, > to > help understainding an add FB IOCTL fail. > > Cc: Chris Wilson > Cc: Ville Syrjälä > Cc: Mika Kahola > Signed-off-by: Imre Deak Reviewed-by: Mika Kahola > ---

Re: [Intel-gfx] [PATCH v2 04/15] drm/i915: Extract framebufer CCS offset checks into a function

On Fri, 2019-12-20 at 12:49 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > intel_fill_fb_info() has grown quite large and wrapping the offset > checks > into a separate function makes the loop a bit easier to follow. > > v2: Skip the check for non-CCS planes. (Mika) > > Cc: Ville

Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Monday, November 23, 2020 8:27 PM > To: intel-gfx@lists.freedesktop.org > Cc: Chery, Nanley G ; Rafael Antognolli > ; Chris Wilson ; > Pandiyan, Dhinakaran ; Syrjala, Ville > ; Shashank Sharma > Subject: [Intel-gfx]

Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Monday, November 23, 2020 8:27 PM > To: intel-gfx@lists.freedesktop.org > Cc: Chery, Nanley G ; Rafael Antognolli > ; Pandiyan, Dhinakaran > ; Kondapally, Kalyan > > Subject: [Intel-gfx] [PATCH 1/2] drm/framebuffer:

Re: [Intel-gfx] [PATCH v7 1/3] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Thursday, January 14, 2021 10:13 PM > To: intel-gfx@lists.freedesktop.org > Cc: Chery, Nanley G ; Rafael Antognolli > ; Daniel Vetter ; > Nikula, Jani ; Pandiyan, Dhinakaran > ; Kondapally, Kalyan > > Subject:

Re: [Intel-gfx] [PATCH v3 20/48] drm/i915/adl_p: Add cdclk support for ADL-P

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Saturday, May 8, 2021 5:28 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 20/48] drm/i915/adl_p: Add cdclk support for > ADL-P > > From: Anusha Srivatsa > > ADL-P has 3 possible refclk

Re: [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement Wa_22011091694

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Saturday, May 8, 2021 5:28 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement > Wa_22011091694 > > From: José Roberto de Souza > > Adding a new hook to ADL-P

Re: [Intel-gfx] [PATCH v3 46/48] drm/i915/display/adl_p: Implement Wa_22011320316

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Saturday, May 8, 2021 5:28 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 46/48] drm/i915/display/adl_p: Implement > Wa_22011320316 > > From: José Roberto de Souza > > Implementation

Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Friday, April 16, 2021 1:13 AM > To: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of > 8 tiles stride for DPT FBs > > On Wed, Apr 14, 2021 at 06:52:07PM

Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL

> -Original Message- > From: Intel-gfx On Behalf Of > Stanislav Lisovskiy > Sent: Thursday, June 3, 2021 9:51 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL > > CDCLK crawl feature allows to change CDCLK frequency

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes

> -Original Message- > From: Mun, Gwan-gyeong > Sent: Tuesday, June 1, 2021 3:48 PM > To: intel-gfx@lists.freedesktop.org > Cc: Souza, Jose ; Lisovskiy, Stanislav > ; ville.syrj...@linux.intel.com; Roper, > Matthew D ; Kahola, Mika > > Subject: [PATCH v2 2/2] d

Re: [Intel-gfx] [PATCH] drm/i915: Reject 446-480MHz HDMI clock on GLK

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 3, 2021 11:31 AM > To: intel-gfx@lists.freedesktop.org > Cc: sta...@vger.kernel.org > Subject: [Intel-gfx] [PATCH] drm/i915: Reject 446-480MHz HDMI clock on GLK > > From: Ville Syrjälä > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Index min_{cdclk, voltage_level}[] with pipe

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, February 4, 2021 4:09 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Index min_{cdclk, voltage_level}[] > with pipe > > From: Ville Syrjälä > > min_cdclk[] and

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use intel_hdmi_port_clock() more

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, February 4, 2021 4:09 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Use intel_hdmi_port_clock() more > > From: Ville Syrjälä > > Replace the hand rolled

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() > after encoder readout > > From: Ville Syrjälä > > The

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's > .get_config() from MST .get_config() > > From: Ville Syrjälä > >

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in > PLL > state tracking > > From: Ville Syrjälä > > All

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, February 25, 2021 6:12 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do > intel_dpll_readout_hw_state() after encoder readout > > From: Ville Syrjälä > > The

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled() > > From: Ville Syrjälä > > Support reading out the

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to > encoder->get_config() > > From: Ville Syrjälä > > Move the

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Extend > icl_sanitize_encoder_pll_mapping() to all DDI platforms > > From: Ville Syrjälä >

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add warn_on in intel_psr_pause()

> -Original Message- > From: Souza, Jose > Sent: Wednesday, October 20, 2021 3:36 AM > To: intel-gfx@lists.freedesktop.org > Cc: Kahola, Mika ; Hogander, Jouni > ; Sripada, Radhakrishna > ; Souza, Jose > Subject: [PATCH 2/2] drm/i915/display: Add warn_on in inte

Re: [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO > underrun > > From: Ville Syrjälä > > Currently a FIFO

Re: [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane > > From: Ville Syrjälä > > In the future we may have

Re: [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC > instance to FBC underrun stuff > > From: Ville Syrjälä >

Re: [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce > intel_fbc_add_plane() > > From: Ville Syrjälä > > In order to better

Re: [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe > > From: Ville Syrjälä > > FBC and double wide pipe are

Re: [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state > > From: Ville Syrjälä > > There isn't a good reason why we'd

Re: [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the > cache and params > > From: Ville Syrjälä > > The FBC

Re: [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc > dynamically > > From: Ville Syrjälä > > In the future we may

Re: [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from > intel_fbc_can_enable() into intel_fbc_check_plane() > > From: Ville

Re: [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance > instead of crtc > > From: Ville Syrjälä > > Pass the FBC

Re: [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update()

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten > __intel_fbc_pre_update() > > From: Ville Syrjälä > > Use an early return

Re: [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache > > From: Ville Syrjälä > > fbc->state_cache has now become

Re: [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into > intel_fbc_state > > From: Ville Syrjälä > > Currently we

Re: [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 24, 2021 1:37 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/ > > From: Ville Syrjälä > > Rename the 'params' to just fbc

Re: [Intel-gfx] [PATCH] drm/i915/fbc: Remember to update FBC state even when not reallocating CFB

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Thursday, December 16, 2021 1:08 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915/fbc: Remember to update FBC state even > when not reallocating CFB > > From: Ville Syrjälä > >

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Monday, November 15, 2021 8:11 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix fastsets on TypeC ports > following a > non-blocking modeset > > After a non-blocking modeset

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Allow cdclk squasher to be reconfigured live

> -Original Message- > From: Intel-gfx On Behalf Of Mika > Kahola > Sent: Friday, November 19, 2021 3:14 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 5/5] drm/i915: Allow cdclk squasher to be > reconfigured live > > From: Ville Syrjälä > > Supposedly we

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Introduce CD clock squashing table

Please ignore this. These CD clock squashing patches needs to be sent as a series. From: Patchwork Sent: Wednesday, November 17, 2021 10:59 PM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Introduce CD clock squashing table Patch

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Sanitize CD clock

Please ignore this. These CD clock squashing patches needs to be sent as a series. From: Patchwork Sent: Thursday, November 18, 2021 12:08 AM To: Kahola, Mika Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915/display/dg2: Sanitize CD clock Patch Details Series

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Read CD clock from squasher table

Please ignore this. These CD clock squashing patches needs to be sent as a series. > -Original Message- > From: Patchwork > Sent: Wednesday, November 17, 2021 11:28 PM > To: Kahola, Mika > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.BUILD: failure for dr

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/dg2: Set CD clock squashing registers

Please ignore this. These CD clock squashing patches needs to be sent as a series. > -Original Message- > From: Patchwork > Sent: Thursday, November 18, 2021 12:06 AM > To: Kahola, Mika > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.BUILD: failure for dr

  1   2   3   >