On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt Atwood
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
v3: whitespace
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt
.
> - Rename register definitions with TGL_ prefix
> v4: Bspec changed. Again. Add WA to rcs_ WA list.
>
> Cc: Daniele Ceraolo Spurio
> Cc: Matt Roper
See whitespace fix,
Reviewed-by: Matt Atwood
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/intel_work
Disable Push Constant buffer addition for A0, which can cause FIFO
underruns.
Fix a minor white space issue while we're here.
Bspec: 52890
Cc: Rafael Antognolli
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h
Disable Push Constant buffer addition for TGL.
v2: typos, add additional Wa reference
v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
message.
Bspec: 52890
Cc: Rafael Antognolli
Cc: Matt Roper
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5
From: Anusha Srivatsa
According to BSpec. Wa_1606931601 applies for all
TGL steppings.This patch moves the WA implementation
out of A0 only block of rcs_engine_wa_init().
The WA is has also been referred to by an alternate name
Wa_1607090982.
Bspec: 46045,52890
Fixes: 3873fd1a43c7 ("drm/i915:
Disable Push Constant buffer addition, which can cause FIFO
underruns.
Fix a minor white space issue while we're here.
v2: typos, add additional Wa reference
Bspec: 52890
Cc: Rafael Antognolli
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
drivers
few specific bits.
>
> Bspec: 49213
> Bspec: 50096
> Fixes: 4cb4585e5a7f ("drm/i915/icl: initialize MBus during display init")
> Cc: Stanislav Lisovskiy
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_po
2:
> - Program registers with rmw to preserve contents of unrelated bits.
> - Switch to the new display uncore helpers.
>
> Bspec: 49213
> Bspec: 50096
> Cc: Stanislav Lisovskiy
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/int
The bspec tells us we need to set this bit to avoid potential underruns.
v2: use new register write convention (Anshuman) add bspec 7386 ref.
Bspec: 7386
Bspec: 33450
Bspec: 33451
Cc: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_reg.h | 1
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
Bspec: 52890
Cc: Matt Roper
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_sprite.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
The bspec tells us we need to set this bit to avoid potential underruns.
Bspec: 33450
Bspec: 33451
Bspec: 33452
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915
Reflect recent Bspec changes
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..30b45c0de6fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
Reflect recent Bspec changes
v2: fix whitespace, typo
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..3d12a0617c84 100644
--- a/drivers
tel/issues/1222
>
> v2: Simplify the table and use 0 for some unused ranges(Matt)
>
> Cc: Matt Roper
Reviewed-by: Matt Atwood
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 31 -
> 1 file changed, 17 inserti
Reflect recent bspec changes.
Bspec: 33451
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
Reflect recent Bspec changes.
Bspec: 33451
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 90a2b9e399b0
; > Let's try applying the HBR3 fix again.
>
> The link training failure still happens the same way on fi-icl-u2.
Previously this only failed on a specific TGL CI system, did you get
failures on both this go around? ICL passed last time.
>
> > >
> > > This r
Add minimum width to planes, variable with specific formats for gen11+
to reflect recent bspec changes.
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 54 +---
1 file changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915
The initial CI results did not include a TGL system which includes a
panel that is having issues with patch. Revert while we triage.
This reverts commit 680c45c767f63e35f063d3ea04f388a9f7ae7079.
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++--
1 file changed, 17
The initial CI results did not include a TGL system which includes a
panel that is having issues with patch. Revert while we triage.
This reverts commit 680c45c767f63e35f063d3ea04f388a9f7ae7079.
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_dp.c | 28
.
v2: Alter intel_dp_set_source_rates final position (Ville/Manasi).
Remove outdated comment (Ville).
Slight optimization of control flow in intel_dp_init_connector.
Slight rewording in commit message.
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_dp.c | 28
On Mon, Jun 01, 2020 at 06:49:10PM -0700, Aditya Swarup wrote:
> Set GMBUS0 Pin Pair Select to 1 at boot and each FLR exit.
> Return GMBUS0 Pin Pair Select to 1 after GMBUS transactions are done.
>
> Cc: Michal Wajdeczko
> Cc: Piotr Piórkowski
> Cc: Matt Roper
> Cc: Jose Souza
>
O Wed, Jun 17, 2020 at 11:00:06AM -0700, Matt Roper wrote:
> This workaround now also applies to TGL and RKL, so extend the PCH test
> to just capture everthing ICP and beyond.
>
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/i915_irq.c |
Update code to reflect recent bspec changes
Bspec: 52890
Bspec: 53508
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm
On Thu, Jun 11, 2020 at 04:31:08PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Enable HW Default flip for small PL.
>
> bspec: 52890
> bspec: 53508
> bspec: 53273
>
> Signed-off-by: Clint Taylor
Reviewed-by: Matt Atwood
>
Add minimum width to planes, variable with specific formats, for gen11+.
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_display.c | 55 +---
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers
On Tue, Jun 16, 2020 at 07:39:09PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > Add minimum width to planes, variable with specific formats, for gen11+.
>
> How did this suddenly become gen11+? Wasn't it rkl only before?
gen11
On Tue, Jun 16, 2020 at 08:34:07PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > Add minimum width to planes, variable with specific formats, for gen11+.
> >
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu
On Fri, Jul 23, 2021 at 10:42:31AM -0700, Matt Roper wrote:
> Bspec: 45101, 45427
> Cc: Ramalingam C (v5)
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
> 1 file changed, 34 inserti
with gslice steering.
>
> Cc: Lionel Landwerlin
> Signed-off-by: Matt Roper
> Acked-by: Lionel Landwerlin
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 7 +++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
> drivers/gpu/d
gt; the code in future patches.
>
> Bspec: 54032
> Bspec: 53881
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Jani Nikula
> Signed-off-by: Nidhi Gupta
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/Makefile
José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index
58")
>
> So this can be propagated to older kernels, will add while applying.
>
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/4145
> > Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915/gt/i
y: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 4 +
> drivers/gpu/drm/i915/intel_uncore.c | 336 +++---
> drivers/gpu/drm/i915/intel_un
> Signed-off-by: Venkata Ramana Nayana
> Signed-off-by: Akeem G Abodunrin
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 65 ++---
> 1 file changed, 59 insertions(+), 6 deletions(-)
>
> diff
On Tue, Jul 13, 2021 at 08:14:58PM -0700, Matt Roper wrote:
> From: John Harrison
>
> Xe_HP can have a lot of extra media engines. This patch adds the reset
> support for them.
>
> Signed-off-by: John Harrison
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
On Tue, Jul 13, 2021 at 08:15:01PM -0700, Matt Roper wrote:
> From: Stuart Summers
>
> Xe_HP changes the format of the context ID from past platforms.
>
> Signed-off-by: Stuart Summers
> Signed-off-by: Umesh Nerlige Ramappa
> Signed-off-by: Matt Roper
Rev
has_master_unit_irq feature flag with an IP version test.
>
> Bspec: 50875
> Cc: Daniele Spurio Ceraolo
> Cc: Stuart Summers
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Lucas De Marchi
> Signed-off-by: Tomasz Lis
> Signed-off-by: Matt Roper
Reviewed-by: M
> To simplify things we do not add a new register definition but just stop
> inverting the fusing masks before processing them.
>
> Bspec: 52615
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> Reviewed-by: Lucas De Marchi
Review
ot; PHY
> units. As such, we don't want intel_phy_is_combo to take us down legacy
> programming paths, so just return false from it on DG2. Instead add a
> new intel_phy_is_snps() that will return true for all DG2 PHYs.
>
> Cc: Anusha Srivatsa
> Cc: Matt Atwood
> S
On Tue, Jul 13, 2021 at 08:15:33PM -0700, Matt Roper wrote:
> Vswing programming for SNPS PHYs is just a single step -- look up the
> value that corresponds to the voltage level from a table and program it
> into the SNPS_PHY_TX_EQ register.
>
> Bspec: 53920
> Cc: Matt At
On Tue, Jul 13, 2021 at 08:15:36PM -0700, Matt Roper wrote:
> Initialization of the PHY is handled by the hardware/firmware, but the
> driver should wait up to 25ms for the PHY to report that its calibration
> has completed.
>
> Bspec: 49189
> Bspec: 50107
> Cc: Matt Atwood
4032
> Cc: Matt Atwood
> Signed-off-by: Matt Roper
> Signed-off-by: Vandita Kulkarni
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> drivers/gpu/drm/i915/display/intel_display.c | 47 +++
> drivers/gpu/drm/i915/display/intel_h
On Wed, Jul 21, 2021 at 10:43:33PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling eDP data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> -
On Wed, Jul 21, 2021 at 10:43:34PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling PSR data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> -
ts to be parsed to be parsed like any other DDI
> port.
> This will be helpful to integrate into just one function the parse of
> information about integrated panels(eDP and DSI).
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt A
global
> one.
> Other VBT blocks will be converted in following patches.
>
> While at is also nucking lvds_dither as it is not used.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/g
On Wed, Jul 21, 2021 at 10:43:31PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Review-by: Matt Atwood
> ---
> drivers/gpu/drm/i915
On Wed, Jul 21, 2021 at 10:43:32PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling backlight data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
ts to be parsed to be parsed like any other DDI
> port.
> This will be helpful to integrate into just one function the parse of
> information about integrated panels(eDP and DSI).
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt A
On Wed, Jul 21, 2021 at 10:43:38PM -0700, José Roberto de Souza wrote:
> Tigerlake and newer has two instances of PPS, to support up to two
> eDP panels.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reveiwed-by: Matt Atwood
> ---
&g
On Wed, Jul 21, 2021 at 10:43:37PM -0700, José Roberto de Souza wrote:
> On newer platform this opregion call always fails, also it do not
> support multiple panels so dropping it.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Review
On Wed, Jul 21, 2021 at 10:43:35PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling DSI data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> -
On Wed, Jul 21, 2021 at 10:43:36PM -0700, José Roberto de Souza wrote:
> All the users was converted now we can drop it.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/disp
he driver.
>
after nit fix,
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 17 +
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 19 ---
> drivers/gpu/drm/i915/gt/intel_reset.c
offset, drop the copy from intel_gt_regs.h
>
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu
On Tue, Feb 08, 2022 at 09:11:37PM -0800, Matt Roper wrote:
> We have both a parameterized RING_MI_MODE() macro and an RCS-specific
> MI_MODE; drop the latter and use the former everywhere.
>
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drive
On Tue, Feb 08, 2022 at 09:11:39PM -0800, Matt Roper wrote:
> Switch all register offsets to use lowercase hex values for consistency.
> Also strip any unnecessary leading 0's. For example, "_MMIO(0x0D08)"
> becomes "_MMIO(0xd08)."
>
Reviewed-by: Matt Atw
s too long, in which
>case a single tab is used.
>
> Final diff for this patch is empty if whitespace is ignored:
>
> $ git diff -w
> $
>
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h |
> A couple duplicated/unused register definitions are dropped while doing
> this re-order: GEN11_GT_INTR_DW{0,1}, GEN11_IIR_REG{0,1}_SELECTOR, and
> GEN11_INTR_IDENTITY_REG{0,1} aren't used anywhere in the driver because
> we have other parameterized macros referencing those registers.
>
hew Brost
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 3 ++-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c
On Thu, Mar 10, 2022 at 12:26:12PM +, Tvrtko Ursulin wrote:
>
> On 10/03/2022 05:18, Matt Atwood wrote:
> > Newer platforms have DSS that aren't necessarily available for both
> > geometry and compute, two queries will need to exist. This introduces
> > the first, whe
flags from hosting 2 8 bit numbers to holding a
i915_engine_class_instance struct
Cc: Ashutosh Dixit
Cc: Matt Roper
Cc: Joonas Lahtinen
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_query.c | 68
Dixit
Cc: Matt Roper
Cc: Joonas Lahtinen
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_query.c | 68 ++-
include/uapi/drm/i915_drm.h | 24 +++
2 files changed, 65
(mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_query.c | 68 ++-
include/uapi/drm/i915_drm.h | 24 +++
2 files changed, 65 insertions(+), 27 deletions(-)
diff --git a/drivers
flags from hosting 2 8 bit numbers to holding a
i915_engine_class_instance struct
v4: add error if non rcs engine passed.
Cc: Ashutosh Dixit
Cc: Matt Roper
Cc: Joonas Lahtinen
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
Signed-off-by: Matt Atwood
---
drivers/gpu
> Cc: Thomas Zimmermann
> Cc: Mauro Carvalho Chehab
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> include/linux/iosys-map.h | 202 ++
>
; Cc: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/shmem_utils.c | 32 +++
> drivers/gpu/drm/i915/gt/shmem_utils.h | 3 +++
> 2 files changed, 35 inse
itialization by abstracting the IO vs system memory.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915
el Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu
f
> destination
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |
t
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Matt Atwood
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 41 --
> 1 file changed, 23 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/in
On Fri, Sep 15, 2023 at 01:10:32AM +0530, Dnyaneshwar Bhadane wrote:
> Invalidate instruction and State cache bit using INDIRECT_CTX on
> every gpu context switch for gen12.
> The goal of this workaround is to actually perform an explicit
> invalidation of that cache (by re-writing the register)
on detection.
>
Bspec: 44477
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/i915_driver.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
>
e the number of condition blocks and to more consistently follow
> the "newest platform first" convention. Code movement only; no
> functional change.
>
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 100 ++
; now-unused IS_DG2_DISPLAY_STEP macro.
Bspec: 44477, 72197
>
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4
> drivers/gpu/drm/i915/i915_drv.h
Matt Roper
> Acked-by: Jani Nikula
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +---
> drivers/gpu/drm/i915/gt/intel_mocs.c| 21 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c |
On Fri, May 27, 2022 at 09:33:48AM -0700, Matt Roper wrote:
> From: Stuart Summers
>
> Bspec: 64027
Reviewed-by: Matt Atwood
> Signed-off-by: Stuart Summers
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
> drivers/gpu/drm
gt; Unlike past platforms, steppings for these components are represented by
> specific bitfields within the PCI revision ID, and we shouldn't make
> assumptions about the non-CT, non-BD bits staying 0. Let's update our
> stepping code accordingly.
>
> Bspec: 44484
Reviewed-by: Matt Atwoo
On Thu, May 26, 2022 at 12:19:35PM +0530, Balasubramani Vivekanandan wrote:
> New updates to HDMI combo PHY voltage swing tables. Actually with this
> update (bspec updated on 08/17/2021), the values are reverted back to be
> same as icelake for HDMI combo PHY.
>
> Bspec: 49291
Re
On Thu, Jun 02, 2022 at 07:27:19PM +0530, Balasubramani Vivekanandan wrote:
> Voltage swing table updated for eDP HBR3
>
> Bspec: 49291
Pending CI results
Reviewed-by: Matt Atwood
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/inte
handling to its own dedicated file in the
> near future and further enhance this with true kerneldoc. But this is a
> good intermediate step to help clarify the behavior a bit.
>
> Cc: Stuart Summers
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drive
On Tue, May 10, 2022 at 11:02:25PM -0700, Matt Roper wrote:
> Add PVC's forcewake ranges.
>
> v2:
> - Drop replicated comment completely; move general cleanup of the
>documentation to a separate patch.
>
> Bspec: 67609
> Cc: Daniele Ceraolo Spurio
> Cc: Stuart
a whole
> lacks a 3D pipeline. Add those restrictions here.
>
> v2:
> - Replace LACKS_3D_PIPELINE checks with !HAS_3D_PIPELINE and add
>has_3d_pipeline to all platforms except PVC. (Lucas)
>
> Bspec: 47112
> Cc: Lucas De Marchi
Reviewed-by: Matt Atwood
> S
On Tue, May 10, 2022 at 11:02:27PM -0700, Matt Roper wrote:
> Intialize ADS system info to reflect the availablity of new BCS engines
>
> Original-author: CQ Tang
> Cc: Stuart Summers
> Cc: John Harrison
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> dr
On Tue, May 10, 2022 at 11:02:28PM -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Disable HuC loading since it is not used on these platforms.
>
> Cc: Stuart Summers
Reviewed-by: Matt Atwood
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matt Ro
ave some additional features coming in
> the future that will also need to loop over each DSS and steer some
> register accesses accordingly.
>
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 ++-
>
ally freed when
> mm.free_work executed and that can happen very late in the suspend
> process causing issues.
> So here draining all freed objects released by display fixing suspend
> issues.
>
Reviewed-by: Matt Atwood
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/
_SLICE_CS_CHICKEN1[14] is once again set by the
> kernel.
>
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
> better performance. We'll add a new "tuning" feature flag to the ATS-M
> device info to enable/disable this setting.
>
> Bspec: 68331
> Cc: Lucas De Marchi
Reviewed-by: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.
Wa_18019271663 applies to all DG2 steppings and skus.
Bspec:45809
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt
Wa_18018764978 applies to specific steppings of DG2 (G11 C0+,
G11 and G12 A0+).
Bspec: 66622
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm
On Thu, Oct 27, 2022 at 02:28:53PM -0300, Gustavo Sousa wrote:
> On Tue, Oct 25, 2022 at 11:03:35AM -0700, Matt Atwood wrote:
> > Wa_18019271663 applies to all DG2 steppings and skus.
> >
> > Bspec:45809
>
> Could we also add the reference to the BSpec containing the
Wa_22015475538 applies to all DG2 (and ATSM) skus. The workaround
implementation is identical to Wa_16011620976. LSC_CHICKEN_BIT_0_UDW is
a general render register instead of rcs so adding this move to the
proper wa init function.
bspec:54077
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915
On Tue, Jan 03, 2023 at 04:18:27PM -0800, Matt Roper wrote:
> On Thu, Dec 15, 2022 at 03:30:55PM -0800, Matt Atwood wrote:
> > From: Matt Roper
> >
> > This patch introduces initial gt workarounds for the MTL platform.
> >
> > v2: drop redundant/stale comments
From: Matt Roper
This patch introduces initial gt workarounds for the MTL platform.
v2: drop redundant/stale comments specifying wa platforms affected
(Lucas).
v3: drop additional redundant stale comments (MattR)
Bspec: 66622
Signed-off-by: Matt Roper
Signed-off-by: Matt Atwood
---
drivers
From: Jouni Högander
This patch introduces initial workarounds for mtl platform
v2: switch IS_MTL_DISPLAY_STEP to use IS_METEORLAKE from testing display
ver. (Tvrtko)
Bspec: 66624
Signed-off-by: Matt Atwood
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4
From: Jouni Högander
This patch introduces initial workarounds for mtl platform
v2: switch IS_MTL_DISPLAY_STEP to use IS_METEORLAKE from testing display
ver. (Tvrtko)
v3: clerical issues, extend 16015201720 to mtl.
Bspec: 66624
Signed-off-by: Matt Atwood
Signed-off-by: Jouni Högander
On Fri, Dec 02, 2022 at 11:00:29AM -0800, Matt Roper wrote:
> On Fri, Dec 02, 2022 at 08:51:43AM -0800, Matt Atwood wrote:
> > From: Jouni Högander
> >
> > This patch introduces initial workarounds for mtl platform
>
> It looks like this patch is only dealing
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