[Intel-gfx] [PATCH v4 2/6] drm/i915: HDMI pixel clock check

: - removed computation for max dot clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk - check for stereo mode added Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_hdmi.c | 8 1 file changed, 8 inse

[Intel-gfx] [PATCH v4 5/6] drm/i915: CRT pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_crt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/g

[Intel-gfx] [PATCH v4 6/6] drm/i915: TV pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_tv.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/dr

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty status check

On Fri, 2015-12-04 at 19:47 +0530, Deepak M wrote: > From: Gaurav K Singh <gaurav.k.si...@intel.com> > > After sending SHUTDOWN or TURN ON packet,check the DPI > FIFO empty status. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Gaurav K S

Re: [Intel-gfx] [BXT MIPI PATCH 1/2] drm/i915: Set the Z inversion overlap field for BXT

On Wed, 2015-12-09 at 17:29 +0530, Deepak M wrote: > For broxton dual link Z-inversion overlap field is present > in MIPI_CTRL register unlike the other platforms, hence > setting the same in this patch. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-of

Re: [Intel-gfx] [BXT DSI timing fixes v1 3/3] drm/i915/bxt: Fixed dsi enc disable and blank at bootup

I applied this patch for testing BXT-M I received this error message [ 16.276906] Hardware name: Intel Corp. Broxton M/RVP, BIOS BXTM_IFWI_X64_R_2015_49_2_03 11/25/2015 [ 16.286793] task: 8801795a2640 ti: 88017830 task.ti: 88017830 [ 16.295047] RIP: 0010:[] []

Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe timing for BXT DSI

On Mon, 2015-10-12 at 22:55 +0530, Uma Shankar wrote: > For BXT DSI, vtotal, vactive, hactive registers are different. > Making changes to intel_crtc_mode_get() and get_pipe_timings(), > to read the correct registers for BXT DSI. > Tested-by: Mika Kahola <mika.kah...@intel.co

[Intel-gfx] [PATCH i-g-t] tools/intel_bios_reader: Fix typo on dump info

Fix typo on intel_bios_reader.c Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- tools/intel_bios_reader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c index b31f648..5ca50ff 100644 --- a/tools/intel_bios_re

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: move VBT based TV presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h |

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: hide away VBT private data in a separate header

ivate header only to be included from intel_bios.c. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > Documentation/DocBook/gpu.tmpl| 2 +- > drivers/gpu/drm/i915/intel_bios.c | 2

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: move VBT based eDP port check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h |

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: move VBT based DSI presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: move VBT based LVDS presence check to intel_bios.c

On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote: > Hide knowledge about VBT child devices in intel_bios.c. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h |

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsi: lose the loose 666 format name in favor of packed

bpp. > > Follow suit with what's in enum mipi_dsi_pixel_format to avoid future > confusion. Rename > > VID_MODE_FORMAT_RGB666 -> VID_MODE_FORMAT_RGB666_PACKED > VID_MODE_FORMAT_RGB666_LOOSE -> VID_MODE_FORMAT_RGB666 > Tested-by: Mika Kahola <mika.kah...@intel.com&

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsi: start using enum mipi_dsi_pixel_format

orth conversion with the VBT -> enum -> > register, since we have just shoved the VBT value into the register > directly. Longer term, all the VBT parsing and deciphering should be > done in intel_bios.c, and abstracted there. > Tested-by: Mika Kahola <mika.kah...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915/bios: Fix the sequence size calculations for MIPI seq v3

e it clearer. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Reported-by: Mika Kahola <mika.kah...@intel.com> > Fixes: 2a33d93486f2 ("drm/i915/bios: add support for MIPI sequence block v3")

Re: [Intel-gfx] [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

On Mon, 2016-01-04 at 18:44 +0200, Ville Syrjälä wrote: > On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote: > > Don't use DP link training optimization if channel EQ is not ok. It has > > been reported that in case of failure in channel EQ check the link training >

[Intel-gfx] [PATCH v6 2/3] drm/i915: Check DP no aux transaction bit on link training

i?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dp_link_training.c | 19 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 21 insertions(+), 1 deletio

[Intel-gfx] [PATCH v6 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

(Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3137187..c

[Intel-gfx] [PATCH v6 0/3] drm/i915: Disable link training optimization if DP config has changed

These three patches are fixes for DP link trainging failures and flickering issues reported by https://bugs.freedesktop.org/show_bug.cgi?id=91393 Mika Kahola (3): drm/i915: Disable fast link training if DP config changes drm/i915: Check DP no aux transaction bit on link training drm/i915

[Intel-gfx] [PATCH v6 1/3] drm/i915: Disable fast link training if DP config changes

/show_bug.cgi?id=91393 Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 5 + drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a

Re: [Intel-gfx] [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

On Mon, 2016-01-04 at 18:53 +0200, Ville Syrjälä wrote: > On Mon, Jan 04, 2016 at 06:44:09PM +0200, Ville Syrjälä wrote: > > On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote: > > > Don't use DP link training optimization if channel EQ is not ok. It has > > >

Re: [Intel-gfx] [PATCH v5 2/2] drm/i915: Check DP no aux transaction bit on link training

On Mon, 2016-01-04 at 18:27 +0100, Thierry Reding wrote: > On Tue, Dec 22, 2015 at 04:53:41PM +0100, Lukas Wunner wrote: > > Hi Mika, > > > > On Mon, Dec 21, 2015 at 01:39:15PM +0200, Mika Kahola wrote: > > > Check if no AUX transactions are required on DP link trai

Re: [Intel-gfx] [PATCH v5 1/3] drm/i915: Disable fast link training if DP config changes

On Mon, 2016-01-04 at 18:42 +0200, Ville Syrjälä wrote: > On Mon, Jan 04, 2016 at 01:21:22PM +0200, Mika Kahola wrote: > > Disable DP link training optimization if DP link configuration > > changes. If one of the DP link parameters i.e. link rate or > > lane count changes t

[Intel-gfx] [PATCH v5 2/3] drm/i915: Check DP no aux transaction bit on link training

Check if no AUX transactions are required on DP link training. If this bit is set, we can reuse the known good drive current and pre-emphasis level from the last "full" link training. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah

[Intel-gfx] [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3137187..0cd1ccb 100644 --- a/drivers/g

[Intel-gfx] [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

These three patches are fixes for DP link trainging failures and flickering issues reported by Mika Kahola (3): drm/i915: Disable fast link training if DP config changes drm/i915: Check DP no aux transaction bit on link training drm/i915: DP channel EQ check for use of DP link training

[Intel-gfx] [PATCH v5 1/3] drm/i915: Disable fast link training if DP config changes

parameters. Instead, disable fast link training feature when link parameters are set (Ville) v2: Readout DPCD register to check if no aux handshaking is required in link training (Ander) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.

Re: [Intel-gfx] [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

On Mon, 2016-01-04 at 13:11 +0100, Maarten Lankhorst wrote: > Op 04-01-16 om 12:21 schreef Mika Kahola: > > These three patches are fixes for DP link trainging failures and flickering > > issues > > reported by > Did your message get accidentally truncated here? It

Re: [Intel-gfx] [PATCH v5 2/2] drm/i915: Check DP no aux transaction bit on link training

On Tue, 2015-12-22 at 16:53 +0100, Lukas Wunner wrote: > Hi Mika, > > On Mon, Dec 21, 2015 at 01:39:15PM +0200, Mika Kahola wrote: > > Check if no AUX transactions are required on DP link training. > > If this bit is set, we can reuse the known good drive current > >

Re: [Intel-gfx] [PATCH 12/12] drm/i915: Calculate visibility in check_plane correctly regardless of dpms.

s enabled but not active run check_plane as if it were on, > but afterwards set plane_state->visible = false for the checks. > Reviewed-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> > --- > driver

[Intel-gfx] [PATCH v5 2/2] drm/i915: Check DP no aux transaction bit on link training

Check if no AUX transactions are required on DP link training. If this bit is set, we can reuse the known good drive current and pre-emphasis level from the last "full" link training. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah

[Intel-gfx] [PATCH v5 1/2] drm/i915: Disable fast link training if DP config changes

parameters. Instead, disable fast link training feature when link parameters are set (Ville) v2: Readout DPCD register to check if no aux handshaking is required in link training (Ander) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.

[Intel-gfx] [PATCH v5 0/2] drm/i915: Disable link training optimization if DP config has changed

These two patches are fixes for DP link trainging failures and flickering issues reported by Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Mika Kahola (2): drm/i915: Disable fast link training if DP config changes drm/i915: Check DP no aux transaction bit on link training

Re: [Intel-gfx] [PATCH 11/12] drm/i915: Keep track of the cdclk as if all crtc's were active.

_scale. The fix is to keep a atomic_cdclk that would be true > if all crtc's were active. > > This is required to get the same calculations done correctly regardless > of dpms mode. > Reviewed-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Maarten Lankh

Re: [Intel-gfx] [PATCH v4] drm/i915: Disable fast link training if DP config changes

On Thu, 2015-12-17 at 15:16 +0200, Ville Syrjälä wrote: > On Thu, Dec 17, 2015 at 02:46:03PM +0200, Mika Kahola wrote: > > Disable DP fast link training if DP link configuration > > changes. If one of the DP link parameters i.e. link > > bandwidth, lane count, rate selecti

[Intel-gfx] [PATCH v4] drm/i915: Disable fast link training if DP config changes

if no aux handshaking is required in link training (Ander) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 8 +++- drivers/gpu/drm/i915/intel_dp_link_training.c | 17 + drivers/gpu/drm/i915/intel_drv.h |

Re: [Intel-gfx] [PATCH 11/11] drm/i915/opregion: handle VBT sizes bigger than 6 KB

#4 otherwise. > Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_opregion.c | 25 +++-- > 2 files changed, 24 ins

[Intel-gfx] [PATCH v3] drm/i915: Disable fast link training if DP config changes

training is started with zero values. v3: Remove cached old link parameters. Instead, disable fast link training feature when link parameters are set (Ville) v2: Readout DPCD register to check if no aux handshaking is required in link training (Ander) Signed-off-by: Mika Kahola <mika.

Re: [Intel-gfx] [PATCH v3] drm/i915: Disable fast link training if DP config changes

On Wed, 2015-12-16 at 14:41 +0200, Ville Syrjälä wrote: > On Wed, Dec 16, 2015 at 02:26:58PM +0200, Mika Kahola wrote: > > Disable DP fast link training if DP link configuration > > changes. If one of the DP link parameters i.e. link > > bandwidth, lane count, rate selecti

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Do not acquire crtc state to check clock during modeset, v3.

On Tue, 2015-12-15 at 10:26 +, Chris Wilson wrote: > On Tue, Dec 15, 2015 at 12:22:40PM +0200, Mika Kahola wrote: > > On Tue, 2015-11-24 at 11:29 +0100, Maarten Lankhorst wrote: > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > > b/drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Do not acquire crtc state to check clock during modeset, v3.

crtc_state->base.active; > + > + if (crtc_state->base.active) { > + dev_priv->active_crtcs |= 1 << crtc->pipe; > + > + if (IS_BROADWELL(dev_priv)) { > + pixclk = ilk_pipe_pixel_rate(crt

Re: [Intel-gfx] [PATCH 1/4] drm/i915/skl: Do not allow scaling when crtc is disabled.

handling a null crtc_state, with all transitional helpers > gone this can no longer happen. > Reviewed-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- >

Re: [Intel-gfx] [MIPI SEQ PARSING v3 01/13] drm/i915: Adding the parsing logic for the i2c element

ni), rebase > v3: corrected the retry loop(Jani), rebase > > Cc: Jani Nikula <jani.nik...@intel.com> Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: vkorjani <vikas.korj...@intel.com> > Signed-off-by: Deepak M <m.dee...@intel.com> > --- >

Re: [Intel-gfx] [MIPI SEQ PARSING v3 02/13] drm/i915: Updating asle structure with new fields

On Tue, 2015-12-01 at 04:17 +0530, Deepak M wrote: > v3: rebase > > Cc: Jani Nikula <jani.nik...@intel.com> Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Deepak M <m.dee...@intel.com> > --- > drivers/gpu/drm/i915/intel_opregion.c | 4 +++- &

Re: [Intel-gfx] [MIPI SEQ PARSING v3 03/13] drm/i915: Add Intel opregion mailbox 5 structure

t; Cc: Jani Nikula <jani.nik...@intel.com> Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Deepak M <m.dee...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_opregion.c | 9 + > 2 files changed, 10 i

Re: [Intel-gfx] [MIPI SEQ PARSING v3 05/13] drm/i915: Add debug entry to get the opregion VBT blob

d way where we get the complete > opregion dump and pick the VBT from the dump wrt to > the VBT offset. > > Cc: Jani Nikula <jani.nik...@intel.com> Tested-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Deepak M <m.dee...@intel.com>

Re: [Intel-gfx] [MIPI SEQ PARSING v3 04/13] drm/i915: Do opregion VBT validation during opregion setup

On Tue, 2015-12-01 at 04:17 +0530, Deepak M wrote: > Calling the validate_vbt before assiging the opregion vbt blob. > Size of the VBT blob cant be more than 6KB when VBT is present > in mailbox 4. > > Cc: Jani Nikula <jani.nik...@intel.com> Tested-by: Mika Kahola <mika.ka

Re: [Intel-gfx] [MIPI SEQ PARSING v3 06/13] drm/i915: Parsing VBT if size of VBT exceeds 6KB

When testing this patch on my BXT-M I received this error message Hardware name: Intel Corp. Broxton M/RVP, BIOS BXTM_IFWI_X64_R_2015_49_2_03 11/25/2015 [0.00] [ cut here ] [0.00] WARNING: CPU: 0 PID: 0 at drivers/iommu/dmar.c:829

[Intel-gfx] [PATCH v2] drm/i915: Disable fast link training if DP config changes

training is started with zero values. v2: Readout DPCD register to check if no aux handshaking is required in link training (Ander) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c

Re: [Intel-gfx] [PATCH] drm/i915: fix fdi related fifo underruns on hsw

ns on ILK-IVB > > we also need to make sure cpu fifo underrun reporting is disabled when > enabling the fdi rx/tx and pch transcoder But somehow this is > only needed when enabling, not also when disabling. > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Signed-off-by: Dan

Re: [Intel-gfx] [PATCH] drm/i915: fix fdi related fifo underruns on hsw

ns on ILK-IVB > > we also need to make sure cpu fifo underrun reporting is disabled when > enabling the fdi rx/tx and pch transcoder But somehow this is > only needed when enabling, not also when disabling. > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Si

[Intel-gfx] [PATCH] drm/i915: Disable FLT if DP config changes

training is started with zero values. The patch is fix for reported screen flickering issue in https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 6 ++ drivers/gpu/dr

[Intel-gfx] [PATCH] drm/i915: Make DP fast link training a module parameter

more conservative approach this feature is disabled by default. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_params.c| 4 drivers/gpu/drm/i915/intel_dp_link_training.c | 11

Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Add HDMI aspect ratio property for SDVO

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Fri, 2015-09-25 at 16:39 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Handle the HDMI aspect ratio property the same way in the SDVO code > as we handle it i

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always use crtc_ timings when dealing with adjustead_mode

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Fri, 2015-09-25 at 16:38 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The adjustead_mode crtc_ timings are what we will program into the hardware, > so it's

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Fri, 2015-09-25 at 16:37 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Rename the function argument to 'adjusted_mode' whenever the function > only ever gets

[Intel-gfx] [PATCH v2] drm/i915: Add CD and pixel clock information

-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5615d3d..3832699 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drive

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add max DOT clock frequency to debugfs

On Thu, 2015-09-24 at 23:49 +0300, Ville Syrjälä wrote: > On Thu, Sep 24, 2015 at 02:28:41PM +0300, Mika Kahola wrote: > > Information on maximum supported pixel clock frequency to > > i915_frequency_info. > > > > Signed-off-by: Mika Kahola <mika.kah...@intel.com

[Intel-gfx] [PATCH 1/3] drm/i915: Add current CD clock frequency to debugfs

Add information on current CD clock frequency to debugfs 'i915_frequency_info' Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/dr

[Intel-gfx] [PATCH 3/3] drm/i915: Add max DOT clock frequency to debugfs

Information on maximum supported pixel clock frequency to i915_frequency_info. Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_deb

[Intel-gfx] [PATCH 2/3] drm/i915: Add max CD clock to debugfs

This adds information on maximum supported CD clock frequency to debugfs 'i915_frequency_info' Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/g

[Intel-gfx] [PATCH 0/3] drm/i915: Add CD and pixel clock information

These patches add information of current and maximum CD clock frequency and pixel clock frequency information on 'i915_debugfs.c'. Mika Kahola (3): drm/i915: Add current CD clock frequency to debugfs drm/i915: Add max CD clock to debugfs drm/i915: Add max DOT clock frequency to debugfs

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Always call the adjusted mode 'adjusted_mode'

coccinelle does a fine job on renaming the variables. Although, it does break the rule of 80 character line width. Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@lin

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Use intel_panel for DVO fixed mode handling

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Replace intel_dvo->panel_fixed_mode with the appropriate intel_panel > stuff. Now all c

Re: [Intel-gfx] [PATCH 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rename the function argument to 'adjusted_mode' whenever the function > only ever gets passed the adjusted_mode. > > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Move HDMI aspect ratio setup to .compute_config()

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > We shouldn't frob adjusted_mode after .compute_config(), so move the > info

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Constify adjusted_mode

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Make adjusted_mode const whereever we don't have to modify it. This only > covers ca

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Always use crtc_ timings when dealing with adjustead_mode

Reviewed-by: Mika Kahola <mika.kah...@intel.com> On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The adjustead_mode crtc_ timings are what we will program into the hardware, > so it's

Re: [Intel-gfx] [PATCH 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

On Tue, 2015-09-08 at 13:40 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rename the function argument to 'adjusted_mode' whenever the function > only ever gets passed the adjusted_mode. > What was the reason why we need to rename the

Re: [Intel-gfx] [PATCH v5 4/4] drm/i915: DVO pixel clock check

On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote: On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH for v4.2] Revert drm/i915: Allow parsing of variable size child device entries from VBT

On Tue, 2015-08-18 at 09:58 -0700, Daniel Vetter wrote: On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula jani.nik...@intel.com wrote: This reverts commit 047fe6e6db9161e69271f56daaafdaf2add023b1 Author: David Weinehall david.weineh...@linux.intel.com Date: Tue Aug 4 16:55:52 2015 +0300

[Intel-gfx] [PATCH v5 3/4] drm/i915: DSI pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk - moved dot clock checking inside 'if (fixed_mode)' V5: - dot clock checked against fixed_mode clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers

[Intel-gfx] [PATCH v5 2/4] drm/i915: LVDS pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - moved supported dotclock check from mode_valid() to intel_lvds_init() V5: - dotclock check moved back to mode_valid() function - dotclock check for fixed mode Signed-off-by: Mika Kahola mika.kah

[Intel-gfx] [PATCH v5 1/4] drm/i915: Store max dotclock

() the rounding method changed from round up to round down when computing max dotclock V4: - Haswell and Broadwell supports now dot clocks up to max CD clock frequency Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH v5 4/4] drm/i915: DVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - clock check against max dotclock moved inside 'if (fixed_mode)' V5: - dot clock check against fixed_mode clock when available Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v5 0/4] Check pixel clock when setting mode

is renamed as max_dotclk throughout the whole series V5: - remaining tweaks for dotclock max frequency computation (HSW and BDW) and LVDS, DSI, and DVO fixes based on Ville's comments Thanks Ville for reviewing the rest of the series! Mika Kahola (4): drm/i915: Store max dotclock drm/i915: LVDS

Re: [Intel-gfx] [PATCH v4 00/11] Check pixel clock when setting mode

On Fri, 2015-08-14 at 15:13 +0200, Daniel Vetter wrote: On Fri, Aug 14, 2015 at 01:03:20PM +0300, Mika Kahola wrote: From EDID we can read and request higher pixel clock than our HW can support. This set of patches add checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH v4 04/11] drm/i915: LVDS pixel clock check

On Fri, 2015-08-14 at 16:09 +0300, Ville Syrjälä wrote: On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH v4 01/11] drm/i915: Store max dotclock

On Fri, 2015-08-14 at 15:55 +0300, Ville Syrjälä wrote: On Fri, Aug 14, 2015 at 01:03:21PM +0300, Mika Kahola wrote: Store max dotclock into dev_priv structure so we are able to filter out the modes that are not supported by our platforms. V2: - limit the max dot clock frequency

[Intel-gfx] [PATCH v4 08/11] drm/i915: TV pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_tv.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 10/11] drm/i915: DVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - clock check against max dotclock moved inside 'if (fixed_mode)' Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Intel-gfx] [PATCH v4 09/11] drm/i915: DisplayPort-MST pixel clock check

MST. V2: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp_mst.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Intel-gfx] [PATCH v4 07/11] drm/i915: CRT pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_crt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 11/11] drm/i915: Max DOT clock frequency to debugfs

Information on maximum supported DOT clock frequency to i915_frequency_info. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH v4 05/11] drm/i915: SDVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_sdvo.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v4 01/11] drm/i915: Store max dotclock

() the rounding method changed from round up to round down when computing max dotclock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 19 +++ 2 files changed, 20 insertions(+) diff --git

[Intel-gfx] [PATCH v4 02/11] drm/i915: DisplayPort pixel clock check

. V2: - removed computation for max DOT clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk renamed as max_dotclk Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH v4 06/11] drm/i915: DSI pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk - moved dot clock checking inside 'if (fixed_mode)' Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dsi.c | 3 +++ 1 file changed

[Intel-gfx] [PATCH v4 04/11] drm/i915: LVDS pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines V4: - moved supported dotclock check from mode_valid() to intel_lvds_init() Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_lvds.c | 15 +++ 1 file changed, 11

[Intel-gfx] [PATCH v4 03/11] drm/i915: HDMI pixel clock check

: - removed computation for max dot clock V3: - cleanup by removing unnecessary lines V4: - max_pixclk variable renamed as max_dotclk - check for stereo mode added Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 8 1 file changed, 8 insertions

[Intel-gfx] [PATCH v4 00/11] Check pixel clock when setting mode

is renamed as max_dotclk throughout the whole series Mika Kahola (11): drm/i915: Store max dotclock drm/i915: DisplayPort pixel clock check drm/i915: HDMI pixel clock check drm/i915: LVDS pixel clock check drm/i915: SDVO pixel clock check drm/i915: DSI pixel clock check drm/i915: CRT pixel

Re: [Intel-gfx] [PATCH v3 01/11] drm/i915: Store max dotclock

On Wed, 2015-08-12 at 22:01 +0300, Ville Syrjälä wrote: On Wed, Aug 12, 2015 at 08:30:23PM +0300, Ville Syrjälä wrote: On Fri, Jul 31, 2015 at 03:13:50PM +0300, Mika Kahola wrote: Store max dotclock into dev_priv structure so we are able to filter out the modes that are not supported

Re: [Intel-gfx] [BUGFIX] drm/i915: Fix for VBT expected size

On Wed, 2015-08-12 at 15:43 +0200, Daniel Vetter wrote: On Wed, Aug 12, 2015 at 04:42:53PM +0300, Jani Nikula wrote: On Wed, 12 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote: On Tue, Aug 11, 2015 at 04:49:33PM +0300, Mika Kahola wrote: Depending on the VBT BDB version the maximum size

[Intel-gfx] [BUGFIX] drm/i915: Fix for VBT expected size

Depending on the VBT BDB version the maximum size can be up to 38 bytes. This fix increases the maximum of the VBT expected size from 33 bytes to 38 bytes and by doing so cures the kernel hang on BSW box. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_bios.h | 2

[Intel-gfx] [PATCH v3 01/11] drm/i915: Store max dotclock

for the older gens - for Cherryview the max dot clock frequency is limited to 95% of the max CD clock frequency - for gen2 and gen3 the max dot clock limit is set to 90% of the 2X max CD clock frequency Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1

[Intel-gfx] [PATCH v3 08/11] drm/i915: TV pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_tv.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index

[Intel-gfx] [PATCH v3 02/11] drm/i915: DisplayPort pixel clock check

. V2: - removed computation for max DOT clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm

[Intel-gfx] [PATCH v3 05/11] drm/i915: SDVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_sdvo.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 10/11] drm/i915: DVO pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c

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