[Intel-gfx] [PATCH v3 00/11] Check pixel clock when setting mode

% of the 2X CD clock frequency as we have on option to use double wide mode - cleanup Mika Kahola (11): drm/i915: Store max dotclock drm/i915: DisplayPort pixel clock check drm/i915: HDMI pixel clock check drm/i915: LVDS pixel clock check drm/i915: SDVO pixel clock check drm/i915: DSI pixel

[Intel-gfx] [PATCH v3 03/11] drm/i915: HDMI pixel clock check

: - removed computation for max dot clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c

[Intel-gfx] [PATCH v3 11/11] drm/i915: Max DOT clock frequency to debugfs

Information on maximum supported DOT clock frequency to i915_frequency_info. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH v3 04/11] drm/i915: LVDS pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_lvds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 06/11] drm/i915: DSI pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c

[Intel-gfx] [PATCH v3 09/11] drm/i915: DisplayPort-MST pixel clock check

MST. V2: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp_mst.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm

[Intel-gfx] [PATCH v3 07/11] drm/i915: CRT pixel clock check

: - removed computation for max pixel clock V3: - cleanup by removing unnecessary lines Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_crt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c

[Intel-gfx] [PATCH v2 02/11] drm/i915: DisplayPort pixel clock check

. V2: - removed computation for max DOT clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 44f8a32..89a150d

[Intel-gfx] [PATCH v2 01/11] drm/i915: Store max dotclock

Store max dotclock into dev_priv structure so we are able to filter out the modes that are not supported by our platforms. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 20 2 files

[Intel-gfx] [PATCH v2 06/11] drm/i915: DSI pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dsi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 18dd7d7..2882978 100644 --- a/drivers

[Intel-gfx] [PATCH v2 09/11] drm/i915: DisplayPort-MST pixel clock check

MST. V2: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp_mst.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 585f0a4

[Intel-gfx] [PATCH v2 10/11] drm/i915: DVO pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index fd5e522..7afcfa4 100644 --- a/drivers

[Intel-gfx] [PATCH v2 11/11] drm/i915: Max DOT clock frequency to debugfs

Information on maximum supported DOT clock frequency to i915_frequency_info. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH v2 05/11] drm/i915: SDVO pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_sdvo.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 2c435a7..753b670 100644

[Intel-gfx] [PATCH v2 08/11] drm/i915: TV pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_tv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 8b9d325..0990f22 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH v2 00/11] Check pixel clock when setting mode

, SDVO, DSI, CRT, TV, and DP-MST. V2: - The maximum DOT clock frequency is added to debugfs i915_frequency_info. - max dotclock cached in dev_priv structure - moved computation of max dotclock to 'intel_display.c' Mika Kahola (11): drm/i915: Store max dotclock drm/i915: DisplayPort pixel clock

[Intel-gfx] [PATCH v2 07/11] drm/i915: CRT pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_crt.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 5d78c1f..6e29bce 100644

[Intel-gfx] [PATCH v2 04/11] drm/i915: LVDS pixel clock check

: - removed computation for max pixel clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_lvds.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index cb634f4..5648295 100644

[Intel-gfx] [PATCH v2 03/11] drm/i915: HDMI pixel clock check

: - removed computation for max dot clock Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 70bad5b..b85efaa

Re: [Intel-gfx] [PATCH v2 06/11] drm/i915: DSI pixel clock check

On Thu, 2015-07-30 at 07:52 +0100, Chris Wilson wrote: On Thu, Jul 30, 2015 at 09:49:33AM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Store max dotclock

On Thu, 2015-07-30 at 08:00 +0100, Chris Wilson wrote: On Thu, Jul 30, 2015 at 09:49:28AM +0300, Mika Kahola wrote: Store max dotclock into dev_priv structure so we are able to filter out the modes that are not supported by our platforms. Signed-off-by: Mika Kahola mika.kah

Re: [Intel-gfx] [PATCH v2 03/11] drm/i915: HDMI pixel clock check

On Thu, 2015-07-30 at 07:54 +0100, Chris Wilson wrote: On Thu, Jul 30, 2015 at 09:49:30AM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Check pixel clock when setting mode for DP

On Fri, 2015-07-03 at 15:57 +0300, Ville Syrjälä wrote: On Fri, Jul 03, 2015 at 02:35:49PM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Check pixel clock when setting mode for DSI

On Fri, 2015-07-03 at 13:38 +0100, Chris Wilson wrote: On Fri, Jul 03, 2015 at 02:35:54PM +0300, Mika Kahola wrote: It is possible the we request to have a mode that has higher pixel clock than our HW can support. This patch checks if requested pixel clock is lower than the one supported

[Intel-gfx] [PATCH 7/9] drm/i915: Check pixel clock when setting mode for CRT

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_crt.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 521af2c..0980f32 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/9] drm/i915: Check pixel clock when setting mode for DP

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fcc64e5..2e55dff 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 9/9] drm/i915: Check pixel clock when setting mode for DP-MST

MST. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp_mst.c | 28 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 6e4cc53..0fb9a3d 100644 --- a/drivers

[Intel-gfx] [PATCH 0/9] drm/i915: Check pixel clock when setting mode

, SDVO, DSI, CRT, TV, and DP-MST. Mika Kahola (9): drm/i915: Check pixel clock when setting mode for DP drm/i915: Check pixel clock when setting mode for HDMI drm/i915: Check pixel clock when setting mode for LVDS drm/i915: Check pixel clock when setting mode for DVO drm/i915: Check pixel

[Intel-gfx] [PATCH 6/9] drm/i915: Check pixel clock when setting mode for DSI

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dsi.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 98998e9..1cf35b8 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c

[Intel-gfx] [PATCH 3/9] drm/i915: Check pixel clock when setting mode for LVDS

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_lvds.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index ea85547..3280413 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c

[Intel-gfx] [PATCH 2/9] drm/i915: Check pixel clock when setting mode for HDMI

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 00c4b40..1886cd4c 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 4/9] drm/i915: Check pixel clock when setting mode for DVO

. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dvo.c | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index ece5bd7..82cbcea 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 8/9] drm/i915: Check pixel clock when setting mode for TV

-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_tv.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 8b9d325..076c1c1 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b

Re: [Intel-gfx] [PATCH v6 7/8] drm/i915: BDW clock change support

On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote: On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote: On Tue, 16 Jun 2015, Jani Nikula jani.nik...@linux.intel.com wrote: On Wed, 03 Jun 2015, Mika Kahola mika.kah...@intel.com wrote: From: Ville Syrjälä ville.syrj

[Intel-gfx] [PATCH 0/3] Broadwell atomic CD clock

This patch series add support for atomic mode setting for Broadwell platform. In addition, the max CD clock computation is unified into one function 'intel_mode_max_pixclk()'. The modeset for global pipes is proposed to be computed in a single function 'intel_modeset_global_pipes()' Mika Kahola

[Intel-gfx] [PATCH 3/3] drm/i915: Unify modesetting for global pipes

Combine global pipe modesetting for Valleyview, Broxton, and Broadwell. This removes some of the repetitive code that exists in routines 'valleyview_modeset_global_pipes()' and 'broadwell_modeset_global_pipes()'. The naming changed to 'intel_modeset_global_pipes()'. Signed-off-by: Mika Kahola

[Intel-gfx] [PATCH 1/3] drm/i915: Broadwell modeset global pipes to atomic

Convert 'broadwell_modeset_global_pipes()' into atomic mode setting. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b

[Intel-gfx] [PATCH 2/3] drm/i915: Max CD clock for Broadwell

Max CD clock for Broadwell platform is added to 'intel_mode_max_pixclk()' function. This patch removes the need for 'ilk_max_pixel_rate()' function. Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 45 +++- 1 file changed

[Intel-gfx] [PATCH v3] Limit CHV max cdclk

For Cherryview the CD clock is limited up to 320MHz. Based on the received comments, I cleaned up the if-else tree. Mika Kahola (1): drm/i915: Limit CHV max cdclk drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.9.1

[Intel-gfx] [PATCH v3] drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz. v2: Rebase to the latest v3: Clean up of if-else tree Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v2] drm/i915: Limit CHV max cdclk

On Thu, 2015-06-11 at 12:03 +0300, Jani Nikula wrote: On Thu, 11 Jun 2015, Mika Kahola mika.kah...@intel.com wrote: Limit CHV maximum cdclk to 320MHz. v2: Rebase to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file

[Intel-gfx] [PATCH v2] Limit CHV max cdclk

For Cherryview the CD clock is limited up to 320MHz. Mika Kahola (1): drm/i915: Limit CHV max cdclk drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz. v2: Rebase to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH v5 1/8] drm/i915: Cache current cdclk frequency in dev_priv

On Tue, 2015-06-02 at 18:17 +0300, Jani Nikula wrote: On Tue, 02 Jun 2015, Mika Kahola mika.kah...@intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Rather that extracting the current cdclk freuqncy every time someone wants to know it, cache the current value and use

[Intel-gfx] [PATCH v6 2/8] drm/i915: Use cached cdclk value

Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_dp.c | 5 +++-- drivers/gpu/drm/i915/intel_pm.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions

[Intel-gfx] [PATCH v6 5/8] drm/i915: Don't enable IPS when pixel rate exceeds 95%

Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 30 -- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH v6 6/8] drm/i915: Add IS_BDW_ULX

From: Ville Syrjälä ville.syrj...@linux.intel.com We need to tell BDW ULT and ULX apart. v2: Rebased to the latest v3: Rebased to the latest v4: Fix for patch style problems Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com Author

[Intel-gfx] [PATCH v6 8/8] drm/i915: HSW cdclk support

Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c | 137 ++- 2 files changed, 136

[Intel-gfx] [PATCH v6 4/8] drm/i915: Store max cdclk value in dev_priv

to assume cdclk is fixed. v2: Rebased to the latest v3: Rebased to the latest v4: Fix for patch style problems Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v6 1/8] drm/i915: Cache current cdclk frequency in dev_priv

: Rebased to the latest v4: Rebased to the latest v5: Removed spurious call to 'intel_update_cdclk(dev)' based on Damien Lespiau's comment Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj

[Intel-gfx] [PATCH v6 0/8] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that has already been reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches are rebased to the latest drm-intel-nightly. The major change to the original series is the patch

[Intel-gfx] [PATCH v6 3/8] drm/i915: Unify ilk and hsw .get_aux_clock_divider

-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 23 +++ 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index

[Intel-gfx] [PATCH v5 5/8] drm/i915: Don't enable IPS when pixel rate exceeds 95%

to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 30 -- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 17 - 3

[Intel-gfx] [PATCH v5 4/8] drm/i915: Store max cdclk value in dev_priv

to assume cdclk is fixed. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu

[Intel-gfx] [PATCH v5 6/8] drm/i915: Add IS_BDW_ULX

From: Ville Syrjälä ville.syrj...@linux.intel.com We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj

[Intel-gfx] [PATCH v5 7/8] drm/i915: BDW clock change support

order shuffle so that Broadwell CD clock change is applied before the patch for Haswell CD clock change Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v5 3/8] drm/i915: Unify ilk and hsw .get_aux_clock_divider

From: Ville Syrjälä ville.syrj...@linux.intel.com ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Signed-off-by: Mika Kahola mika.kah

[Intel-gfx] [PATCH v5 1/8] drm/i915: Cache current cdclk frequency in dev_priv

ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest v4: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 26 +- 1 file changed

[Intel-gfx] [PATCH v5 8/8] drm/i915: HSW cdclk support

patch Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_display.c | 137 ++- 2 files changed, 136 insertions(+), 3 deletions(-) diff

[Intel-gfx] [PATCH v5 2/8] drm/i915: Use cached cdclk value

From: Ville Syrjälä ville.syrj...@linux.intel.com Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Signed-off-by: Mika Kahola

[Intel-gfx] [PATCH v5 0/8] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that has already been reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches are rebased to the latest drm-intel-nightly. The major change to the original series is the patch

[Intel-gfx] [PATCH v4 11/12] drm/i915: Add IS_BDW_ULX

From: Ville Syrjälä ville.syrj...@linux.intel.com We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj

[Intel-gfx] [PATCH v4 07/12] drm/i915: Unify ilk and hsw .get_aux_clock_divider

From: Ville Syrjälä ville.syrj...@linux.intel.com ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah

[Intel-gfx] [PATCH v4 00/12] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that are already reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches are rebased to the latest drm-intel-nightly and while I was doing it I tagged the reviewed-by. Maybe

[Intel-gfx] [PATCH v4 04/12] drm/i915: Warn when cdclk for the platforms is not known

that they have to provide this function for new platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 12/12] drm/i915: BDW clock change support

-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 139 ++- 2 files changed, 122 insertions(+), 18 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH v4 06/12] drm/i915: Use cached cdclk value

From: Ville Syrjälä ville.syrj...@linux.intel.com Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola

[Intel-gfx] [PATCH v4 8/8] drm/i915: Store max cdclk value in dev_priv

to assume cdclk is fixed. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu

[Intel-gfx] [PATCH v4 10/12] drm/i915: HSW cdclk support

. .global_resources() reordering Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v3: Rebased to the latest v4: Reformatting 'haswell_modeset_global_pipes' function to support atomic state Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com

[Intel-gfx] [PATCH v4 01/12] drm/i915: Fix i855 get_display_clock_speed

is some of the platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 11

[Intel-gfx] [PATCH v4 05/12] drm/i915: Cache current cdclk frequency in dev_priv

ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 25 ++--- 1 file changed, 18 insertions(+), 7

[Intel-gfx] [PATCH v4 09/12] drm/i915: Don't enable IPS when pixel rate exceeds 95%

to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 30 -- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 17 - 3 files

[Intel-gfx] [PATCH v4 02/12] drm/i915: Fix 852GM/GMV cdclk

, but according to the specs it should work. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 03/12] drm/i915: Add cdclk extraction for g33, g965gm and g4x

of 444 MHz which seems perfectly sane for this machine. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915: CD clock frequency to debugfs

On Mon, 2015-05-04 at 16:18 +0200, Daniel Vetter wrote: On Fri, Apr 24, 2015 at 11:06:10AM +0300, Mika Kahola wrote: This patch adds information on current CD clock frequency to debugfs i915_frequency_info Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 2/2] drm/i915: DP link training optimization

This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase V3: - rebase V4: - when HPD long pulse is received, the flag is cleared that indicates if DP link training is required or not (based on Sivakumar's comment) Signed-off-by: Mika Kahola

[Intel-gfx] [PATCH v4 1/2] drm/i915: DP link training optimization

handling for eDP case to clear the flag that indicates to reuse the current link training parameters. (based on Sivakumar's comment) Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 27 --- drivers/gpu/drm/i915/intel_drv.h | 1 + 2

[Intel-gfx] [PATCH v4 0/2] drm/i915: DP link training optimization

only where we reuse the previously trained link training values from cache i.e. voltage swing and pre-emphasis levels. The second patch is a generalization to cover DP case. Mika Kahola (2): drm/i915: DP link training optimization drm/i915: DP link training optimization drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: DP link training optimization

On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote: On 4/28/2015 12:13 PM, Mika Kahola wrote: This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase V3: - rebase Signed-off-by: Mika Kahola mika.kah...@intel.com

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: DP link training optimization

On Tue, 2015-04-28 at 15:18 +0530, Sivakumar Thulasimani wrote: On 4/28/2015 3:12 PM, Mika Kahola wrote: On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote: On 4/28/2015 1:44 PM, Mika Kahola wrote: On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote: On 4/28/2015

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: DP link training optimization

On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote: On 4/28/2015 1:44 PM, Mika Kahola wrote: On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote: On 4/28/2015 12:13 PM, Mika Kahola wrote: This patch adds DP link training optimization by reusing the previously

[Intel-gfx] [PATCH v3 1/2] drm/i915: DP link training optimization

training parameters are set to zero and training is restarted. V2: - flag that indicates if DP link is trained and valid renamed from 'link_trained' to 'train_set_valid' - removed routine 'intel_dp_reuse_link_train' V3: - rebased against the latest drm-intel-nightly Signed-off-by: Mika Kahola

[Intel-gfx] [PATCH v3 2/2] drm/i915: DP link training optimization

This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase V3: - rebase Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3] drm/i915: DP link training optimization

only where we reuse the previously trained link training values from cache i.e. voltage swing and pre-emphasis levels. The second patch is a generalization to cover all cases. Mika Kahola (1): drm/i915: DP link training optimization drivers/gpu/drm/i915/intel_dp.c | 29

[Intel-gfx] [PATCH] drm/i915: CD clock frequency to debugfs

This patch adds information on current CD clock frequency to debugfs i915_frequency_info Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: CD clock frequency to debugfs

This patch adds information on current CD clock frequency to debugfs 'i915_frequency_info'. Mika Kahola (1): drm/i915: CD clock frequency on debugfs drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ 1 file changed, 3 insertions(+) -- 1.9.1 ___ Intel

[Intel-gfx] [PATCH 10/12] drm/i915: HSW cdclk support

. .global_resources() reordering Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v3: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 12/12] drm/i915: BDW clock change support

that into account when computing the max pixel rate. v2: Grab rps.hw_lock around sandybridge_pcode_write() v3: Rebase due to power well vs. .global_resources() reordering Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v4: Rebased to the latest Signed-off-by: Mika Kahola mika.kah

[Intel-gfx] [PATCH 03/12] drm/i915: Add cdclk extraction for g33, g965gm and g4x

of 444 MHz which seems perfectly sane for this machine. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com V2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3

[Intel-gfx] [PATCH 11/12] drm/i915: Add IS_BDW_ULX

From: Ville Syrjälä ville.syrj...@linux.intel.com We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers

[Intel-gfx] [PATCH 05/12] drm/i915: Cache current cdclk frequency in dev_priv

ville.syrj...@linux.intel.com V2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 40 +++- 2 files

[Intel-gfx] [PATCH 04/12] drm/i915: Warn when cdclk for the platforms is not known

that they have to provide this function for new platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 4 +++- 1

[Intel-gfx] [PATCH 01/12] drm/i915: Fix i855 get_display_clock_speed

is some of the platforms. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 11 --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 07/12] drm/i915: Unify ilk and hsw .get_aux_clock_divider

From: Ville Syrjälä ville.syrj...@linux.intel.com ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville

[Intel-gfx] [PATCH 00/12] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that are already reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches include modifications to Ville Syrjälä (12): drm/i915: Fix i855 get_display_clock_speed drm/i915:

[Intel-gfx] [PATCH 09/12] drm/i915: Don't enable IPS when pixel rate exceeds 95%

pipe_config_supports_ips() (Chris) v3: Compare against the max cdclk insted of the current cdclk Tested-by: Timo Aaltonen tjaal...@ubuntu.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497 Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v4: Rebased to the latest Signed-off-by: Mika

[Intel-gfx] [PATCH 02/12] drm/i915: Fix 852GM/GMV cdclk

, but according to the specs it should work. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1 file

[Intel-gfx] [PATCH 08/12] drm/i915: Store max cdclk value in dev_priv

to assume cdclk is fixed. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author:Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 06/12] drm/i915: Use cached cdclk value

From: Ville Syrjälä ville.syrj...@linux.intel.com Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com v2: Rebased to the latest Signed-off-by: Mika Kahola mika.kah...@intel.com Author

[Intel-gfx] [PATCH 11/14] drm/i915: Add IS_BDW_ULX

We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Mika Kahola mika.kah...@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915

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