Hi Ville,
Thanks for the comments and suggestions. Please find my response inline:
On 3/8/2023 8:56 PM, Ville Syrjälä wrote:
On Wed, Mar 08, 2023 at 05:10:57PM +0200, Ville Syrjälä wrote:
On Mon, Feb 27, 2023 at 09:33:14AM +0530, Ankit Nautiyal wrote:
For YCbCr420 output, scaler is required
Hi Manasi,
I just realized that there is a newer version of the patch in another
series for DSC 420 support [1].
I added this patch when I was debugging an issue with PCON + 8k YCbCr420
only mode, and noticed that we set the output_format first and then
check for DSC.
Later this patch was
Thanks Stan for the review.
On 3/9/2023 4:14 PM, Lisovskiy, Stanislav wrote:
On Thu, Feb 23, 2023 at 05:25:09PM +0530, Ankit Nautiyal wrote:
While computing compressed bpp, maximum value of bits_per_pixel is
calculated that can be supported with the given link configuration
for a given mode.
On 2/17/2023 4:43 AM, Ville Syrjala wrote:
From: Ville Syrjälä
SKL/derivatives have DDI E but no AUX E, so we need to pick
another aux ch as the platform default. DDI E is more or less
the other half of DDI A, so we pick AUX A.
In all other cases we should have a corresponding aux ch for
On 2/17/2023 5:32 PM, Ville Syrjälä wrote:
On Fri, Feb 17, 2023 at 03:15:59PM +0530, Nautiyal, Ankit K wrote:
On 2/17/2023 4:43 AM, Ville Syrjala wrote:
From: Ville Syrjälä
SKL/derivatives have DDI E but no AUX E, so we need to pick
another aux ch as the platform default. DDI E is more
On 2/17/2023 6:42 PM, Ville Syrjälä wrote:
On Fri, Feb 17, 2023 at 06:35:51PM +0530, Nautiyal, Ankit K wrote:
On 2/17/2023 5:32 PM, Ville Syrjälä wrote:
On Fri, Feb 17, 2023 at 03:15:59PM +0530, Nautiyal, Ankit K wrote:
On 2/17/2023 4:43 AM, Ville Syrjala wrote:
From: Ville Syrjälä
SKL
On 2/23/2023 10:50 PM, Ville Syrjälä wrote:
On Tue, Feb 21, 2023 at 02:06:06PM +0530, Nautiyal, Ankit K wrote:
On 2/21/2023 1:07 AM, Ville Syrjälä wrote:
On Mon, Feb 20, 2023 at 05:53:48PM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should
Patch looks good to me.
There are a few nitpicks, typos mentioned inline.
On 2/17/2023 4:43 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Restructure intel_bios_port_aux_ch() to resemble the ddc_pin
counterpart, where the intel_bios.c stuff only deals with the
child device definition, and the
On 2/17/2023 4:43 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Use encoer->name rather than port_name() in the debug messages
typo : encoder
LGTM. encoder->name has sufficient information.
Reviewed-by: Ankit Nautiyal
so that they actually make more sense.
Signed-off-by: Ville Syrjälä
On 2/21/2023 1:07 AM, Ville Syrjälä wrote:
On Mon, Feb 20, 2023 at 05:53:48PM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new member to crtc_state to represent the final
output_format to the
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The macro values just don't match the specs. Fix them.
Fixes: 1482ec00be4a ("drm: Add missing DP DSC extended capability definitions.")
Cc: Vinod Govindapillai
Cc: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
On 4/18/2023 6:16 PM, Ville Syrjälä wrote:
On Mon, Apr 17, 2023 at 03:48:12PM -0700, Manasi Navare wrote:
Hi Ville,
Could you suggest how to handle the intel_dp_link_compute_config()
when the max_bpp is returned as 0, currently
it just exits the loop and returns a -EINVAL and this triggers
On 4/19/2023 10:29 AM, Nautiyal, Ankit K wrote:
On 4/19/2023 4:12 AM, Manasi Navare wrote:
Hi Ville and Ankit,
I actually do not think this is a problem with the DSC logic, but it
is a problem with the intel_dp_link_compute_config() where we should
do something if max_bpp is 0 instead
:
On Tue, Apr 18, 2023 at 08:09:16PM +0530, Nautiyal, Ankit K wrote:
On 4/18/2023 6:16 PM, Ville Syrjälä wrote:
On Mon, Apr 17, 2023 at 03:48:12PM -0700, Manasi Navare wrote:
Hi Ville,
Could you suggest how to handle the intel_dp_link_compute_config()
when the max_bpp is returned as 0, currently
On 4/24/2023 6:39 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:00PM +0530, Ankit Nautiyal wrote:
This series fixes issues faced when an HDMI2.1 sink that does not
support DSC is connected via HDMI2.1PCON. It also includes other minor
HDMI2.1 PCON fixes/refactoring.
Patch 1-2 Have
On 4/24/2023 6:16 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:02PM +0530, Ankit Nautiyal wrote:
New member to store the YCBCR20 Pass through capability of the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
1 file changed, 1
On 4/24/2023 6:21 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:08PM +0530, Ankit Nautiyal wrote:
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For
Hi Ville,
Thanks for pointing out the issues and suggestions.
I agree with the suggested changes and corrections and will make the
changes in the next version.
Regards,
Ankit
On 4/24/2023 6:01 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:03PM +0530, Ankit Nautiyal wrote:
The
On 4/24/2023 6:34 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:13PM +0530, Ankit Nautiyal wrote:
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
On 4/24/2023 6:07 PM, Ville Syrjälä wrote:
On Fri, Mar 31, 2023 at 03:46:05PM +0530, Ankit Nautiyal wrote:
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support
On 3/29/2023 7:14 PM, Lisovskiy, Stanislav wrote:
On Wed, Mar 29, 2023 at 02:35:38PM +0300, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 05:00:55PM +0530, Nautiyal, Ankit K wrote:
On 3/29/2023 4:23 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 04:06:21PM +0530, Nautiyal, Ankit K wrote
On 3/29/2023 5:05 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 05:00:55PM +0530, Nautiyal, Ankit K wrote:
On 3/29/2023 4:23 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 04:06:21PM +0530, Nautiyal, Ankit K wrote:
On 3/29/2023 3:27 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 02
Change looks good to me. I think it will be good to add Fixes tag.
Regards,
Ankit
On 3/27/2023 12:12 PM, Stanislav Lisovskiy wrote:
For obvious reasons, we use compressed bpp instead of pipe bpp for
DSC DP SST case. Lets be consistent and use compressed bpp instead of
pipe bpp, also in DP MST
Hi Suraj,
Thanks for the patch, please find my comments inline:
On 4/3/2023 1:31 PM, Suraj Kandpal wrote:
Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
Workaround: Increase the timeout.
WA: 14017271110
Lets use Wa_ as per convention.
Also I am wondering if we
On 4/4/2023 3:03 AM, Manasi Navare wrote:
On Thu, Mar 30, 2023 at 4:11 AM Nautiyal, Ankit K
wrote:
On 3/29/2023 5:05 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 05:00:55PM +0530, Nautiyal, Ankit K wrote:
On 3/29/2023 4:23 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 04:06:21PM
On 4/6/2023 2:33 PM, Nautiyal, Ankit K wrote:
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville
On 3/29/2023 7:20 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Include the csc matrices in the state dump. The format being
hardware specific we just dump as hex for now. Might have
to think of some way to get a bit more human readable
output...
Yeah if we can read coeff and print in
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Embed a pair of intel_csc_matrix structs in the crtc state,
and fill them out appropriately during atomic_check().
Since pre-ivb platforms don't have programmable post offsets
we shall leave those zeroed, mainly in preparation
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville Syrjälä
---
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Make sure the csc enable bit(s) match the way we're about to
fill the csc matrices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 ++
On 4/6/2023 4:40 PM, Ville Syrjälä wrote:
On Thu, Apr 06, 2023 at 04:26:48PM +0530, Nautiyal, Ankit K wrote:
Hi Ville,
HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
And black level of 4096.
Got me thinking that we might need to consider bpc for getting the
Coeffs
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Introduce a structure that can hold our CSC matrices. In there
we shall have the preoffsets, postoffsets, and coefficients,
all in platform specific format (at least for now).
We shall start by converting the ilk+ code to make
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Convert chv_cgm_csc_convert_ctm() over to using the nee
nitpick: typo: new.
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
intel_csc_matrix structure. No pre/post offsets on this
hardware so only the coefficients get filled
Hi Ville,
HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
And black level of 4096.
Got me thinking that we might need to consider bpc for getting the
Coeffs and the offsets.
IIUC for CSC Full range to Limited range:
out = in * gain + offset
Gain :
So for 8 bpc, as you have
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Read out the csc matrix on chv, and stash the result into the
correct spot in the crtc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:20 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Have the state checker validate that the csc matrices
look correct when read back from the hardware.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Store the chv cgm csc matrix in the crtc state as well. We
shall store it in the same place where we store the ilk+
pipe csc matrix (as opposed to the output csc matrix).
Signed-off-by: Ville Syrjälä
---
Patch LGTM.
Perhaps TODO part, to check for case of PSR and if DC states are already
off can be taken as separate patch.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Read out the pipe/output csc matrices on ilk+ and stash the results
(in the
On 4/11/2023 10:37 AM, Ville Syrjälä wrote:
@@ -294,13 +293,20 @@ static bool ilk_csc_limited_range(const struct
intel_crtc_state *crtc_state)
}
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
- u16 coeffs[9], bool
On 3/29/2023 4:24 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 02:37:45PM +0530, Ankit Nautiyal wrote:
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
Signed-off-by: Ankit Nautiyal
---
On 3/29/2023 3:27 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 02:14:49PM +0530, Ankit Nautiyal wrote:
As per Bspec, Big Joiner BW check is:
Output bpp <= PPC * CDCLK frequency * Big joiner interface bits /
Pixel clock
Currently we always use max_cdclk in the check for both modevalid
and
On 3/29/2023 4:23 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 04:06:21PM +0530, Nautiyal, Ankit K wrote:
On 3/29/2023 3:27 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 02:14:49PM +0530, Ankit Nautiyal wrote:
As per Bspec, Big Joiner BW check is:
Output bpp <= PPC * CDCLK freque
I think we can add fixes tag:
Fixes: 883631771038 ("drm/i915/mtl: Add HDCP GSC interface")
with relevant folks in CC.
Otherwise, LGTM.
Reviewed-by: Ankit Nautiyal
On 5/3/2023 3:42 PM, Suraj Kandpal wrote:
Check if media_gt exists if we are using gsc cs
--v2
-correct typo [Ankit]
-assign
On 6/15/2023 5:24 AM, Pablo Ceballos wrote:
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled",
followed by link training errors. Intel engineers recommended increasing
this timeout and that does resolve the issue.
On some CometLake-based device designs the Parade PS175
On 6/2/2023 4:21 PM, Suraj Kandpal wrote:
Allocate a multipage object that can be used for input
and output for intel_hdcp_gsc_message so that corruption of
output message can be avoided by the current overwriting method.
Modify intel_gsc_send_sync() to take into account header_out
and addr_out
On 6/28/2023 3:38 PM, Stanislav Lisovskiy wrote:
We are currently having FIFO underruns happening for kms_dsc test case,
problem is that, we check if curreny cdclk is >= pixel rate only if
there is a single VDSC engine enabled(i.e dsc_split=false) however if
we happen to have 2 VDSC engines
On 7/3/2023 2:20 PM, Lisovskiy, Stanislav wrote:
On Mon, Jul 03, 2023 at 10:23:00AM +0530, Nautiyal, Ankit K wrote:
On 6/28/2023 3:38 PM, Stanislav Lisovskiy wrote:
We are currently having FIFO underruns happening for kms_dsc test case,
problem is that, we check if curreny cdclk is >= pi
On 7/13/2023 6:17 PM, Jani Nikula wrote:
On Thu, 13 Jul 2023, Suraj Kandpal wrote:
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of
On 7/17/2023 3:39 PM, Suraj Kandpal wrote:
> Use a Macro to clean up intel_dsc_get_pps_reg so that we don't have
> to replicate so many if/else blocks.
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 124 ++
> 1 file changed, 32
On 7/18/2023 2:54 PM, Nautiyal, Ankit K wrote:
> On 7/17/2023 3:39 PM, Suraj Kandpal wrote:
>> Use a Macro to clean up intel_dsc_get_pps_reg so that we don't have
>> to replicate so many if/else blocks.
>>
>> Signed-off-by: Suraj Kandpal
>> ---
>>dr
On 7/4/2023 6:47 PM, Stanislav Lisovskiy wrote:
We are currently having FIFO underruns happening for kms_dsc test case,
problem is that, we check if curreny cdclk is >= pixel rate only if
there is a single VDSC engine enabled(i.e dsc_split=false) however if
we happen to have 2 VDSC engines
LGTM.
Reviewed-by: Ankit Nautiyal
On 7/4/2023 6:47 PM, Stanislav Lisovskiy wrote:
Currently we are using dsc_split and bigjoiner variables for determining
amount of VDSC instances, however that might change in future, if we happen
to have more of those.
So lets pack all that logic into single
On 7/8/2023 1:04 AM, Pablo Ceballos wrote:
On Wed, Jun 14, 2023 at 9:35 PM Nautiyal, Ankit K
wrote:
I was wondering if trying to set LS/PCON mode multiple time will have
any effect.
Unfortunately I do not have access to machine with Parade LSPCON chip,
had suggested in yet another git lab
On 7/5/2023 10:45 AM, Suraj Kandpal wrote:
Some rc_range_parameter calculations were missed for YCbCr420,
add them to calculate_rc_param()
--v2
-take into account the new formula to get bpp_i
--v4
-Fix range_bpg_offset formula for YCbCr420 bpp <= 16 [Ankit]
Cc: Vandita Kulkarni
Cc: Ankit
On 7/3/2023 3:42 PM, Suraj Kandpal wrote:
Fix comment for YUV420 qp table declaration of max value
YCbCr420 instead of YUV420, as used in other patches.
where the min value is 4 and the max value is 12/15/18
depending on bpc.
Signed-off-by: Suraj Kandpal
---
On 7/3/2023 3:42 PM, Suraj Kandpal wrote:
Move rc_param calculation for native_420 into calculate_rc_parameter.
second_line_bpg_offset and second_line_offset_adj are both rc params
and it would be better to have these calculated where all the other
rc parameters are calculated.
--v2
-Add the
On 7/3/2023 3:42 PM, Suraj Kandpal wrote:
Some rc_range_parameter calculations were missed for YCBCR420,
add them to calculate_rc_param()
--v2
-take into account the new formula to get bpp_i
Cc: Vandita Kulkarni
Cc: Ankit Nautiyal
Cc: Uma Shankar
Signed-off-by: Suraj Kandpal
---
On 6/26/2023 7:26 PM, Luca Coelho wrote:
On Mon, 2023-06-26 at 18:35 +0530, Suraj Kandpal wrote:
Remove the FIXME and the code related to it as after verification
it does seem the previous values were typos and no hardware spec
mentions using these particular rc_params.
Signed-off-by: Suraj
On 7/5/2023 10:44 AM, Suraj Kandpal wrote:
Calculations for YUV420 were missing from calculate_rc_param,
add them be in line with DSC 1.2a specs.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (3):
drm/i915/dsc: Move rc param calculation for native_420
drm/i915/drm: Fix comment for
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sdvo.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git
On 5/29/2023 10:52 AM, Nautiyal, Ankit K wrote:
LGTM.
Reviewed-by: Ankit Nautiyal
(This patch would require a rebas.e)
Regards,
Ankit
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info. Add intel_dp_has_hdmi_sink()
helper to access it.
Signed-off
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info. Add intel_dp_has_hdmi_sink()
helper to access it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Since we already iterate everything that's needed for determining audio,
reduce the need to call drm_detect_monitor_audio() by storing has_audio
to connector info.
Signed-off-by: Jani Nikula
---
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 +++-
drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_hdmi.c
LGTM.
Only minor difference I can see, is an extra message log for CEA audio
formats, while using drm_detect_monitor_audio.
I am wondering, whether drm_detect_monitor_audio can be removed.
Anyways the change looks good to me.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sdvo.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Use the information stored in display info.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++-
2 files
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Convert the topology manager to use struct drm_edid, add
drm_dp_mst_edid_read() that returns drm_edid, and rewrite the old
drm_dp_mst_get_edid() to use it.
Note that the old drm_get_edid() ended up calling
drm_connector_update_edid_property(). This
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
It's a bit tedious to check for NULL before calling
drm_edid_duplicate(). Make it handle NULL parameter graciously.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 3 +++
1 file changed, 3
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Add a switcheroo variant to the struct drm_edid based EDID read
functions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 29 +
include/drm/drm_edid.h | 2 ++
2 files
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/21/2023 5:17 PM, Jani Nikula wrote:
Convert the remaining uses of struct edid based drm_get_edid(),
drm_connector_update_edid_property() and drm_add_edid_modes() calls to
the struct drm_edid based drm_edid_read_ddc(),
drm_edid_connector_update() and
On 5/29/2023 4:37 PM, Suraj Kandpal wrote:
Some basic cleanup of hdcp code.
Consists of
-rename dev_priv to i915.
-move away from master naming rename it to arbiter.
-rename comp_mutex to hdcp_mutex.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (3):
drm/i915/hdcp: Rename dev_priv to i915
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
LGTM.
Acked-by: Ankit Nautiyal
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from
Thanks for the patches and the reviews, pushed to drm-intel-next.
Regards,
Ankit
On 7/27/2023 5:27 PM, Nautiyal, Ankit K wrote:
LGTM.
Acked-by: Ankit Nautiyal
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits
On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above
On 7/20/2023 2:54 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:34PM +0530, Ankit Nautiyal wrote:
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is
On 8/3/2023 9:32 PM, Suraj Kandpal wrote:
On checking DSC1.1 Errata and DSC 1.2 spec the current formula
we were using was incorrect to calculate first_line_bpg_offset.
The new fixed formula is derived from C model.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c
On 8/3/2023 6:33 PM, Suraj Kandpal wrote:
With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.
--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]
On 8/3/2023 6:33 PM, Suraj Kandpal wrote:
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
On 8/3/2023 6:33 PM, Suraj Kandpal wrote:
Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.
--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]
--v3
On 8/7/2023 7:33 PM, Kandpal, Suraj wrote:
On 8/3/2023 6:33 PM, Suraj Kandpal wrote:
Add function to read any PPS register based on the intel_dsc_pps enum
provided. Add a function which will call the new pps read function and
place it in crtc state. Only PPS0 and
PPS1 are readout the rest of
LGTM.
Perhaps we can have shorter name for the helper and variable.
something like intel_dsc_get_vdsc_per_pipe, vdsc_instanances_per_pipe?
With that fixed, this is:
Reviewed-by: Ankit Nautiyal
On 8/3/2023 6:33 PM, Suraj Kandpal wrote:
We have a function that gets us the total of the vdsc
On 8/2/2023 5:35 PM, Lisovskiy, Stanislav wrote:
On Fri, Jul 28, 2023 at 09:41:40AM +0530, Ankit Nautiyal wrote:
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
On 7/25/2023 4:49 PM, Nautiyal, Ankit K wrote:
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote
On 7/20/2023 1:37 PM, Suraj Kandpal wrote:
In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.
--v3
-Remove superfluos new
Hi Suraj,
I agree with overall approach, but I suggest that we use num of vdsc
engines per pipe to avoid changes in future.
This would perhaps need a small patch first to get num of vdsc engines
per pipe though, more details inline for the case:
On 7/20/2023 1:37 PM, Suraj Kandpal wrote:
LGTM.
Reviewed-by: Ankit Nautiyal
On 7/20/2023 1:37 PM, Suraj Kandpal wrote:
This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field
On 8/2/2023 4:45 PM, Kandpal, Suraj wrote:
1.1
This change is required for DSC 1.1 because the current calculation is for DSC
1.2 and may get a calculated value which is not recommended by DSC 1.1, for
example, the calculated value at 8bpp becomes 15, not the value of 12
recommened by DSC
On 7/25/2023 3:40 PM, Lisovskiy, Stanislav wrote:
On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
Currently we assume 2 Pixels Per Clock (PPC) while computing
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
On Thu, Jul 13, 2023 at 04:03:32PM +0530
LGTM.
Reviewed-by: Ankit Nautiyal
Please add Fixes tag.
Regards,
Ankit
On 6/22/2023 2:02 PM, Suraj Kandpal wrote:
Currently hdcp->content_type is being assigned the content_type field
in drm_connector_state which is wrong and instead it needs to be
assigned hdcp_content_type field from
On 5/24/2023 8:25 AM, Suraj Kandpal wrote:
Move rc_param calculation for native_420 into calculate_rc_parameter.
second_line_bpg_offset and second_line_offset_adj are both rc params
and it would be better to have these calculated where all the other
rc parameters are calculated.
--v2
-Add the
On 5/11/2023 11:27 AM, Suraj Kandpal wrote:
Since topology state is being added to drm_atomic_state now all
drm_modeset_lock required are being taken from core this raises
an issue when we try to loop over connector and assign vcpi id to
our streams as we did not have atomic state to derive
LGTM.
Reviewed-by: Ankit Nautiyal
On 5/15/2023 10:45 AM, Suraj Kandpal wrote:
stream_id and k(no of streams) should be set in
intel_hdcp_set_content_streams. stream_type should be set in
intel_hdcp_required_content_stream.
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
LGTM.
Reviewed-by: Ankit Nautiyal
On 5/15/2023 4:02 PM, Suraj Kandpal wrote:
Since topology state is being added to drm_atomic_state now all
drm_modeset_lock required are being taken from core. This raises
an issue when we try to loop over connector and assign vcpi id to
our streams as we did
On 5/15/2023 4:02 PM, Suraj Kandpal wrote:
stream_id and k(no of streams) should be set in
intel_hdcp_set_content_streams. stream_type should be set in
intel_hdcp_required_content_stream.
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
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