Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

> -Original Message- > From: De Marchi, Lucas > Sent: Thursday, September 29, 2022 5:11 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org > Subject: Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts &

Re: [Intel-gfx] [PATCH v3 07/14] drm/i915: Use a DRM-managed action to release the PCI bridge device

> -Original Message- > From: dri-devel On Behalf Of Matt > Roper > Sent: Tuesday, September 6, 2022 4:49 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Subject: [PATCH v3 07/14] drm/i915: Use a DRM-managed action to release the > PCI bridge device > >

Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw

Hi Lucas/Matt, > -Original Message- > From: De Marchi, Lucas > Sent: Wednesday, September 7, 2022 3:21 PM > To: Roper, Matthew D > Cc: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Vivi, Rodrigo > > Subject: Re:

Re: [Intel-gfx] [PATCH v3 02/11] drm/i915: Read graphics/media/display arch version from hw

Hi Jani, > -Original Message- > From: Jani Nikula > Sent: Thursday, September 1, 2022 12:58 AM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v3 02/11] drm/i915: Read >

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Rename and expose common GT early init routine

> -Original Message- > From: Roper, Matthew D > Sent: Monday, August 29, 2022 10:03 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Sripada, Radhakrishna > ; Roper, Matthew D > > Subject: [PATCH 5/8] drm/i915: Rename and exp

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Prepare more multi-GT initialization

> -Original Message- > From: Roper, Matthew D > Sent: Monday, August 29, 2022 10:03 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Sripada, Radhakrishna > ; Roper, Matthew D > ; Iddamsetty, Aravind > > Subject: [PATCH 4/8] d

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects

> -Original Message- > From: Roper, Matthew D > Sent: Monday, August 29, 2022 10:03 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Sripada, Radhakrishna > ; Roper, Matthew D > > Subject: [PATCH 3/8] drm/i915: Use managed allo

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Monday, August 29, 2022 10:03 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Sripada, Radhakrishna > ; Roper, Matthew D > > Subject: [PATCH 2/8] drm/i915: On

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume}

> -Original Message- > From: Roper, Matthew D > Sent: Monday, August 29, 2022 10:03 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Sripada, Radhakrishna > ; Roper, Matthew D > > Subject: [PATCH 1/8] drm/i915: Move loc

Re: [Intel-gfx] [PATCH] drm/i915: Skip Bit12 fw domain reset for gen12+

Hi G.G, > -Original Message- > From: Mun, Gwan-gyeong > Sent: Tuesday, August 23, 2022 11:14 PM > To: Roper, Matthew D ; Sripada, Radhakrishna > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Skip Bit12 fw domain reset for > g

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

> -Original Message- > From: Intel-gfx On Behalf Of José > Roberto de Souza > Sent: Tuesday, March 29, 2022 12:46 AM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani > Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program > PIPE_MBUS_DBOX_CTL with adl-p values > >

Re: [Intel-gfx] [PATCH 1/1] drm/i915/dmc: Update DMC to v2.16 on ADL-P

> -Original Message- > From: Intel-gfx On Behalf Of > Madhumitha Tolakanahalli Pradeep > Sent: Wednesday, February 23, 2022 2:28 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/1] drm/i915/dmc: Update DMC to v2.16 on ADL-P > > Changes since v2.14: > -

Re: [Intel-gfx] [PATCH v1] drm/i915: fix null pointer dereference

> -Original Message- > From: Łukasz Bartosik > Sent: Tuesday, February 8, 2022 8:20 AM > To: Jani Nikula ; Joonas Lahtinen > ; Vivi, Rodrigo ; > Tvrtko Ursulin > Cc: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org; upstr...@semihalf.com; Ville Syrj

Re: [Intel-gfx] [PATCH] drm/i915: Introduce G12 subplatform of DG2

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Thursday, January 20, 2022 3:50 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915: Introduce G12 subplatform of DG2 > > Another fork of the DG2 design has appeared, known as

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix Memory BW formulae for ADL-P

CI IGT reported some failures but they do not look to be related to the changes proposed. Thanks, Radhakrishna(RK) Sripada From: Patchwork Sent: Friday, November 5, 2021 6:51 PM To: Sripada, Radhakrishna Cc: intel-gfx@lists.freedesktop.org Subject: ✓ Fi.CI.BAT: success for drm/i915: Fix

Re: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth formulae

> -Original Message- > From: Srivatsa, Anusha > Sent: Thursday, October 28, 2021 2:04 PM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth > formulae > > Replying t

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Update memory bandwidth parameters (rev2)

> -Original Message- > From: Roper, Matthew D > Sent: Wednesday, September 15, 2021 1:46 PM > To: intel-gfx@lists.freedesktop.org > Cc: Sripada, Radhakrishna ; Vudum, > Lakshminarayana ; Kijanczuk, Damian > > Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn off infoframes

> -Original Message- > From: Intel-gfx On Behalf Of José > Roberto de Souza > Sent: Friday, May 14, 2021 4:23 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn > off infoframes > > intel_dp_set_infoframes() call in

Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/xelpd: Implement Wa_14013475917

On Sat, Apr 17, 2021 at 05:21:26PM -0700, José Roberto de Souza wrote: > This workaround requires that VIDEO_DIP_ENABLE_VSC_HSW is never set > with PSR. > > BSpec: 54369 > BSpec: 54077 Reviewed-by: Radhakrishna Sripada > Cc: Matt Atwood > Cc: Gwan-gyeong Mun > Signed-off-by: José Roberto de

Re: [Intel-gfx] [PATCH 4/5] drm/i915/display: Drop dead code from hsw_read_infoframe()

On Sat, Apr 17, 2021 at 05:21:25PM -0700, José Roberto de Souza wrote: > HSW_TVIDEO_DIP_CTL is read but not used. > Reviewed-by: Radhakrishna Sripada > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +--- > 1 file changed, 1 insertion(+), 3

Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Drop duplicated code in intel_dp_set_infoframes()

On Sat, Apr 17, 2021 at 05:21:24PM -0700, José Roberto de Souza wrote: > No functional changes in here. > > Cc: Matt Atwood Reviewed-by: Radhakrishna Sripada > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/display/intel_dp.c | 17 ++--- > 1 file changed, 6

Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Replace intel_psr_enabled() calls by intel_crtc_state check

On Sat, Apr 17, 2021 at 05:21:23PM -0700, José Roberto de Souza wrote: > All of this places don't need to intel_psr_enabled() that will lock > psr mutex, check state and unlock. > > Instead it can directly check PSR state in intel_crtc_state, the only > place that was not possible was

Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Fill PSR state during hardware configuration read out

On Sat, Apr 17, 2021 at 05:21:22PM -0700, José Roberto de Souza wrote: > So far if we had a mismatch between the state asked and what was > programmed in hardware for PSR, this mismatch would go unnoticed. > > So here adding the PSR to the hardware configuration readout, > EDP_PSR_CTL and

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Eliminate IS_GEN9_{BC, LP}

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Monday, March 29, 2021 11:54 AM > To: intel-gfx@lists.freedesktop.org > Cc: De Marchi, Lucas > Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Eliminate IS_GEN9_{BC, LP} > > Now that we've eliminated INTEL_GEN(),

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: skip display initialization when there is no display

On Mon, Mar 22, 2021 at 01:58:05PM -0700, José Roberto de Souza wrote: > Display features should not be initialized or de-initialized when there > is no display. Skip modeset initialization, output setup, plane, crtc, > encoder, connector registration, display cdclk and rawclk > initialization,

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Do not set any power wells when there is no display

On Mon, Mar 22, 2021 at 01:58:04PM -0700, José Roberto de Souza wrote: > Power wells are only part of display block and not necessary when > running a headless driver. > > Cc: Lucas De Marchi Reviewed-by: Radhakrishna Sripada > Signed-off-by: José Roberto de Souza > Signed-off-by: Jani Nikula

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Skip display interruption setup when display is not available

On Mon, Mar 22, 2021 at 01:58:03PM -0700, José Roberto de Souza wrote: > Return ealier in the functions doing interruption setup for GEN8+ also > adding a warning in gen8_de_irq_handler() to let us know that > something else is still missing. > > Cc: Ville Syrjälä > Cc: Lucas De Marchi

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Wa_14011059788

> -Original Message- > From: Intel-gfx On Behalf Of Matt > Atwood > Sent: Wednesday, April 15, 2020 12:36 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2] drm/i915/tgl: Wa_14011059788 > > Reflect recent Bspec changes > > v2: fix whitespace, typo > >

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Update forcewake firmware ranges

Thanks for the review Matt :) > -Original Message- > From: Atwood, Matthew S > Sent: Friday, April 17, 2020 8:19 AM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Update forcewake firmware > range

Re: [Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges

> -Original Message- > From: Roper, Matthew D > Sent: Wednesday, April 15, 2020 7:52 AM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges > > On Wed, Apr 15, 2020 at 0

Re: [Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Tuesday, April 14, 2020 11:40 AM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges > > On Mon, Apr 13,

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409825376 to tgl

> -Original Message- > From: Roper, Matthew D > Sent: Thursday, January 9, 2020 2:12 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/tgl: Add Wa_1409825376 to tgl > > On Thu, Jan 09, 2020 at 02:02:26PM -08

Re: [Intel-gfx] [PATCH v2 06/15] drm/i915/tgl: Gen-12 render decompression

On Wed, 2019-12-18 at 19:07 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Gen-12 display decompression operates on Y-tiled compressed main > surface. > The CCS is linear and has 4 bits of metadata for each main surface > cache > line pair, a size ratio of 1:256. Gen-12 display

Re: [Intel-gfx] [PATCH 13/15] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Detect the modifier corresponding to media compression to enable > display decompression for YUV and xRGB packed formats. A new modifier > is > added so that the driver can distinguish between media and render >

Re: [Intel-gfx] [PATCH 06/15] drm/i915/tgl: Gen-12 render decompression

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote: > From: Dhinakaran Pandiyan > > Gen-12 display decompression operates on Y-tiled compressed main > surface. > The CCS is linear and has 4 bits of metadata for each main surface > cache > line pair, a size ratio of 1:256. Gen-12 display

Re: [Intel-gfx] [PATCH] drm/i915/irq: Refactor gen11 display interrupt handling

n the > future > if new platforms wind up needing different display handling logic. > > Cc: Lucas De Marchi LGTM. Reviewed-by: Radhakrishna Sripada - Radhakrishna(RK) Sripada > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/i915_irq.c | 57 ---

Re: [Intel-gfx] [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

> -Original Message- > From: Roper, Matthew D > Sent: Tuesday, November 26, 2019 2:00 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > ; Syrjala, Ville ; > Sharma, Shashank ; Antognolli, Rafael > ; Chery, Nanley G >

Re: [Intel-gfx] [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Tuesday, November 26, 2019 12:49 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > ; Syrjala, Ville ; > Sharma, Shashank ; Antognolli, Rafael > ; Chery,

Re: [Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

Hi Nanley, > -Original Message- > From: Chery, Nanley G > Sent: Tuesday, October 29, 2019 5:05 PM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org > Cc: Pandiyan, Dhinakaran ; Syrjala, Ville > ; Sharma, Shashank > ; Antognolli, Rafael > ; Ville

Re: [Intel-gfx] [PATCH v4 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Tuesday, October 22, 2019 11:15 AM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > ; Syrjala, Ville ; > Sharma, Shashank ; Antognolli, Rafael > ; Chery,

Re: [Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

HI, > -Original Message- > From: Pandiyan, Dhinakaran > Sent: Friday, October 4, 2019 5:08 PM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.org > Cc: Syrjala, Ville ; Sharma, Shashank > ; Antognolli, Rafael > ; Roper, Matthew D > ; Chery,

Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Friday, October 4, 2019 4:53 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > ; Syrjala, Ville ; > Sharma, Shashank ; Antognolli, Rafael > ; Chery, Nanley

Re: [Intel-gfx] [PATCH 6/6] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression

Hi Matt, > -Original Message- > From: Roper, Matthew D > Sent: Tuesday, September 17, 2019 2:53 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > ; Syrjala, Ville ; > Sharma, Shashank ; Antognolli, Rafael > ; Chery,

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement Wa_1409142259

Hi Daniele, Thanks for the review. Can you help me merge this pathc? Thanks, Radhakrishna(RK) Sripada > -Original Message- > From: Ceraolo Spurio, Daniele > Sent: Wednesday, September 11, 2019 11:12 AM > To: Sripada, Radhakrishna ; intel- > g...@lists.freedesktop.or

Re: [Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Lucas De Marchi > Sent: Friday, August 23, 2019 1:21 AM > To: intel-gfx@lists.freedesktop.org > Cc: Vetter, Daniel ; Pandiyan, Dhinakaran > > Subject: [Intel-gfx] [PATCH v3 21/23]

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

On Mon, 2019-05-13 at 17:16 +0300, Ville Syrjälä wrote: > On Wed, May 08, 2019 at 09:05:06PM +0000, Sripada, Radhakrishna > wrote: > > On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > ICL has so many plane

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > ICL has so many planes that it can easily exceed the maximum > effective memory bandwidth of the system. We must therefore check > that we don't exceed that limit. > > The algorithm is very magic number heavy and

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register

On Fri, 2019-05-03 at 22:08 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > The pcode mailbox has two data registers. So far we've only ever used > the one, but that's about to change. Expose the second data register > to > the callers of sandybridge_pcode_read(). > > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/sdvo: Check that we have space for the infoframe

On Tue, 2019-04-23 at 17:34 +0300, Ville Syrjälä wrote: > On Mon, Apr 22, 2019 at 06:37:48PM +0000, Sripada, Radhakrishna > wrote: > > On Wed, 2019-04-10 at 20:08 +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Before we go writin

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/sdvo: Check that we have space for the infoframe

On Wed, 2019-04-10 at 20:08 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Before we go writing the infoframe let's make sure we have > the space for it. Not that it really matters since the write > loop would just terminate early in that case. > > v2: Check after the debug print and ++

Re: [Intel-gfx] [PATCH v7] drm/i915/icl: Fix clockgating issue when using scalers

On Tue, 2019-04-16 at 17:14 +0300, Ville Syrjälä wrote: > On Mon, Apr 15, 2019 at 03:55:19PM -0700, Radhakrishna Sripada wrote: > > Fixes the clock-gating issue when pipe scaling is enabled. > > (Lineage #2006604312) > > > > V2: Fix typo in headline(Chris) > > Handle the non double buffered

Re: [Intel-gfx] [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers

On Thu, 2019-04-11 at 14:41 -0700, Souza, Jose wrote: > On Fri, 2019-04-05 at 14:14 -0700, Radhakrishna Sripada wrote: > > Fixes the clock-gating issue when pipe scaling is enabled. > > (Lineage #2006604312) > > > > V2: Fix typo in headline(Chris) > > Handle the non double buffered nature of

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats

On Thu, 2019-04-11 at 21:27 +0300, Ville Syrjälä wrote: > On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote: > > On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote: > > > On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan > > > wrote: > > > > On Tue, 2019-03-26 at

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Add "10.6" LUT mode for i965+

On Thu, 2019-03-28 at 23:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > i965+ have an interpolate 10bit LUT mode. Let's expose that so > that we can actually enjoy real 10bpc. > > Signed-off-by: Ville Syrjälä LGTM Reviewed-by: Radhakrishna Sripada > --- >

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3

On Thu, 2019-03-28 at 23:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Just so we don't leave gen2/3 out in the cold let's advertize the > legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props. Without the > GAMMA_LUT prop we can't actually load a LUT using the atomic ioctl > (in

Re: [Intel-gfx] [PATCH v4] drm/i915/icl: Fix clockgating issue when using scalers

On Fri, 2019-03-29 at 20:39 +0200, Ville Syrjälä wrote: > On Thu, Mar 28, 2019 at 10:35:19AM -0700, Radhakrishna Sripada wrote: > > Fixes the clock-gating issue when pipe scaling is enabled. > > (Lineage #2006604312) > > > > V2: Fix typo in headline(Chris) > > Handle the non double buffered

Re: [Intel-gfx] [PATCH v3] drm/i915/icl: Fix clockgating issue when using scalers

On Fri, 2019-03-22 at 15:14 +0200, Ville Syrjälä wrote: > On Thu, Mar 21, 2019 at 02:44:31PM -0700, Radhakrishna Sripada wrote: > > Fixes the clock-gating issue when pipe scaling is enabled. > > (Lineage #2006604312) > > > > V2: Fix typo in headline(Chris) > > Handle the non double buffered

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix clockgating issue when using scalars

On Mon, 2019-03-18 at 21:22 +, Chris Wilson wrote: > Quoting Sripada, Radhakrishna (2019-03-18 21:19:29) > > On Fri, 2019-03-15 at 22:23 +, Chris Wilson wrote: > > > Scalars as opposed to vector instructions? EU clock gating issues > > > with > > > certa

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix clockgating issue when using scalars

On Mon, 2019-03-18 at 15:30 +0200, Ville Syrjälä wrote: > On Fri, Mar 15, 2019 at 03:18:38PM -0700, Radhakrishna Sripada wrote: > > Fixes the clock-gating issue when pipe scaling is enabled. > > (Lineage #2006604312) > > > > Cc: Rodrigo Vivi > > Cc: Anusha Srivatsa > > Cc: Aditya Swarup > >

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix clockgating issue when using scalars

On Fri, 2019-03-15 at 22:23 +, Chris Wilson wrote: > Scalars as opposed to vector instructions? EU clock gating issues > with > certain shaders? > Hi Chris, The scalers mentioned for this WA around are specific to display scaling. They are not related to EU clock gating. -Radhakrishna(RK)

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Always free spinner on __sseu_prepare error

Hi Chris, Looks clean. Reviewed-by: Radhakrishna Sripada -Radhakrishna(RK) Sripada > -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Friday, February 15, 2019 11:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: Chris Wilson ; Sripad

Re: [Intel-gfx] [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

Looks good to me. > -Original Message- > From: Souza, Jose > Sent: Friday, January 4, 2019 9:37 AM > To: intel-gfx@lists.freedesktop.org > Cc: Oscar Mateo ; Sripada, Radhakrishna > ; Souza, Jose > Subject: [PATCH] drm/i915/icl: Apply > WaEnablePreemptio

Re: [Intel-gfx] [PATCH i-g-t v3] tests/kms_rotation_crc: Move platform checks to one place for non exhaust fence cases

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Wednesday, March 28, 2018 3:36 AM > To: Maarten Lankhorst <maarten.lankho...@linux.intel.com> > Cc: Sripada, Radhakrishna <radhakrishna.srip...@intel.com>; igt- > d..

Re: [Intel-gfx] [RESEND v2 1/2] drm/i915: Add connector property to limit max bpc

> -Original Message- > From: Vivi, Rodrigo > Sent: Thursday, November 9, 2017 1:25 PM > To: Sripada, Radhakrishna <radhakrishna.srip...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Zanoni, Paulo R > <paulo.r.zan...@intel.com> > Subject: Re: [Intel-g

Re: [Intel-gfx] [RFC 1/2] drm/i915: Add connector property to force bpc

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Thursday, October 19, 2017 7:09 AM > To: Jani Nikula <jani.nik...@linux.intel.com> > Cc: Daniel Vetter <dan...@ffwll.ch>; Sripada, Radhakrishna > <radhakris

[Intel-gfx] [RFC 1/2] drm/i915: Add connector property to force bpc

Currently the user space does not have a way to force the bpc. The default bpc to be programmed is decided by the driver and is run against connector limitations. Creating a new property for the userspace to recommend a certain color depth while scanning out the pixels. Cc: Ville Syrjälä

[Intel-gfx] [RFC 2/2] drm/i915: Allow force_bpc property to limit pipe_bpp

Use the newly added force_bpc connector property to limit pipe bpp. Cc: Ville Syrjälä Cc: Paulo Zanoni Cc: Manasi Navare Signed-off-by: Radhakrishna Sripada ---

Re: [Intel-gfx] [PATCH i-g-t v2] tests/psr: Don't strcmp CRCs that are not NULL terminated.

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Dhinakaran Pandiyan > Sent: Tuesday, September 19, 2017 3:48 PM > To: intel-gfx@lists.freedesktop.org > Cc: Pandiyan, Dhinakaran ; Vivi, Rodrigo >

Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest

> -Original Message- > From: Vivi, Rodrigo > Sent: Thursday, September 21, 2017 7:54 AM > To: Sripada, Radhakrishna <radhakrishna.srip...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > <dhinakaran.pandi...@intel.com> > Subjec

Re: [Intel-gfx] [PATCH v2] drm/i915: Disable DRRS when PSR is enabled

> -Original Message- > From: Nikula, Jani > Sent: Tuesday, September 12, 2017 7:18 AM > To: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>; Sripada, > Radhakrishna <radhakrishna.srip...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Vivi, R

Re: [Intel-gfx] [PATCH] drm/i915: Disable DRRS when PSR is enabled

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Monday, September 4, 2017 1:14 AM > To: Sripada, Radhakrishna <radhakrishna.srip...@intel.com> > Cc: Vivi, Rodrigo <rodrigo.v...@intel.com

Re: [Intel-gfx] [PATCH] drm/i915: Disable DRRS when PSR is enabled

> -Original Message- > From: Vivi, Rodrigo > Sent: Wednesday, August 30, 2017 5:59 PM > To: Sripada, Radhakrishna <radhakrishna.srip...@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > <dhinakaran.pandi...@intel.com>; Nikula, Jani <

Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in multi-pipe config

Thanks for the input Rodrigo, Arthur. I will update commit message and repost the patch. Thanks, Radhakrishna Sripada -Original Message- From: Runyan, Arthur J Sent: Thursday, June 23, 2016 1:04 PM To: Rodrigo Vivi <rodrigo.v...@gmail.com> Cc: Sripada, Radhakrishna <radhakri

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915/skl: Increase cursor ddb blocks in multi-pipe config

> -Original Message- > From: Patchwork [mailto:patchw...@emeril.freedesktop.org] > Sent: Monday, June 13, 2016 10:54 PM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Ro.CI.BAT: failure for drm/i915/skl: Increase cursor ddb blocks in &

Re: [Intel-gfx] [PATCH v3.1 08/16] drm/i915/gen9: Compute DDB allocation at atomic check time (v3)

I was facing the same issue that was reported by Lyude both on Arch Linux and ChromeOs. This patch did not help me while testing on a SKL RVP. The check for skip_intermediate_wm would not pass on gen9. sanitize_watermarks() would return immediately as dev_priv->display.optimize_watermarks is

Re: [Intel-gfx] [PATCH 4/8] drm/i915/skl+: Use scaling amount for plane data rate calculation (v3)

This commit introduced a divide-by-zero crash on plugging in an external display to the system. Below is the crash. [ 122.320882] divide error: [#1] PREEMPT SMP [ 122.320893] Modules linked in: rfcomm i2c_dev uinput snd_soc_hdac_hdmi snd_soc_dmic aesni_intel aes_x86_64

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