indentation
v4: Thierry's review comments.
- Return ENOMEM when property creation fails
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
---
drivers/gpu/drm/drm_crtc.c | 33 +
include/drm/drm_crtc.h
On Jun-18-2014 9:22 PM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register
On Jul-07-2014 2:11 PM, Daniel Vetter wrote:
On Tue, Jul 01, 2014 at 10:39:52AM +0530, Vandana Kannan wrote:
On Jun-18-2014 9:22 PM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 07:47:24PM +0530, Vandana Kannan wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required
) and added bool has_drrs to pipe_config to
track drrs support
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 36
drivers/gpu/drm/i915/intel_dp.c | 16
. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen 8.
v6: Added check to compare dp_m2_n2 only when DRRS is enabled
v7: Modified drrs check to use has_drrs
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc
On Jul-10-2014 2:42 AM, Jesse Barnes wrote:
On Mon, 7 Jul 2014 14:59:45 +0530
Vandana Kannan vandana.kan...@intel.com wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state
) and added bool has_drrs to pipe_config to
track drrs support
v4: Jesse's review comments
- Made changes to set m2_n2 in intel_dp_set_m_n()
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jesse Barnes jbar...@virtuousgeek.org
-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jani Nikula jani.nik...@linux.intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 75
1 file changed, 67 insertions(+), 8
On Jul-15-2014 12:18 PM, Daniel Vetter wrote:
[...]
I've pulled all 4 patches. Please double-check that I've picked up the
right ones since the series is a bit spread out.
Thanks, Daniel
Hi Daniel,
I checked the 4 patches in -next-queued. They are the correct version.
Thanks,
Vandana
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1
-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_display.c | 4
On Aug-05-2014 6:39 PM, Ville Syrjälä wrote:
On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote:
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
Signed-off-by: Vandana Kannan vandana.kan
CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
v2: Ville's review comments
- Re-ordered CCK_CZ_CONTROL
- Refactored get_clock_speed
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Rename the DISPLAY_TRUNK_* and DISPLAY_FREQUENCY_* bits to CCK_... instead
of DISPLAY_... to make it clear they apply to all CCK clock control registers.
Suggested by Ville.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Ville Syrjä ville.syrj...@linux.intel.com
---
drivers/gpu/drm
-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_display.c | 4
not supported log to patch2.
Patch rebased.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
Cc: Daniel Vetter dan...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915
at 3:45 PM, Vandana Kannan vandana.kan...@intel.com
wrote:
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane
on them next week..
Thanks,
Vandana
On Aug-08-2014 6:33 PM, Ville Syrjälä wrote:
On Thu, Aug 07, 2014 at 06:40:03PM +0530, Vandana Kannan wrote:
From: Vidya Srinivas vidya.srini...@intel.com
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end
state readout code for M2_N2. dp_m2_n2 comparison to be done
only when high RR is not in use (This is because alternate m_n register
programming will be done only when low RR is being used).
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers
On May-12-2014 3:57 PM, Ville Syrjälä wrote:
On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode
On May-13-2014 2:28 PM, Daniel Vetter wrote:
On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
On May-12-2014 3:57 PM, Ville Syrjälä wrote:
On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
Adding relevant read out comparison code, in check_crtc_state, for the new
On May-13-2014 3:10 PM, Vandana Kannan wrote:
On May-13-2014 2:28 PM, Daniel Vetter wrote:
On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
On May-12-2014 3:57 PM, Ville Syrjälä wrote:
On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
Adding relevant read out
On May-15-2014 3:01 PM, Ville Syrjälä wrote:
On Thu, May 15, 2014 at 02:48:02PM +0530, Vandana Kannan wrote:
On May-13-2014 3:10 PM, Vandana Kannan wrote:
On May-13-2014 2:28 PM, Daniel Vetter wrote:
On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
On May-12-2014 3:57 PM, Ville
On May-15-2014 2:48 PM, Vandana Kannan wrote:
On May-13-2014 3:10 PM, Vandana Kannan wrote:
On May-13-2014 2:28 PM, Daniel Vetter wrote:
On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
On May-12-2014 3:57 PM, Ville Syrjälä wrote:
On Mon, May 05, 2014 at 01:49:31PM +0530
and below. compare the structures
based on DRRS state for gen 8 and above.
Save and restore M2 N2 registers for gen 7 and below
v4: For Gen=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
only one set of M_N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet
. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen 8.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 68
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_crtc.c | 31
In case user has specified an input for aspect ratio through the property,
then the user space value for PAR would take preference over the value from
CEA mode list.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 9
Create and attach the drm property to set aspect ratio. If there is no user
specified value, then PAR_NONE/Automatic option is set by default. User can
select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would
come into effect with a mode set.
Signed-off-by: Vandana Kannan
come into effect with a mode set.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
3 files changed, 37 insertions
On May-22-2014 5:08 PM, Thierry Reding wrote:
On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
Signed-off-by: Vandana Kannan vandana.kan
On May-22-2014 5:12 PM, Thierry Reding wrote:
On Thu, May 22, 2014 at 04:50:49PM +0530, Vandana Kannan wrote:
In case user has specified an input for aspect ratio through the property,
then the user space value for PAR would take preference over the value from
CEA mode list.
Signed-off
On May-22-2014 5:46 PM, Daniel Vetter wrote:
On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
Signed-off-by: Vandana Kannan vandana.kan
On May-23-2014 4:18 PM, Vandana Kannan wrote:
On May-22-2014 5:46 PM, Daniel Vetter wrote:
On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property
variable
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/drm_crtc.c | 27 +++
include/drm/drm_crtc.h | 2 ++
include/uapi/drm/drm_mode.h | 5 +
3 files
In case user has specified an input for aspect ratio through the property,
then the user space value for PAR would take preference over the value from
CEA mode list.
v2: Thierry's review comments.
- Modified the comment Populate... as per review comments
Signed-off-by: Vandana Kannan
on changes to aspect ratio enum list.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
2 files
: Removed the chunk which saves and restores M2_N2 registers. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen 8.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
variable
v3: Thierry's review comments.
- Fixed indentation drm_mode_create_aspect_ratio_property()
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
---
drivers/gpu/drm/drm_crtc.c | 27 +++
include/drm/drm_crtc.h
.
- Modified the comment to block comment format.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
---
drivers/gpu/drm/drm_edid.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b
On Jun-05-2014 2:58 PM, Thierry Reding wrote:
On Thu, Jun 05, 2014 at 02:40:08PM +0530, Vandana Kannan wrote:
[...]
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
[...]
/**
+ * drm_mode_create_aspect_ratio_property - create aspect ratio property
+ * @dev: DRM device
variable
v3: Thierry's review comments.
- Fixed indentation
v4: Thierry's review comments.
- Return ENOMEM when property creation fails
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red...@gmail.com
---
drivers/gpu/drm/drm_crtc.c | 33
aspect ratio enum changes
v3: Modified the patch according the change in the earlier patch to return
errno in case property creation fails. With this change, property will be
attached only if creation is successful
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Thierry Reding thierry.red
Updated drm documentation to include desscription of aspect ratio property.
v2: Updated aspect ratio specific documentation on top of the HTML table
created.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Sagar Kamble sagar.a.kam...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
On Jun-17-2014 10:12 PM, Daniel Vetter wrote:
On Tue, Jun 17, 2014 at 05:52:24PM +0300, Jani Nikula wrote:
On Mon, 16 Jun 2014, Vandana Kannan vandana.kan...@intel.com wrote:
On Jun-13-2014 7:42 PM, Jani Nikula wrote:
On Thu, 22 May 2014, Vandana Kannan vandana.kan...@intel.com wrote:
Adding
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
v2: Patch rebased
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc
On Jun-18-2014 4:16 PM, Daniel Vetter wrote:
On Wed, Jun 18, 2014 at 10:11:20AM +0530, Vandana Kannan wrote:
On Jun-17-2014 10:12 PM, Daniel Vetter wrote:
On Tue, Jun 17, 2014 at 05:52:24PM +0300, Jani Nikula wrote:
On Mon, 16 Jun 2014, Vandana Kannan vandana.kan...@intel.com wrote:
On Jun-13
. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen 8.
v6: Added check to compare dp_m2_n2 only when DRRS is enabled
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jani
) and added bool has_drrs to pipe_config to
track drrs support
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 36
drivers/gpu/drm/i915/intel_dp.c | 16
. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen 8.
v6: Added check to compare dp_m2_n2 only when DRRS is enabled
v7: Modified drrs check to use has_drrs
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Cc
If one mode of a internal panel has more than one refresh rate, then a reduced
clock is found for the LFP (LVDS/eDP). This enables switching between low
and high frequency dynamically. Moving downclock calculation to intel_panel
so that it is common for LVDS and eDP.
Signed-off-by: Vandana Kannan
If one mode of a internal panel has more than one refresh rate, then a reduced
clock is found for the LFP (LVDS/eDP). This enables switching between low
and high frequency dynamically. Moving downclock calculation to intel_panel
so that it is common for LVDS and eDP.
Signed-off-by: Vandana Kannan
-display mode.
Change-Id: I17b011b3867a39588375f2b97b992444972f7760
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 19 ++
drivers/gpu/drm/i915/intel_display.c | 13
drivers/gpu/drm/i915
[Intel-gfx] drm/i915: Parse EDID probed modes for DRRS support
[Intel-gfx] drm/i915: Add support for DRRS to switch RR
Vandana Kannan (2):
[Intel-gfx] drm/i915: Idleness detection for DRRS
[Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR
drivers/gpu/drm/i915/i915_drv.h
...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 109 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
3 files changed, 115 insertions(+), 1 deletion(-)
diff --git
frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers
...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/intel_dp.c | 47 ++
drivers/gpu/drm/i915/intel_drv.h | 29 +++
3 files changed, 78 insertions(+)
diff
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |9 +
drivers/gpu/drm/i915/intel_bios.c | 23 +++
drivers/gpu/drm/i915/intel_bios.h | 29 +
3 files changed, 61 insertions(+)
diff --git
On Dec-17-2013 5:56 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:23AM +0530, Vandana Kannan wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing
On Dec-17-2013 5:58 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:24AM +0530, Vandana Kannan wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode, based on the implementaion
On Dec-17-2013 5:59 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:26AM +0530, Vandana Kannan wrote:
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable
On Dec-17-2013 6:00 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N
On Dec-18-2013 2:31 PM, Chris Wilson wrote:
On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote:
On Dec-17-2013 6:00 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per
transcoder
On Dec-18-2013 2:34 PM, Chris Wilson wrote:
On Wed, Dec 18, 2013 at 01:48:12PM +0530, Vandana Kannan wrote:
On Dec-17-2013 5:59 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:26AM +0530, Vandana Kannan wrote:
Adding support to detect display idleness by tracking page flip from
user
On Dec-18-2013 2:36 PM, Chris Wilson wrote:
On Wed, Dec 18, 2013 at 01:41:21PM +0530, Vandana Kannan wrote:
On Dec-17-2013 5:58 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:24AM +0530, Vandana Kannan wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out
On Dec-18-2013 2:41 PM, Chris Wilson wrote:
On Wed, Dec 18, 2013 at 01:38:44PM +0530, Vandana Kannan wrote:
On Dec-17-2013 5:56 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:23AM +0530, Vandana Kannan wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support
On Dec-18-2013 2:54 PM, Daniel Vetter wrote:
On Tue, Dec 17, 2013 at 10:58:22AM +0530, Vandana Kannan wrote:
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which
enables switching between low and high refresh rates based on the usage
scenario
.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/drm_edid.c | 374
++-
drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
drivers/gpu/drm/i915/intel_display.c
downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers
[Intel-gfx] drm/i915: Add support for DRRS to switch RR
Vandana Kannan (2):
[Intel-gfx] drm/i915: Idleness detection for DRRS
[Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR
drivers/gpu/drm/i915/i915_drv.h | 25 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers
Removed intel_ as a prefix for DRRS specific declarations.
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h |9 +
drivers/gpu/drm/i915
in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed
-display mode.
v2: Chris's review comments
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
Change-Id: I17b011b3867a39588375f2b97b992444972f7760
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat
Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
CEA-861E Table 4. This is useful for filling up the detail in AVI
infoframe.
v2: Ville's review comments incorporated
Added picture aspect ratio as part of edid_cea_modes instead of DRM_MODE
Signed-off-by: Vandana Kannan
On Dec-19-2013 5:21 PM, Jani Nikula wrote:
On Tue, 17 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode, based on the implementaion
drrs_support_type.
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Jani Nikula jani.nik...@linux.intel.com
---
drivers/gpu/drm/i915
[Intel-gfx] drm/i915: Add support for DRRS to switch RR
Vandana Kannan (2):
[Intel-gfx] drm/i915: Idleness detection for DRRS
[Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR
drivers/gpu/drm/i915/i915_drv.h | 25 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers
frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers
-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 106 ++
drivers/gpu/drm/i915
On Dec-20-2013 7:35 PM, Daniel Vetter wrote:
On Fri, Dec 20, 2013 at 1:29 PM, Jani Nikula
jani.nik...@linux.intel.com wrote:
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed
Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
CEA-861E Table 4. This is useful for filling up the detail in AVI
infoframe.
v2: Ville's inputs incorporated. Added picture aspect ratio as part of
edid_cea_modes instead of DRM_MODE
Signed-off-by: Vandana Kannan vandana.kan
-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 106 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
3 files changed, 112 insertions
Removed intel_ as a prefix for DRRS specific declarations.
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |9 +
drivers/gpu/drm/i915/intel_bios.c | 23 +++
drivers/gpu
-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
drrs_support_type.
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 45 ++
drivers/gpu/drm/i915/intel_drv.h | 30 +
2 files changed, 75 insertions
for DRRS to switch RR
Vandana Kannan (2):
drm/i915: Idleness detection for DRRS
drm/i915/bdw: Add support for DRRS to switch RR
drivers/gpu/drm/i915/i915_drv.h | 25 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_bios.c| 23 +
drivers/gpu/drm
frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 32
On Jan-02-2014 4:05 AM, Ben Widawsky wrote:
Hi Daniel, and welcome back.
Tomorrow I go on vacation, and since it's more or less the end of the
day for anyone still submitting or reviewing patches, I figured now is
as good a time as any to do this.
On Jan-22-2014 6:39 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing
On Jan-22-2014 7:03 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode, based on the implementaion
On Jan-22-2014 7:44 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
On Jan-22-2014 7:56 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable
On Jan-22-2014 8:04 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N
On Jan-30-2014 11:50 AM, Jani Nikula wrote:
On Thu, 30 Jan 2014, Vandana Kannan vandana.kan...@intel.com wrote:
On Jan-22-2014 6:39 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS
On Jan-30-2014 12:22 PM, Jani Nikula wrote:
On Thu, 30 Jan 2014, Vandana Kannan vandana.kan...@intel.com wrote:
On Jan-22-2014 7:44 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch computes
Instead of modifying intel_panel in lvds_init_connector/dsi_init_connector/
edp_init_connector, making changes to move intel_panel-downclock_mode
initialization to intel_panel_init()
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
On Jan-30-2014 9:03 AM, Vandana Kannan wrote:
On Jan-22-2014 7:03 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out the lowest refresh rate supported for the
resolution
same
-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c|2 +-
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_lvds.c | 10
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