Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Impletments dynamic WOPCM partitioning.

On 11/15/2017 09:58 AM, Chris Wilson wrote: Quoting Jackie Li (2017-11-15 17:17:08) Static WOPCM partitioning will lead to GuC loading failure if the GuC/HuC firmware size exceeded current static 512KB partition boundary. This patch enables the dynamical calculation of the WOPCM aperture used

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Impletments dynamic WOPCM partitioning.

On 11/16/2017 01:47 PM, Michal Wajdeczko wrote: On Thu, 16 Nov 2017 08:34:01 +0100, Sagar Arun Kamble wrote: Typo in the subject. GLK showing failure to load GuC with this approach on CI. On 11/15/2017 10:47 PM, Jackie Li wrote: Static WOPCM partitioning will lead

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Impletments dynamic WOPCM partitioning.

On 11/16/2017 08:00 PM, Sagar Arun Kamble wrote: On 11/17/2017 3:17 AM, Michal Wajdeczko wrote: On Thu, 16 Nov 2017 08:34:01 +0100, Sagar Arun Kamble wrote: Typo in the subject. GLK showing failure to load GuC with this approach on CI. On 11/15/2017 10:47 PM,

Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning

On 12/14/2017 03:43 AM, Joonas Lahtinen wrote: On Wed, 2017-12-13 at 14:59 -0800, Yaodong Li wrote: On 12/13/2017 01:34 PM, Michal Wajdeczko wrote: On Wed, 13 Dec 2017 19:19:06 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 12/13/2017 01:11 AM, Joonas Lahtinen wrote: On Tue, 2017

Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning

On 12/15/2017 02:21 AM, Joonas Lahtinen wrote: On Thu, 2017-12-14 at 20:55 -0800, Yaodong Li wrote: On 12/14/2017 03:43 AM, Joonas Lahtinen wrote: On Wed, 2017-12-13 at 14:59 -0800, Yaodong Li wrote: On 12/13/2017 01:34 PM, Michal Wajdeczko wrote: On Wed, 13 Dec 2017 19:19:06 +0100, Yaodong

Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning

On 12/13/2017 01:11 AM, Joonas Lahtinen wrote: On Tue, 2017-12-12 at 14:56 -0800, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM partition size versus HuC firmware size. With static WOPCM partitioning, there's no way to adjust the GuC WOPCM partition size based on the

Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files

On 12/13/2017 12:19 AM, Joonas Lahtinen wrote: On Tue, 2017-12-12 at 14:56 -0800, Jackie Li wrote: intel_guc_reg.h should only include definition for GuC registers and related register bits. GuC WOPCM related values should not be defined in intel_guc_reg.h This patch creates a better file

Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

On 12/18/2017 01:47 PM, Chris Wilson wrote: Quoting Jackie Li (2017-12-18 21:22:08) From: Zhipeng Gong SKL platforms requires a higher ring multiplier when there's massive GPU load. Current driver doesn't provide a way to override the ring multiplier. This patch adds

Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning

On 12/13/2017 01:34 PM, Michal Wajdeczko wrote: On Wed, 13 Dec 2017 19:19:06 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 12/13/2017 01:11 AM, Joonas Lahtinen wrote: On Tue, 2017-12-12 at 14:56 -0800, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM partitio

Re: [Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

On 11/06/2017 05:24 AM, Ville Syrjälä wrote: On Fri, Nov 03, 2017 at 05:01:09PM -0700, Jackie Li wrote: Static WOPCM partitioning would lead to GuC loading failure if the GuC/HuC firmware size exceeded current static 512KB partition boundary. This patch enabled the dynamical calculation of the

Re: [Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

On 11/06/2017 12:16 AM, Sagar Arun Kamble wrote: Please update the subject to "Implement dynamic WOPCM partitioning" Also, commit description should be written in present tense form. Will update it in v2. On 11/4/2017 5:48 AM, Jackie Li wrote: Static WOPCM partitioning would lead to GuC

Re: [Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

On 11/07/2017 02:52 AM, Joonas Lahtinen wrote: On Fri, 2017-11-03 at 17:18 -0700, Jackie Li wrote: Static WOPCM partitioning would lead to GuC loading failure if the GuC/HuC firmware size exceeded current static 512KB partition boundary. This patch enabled the dynamical calculation of the

Re: [Intel-gfx] [PATCH 1/2] drm/i915: implemented dynamic WOPCM partition.

On 11/03/2017 05:01 PM, Jackie Li wrote: Static WOPCM partitioning would lead to GuC loading failure if the GuC/HuC firmware size exceeded current static 512KB partition boundary. This patch enabled the dynamical calculation of the WOPCM aperture used by GuC/HuC firmware. GuC WOPCM offset was

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning

On 12/08/2017 01:57 PM, Chris Wilson wrote: Quoting Jackie Li (2017-12-08 21:41:50) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 21ce374..89ecf2c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++

Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL

On 12/08/2017 03:03 PM, Chris Wilson wrote: Quoting Jackie Li (2017-12-08 21:41:51) +static inline int cnl_a0_wopcm_size_check(struct drm_i915_private *i915) +{ + struct intel_guc_wopcm *wopcm = >guc.wopcm; + u32 huc_size = intel_uc_fw_get_size(>huc.fw); + + /* +* On

Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

he pending request count reaches a center tunable threshold??). On 1/3/2018 11:51 PM, Yaodong Li wrote: You are thinking of plugging into intel_pstate to make it smarter for ia freq transitions? Yep. This seems a correct step to give some automatic support instead of parameter/hardcoded multipli

Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

On 01/05/2018 02:15 AM, Sagar Arun Kamble wrote: On 1/5/2018 3:22 AM, Yaodong Li wrote: On 01/03/2018 10:10 PM, Sagar Arun Kamble wrote: Since ring frequency programming needs consideration of both IA and GT frequency requests I think keeping the logic to program the ring frequency table

Re: [Intel-gfx] [PATCH v7 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c index ac62753..7215594 100644 --- a/drivers/gpu/drm/i915/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/intel_guc_ads.c @@ -113,17 +113,6 @@ int intel_guc_ads_create(struct intel_guc *guc)  

Re: [Intel-gfx] [PATCH v7 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

On 01/31/2018 11:38 PM, Chris Wilson wrote: Quoting Jackie Li (2018-01-19 01:29:28) GuC related exported functions should start with "intel_guc_" prefix and pass intel_guc as the first parameter since its guc related. Current guc_ggtt_offset() failed to follow this code convention. But it was

Re: [Intel-gfx] [PATCH v7 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

On 01/31/2018 11:37 PM, Chris Wilson wrote: Quoting Jackie Li (2018-01-19 01:29:27) intel_guc_reg.h should only include definition for GuC registers and related register bits. GuC WOPCM related values should not be defined in intel_guc_reg.h GuC registers does not include GuC WOPCM? The code

Re: [Intel-gfx] [PATCH v7 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 01/31/2018 11:41 PM, Chris Wilson wrote: - Fixed patch format issues Cc: Michal Wajdeczko Cc: Chris Wilson Cc: Joonas Lahtinen Signed-off-by: Jackie Li --- +static inline

Re: [Intel-gfx] [PATCH v7 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

On 02/01/2018 02:35 PM, Chris Wilson wrote: Quoting Yaodong Li (2018-02-01 19:47:53) On 01/31/2018 11:38 PM, Chris Wilson wrote: Quoting Jackie Li (2018-01-19 01:29:28) GuC related exported functions should start with "intel_guc_" prefix and pass intel_guc as the first parameter

Re: [Intel-gfx] [PATCH v7 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/01/2018 12:38 AM, Sagar Arun Kamble wrote: On 1/19/2018 6:59 AM, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM size It would be good if you can tell about Gen9/CNL restriction briefly here. versus HuC firmware size. With static GuC WOPCM size, there's no way

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/07/2018 09:24 AM, Michal Wajdeczko wrote: On Wed, 07 Feb 2018 05:02:00 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 02/06/2018 02:56 PM, Michal Wajdeczko wrote: +    /* Explicitly cast the return value to bool. */ +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCK

Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/07/2018 09:24 AM, Michal Wajdeczko wrote:  int guc_wopcm_check_huc_fw_size(struct guc_wopcm *wopcm, u32 huc_size) patch 1/6 & 2/6 are only for some code movings. but have to make it clean. but I do not need this func anymore:o) so maybe part of these code movement was unnecessary, and

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/08/2018 03:31 PM, Chris Wilson wrote: Quoting Jackie Li (2018-02-08 23:03:54) @@ -95,7 +97,11 @@ struct intel_guc_wopcm { u32 offset; u32 size; u32 top; - u32 valid; + + /* GuC WOPCM flags below. */ + u32 valid:1; + u32 hw_updated:1; +

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/05/2018 10:39 PM, Sagar Arun Kamble wrote: +/** + * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers. + * @guc: intel guc. + * + * Setup the GuC WOPCM size and offset registers with the stored values. It will + * also check the registers locking status to determine whether these

Re: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

On 02/06/2018 01:11 PM, Michal Wajdeczko wrote: On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble wrote: On 2/6/2018 5:32 AM, Jackie Li wrote: intel_guc_reg.h should only include definition for GuC registers and related register bits. Non-register related

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/06/2018 02:56 PM, Michal Wajdeczko wrote: +    /* Explicitly cast the return value to bool. */ +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED); you should avoid reusing bits defined for one register in others it's a common bit. use BIT(0) instead? +    offset &=

Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/06/2018 02:25 PM, Michal Wajdeczko wrote: default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);   -    /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not +    /* + * GuC requires the ring to be placed above GuC WOPCM top. If GuC is not    *

Re: [Intel-gfx] [PATCH v9 1/7] drm/i915/guc: Move GuC WOPCM related code into separate files

On 02/09/2018 08:46 AM, Michal Wajdeczko wrote: --- /dev/null +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2017-2018 Intel Corporation + * Do we really want to keep legacy license text? Note that in other file

Re: [Intel-gfx] [PATCH v9 3/7] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/09/2018 09:24 AM, Michal Wajdeczko wrote: +    struct intel_guc *guc = +    container_of(guc_wopcm, struct intel_guc, wopcm); If you define this as "wopcm_to_guc" inline helper, then maybe all your functions could take "wopcm" as first parameter? First thought is this is only one

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/09/2018 02:47 AM, Joonas Lahtinen wrote: +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c +static inline bool guc_wopcm_locked(struct intel_guc *guc) +{ + struct drm_i915_private *i915 = guc_to_i915(guc); + bool size_reg_locked = __reg_locked(i915, GUC_WOPCM_SIZE); + bool

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/09/2018 11:42 AM, Michal Wajdeczko wrote: +static inline bool __reg_locked(struct drm_i915_private *dev_priv, +    i915_reg_t reg) +{ +    /* Set of bit-0 means this write-once register is locked. */ +    return I915_READ(reg) & BIT(0); +} Hmm, I'm still not happy as not

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/13/2018 07:56 AM, Michal Wajdeczko wrote: + +/* GUC WOPCM offset needs to be 16KB aligned. */ +#define GUC_WOPCM_OFFSET_ALIGNMENT    (16 << 10) +/* 16KB reserved at the beginning of GuC WOPCM. */ +#define GUC_WOPCM_RESERVED    (16 << 10) +/* 8KB from GUC_WOPCM_RESERVED is reserved for

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915/guc: Add HuC firmware size related restriction for Gen9 and CNL A0

On 02/13/2018 08:06 AM, Michal Wajdeczko wrote: +static inline int check_huc_fw_fits(struct intel_guc_wopcm *guc_wopcm, +    u32 huc_fw_size) +{ +    /* + * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM + * size to be larger than or equal to HuC

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/13/2018 07:56 AM, Michal Wajdeczko wrote: Also, comparing again your drawing with the spec I think it should look like this:    + ++ <== WOPCM top   /|\    | HW RESERVED    |    | +--- +    | |    |    | 

Re: [Intel-gfx] [PATCH v10 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/13/2018 09:39 AM, Michal Wajdeczko wrote: + +static inline u32 lockable_reg_read(struct lockable_reg *lreg) +{ +    struct drm_i915_private *dev_priv = guc_to_i915(lreg->guc); + +    lreg->reg_val = I915_READ(lreg->reg); + +    return lreg->reg_val; +} + +static inline bool

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915/guc: Add HuC firmware size related restriction for Gen9 and CNL A0

On 02/13/2018 02:59 PM, Michal Wajdeczko wrote: Hmm, that only proves that current partitioning code is too complicated :) If you look at diagram it should be possible to implement it as current calculation tries to set the maximum available WOPCM to avoid Gen9 limitations. that the reason I

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915/guc: Add HuC firmware size related restriction for Gen9 and CNL A0

On 02/14/2018 09:24 AM, Michal Wajdeczko wrote: On Wed, 14 Feb 2018 01:41:57 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 02/13/2018 02:59 PM, Michal Wajdeczko wrote: Hmm, that only proves that current partitioning code is too complicated :) If you look at diagram it

Re: [Intel-gfx] [PATCH v10 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/13/2018 05:18 PM, Yaodong Li wrote: On 02/13/2018 09:39 AM, Michal Wajdeczko wrote: + +static inline u32 lockable_reg_read(struct lockable_reg *lreg) +{ +    struct drm_i915_private *dev_priv = guc_to_i915(lreg->guc); + +    lreg->reg_val = I915_READ(lreg->reg); + +    re

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/14/2018 09:38 AM, Michal Wajdeczko wrote: On Wed, 14 Feb 2018 03:26:12 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 02/13/2018 07:56 AM, Michal Wajdeczko wrote: Also, comparing again your drawing with the spec I think it should loo

Re: [Intel-gfx] [PATCH v10 6/7] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/14/2018 09:07 AM, Michal Wajdeczko wrote: On Wed, 14 Feb 2018 02:18:29 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 02/13/2018 09:39 AM, Michal Wajdeczko wrote: + +#define DEFINE_LOCKABLE_REG(var, rg, lb, func)    \ +    struct lockable_reg var = {    \ +   

Re: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier

You are thinking of plugging into intel_pstate to make it smarter for ia freq transitions? Yep. This seems a correct step to give some automatic support instead of parameter/hardcoded multiplier. Does this mean we should use cpufreq/intel_pstate based approach instead of the current

Re: [Intel-gfx] [PATCH v12 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

Failed to receive this mail for 5/6 patch (couldn't find it in my mailbox). So pasted the comments from patchwork. Quoting Jackie Li (2018-03-02 02:16:45) > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -219,3 +219,67 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) > > return 0; >

Re: [Intel-gfx] [PATCH v2] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

On 03/14/2018 11:54 PM, Sagar Arun Kamble wrote: Are we required to add reference to intel_guc.c and intel_wopcm.c in Documentation/gpu/i915.rst? hmm, I have the same question too:-). Can I modify the i915.rst to include kernel-doc from WOPCM and GuC WOPCM related changes? or someone would

Re: [Intel-gfx] [PATCH v2] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

On 03/14/2018 12:26 PM, Michal Wajdeczko wrote: On Wed, 14 Mar 2018 19:44:43 +0100, Jackie Li wrote: GuC Address Space and WOPCM Layout diagrams won't be generated correctly by sphinx build if not using proper reST syntax. This patch uses reST literal blocks to make

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

On 04/13/2018 07:15 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:17 +0200, Jackie Li wrote: After enabled the WOPCM write-once registers locking status checking, reloading of the i915 module will fail with modparam enable_guc set to 3 (enable GuC and HuC

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

On 04/13/2018 07:26 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:18 +0200, Jackie Li wrote: The enable_guc modparam is used to enable/disable GuC/HuC FW uploading dynamcially during i915 module loading. If WOPCM offset register was   typo D'oh! I really

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

On 04/13/2018 09:20 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:19 +0200, Jackie Li wrote: In current code, we only compare the locked WOPCM register values with the calculated values. However, we can continue loading GuC/HuC firmware if the locked (or

Re: [Intel-gfx] [PATCH v4 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

On 04/19/2018 08:45 AM, Michal Wajdeczko wrote: On Wed, 18 Apr 2018 19:01:31 +0200, Jackie Li wrote: After enabled the WOPCM write-once registers locking status checking, reloading of the i915 module will fail with modparam enable_guc set to 3 (enable GuC and HuC

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

On 04/19/2018 08:31 AM, Michal Wajdeczko wrote: On Mon, 16 Apr 2018 19:28:04 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 07:15 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:17 +0200, Jackie Li <yaodong...@intel.com> wrote: After enabled the WOPC

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

On 04/19/2018 08:52 AM, Michal Wajdeczko wrote: On Mon, 16 Apr 2018 19:43:52 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 07:26 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:18 +0200, Jackie Li <yaodong...@intel.com> wrote: The enable_guc modp

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

On 04/19/2018 09:37 AM, Michal Wajdeczko wrote: On Mon, 16 Apr 2018 20:43:39 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 09:20 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:19 +0200, Jackie Li <yaodong...@intel.com> wrote: In current code, we

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add code to accept valid locked WOPCM register values

On 03/26/2018 12:15 AM, Joonas Lahtinen wrote: Quoting Yaodong Li (2018-03-23 19:33:15) As I said, I agree that we would likely solve the enable_guc=1 then enable_guc=3 case with these changes which I think this the the only benefit that we can get from the starting from the top way. But my

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Use GuC FW size and HW restrictions to determine WOPCM partition

On 03/26/2018 03:04 AM, Michał Winiarski wrote: On Fri, Mar 23, 2018 at 01:00:35PM -0700, Yaodong Li wrote: On 03/23/2018 05:34 AM, Michał Winiarski wrote: We need GuC to load HuC, but it's also possible for GuC to operate on its own. We don't know what the size of HuC FW may be, so

Re: [Intel-gfx] [PATCH] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On 03/22/2018 09:18 AM, Piotr Piórkowski wrote: If GuC firmware is not available on the system and we load i915 with enable GuC, then we hit this null pointer dereference issue: [ 71.098873] BUG: unable to handle kernel NULL pointer dereference at 0008 [ 71.098938] IP:

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add code to accept valid locked WOPCM register values

On 03/22/2018 01:38 PM, Michał Winiarski wrote: On Tue, Mar 20, 2018 at 04:18:46PM -0700, Jackie Li wrote: In current code, we only compare the locked WOPCM register values with the calculated values. However, we can continue loading GuC/HuC firmware if the locked (or partially locked) values

Re: [Intel-gfx] [PATCH v3] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

Thanks Sagar and Joonas! I probably need reconfigure my email client. I will add these docs to i915.rst. Since we've already had a GuC chapter defined in i915.rst, so I will include these doc like: WOPCM         WOPCM Layout doc GuC             GuC Address Space doc Please let me

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On 03/23/2018 05:27 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 13:07:15 +0100, Sagar Arun Kamble wrote: On 3/23/2018 4:53 PM, Piotr Piórkowski wrote: If GuC firmware is not available on the system and we load i915 with enable GuC, then we hit this null

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On 03/23/2018 11:26 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 19:03:47 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 03/23/2018 05:27 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 13:07:15 +0100, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/23/

Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Separate WOPCM partitioning from constraints check

On 03/23/2018 05:34 AM, Michał Winiarski wrote: In the following patches we're going to support constraints checking on an already locked partitioning. Let's structure the code now to allow for code reuse and reduce the churn later on. Signed-off-by: Michał Winiarski

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Use GuC FW size and HW restrictions to determine WOPCM partition

On 03/23/2018 05:34 AM, Michał Winiarski wrote: We need GuC to load HuC, but it's also possible for GuC to operate on its own. We don't know what the size of HuC FW may be, so, not wanting to make any platform-specific hardcoded guesses, we assume that its size is 0... Which is a very bad

Re: [Intel-gfx] [PATCH v3] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On 03/22/2018 11:17 AM, Piotr Piórkowski wrote: If GuC firmware is not available on the system and we load i915 with enable GuC, then we hit this null pointer dereference issue: [ 71.098873] BUG: unable to handle kernel NULL pointer dereference at 0008 [ 71.098938] IP:

Re: [Intel-gfx] [PATCH 7/8] drm/i915/guc: Don't touch WOPCM if we're not using GuC

On 03/23/2018 05:34 AM, Michał Winiarski wrote: We probably shouldn't print out WOPCM size on platforms that don't have GuC. We also want to make sure we don't hit any asserts if user explicitly sets enable_guc != 0 on non-guc platforms. Signed-off-by: Michał Winiarski

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add code to accept valid locked WOPCM register values

On 03/23/2018 07:01 AM, Michał Winiarski wrote: On Thu, Mar 22, 2018 at 02:27:59PM -0700, Yaodong Li wrote: On 03/22/2018 01:38 PM, Michał Winiarski wrote: On Tue, Mar 20, 2018 at 04:18:46PM -0700, Jackie Li wrote: In current code, we only compare the locked WOPCM register values

Re: [Intel-gfx] [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote: Cc: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH v11 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0

On 03/01/2018 05:14 AM, Michal Wajdeczko wrote: On Thu, 01 Mar 2018 02:01:38 +0100, Jackie Li wrote: On CNL A0 and Gen9, there's a hardware restriction that requires the available GuC WOPCM size to be larger than or equal to HuC firmware size. This patch adds new

Re: [Intel-gfx] [PATCH v11 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

On 03/01/2018 04:56 AM, Michal Wajdeczko wrote: On Thu, 01 Mar 2018 02:01:36 +0100, Jackie Li wrote: +    if (guc_fw_size >= wopcm->size) { +    DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.", +  guc_fw_size / 1024); +    return -E2BIG; +  

Re: [Intel-gfx] [PATCH v11 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 03/01/2018 05:37 AM, Michal Wajdeczko wrote: On Thu, 01 Mar 2018 02:01:39 +0100, Jackie Li wrote: + +    err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, +   dev_priv->wopcm.guc.size, you should use wopcm-> instead dev_priv->wopcm. (same below)

Re: [Intel-gfx] [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:  (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED) + +/** + * intel_wopcm_init_early() - Early initialization of the WOPCM. + * @wopcm: pointer to intel_wopcm. + * + * Setup the size of WOPCM which will be used by later on WOPCM partitioning. + */