[Intel-gfx] [PATCH] drm/i915: Add a debugfs file to dump complete context

zeros, contiguous sequence of zeros are skipped in the output. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Armin Reese <armin.c.re...@intel.com> (v1) Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com

[Intel-gfx] [PATCH 0/2] capture error context

and one other small change. Arun Siluvery (1): drm/i915/error: Use yesno() to report iommu enable status Dave Gordon (1): drm/i915/error: capture errored context based on request context-id drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 48

[Intel-gfx] [PATCH 1/2] drm/i915/error: Use yesno() to report iommu enable status

Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index eecb870..3209f6a 100644 --- a/drive

[Intel-gfx] [PATCH 2/2] drm/i915/error: capture errored context based on request context-id

again by using a different way of identifying the context of interest in execlist mode. For: VIZ-2021 Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Dave Gordon <david.s.gor...@intel.com> Signed-off-by: Arun Siluvery <ar

[Intel-gfx] [PATCH v2 08/11] drm/i915: Skip reset request if there is one already

issues reset request again which is unnecessary. To avoid this we check if the engine is already prepared, if so we just exit from that point. Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i

[Intel-gfx] [PATCH v2 09/11] drm/i915/tdr: Add engine reset count to error state

Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/g

[Intel-gfx] [PATCH v2 06/11] drm/i915/tdr: Modify error handler for per engine hang recovery

event as usual. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Ian Lister <ian.lis...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com

[Intel-gfx] [PATCH v2 11/11] drm/i915/tdr: Enable Engine reset and recovery support

This feature is made available only from Gen8, for previous gen devices driver uses legacy full gpu reset. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_params.c | 4 ++-- 1 file changed,

[Intel-gfx] [PATCH v2 05/11] drm/i915: Separate out reset flags from the reset counter

we do not inspect the reset state during reset itself i.e. we no longer emit requests during reset, is that we can use the atomic updates of the state flags to ensure that only one reset worker is active. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Arun Siluvery <arun.siluv...@

[Intel-gfx] [PATCH v2 10/11] drm/i915/tdr: Export reset count info to debugfs

A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they areexpected to trigger reset; these counts are checked before and after the test to ensure the same. Signed-off-by: Arun Siluvery <arun.si

[Intel-gfx] [PATCH v2 01/11] drm/i915: Record the position of the start of the request

From: Chris Wilson Not only does it make for good documentation and debugging aide, but it is also vital for when we want to unwind requests - such as when throwing away an incomplete request. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH v2 02/11] drm/i915: Simplify ELSP queue request tracking

nstead of directly manipulating the elsp queue from reset path we can examine these ports, fix up ringbuffer pointers using the incomplete request and restart submissions again after reset. Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Arun Si

[Intel-gfx] [PATCH v2 07/11] drm/i915/tdr: Add support for per engine reset recovery

ff-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 59 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/

[Intel-gfx] [PATCH v2 00/11] Execlist based Engine reset patches

. v2: ELSP queue request tracking and reset path changes to handle incomplete requests during reset. Thanks to Chris Wilson for providing these patches. Arun Siluvery (6): drm/i915: Update i915.reset to handle engine resets drm/i915/tdr: Modify error handler for per engine hang recovery drm

[Intel-gfx] [PATCH v2 03/11] drm/i915: Update reset path to fix incomplete requests

kipped and head is reset to the start of breadcrumb. This allows us to resume from where we left-off. Since this request didn't complete normally we also need to cleanup elsp queue manually. Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915: fix WaInsertDummyPushConstPs

+ if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); Reviewed-by: Arun Siluvery <arun.siluv...@linux.intel.com> regards Arun _

Re: [Intel-gfx] [Beignet] [Patch V3] intel: Export pooled EU and min no. of eus in a pool.

On 02/08/2016 07:20, Yang, Rong R wrote: I sent a new version, could you check this and give comments/ACK? Cc: Daniel, intel-gfx mailing list. regards Arun Thanks, Yang Rong -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Yang Rong

Re: [Intel-gfx] [PATCH 05/11] drm/i915/tdr: Identify hung request and drop it

On 26/07/2016 22:37, Chris Wilson wrote: On Tue, Jul 26, 2016 at 05:40:51PM +0100, Arun Siluvery wrote: The current active request is the one that caused the hang so this is retrieved and removed from elsp queue, otherwise we cannot submit other workloads to be processed by GPU. A consistency

Re: [Intel-gfx] [PATCH 03/11] drm/i915/tdr: Update reset_in_progress to account for engine reset

On 27/07/2016 12:41, Chris Wilson wrote: On Wed, Jul 27, 2016 at 12:16:04PM +0100, Arun Siluvery wrote: On 26/07/2016 22:52, Chris Wilson wrote: A totally unexplained change. If it is because you think to want to break waiters on struct_mutex, try again. So you don't want error->fl

Re: [Intel-gfx] [PATCH 07/11] drm/i915/tdr: Add support for per engine reset recovery

On 26/07/2016 22:51, Chris Wilson wrote: On Tue, Jul 26, 2016 at 05:40:53PM +0100, Arun Siluvery wrote: This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back to the legacy full GPU reset recovery mode

Re: [Intel-gfx] [PATCH 03/11] drm/i915/tdr: Update reset_in_progress to account for engine reset

On 26/07/2016 22:52, Chris Wilson wrote: On Tue, Jul 26, 2016 at 05:40:49PM +0100, Arun Siluvery wrote: Now that we track reset progress using separate set of flags, update it to account for engine reset as well. A bit corresponding engine->id is set if reset is in progress for that eng

[Intel-gfx] [PATCH 09/11] drm/i915/tdr: Add engine reset count to error state

Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/g

[Intel-gfx] [PATCH 08/11] drm/i915: Skip reset request if there is one already

issues reset request again which is unnecessary. To avoid this we check if the engine is already prepared, if so we just exit from that point. Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i

[Intel-gfx] [PATCH 10/11] drm/i915/tdr: Export reset count info to debugfs

A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they areexpected to trigger reset; these counts are checked before and after the test to ensure the same. Signed-off-by: Arun Siluvery <arun.si

[Intel-gfx] [PATCH 11/11] drm/i915/tdr: Enable Engine reset and recovery support

Everything in place, flip the switch. This feature is available only from Gen8, for previous gen devices driver falls back to legacy full gpu reset. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 00/11] Execlist based Engine reset patches

. Arun Siluvery (9): drm/i915: Update i915.reset to handle engine resets drm/i915/tdr: Update reset_in_progress to account for engine reset drm/i915/tdr: Modify error handler for per engine hang recovery drm/i915/tdr: Identify hung request and drop it drm/i915/tdr: Restart submission after

[Intel-gfx] [PATCH 01/11] drm/i915: Update i915.reset to handle engine resets

In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_params.c | 6 +++--- drivers/gpu/drm/i915/i915_params

[Intel-gfx] [PATCH 06/11] drm/i915/tdr: Restart submission after engine reset

; Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 45 +--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8fc5a

[Intel-gfx] [PATCH 02/11] drm/i915: Separate out reset flags from the reset counter

we do not inspect the reset state during reset itself i.e. we no longer emit requests during reset, is that we can use the atomic updates of the state flags to ensure that only one reset worker is active. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Arun Siluvery <arun.siluv...@

[Intel-gfx] [PATCH 04/11] drm/i915/tdr: Modify error handler for per engine hang recovery

ter <ian.lis...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 23 +++ drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu

[Intel-gfx] [PATCH 07/11] drm/i915/tdr: Add support for per engine reset recovery

that caused the hang - reset itself failed for some reason Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/

[Intel-gfx] [PATCH 03/11] drm/i915/tdr: Update reset_in_progress to account for engine reset

Now that we track reset progress using separate set of flags, update it to account for engine reset as well. A bit corresponding engine->id is set if reset is in progress for that engine. Bit0 is for full gpu reset. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- dr

[Intel-gfx] [PATCH 05/11] drm/i915/tdr: Identify hung request and drop it

and we fallback to full gpu reset. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 116 +++ dr

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Add WaDisableGatherAtSetShaderCommonSlice

On 16/06/2016 15:44, Mika Kuoppala wrote: Add WaDisableGatherAtSetShaderCommonSlice for all gen9 as stated by bspec. References: HSD#2135817 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 7 +++ 2

Re: [Intel-gfx] [Beignet] [Patch V2] intel: Export pooled EU and min no. of eus in a pool.

On 15/07/2016 08:08, Yang Rong wrote: Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default

Re: [Intel-gfx] [PATCH v2] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

-- No code changes from v1 except for adding hsd ref. Reviewed-by: Arun Siluvery <arun.siluv...@linux.intel.com> regards Arun drivers/gpu/drm/i915/intel_lrc.c | 25 + 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/dr

Re: [Intel-gfx] [PATCH] intel: Export pooled EU and min no. of eus in a pool.

On 15/06/2016 09:19, Yang Rong wrote: Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default

Re: [Intel-gfx] [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

/* Pad to end of cacheline */ while (index % CACHELINE_DWORDS) wa_ctx_emit(batch, index, MI_NOOP); looks good to me, Reviewed-by: Arun Siluvery <arun.siluv...@linux.intel.com> regards Arun ___ Intel-gfx m

Re: [Intel-gfx] [PATCH] Runtime: set the sub slice according to kernel pooled EU configure.

On 30/06/2016 09:43, Song, Ruiling wrote: LGTM Ruiling Could you please let me know whether these patches are merged/yet to be merged? I have submitted kernel patch which is ready to be merged but we would like to know if userspace bits are merged or not?

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Export pooled eu info to userspace

On 01/07/2016 12:56, Chris Wilson wrote: On Fri, Jul 01, 2016 at 11:43:02AM +0100, Arun Siluvery wrote: Pooled EU is a bxt only feature and kernel changes are already merged. This feature is not yet exposed to userspace as the support was not yet available. Beignet team expressed interest

[Intel-gfx] [PATCH] drm/i915/bxt: Export pooled eu info to userspace

R <rong.r.y...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 6 ++ include/uapi/drm/i915_drm.h | 2 ++ 2 files changed, 8 inserti

[Intel-gfx] [PATCH] drm/i915/bxt: Export pooled eu info to userspace

el.com> Cc: Tim Gore <tim.g...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 6 ++ include/uapi/drm/i915_drm.h | 2 ++ 2 files changed, 8 insertions(+) diff --git

Re: [Intel-gfx] [Beignet] [PATCH] intel: Export pooled EU and min no. of eus in a pool.

...@lists.freedesktop.org] On Behalf Of Arun Siluvery Sent: Wednesday, June 15, 2016 16:17 To: Yang, Rong R <rong.r.y...@intel.com>; beig...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org Subject: Re: [Beignet] [PATCH] intel: Export pooled EU and min no. of eus in a pool. On 15/06/2016

Re: [Intel-gfx] [PATCH] drm/i915: Remove request->reset_counter

e competed reset using the global gpu_error->reset_counter s/competed/completed anymore, we do not need to track the reset_counter epoch inside the request. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Arun Siluvery <arun.siluv...@linux.intel.com> Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Add WaInPlaceDecompressionHang

IT(GEN9_GAMT_ECO_REG_RW_IA, + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); + /* WaDisableLSQCROPERFforOCL:kbl */ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); if (ret) with the indentation fixed, it is, Reviewed-by: Arun Siluvery <arun.siluv...@l

[Intel-gfx] [PATCH v2 08/15] drm/i915/tdr: Add support for per engine reset recovery

the hang - reset itself failed for some reason Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/

[Intel-gfx] [PATCH v2 13/15] drm/i915/tdr: Export reset count info to debugfs

A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they areexpected to trigger reset; these counts are checked before and after the test to ensure the same. Signed-off-by: Arun Siluvery <arun.si

[Intel-gfx] [PATCH v2 04/15] drm/i915/tdr: Modify error handler for per engine hang recovery

ter <ian.lis...@intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 23 drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu

[Intel-gfx] [PATCH v2 11/15] drm/i915: Port of Added scheduler support to __wait_request() calls

gt; Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: John Harrison <john.c.harri...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 7 ++- drivers/gpu/drm/i915/i915_gem.c | 34 +

[Intel-gfx] [PATCH v2 07/15] drm/i915/tdr: Restore engine state and start after reset

is resubmitted to HW. The request that caused the hang would be at the start of execlist queue, unless we resubmit and complete this request, it cannot be removed from the queue. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: A

[Intel-gfx] [PATCH v2 14/15] drm/i915/tdr: Enable Engine reset and recovery support

Everything in place, flip the switch. This feature is available only from Gen8, for previous gen devices driver falls back to legacy full gpu reset. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH v2 10/15] drm/i915: Extending i915_gem_check_wedge to check engine reset in progress

and that it needs to back off. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Ian Lister <ian.lis...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.in

[Intel-gfx] [PATCH v2 12/15] drm/i915/tdr: Add engine reset count to error state

Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/g

[Intel-gfx] [ONLY FOR BAT v2 15/15] drm/i915: Disable GuC submission for testing Engine reset patches

Engine reset implementation is currently supported with Execlist based submission, GuC submission need to be disabled for BAT testing purpose. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- Current TDR implementation is only for Execlist submission, we need this patch to

[Intel-gfx] [PATCH v2 00/15] Execlist based Engine reset and recovery

://lists.freedesktop.org/archives/intel-gfx/2016-April/092349.html Arun Siluvery (13): drm/i915: Update i915.reset to handle engine resets drm/i915/tdr: Extend the idea of reset_counter to engine reset drm/i915/tdr: Modify error handler for per engine hang recovery drm/i915/tdr: Prepare

[Intel-gfx] [PATCH v2 05/15] drm/i915/tdr: Prepare execlist submission to handle tdr resubmission after reset

the hang, once this is done then we continue with the normally submission of two contexts at a time. The intention is to restore the submission state at the time of hang. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/

[Intel-gfx] [PATCH v2 06/15] drm/i915/tdr: Capture engine state before reset

in execlist mode relies on the context resubmission after reset. If the state is inconsistent, resubmission can cause unforseen side-effects such as unexpected preemptions. Engine is restarted after reset with this state. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Si

[Intel-gfx] [PATCH v2 09/15] drm/i915: Skip reset request if there is one already

issues reset request again which is unnecessary. To avoid this we check if the engine is already prepared, if so we just exit from that point. Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i

[Intel-gfx] [PATCH v2 02/15] drm/i915/tdr: Extend the idea of reset_counter to engine reset

. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9fa9698..8bb05b2 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v2 03/15] drm/i915: Reinstate hang recovery work queue.

com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 26 +- 3 files changed, 23 inser

[Intel-gfx] [PATCH v2 01/15] drm/i915: Update i915.reset to handle engine resets

In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@

Re: [Intel-gfx] [PATCH] intel: Export pooled EU and min no. of eus in a pool.

On 15/06/2016 13:49, Yang Rong wrote: Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default

Re: [Intel-gfx] [PATCH v3] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate

U_SYNC_SWITCH_DISABLE)); + agrees with spec. It would've been good to have correct spelling but to match with existing documentation we have to use the same name. Reviewed-by: Arun Siluvery <arun.siluv...@linux.intel.com> regards Arun /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt

Re: [Intel-gfx] [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate

On 10/06/2016 12:16, Gore, Tim wrote: Tim Gore Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ -Original Message- From: Arun Siluvery [mailto:arun.siluv...@linux.intel.com] Sent: Friday, June 10, 2016 7:30 AM To: Gore, Tim; intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate

On 09/06/2016 20:19, tim.g...@intel.com wrote: From: Tim Gore This patch enables a workaround for a mid thread preemption issue where a hardware timing problem can prevent the context restore from happening, leading to a hang. v2: move to gen9_init_workarounds (Arun)

Re: [Intel-gfx] [PATCH] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate

On 09/06/2016 13:48, tim.g...@intel.com wrote: From: Tim Gore This patch enables a workaround for a mid thread preemption issue where a hardware timing problem can prevent the context restore from happening, leading to a hang. Signed-off-by: Tim Gore

Re: [Intel-gfx] [PATCH 08/62] drm/i915: Remove stop-rings debugfs interface

| 44 ++--- drivers/gpu/drm/i915/intel_lrc.c| 3 --- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 -- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 - 7 files changed, 15 insertions(+), 112 deletions(-) looks good to me, Reviewed-by: Arun Siluvery <arun.siluv...@linux.

Re: [Intel-gfx] [PATCH 12/62] drm/i915: Skip capturing an error state if we already have one

On 03/06/2016 22:06, Chris Wilson wrote: As we only ever keep the first error state around, we can avoid some work that can be quite intrusive if we don't record the error the second time around. This does move the race whereby the user could discard one error state as the second is being

Re: [Intel-gfx] [PATCH 05/21] drm/i915: Separate GPU hang waitqueue from advance

On 06/06/2016 18:30, Tvrtko Ursulin wrote: On 03/06/16 17:08, Chris Wilson wrote: Currently __i915_wait_request uses a per-engine wait_queue_t for the dual purpose of waking after the GPU advances or for waking after an error. In the future, we may add even more wake sources and require

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)

On 06/06/2016 14:58, Patchwork wrote: == Series Details == Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2) URL : https://patchwork.freedesktop.org/series/8218/ State : warning == Summary == Series 8218v2 drm/i915/gen9: Add

[Intel-gfx] [RESEND_FOR_CI] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear

Kernel only need to add a register to HW whitelist, required for a preemption related issue. Reference: HSD#2131039 Reviewed-by: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3)

On 03/06/2016 16:28, Patchwork wrote: == Series Details == Series: BXT Pooled EU kernel support and WA patches (rev3) URL : https://patchwork.freedesktop.org/series/8200/ State : warning == Summary == Series 8200v3 BXT Pooled EU kernel support and WA patches

Re: [Intel-gfx] [PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

On 03/06/2016 21:31, Matthew Auld wrote: What about skl, this also seems to need the WA until A0? SKL:A0 is pre-production stepping, it can be ignored. regards Arun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

[Intel-gfx] [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear

Kernel only need to add a register to HW whitelist, required for a preemption related issue. Reference: HSD#2131039 Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 5 + 2 files c

[Intel-gfx] [PATCH v3 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

eff.mc...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH v3 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

.r.y...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 10 ++ drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

to be exported using getparam ioctls. Cc: Winiarski, Michal <michal.winiar...@intel.com> Cc: Zou, Nanhai <nanhai@intel.com> Cc: Yang, Rong R <rong.r.y...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery

[Intel-gfx] [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

This is a WA affecting pooled eu which is a bxt specific feature. Cc: Winiarski, Michal <michal.winiar...@intel.com> Cc: Zou, Nanhai <nanhai@intel.com> Cc: Yang, Rong R <rong.r.y...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery <ar

[Intel-gfx] [PATCH v2 0/3] BXT Pooled EU kernel support and WA patches

of the related WA patches are also included in this series. [1] https://lists.freedesktop.org/archives/intel-gfx/2016-May/095890.html Arun Siluvery (3): drm/i915:bxt: Enable Pooled EU support drm/i915/bxt: Add WaEnablePooledEuFor2x6 drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix drivers/gpu

[Intel-gfx] [PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support

ris-wilson.co.uk> Cc: Armin Reese <armin.c.re...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Signed-off-by: Jeff McGee <jeff.mc...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c

Re: [Intel-gfx] [PATCH 06/23] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

On 26/05/2016 20:59, Mika Kuoppala wrote: We need this crucial workaround from skl also to all kbl revisions. Lack of it was causing system hangs on skl enabling so this is a must have. References: HSD#2126660 Signed-off-by: Mika Kuoppala ---

Re: [Intel-gfx] [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support

On 17/05/2016 15:34, Daniel Vetter wrote: On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: This mode allows to assign EUs to pools which can process work collectively. The command to enable this mode should be issued as part of context initialization. The pooled mode is global

[Intel-gfx] [PATCH 0/2] BXT Pooled EU kernel support

, they are currently adding userspace and libdrm support, meanwhile we can get some testing done on these patches. Arun Siluvery (2): drm/i915:bxt: Enable Pooled EU support drm/i915/bxt: Add WaEnablePooledEuFor2x6 drivers/gpu/drm/i915/i915_debugfs.c | 5 drivers/gpu/drm/i915/i915_dma.c

[Intel-gfx] [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support

Zou, Nanhai <nanhai@intel.com> Cc: Yang, Rong R <rong.r.y...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Armin Reese <armin.c.re...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Signed-off-by: Jeff McGee <

[Intel-gfx] [PATCH 2/2] drm/i915/bxt: Add WaEnablePooledEuFor2x6

. Cc: Winiarski, Michal <michal.winiar...@intel.com> Cc: Zou, Nanhai <nanhai@intel.com> Cc: Yang, Rong R <rong.r.y...@intel.com> Cc: Tim Gore <tim.g...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH 00/14] Gen8 Execlist based Engine reset and recovery support

. These are based on nightly tree pulled on 11th April. Arun Siluvery (12): drm/i915: Update i915.reset to handle engine resets drm/i915/tdr: Extend the idea of reset_counter to engine reset drm/i915/tdr: Modify error handler for per engine hang recovery drm/i915/tdr: Prepare execlist submission

[Intel-gfx] [PATCH 12/14] drm/i915/tdr: Add engine reset count to error state

Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the workloads it is executing before this error state. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/g

[Intel-gfx] [PATCH 14/14] drm/i915/tdr: Enable Engine reset and recovery support

Everything in place, flip the switch. This feature is available only from Gen8, for previous gen devices driver falls back to legacy full gpu reset. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 11/14] drm/i915: Port of Added scheduler support to __wait_request() calls

gt; Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: John Harrison <john.c.harri...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- Note: These names for WAIT_INTERRUPTIBLE and WAIT_LOCKED are not consistent with the ones used in Sched

[Intel-gfx] [PATCH 13/14] drm/i915/tdr: Export reset count info to debugfs

A new variable is added to export the reset counts to debugfs, this includes full gpu reset and engine reset count. This is useful for tests where they areexpected to trigger reset; these counts are checked before and after the test to ensure the same. Signed-off-by: Arun Siluvery <arun.si

[Intel-gfx] [PATCH 06/14] drm/i915/tdr: Capture engine state before reset

in execlist mode relies on the context resubmission after reset. If the state is inconsistent, resubmission can cause unforseen side-effects such as unexpected preemptions. Engine is restarted after reset with this state. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Si

[Intel-gfx] [PATCH 10/14] drm/i915: Extending i915_gem_check_wedge to check engine reset in progress

<ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 39 +++-- drivers/gpu/dr

[Intel-gfx] [PATCH 08/14] drm/i915/tdr: Add support for per engine reset recovery

the hang - reset itself failed for some reason Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/

[Intel-gfx] [PATCH 07/14] drm/i915/tdr: Restore engine state and start after reset

is resubmitted to HW. The request that caused the hang would be at the start of execlist queue, unless we resubmit and complete this request, it cannot be removed from the queue. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: A

[Intel-gfx] [PATCH 05/14] drm/i915/tdr: Prepare execlist submission to handle tdr resubmission after reset

the hang, once this is done then we continue with the normally submission of two contexts at a time. The intention is to restore the submission state at the time of hang. Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/

[Intel-gfx] [PATCH 09/14] drm/i915: Skip reset request if there is one already

issues reset request again which is unnecessary. To avoid this we check if the engine is already prepared, if so we just exit from that point. Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i

[Intel-gfx] [PATCH 04/14] drm/i915/tdr: Modify error handler for per engine hang recovery

intel.com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 23 drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_irq.c | 233 ++

[Intel-gfx] [PATCH 02/14] drm/i915/tdr: Extend the idea of reset_counter to engine reset

. Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5424016..ca9b1ec 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH 03/14] drm/i915: Reinstate hang recovery work queue.

com> Signed-off-by: Tomas Elf <tomas@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 29 ++--- 3 files changed,

[Intel-gfx] [PATCH 01/14] drm/i915: Update i915.reset to handle engine resets

In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Arun Siluvery <arun.siluv...@

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