> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, March 23, 2022 1:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni ; Runyan, Arthur J
>
> Subject: [PATCH] drm/i915/adlp: Fix register corruption after DDI clock
> enabling
>
> Acce
I remember some strangeness about the blnclegdisbl. I'll see if I can dig up
some more.
-Original Message-
From: Ville Syrjälä
Sent: Monday, August 24, 2020 11:05 AM
To: Kai-Heng Feng
Cc: Runyan, Arthur J ; Vivi, Rodrigo
; intel-gfx
Subject: Re: [Regression] "drm/i915: Impl
, Arthur J
Cc: Vivi, Rodrigo ; Ville Syrjälä
; intel-gfx
Subject: Re: [Regression] "drm/i915: Implement display w/a #1143" breaks HDMI
on ASUS GL552VW
Hi,
> On Aug 14, 2020, at 01:56, Runyan, Arthur J wrote:
>
> The workaround is freeing up stuck vswing values to let new vswing
To: Kai-Heng Feng ; Runyan, Arthur J
Cc: Ville Syrjälä ; intel-gfx
Subject: Re: [Regression] "drm/i915: Implement display w/a #1143" breaks HDMI
on ASUS GL552VW
Art, any comment here?
I just checked and the W/a 1143 is implemented as described, but it is failing
HDMI on this hyb
> -Original Message-
> From: Imre Deak
> Sent: Monday, 26 August, 2019 6:42 AM
> To: Souza, Jose ; De Marchi, Lucas
> ; Runyan, Arthur J
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
>
> Subject: Re: [Intel-gfx] [PATCH v3 04/23] drm/i915/bdw+: Enab
> From: Vivi, Rodrigo
> Sent: Wednesday, 3 April, 2019 5:22 PM
> To: Souza, Jose ; Runyan, Arthur J
>
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
>
> Subject: Re: [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround
> comment
>
> On Wed, Apr 03
PSR2 logic is incorrectly looking at this register bit during DC5 exit.
Not a DMC problem, but DMC enables DC5.
I'll update Bspec to require the bit to be not set when PSR2 is used.
> -Original Message-
> From: Runyan, Arthur J
> Sent: Tuesday, 12 March, 2019 4:42 PM
> To:
Strange. DMC doesn't look at training patterns. I've asked the PSR2 guys to
look for any cross-connection.
> -Original Message-
> From: Souza, Jose
> Sent: Tuesday, 12 March, 2019 2:29 PM
> To: Vivi, Rodrigo ; Pandiyan, Dhinakaran
>
> Cc: Runyan, Arthur J ; Aigal,
I'll check on it.
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, 29 November, 2018 3:47 PM
> To: Vivi, Rodrigo
> Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> Runyan, Arthur J ; Pandiyan, Dhinakaran
>
> Subject: Re: [PAT
ille Syrjälä ; Runyan, Arthur J
>
> Cc: Navare, Manasi D ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Vivi, Rodrigo
>
> Subject: Re: [Intel-gfx] [PATCH v4 19/25] drm/i915/dsc: Add a power domain
> for VDSC on eDP/MIPI DSI
>
> On Fri, Sep 21, 201
across
planes on the same pipe. Multiple pipes will still require a wait for vblank.
From: Vyas, Tarun
Sent: Thursday, 12 April, 2018 9:57 AM
To: intel-gfx@lists.freedesktop.org
Cc: Runyan, Arthur J <arthur.j.run...@intel.com>; Shaikh, Azhar
<azhar.sha...@intel.com>; Herbert, Mar
Ok, please update the workaround page to show all the impacted projects
https://gfxspecs.intel.com/Predator/Home/Index/21829
> -Original Message-
> From: Mullah, Abid A
> Sent: Tuesday, 27 February, 2018 8:52 AM
> To: Runyan, Arthur J <arthur.j.run...@intel.com>; Pa
Abid or Hari, please check. There was a workaround to set AUD_CHICKENBIT_REG
bit 15 (Codec Wake overwrite to DACFEUNIT) on SKL and KBL. Does it apply to
BXT also?
> -Original Message-
> From: Pandiyan, Dhinakaran
> Sent: Monday, 26 February, 2018 6:04 PM
> To: Runy
Good question. We forgot that one. It's 0x162A90.
-Original Message-
From: Vivi, Rodrigo
Sent: Tuesday, 23 January, 2018 8:30 AM
To: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
<lucas.demar...@intel.com>; Runy
<ville.syrj...@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org; Runyan, Arthur J
<arthur.j.run...@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Implement display w/a #1143
On Fri, Jan 19, 2018 at 06:45:49PM +, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj.
..@intel.com; Runyan, Arthur J <arthur.j.run...@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm: i915: Fix audio issue on BXT
+Art
On Thu, 2018-01-04 at 22:13 +0530, Singh, Gaurav K wrote:
>
> On 1/4/2018 2:48 AM, Rodrigo Vivi wrote:
> > On Wed, Jan 03, 2018 at 08:31:10PM +00
, Dhinakaran <dhinakaran.pandi...@intel.com>
Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org; Runyan, Arthur J
<arthur.j.run...@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS
on GLK
On Mon, Dec 11, 2017 at 06:41:05PM +, Pandiyan
nobody is
validating it that way.
You do want to lower voltage to save power.
-Original Message-
From: Vivi, Rodrigo
Sent: Friday, 20 October, 2017 1:37 PM
To: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Runyan, Arthur J <arthur.j.run...@intel.com>;
intel-gfx@lists.fre
<rodrigo.v...@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika <mika.kah...@intel.com>;
Navare, Manasi D <manasi.d.nav...@intel.com>; Runyan, Arthur J
<arthur.j.run...@intel.com>
Subject: Re: [PATCH 8/8] drm/i915: Adjust system agent voltage on CNL if
required b
e.syrj...@linux.intel.com;
jani.nik...@linux.intel.com; Runyan, Arthur J <arthur.j.run...@intel.com>;
b...@bwidawsk.net
Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting
On Wed, Oct 04, 2017 at 08:09:22PM +, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do
The workaround needs to come before you enable the detection in SHOTPLUG_CTL.
-Original Message-
From: Vivi, Rodrigo
Sent: Friday, 8 September, 2017 5:38 PM
To: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>; Runyan, Arthur J
<arthur.j.run...@intel.com>
Cc: b...@
will be restricting package C states even at
1920x1080 60hz. The 8 number was based on what hardware did for allocation on
past projects.
-Original Message-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
Sent: Thursday, June 23, 2016 12:50 PM
To: Runyan, Arthur J
Cc: Sripada
-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
Sent: Thursday, June 16, 2016 4:20 PM
To: Sripada, Radhakrishna
Cc: intel-gfx; drm-intel-fi...@lists.freedesktop.org; Runyan, Arthur J
Subject: Re: [Intel-gfx] [PATCH] drm/i915/skl: Increase cursor ddb blocks in
multi-pipe config
I believe we
ers. I'll send you the internal link.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Wednesday, May 18, 2016 11:47 AM
To: Ville Syrjälä; Runyan, Arthur J
Cc: Vetter, Daniel; Intel Graphics Development; Pandiyan, Dhinakaran; Vivi,
Rodrigo
Subject: Re: [Intel-gfx
, looks wrong since the Fast Wake Sync
Pulse Count is zeroed out. Check what value it uses after 15msec when aux is
working.
>-Original Message-
>From: Lyude [mailto:cp...@redhat.com]
>Sent: Tuesday, March 01, 2016 9:15 AM
>To: Runyan, Arthur J
>Cc: intel-gfx@lists.freedesk
>-Original Message-
>From: Deak, Imre
...
>The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT
>(looks like a recent addition to work around something), but it doesn't
>say it's needed for other platforms. The register description doesn't
>make a difference though.
>
e.syrj...@linux.intel.com]
>Sent: Wednesday, February 17, 2016 9:37 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Paulo Zanoni; Runyan, Arthur J
>Subject: Re: [PATCH] drm/i915: Disable FDI RX before DDI_BUF_CTL
>
>On Tue, Dec 08, 2015 at 04:47:55PM +0200, ville.syrj...@linux.intel.c
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
That fuse may not be correct on all SKUs, but I assume you have other ways to
recognize what kind of package it is. I originally listed out ULT and ULX,
but it
became more complicated with BDW.
I'm not aware of any way of identifying
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
On Wed, Aug 26, 2015 at 04:13:52PM -0300, Paulo Zanoni wrote:
...
Although the doc for LPT _suggests_ this is only for LPT:LP, it
doesn't mark this bit as LPT:LP-specific just like it marks all the
other LPT:LP-specific bits in every
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
On Mon, Jun 22, 2015 at 3:31 PM Runyan, Arthur J arthur.j.run...@intel.com
wrote:
-- Daniel
I guess I don't really understand your description, but it does sound
strange ... runtime pm enabling from my patch is only about D3, power
well
-- Daniel
I guess I don't really understand your description, but it does sound
strange ... runtime pm enabling from my patch is only about D3, power
well changes are still done. And as long as we have anything enabled
(even with PSR) we'll prevent D3.
So the only thing I can think of is
From: Konduru, Chandra
Hi Daniel,
NV12 programming is documented in bspec under display planes Plane
Planar YUV programming. There it talks about aux_dist which is the
distance between y and uv planes expecting uv to be after y.
Bspec talks about wrap-around, which at least
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
On Mon, May 18, 2015 at 07:19:19PM +, Runyan, Arthur J wrote:
The statement is correct - the X offset must always be even for
YUV422+NV12,
and the Y offset must be even when rotated 90/270 degrees.
Hmm. Can you elaborate a bit
From: Konduru, Chandra
Hi Daniel,
NV12 programming is documented in bspec under display planes Plane
Planar YUV programming. There it talks about aux_dist which is the
distance between y and uv planes expecting uv to be after y.
Bspec talks about wrap-around, which at least indicates
The statement is correct - the X offset must always be even for YUV422+NV12,
and the Y offset must be even when rotated 90/270 degrees.
From: Konduru, Chandra
From: Runyan, Arthur J
I'll take a look.
Art, Any update to close on this?
[snip]
@@ -13144,6 +13149,10
I'll take a look.
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Tuesday, May 12, 2015 3:44 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Syrjala, Ville; Jindal,
Sonika; Runyan, Arthur J
Subject: Re: [Intel-gfx] [PATCH
I think there may be a restriction that we cannot set 0us to all the training
patterns. I'll check on that.
-Original Message-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
Sent: Tuesday, March 24, 2015 8:30 AM
To: Vivi, Rodrigo
Cc: intel-gfx; Runyan, Arthur J
Subject: Re: [Intel
I think your ilk_wm_method2 is busted. Method 2 should always give more than
one full line, making this 1 line redundant.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Monday, March 02, 2015 9:09 AM
To: Intel Graphics Development; Runyan, Arthur J
Cc
+ /*
+* FIXME if we compare against max we should then
+* increase the cdclk frequency when the current
+* value is too low. The other option is to compare
+* against the cdclk frqeuncy we're going have post
+* modeset (ie. one we computed using
From: Daniel Vetter
On Thu, Oct 30, 2014 at 05:35:55AM -0700, Rodrigo Vivi wrote:
It was identified that in some cases when moving cursor Hardware can do
mistake with idle_frame count. So Spec is being updated to use
2 as minimum idle_frames.
Reference:
So did you verify that the register really is a transcoder register?
Eg. set PIPE_MULT(A) to 1x and use pipe A to drive the EDP transcoder.
I did not verify. This change was done based on the fact that the
register does not exist in the VPG HTML version of the BPEC for
Transcoder_EDP,
Looks good
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2
You updated FDI entry 6 here, but Predator r74080 is just DP entry 6. I'll
find out if FDI needs a similar change.
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 2
That was a fast fix. Looks good now.
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
02, 2014 5:27 PM
To: Runyan, Arthur J; Daniel Vetter
Cc: Jani Nikula; Ville Syrjälä; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL
Enable assert
On 08/27/2014 01:54 PM, Runyan, Arthur J wrote:
:-) We pulled most of the mobile
Vetter
Sent: Tuesday, August 26, 2014 2:52 AM
To: Runyan, Arthur J
Cc: Jani Nikula; Taylor, Clinton A; Ville Syrjälä;
Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL
Enable assert
On Fri, Aug 22, 2014 at 05:12:25PM +, Runyan, Arthur J
A; Ville Syrjälä; Runyan, Arthur J
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL
Enable assert
+Art
On Thu, 21 Aug 2014, Clint Taylor clinton.a.tay...@intel.com wrote:
There is also a need to add this delay when turning off
You give me too much credit. I just gave you an explanation of what the
hardware does, then you ran with it.
On Thu, Jun 19, 2014 at 12:06:13PM -0700, Ben Widawsky wrote:
+ DRM_INFO(Reducing the compressed framebuffer size. This may
lead to increased power. Try to increase stolen
-Original Message-
From: Ben Widawsky [mailto:benjamin.widaw...@linux.intel.com]
Sent: Thursday, April 10, 2014 11:41 AM
To: Chris Wilson; Widawsky, Benjamin; Intel GFX; Runyan, Arthur J
Subject: Re: [Intel-gfx] [PATCH] drm/i915/bdw: Add 42ms delay for IPS disable
On Thu, Apr 10, 2014
Ben explained some of the fine details of the code to me, and I'm happy.
Reviewed-by: Art Runyan arthur.j.run...@intel.com
From: Ben Widawsky benjamin.widaw...@linux.intel.com
This is a requirement added to the spec. This patch will prevent
persistent corruption on the display.
v2: Make the
, March 21, 2014 3:19 AM
To: Nikula, Jani; Runyan, Arthur J; Syrjala, Ville
Cc: intel-gfx
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Increase WM memory latency values
on SNB with
high pixel clock
On Fri, Mar 21, 2014 at 11:00:48AM +0200, Jani Nikula wrote:
From: Ville Syrjälä ville.syrj
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Wednesday, January 22, 2014 2:40 PM
To: Intel Graphics Development
Cc: Daniel Vetter; Chris Wilson; Runyan, Arthur J; Dave Airlie
Subject: [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only
At least I couldn't find
, 2014 12:57 AM
To: Intel Graphics Development
Cc: Daniel Vetter; Runyan, Arthur J; Dave Airlie
Subject: [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only
At least I couldn't find it in the Haswell Bspec any more and we've
tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
hit
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